* Order patch application
Per discussion with @demarchi this PR adds ordering to the
patch application.
This alos add some encoding
00000 series - is for px4 non up streamable changes
60000 (bp) series - is for back ports
90000 series - is for wip that shold make it upstream
* Restore 00010-workarround-for-flash-data-cache-corruption
Extract this from the 90000-wip-inflight-to-upstream.patch
and orders it.
* Moved upstreamed 0dbf44e flash fix to bp patch
* Moved upstreamed 5481087 cdcacm fix to bp patch
* Moved upstreamed ec85425 STM32F7 copy paste errors to bp patch
* Moved upstreamed 20e7237 HSI should not be turned off to bp patch
* Moved upstreamed ca895b9 Adding missing CONFIG_ prefix to bp patch
* Moved upstreamed 169b398 STM32: Fixes the bkp reference counter issue to bp patch
* Moved upstreamed 550d259 STM32F7: Fixes the bkp reference counter issue to bp patch
* Moved upstreamed 02825f3 STM32F3X: Add missing STM32_BKP_BASE to bp patch
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Order Patches by Name
This reverts commit 22738b1213fff704d288ec84976fa84ff9535aba.
The command was added due to a lack of my understanding of how the pwm command can be used.
The command is not needed as the all flag can be used or a proper
mask WHIHOUT -g
fmu task mode_pwm
pwm rate -a -r 50 -d /dev/pwm_output0
pwm arm
pwm test -a -p 500
fmu task mode_pwm
pwm oneshot -a -d /dev/pwm_output0 is the same as pwm oneshot -m 0xff -d /dev/pwm_output0
pwm arm
pwm test -a -p 500
Since the Onshot<->PWM mode is changed based on rate. The
this signale the higher layers that the operation is invalid
test case:
fmu task mode_pwm2cap2
pwm oneshot -m 0xf -g 0 -d /dev/pwm_output0
should fail, because all the channels in the group are
not in the same mode.
1) Updated copyright
2) Defined BOARD overrideable BOARD_PWM_FREQ and BOARD_ONSHOT_FREQ
Not recogmended but allow experimentation
3) Solved the support for BOARD_PWM_DRIVE_ACTIVE_LOW using
the Polarity control bits as apposed to the negation of
the ARR.
4) Added a cache for getting a timers channels. This is static
and benifits from the qucik response.
5) Added a function to realocate all channes in a given timer
from one mode to another.
6) Removed the frequecy table in favor of the intended use of the
channel mode set. At it is the way to determine the mode of a
channel. Or in onshot's case a timers's complete set channels.
7) Added 2 lowlevel mode changing functions:
io_timer_set_oneshot_mode and io_timer_set_PWM_mode
that encapsalate the changes in mode to one place
in the code.
8) Added io_timer_trigger (the up_pwm_update) with low
latancy timer to time in updating.
9) io_timer_set_rate - use sets to enforce all or none
rules for switching PWM<->OneShot.
Onshot is entered using the very approriate rate of 0.
Only deltas will change the HW state.
1) Define IOTimerChanMode_OneShot
2) Added detailed commnent on .clock_freq and how it is used
3) Added single additional API point in support of Onshot mode
io_timer_trigger - That trigger all timer's channels in Oneshot
mode to fire the oneshots with updated values.
1) Validate timer paramater before using it.
2) Allow rate of 0 to enter Oneshot mode
At first blush this seamed like a hack, but at Mark
pointed out to me, Onshot PWM does not have a rate
So this is a realy a clever and beautiful simplification
on his part!
3) Exposes up_pwm_update that runs io_timer_trigger
Which trigger all timer's channels in Oneshot mode to
fire the oneshots with updated values.
The fmu now support the commandline option to be run as a task
or off a work queue.
This reverts the board_config.h changes from commit
e33af23122f5ee3030bb9745bbbf616b24c2a14a.
Conflicts:
src/drivers/px4fmu/fmu.cpp
* Backport:stm32f7: stm32_allocateheap: allow use DTCM memory for heap
Back port of upstrem contrib by Jussi Kivilinna <jussi.kivilinna@haltian.com>
stm32f7: stm32_allocateheap: allow use DTCM memory for heap
STM32F7 has up to 128KiB of DTCM memory that is currently left unused.
This patch adds DTCM to main heap if CONFIG_STM32F7_DTCMEXCLUDE is not enabled.
* px4fmu-v5_default:Enable inclusion of the DTCM in the heap
CONFIG_MM_REGIONS=3 adds the DTCM region to the heap.
Backport of upstream:
7601a27cee348f70bebcac95e8e8372fe0651bbf David Sidrane Thu Mar 16 14:16:18 2017 -1000 sem_holder:The logic for the list version is unchanged
3cc2a4f7c9bb495da6c59f373f8d0e7672e4ee13 David Sidrane Wed Mar 15 14:02:55 2017 -1000 sem_holder: Fixes improper restoration of base_priority
caf8bac7fb9452f25a3297147e7b414d46e74c6f David Sidrane Mon Mar 13 22:54:13 2017 +0000 missing semi
d66fd9f965f27eb0446d6aed24b8758674f98b53 David Sidrane Mon Mar 13 12:34:39 2017 -1000 semaphore:sem_boostholderprio prevent overrun of pend_reprios
3c00651cfef3a0d90bb9e6522463965ad8989e6c David Sidrane Mon Mar 13 11:56:31 2017 -1000 semaphore:sem_holder sem_findholder missing inintalization of pholder
4d760c5ea44c5f8d30a1a595800e9fbf4874e705 David Sidrane Mon Mar 13 10:46:26 2017 -1000 semaphore:sem_holder add DEBUGASSERTs
modified 399f3067441941072664bdbfa1bfec8ff35aa449 Gregory Nutt Sat Mar 11 08:57:34 2017 -0600 A few cosmetic changes (removed file that had nothing to do with semaphore commit by OA)
60d8606b19a7e7c1285a0ef5e8addaaedf26b95f David Sidrane Fri Mar 10 06:38:17 2017 -1000 Priority Inversion fixes:Initalization
6cc8f9100b3c8026e73ca738aaa5120bd78dae74 David Sidrane Fri Mar 10 06:37:46 2017 -1000 Priority Inversion fixes:typo
360539afacc83132acdb83da8f20c468dbe4c63d Gregory Nutt Fri Mar 10 09:30:15 2017 -0600 Priority inheritance: When CONFIG_SEM_PREALLOCHOLDERS==0, there is only a single, hard-allocated holder structure.
This is problem because in sem_wait() the holder is released, but needs to remain in the holder container
a93e46d00c1bc3447fb290b866ed21d8f9c8e146 Gregory Nutt Fri Mar 10 08:54:50 2017 -0600 Cosmetic (missleading OA commit message) Using !pholder is now pholder == NULL
sem_holder: Fixes improper restoration of base_priority
in the case of CONFIG_SEM_PREALLOCHOLDERS=0
Original code did not take into accout that 2 holder are needed
and failed silently when a slot could not be allocated
The call to sem_restorebaseprio_task context switches in the
sem_foreachholder(sem, sem_restoreholderprioB, stcb); call
prior to releasing the holder. So the running task is left
as a holder as is the started task. Leaving both slots filled
Thus failing to perforem the boost/or restoration on the
correct tcb.
This PR fixes this by releasing the running task slot prior
to reprioritization that can lead to the context switch.
To faclitate this, the interface to sem_restorebaseprio
needed to take the tcb from the holder prior to the
holder being freed. In the failure case where sched_verifytcb
fails it added the overhead of looking up the holder.
There is also the additional thunking on the foreach to
get from holer to holder->tcb.
Backport of upstream NuttX
86400a252dcbe6e4aef3ecca000b469a0fe96b67
08e92abb0ba744927ed0b32294859b0f47726f82
4b65817e99cbdf04fefad883eca0e7c8a9add63c
Improper rounding in redundant stack coloring
routines could overwriting the TOS+1 and BOS-1
depending on the value of CONFIG_ARCH_INTERRUPTSTACK
This applies the compelet upstream set of fixes from
David Cabecinhas <david.cab+bitbucket@gmail.com>
Improper rouding in redundant stack coloring
routines was overwriting the TOS+1 and BOS-1
The legacy OABI 4 byte stack alingment was removed
Only the EABI 8 byte alinement is supported
The redundant interrupt stack coloring. up_initalize
had the correct implemantation (last verson of patch)
and the redundant version in the
arch/arm/src/stmxxx/stmxx_irq.c was calculating the size
wrong.
This is fixed by rounding up CONFIG_ARCH_INTERRUPTSTACK
by 4 bytes when allocated and alining on a 8 byte boundry
nuttx-patches/workarround_for_flash_data_cache_corruption.patch was
patching a file patched in nuttx-patches/wip_inflight_to_upstream.patch
The changes in workarround_for_flash_data_cache_corruption.patch
will be submitted upstream once refactored (upstream coding style
compliant and moved to correct location)
backport 3cd66af889b42b036d6c9d88e067fc3b8abbdb2a and pr 258
Applies to STM32F4 and STM32F7
STM32, STM32 F7, and STM32 L4: Clone Freddie Chopin's I2C change to similar STM32 I2C drivers.
Save elapsed time before handling I2C in stm32_i2c_sem_waitstop()
This patch follows the same logic as in previous fix to
stm32_i2c_sem_waitdone().
It is possible that a context switch occurs after I2C registers are read
but before elapsed time is saved in stm32_i2c_sem_waitstop(). It is then
possible that the registers were read only once with "elapsed time"
equal 0. When scheduler resumes this thread it is quite possible that
now "elapsed time" will be well above timeout threshold. In that case
the function returns and reports a timeout, even though the registers
were not read "recently".
Fix this by inverting the order of operations in the loop - save elapsed
time before reading registers. This way a context switch anywhere in the
loop will not cause an erroneous "timeout" error.
5a6d95dd9f051be548a8d2378aaef75f0a1ba5e1 and ee5ae3a57dbbe835584f164c956e0374da1ed2eb
Applies to STM32F4 and STM32F7
Save elapsed time before handling I2C in stm32_i2c_sem_waitdone()
It is possible that a context switch occurs after stm32_i2c_isr() call
but before elapsed time is saved in stm32_i2c_sem_waitdone(). It is then
possible that the handling code was executed only once with "elapsed
time" equal 0. When scheduler resumes this thread it is quite possible
that now "elapsed time" will be well above timeout threshold. In that
case the function returns and reports a timeout, even though the
handling code was not executed "recently".
Fix this by inverting the order of operations in the loop - save elapsed
time before handling I2C. This way a context switch anywhere in the loop
will not cause an erroneous "timeout" error.
Remove the notion of legacy from the api. The board level code
will perform the traslation to lecacy format on the STM32.
new targets will not need to do this as there is no case
where the serial number were used by mfg for tracking.
Extend board common api to get mfguid and mfguid formatted
This adds an api that return the MFGUID as an array of bytes
or a string.
The data is returned with the MSD at index 0 and the LSD at
index PX4_CPU_MFGUID_BYTE_LENGTH-1.
Removed all reodering defines from the api and hal
Compliments the Bootloader change To simplify the ripple effect on the tools, we will be using /dev/serial/by-id/*_PX4_* to locate PX4 devices. Therefore moving forward all Bootloaders must contain the prefix "PX4 BL " in the USBDEVICESTRING
* Added tool to restore defconfig sections after make [old|menu]config
* Use tool to restore defconfig sections after make [old|menu]config
invocation:
make px4fmu-v2_default oldconfig_px4fmu-v2
make px4fmu-v2_default menuconfig_px4fmu-v2
This abstraction will support mcu's other than the stm32 family.
It moves the systemlib/mcu_version.c functionality to
common/stm32/board_mcu_version.c
David Sidrane