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drv_io_timer Support OneShot
1) Updated copyright
2) Defined BOARD overrideable BOARD_PWM_FREQ and BOARD_ONSHOT_FREQ
Not recogmended but allow experimentation
3) Solved the support for BOARD_PWM_DRIVE_ACTIVE_LOW using
the Polarity control bits as apposed to the negation of
the ARR.
4) Added a cache for getting a timers channels. This is static
and benifits from the qucik response.
5) Added a function to realocate all channes in a given timer
from one mode to another.
6) Removed the frequecy table in favor of the intended use of the
channel mode set. At it is the way to determine the mode of a
channel. Or in onshot's case a timers's complete set channels.
7) Added 2 lowlevel mode changing functions:
io_timer_set_oneshot_mode and io_timer_set_PWM_mode
that encapsalate the changes in mode to one place
in the code.
8) Added io_timer_trigger (the up_pwm_update) with low
latancy timer to time in updating.
9) io_timer_set_rate - use sets to enforce all or none
rules for switching PWM<->OneShot.
Onshot is entered using the very approriate rate of 0.
Only deltas will change the HW state.
This commit is contained in:
David Sidrane
Lorenz Meier
parent
96db91c468
commit
f5bc3dbc4e
@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (C) 2012 PX4 Development Team. All rights reserved.
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* Copyright (C) 2012, 2017 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -65,6 +65,21 @@
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#define arraySize(a) (sizeof((a))/sizeof(((a)[0])))
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/* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
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* then configure the timer to free-run at 1MHz.
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* Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
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* For instance .clock_freq = 1000000 would set the prescaler to 1.
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* We also allow for overrides here but all timer register usage need to be
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* taken into account
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*/
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#if !defined(BOARD_PWM_FREQ)
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#define BOARD_PWM_FREQ 1000000
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#endif
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#if !defined(BOARD_ONSHOT_FREQ)
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#define BOARD_ONSHOT_FREQ 8000000
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#endif
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#define MAX_CHANNELS_PER_TIMER 4
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#define _REG32(_base, _reg) (*(volatile uint32_t *)(_base + _reg))
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@ -103,17 +118,18 @@
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#define CCMR_C1_PWMOUT_INIT (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE
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#define CCMR_C1_ONESHOT_INIT (GTIM_CCMR_MODE_PWM2 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE
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#define CCMR_C1_PWMIN_INIT 0 // TBD
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#if defined(BOARD_PWM_DRIVE_ACTIVE_LOW)
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#define CCER_C1_INIT (GTIM_CCER_CC1P | GTIM_CCER_CC1E)
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#else
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#define CCER_C1_INIT GTIM_CCER_CC1E
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#endif
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// NotUsed PWMOut PWMIn Capture OneShot
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io_timer_channel_allocation_t channel_allocations[IOTimerChanModeSize] = { UINT8_MAX, 0, 0, 0, 0 };
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typedef uint8_t io_timer_allocation_t; /* big enough to hold MAX_IO_TIMERS */
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static uint8_t timer_freq[MAX_IO_TIMERS] = { 1, 1, 1, 1 }; /* default 1 MHz counter frequency */
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static io_timer_allocation_t once = 0;
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typedef struct channel_stat_t {
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@ -240,20 +256,42 @@ static inline int channels_timer(unsigned channel)
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return timer_io_channels[channel].timer_index;
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}
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static inline int get_timers_firstchannels(unsigned timer)
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{
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int channel = -1;
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if (validate_timer_index(timer) == 0) {
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channel = timer_io_channels[io_timers[timer].first_channel_index].timer_channel;
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}
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return channel;
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}
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static uint32_t get_timer_channels(unsigned timer)
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{
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uint32_t channels = 0;
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static uint32_t channels_cache[MAX_IO_TIMERS] = {0};
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if (validate_timer_index(timer) == 0) {
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const io_timers_t *tmr = &io_timers[timer];
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/* Gather the channel bits that belong to the timer */
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if (validate_timer_index(timer) < 0) {
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return channels;
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for (unsigned chan_index = tmr->first_channel_index; chan_index <= tmr->last_channel_index; chan_index++) {
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channels |= 1 << chan_index;
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} else {
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if (channels_cache[timer] == 0) {
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const io_timers_t *tmr = &io_timers[timer];
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/* Gather the channel bits that belong to the timer */
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for (unsigned chan_index = tmr->first_channel_index; chan_index <= tmr->last_channel_index; chan_index++) {
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channels |= 1 << chan_index;
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}
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/* cache them */
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channels_cache[timer] = channels;
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}
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}
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return channels;
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return channels_cache[timer];
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}
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static inline int is_channels_timer_uninitalized(unsigned channel)
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@ -316,6 +354,32 @@ int io_timer_get_channel_mode(unsigned channel)
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return -1;
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}
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static int reallocate_channel_resources(uint32_t channels, io_timer_channel_mode_t mode,
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io_timer_channel_mode_t new_mode)
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{
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/* If caller mode is not based on current setting adjust it */
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if ((channels & channel_allocations[IOTimerChanMode_NotUsed]) == channels) {
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mode = IOTimerChanMode_NotUsed;
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}
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/* Remove old set of channels from original */
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channel_allocations[mode] &= ~channels;
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/* Will this change ?*/
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uint32_t before = channel_allocations[new_mode] & channels;
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/* add in the new set */
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channel_allocations[new_mode] |= channels;
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/* Indicate a mode change */
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return before ^ channels;
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}
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static inline int allocate_channel_resource(unsigned channel, io_timer_channel_mode_t mode)
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{
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int rv = io_timer_is_channel_free(channel);
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@ -378,13 +442,9 @@ static int allocate_channel(unsigned channel, io_timer_channel_mode_t mode)
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static int timer_set_rate(unsigned timer, unsigned rate)
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{
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/* Configure the timer to run at 1MHz (other system code _assumes_ that timers run at 1MHz).
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* If you want to hack this to achieve a different frequency, alter the value of
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* .clock_freq in the relevant driver/boards/xxxx/xxx_timer_config.c file.
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*/
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timer_freq[timer] = 1;
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rPSC(timer) = (io_timers[timer].clock_freq / 1000000) - 1;
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rARR(timer) = timer_freq[timer] * 1000000 / rate;
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/* configure the timer to update at the desired rate */
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rARR(timer) = BOARD_PWM_FREQ / rate;
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/* generate an update event; reloads the counter and all registers */
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rEGR(timer) = GTIM_EGR_UG;
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@ -392,30 +452,56 @@ static int timer_set_rate(unsigned timer, unsigned rate)
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return 0;
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}
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void io_timer_set_oneshot_mode(unsigned timer)
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{
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/* This timer MUST run at 8MHz */
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timer_freq[timer] = 8;
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rPSC(timer) = (io_timers[timer].clock_freq / 8000000) - 1;
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// set rate to 125Hz (lowest possible at 8MHz is ~122Hz)
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// io_timer_set_ccr() must be called at > 125Hz to minimize latency
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rARR(timer) = timer_freq[timer] * 1000000 / 125;
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static inline void io_timer_set_oneshot_mode(unsigned timer)
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{
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/* Ideally, we would want per channel One pulse mode in HW
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* Alas OPE stops the Timer not the channel
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* todo:We can do this in an ISR later
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* But since we do not have that
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* We try to get the longest rate we can.
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* On 16 bit timers this is 8.1 Ms.
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* On 32 but timers this is 536870.912
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*/
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rARR(timer) = 0xffffffff;
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rPSC(timer) = (io_timers[timer].clock_freq / BOARD_ONSHOT_FREQ) - 1;
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rEGR(timer) = GTIM_EGR_UG;
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}
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uint8_t io_timer_get_freq(unsigned timer)
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static inline void io_timer_set_PWM_mode(unsigned timer)
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{
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return timer_freq[timer];
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rPSC(timer) = (io_timers[timer].clock_freq / BOARD_PWM_FREQ) - 1;
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}
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void io_timer_force_update()
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void io_timer_trigger(void)
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{
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for (int i = 0; i < MAX_IO_TIMERS; i++) {
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if (timer_freq[i] == 8) {
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// force update of channel compare register
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rEGR(i) |= GTIM_EGR_UG;
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int oneshots = io_timer_get_mode_channels(IOTimerChanMode_OneShot);
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uint32_t action_cache[MAX_IO_TIMERS] = {0};
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int actions = 0;
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/* Pre-calculate the list of timers to Trigger */
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for (int timer = 0; timer < MAX_IO_TIMERS; timer++) {
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if (validate_timer_index(timer) == 0) {
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int channels = get_timer_channels(timer);
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if (oneshots & channels) {
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action_cache[actions++] = io_timers[timer].base;
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}
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}
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}
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/* Now do them all wit the shortest delay in between */
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irqstate_t flags = px4_enter_critical_section();
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for (actions = 0; action_cache[actions] != 0 && actions < MAX_IO_TIMERS; actions++) {
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_REG32(action_cache[actions], STM32_GTIM_EGR_OFFSET) |= GTIM_EGR_UG;
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}
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px4_leave_critical_section(flags);
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}
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int io_timer_init_timer(unsigned timer)
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@ -456,6 +542,8 @@ int io_timer_init_timer(unsigned timer)
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rBDTR(timer) = ATIM_BDTR_MOE;
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}
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io_timer_set_PWM_mode(timer);
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/*
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* Note we do the Standard PWM Out init here
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* default to updating at 50Hz
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@ -481,20 +569,53 @@ int io_timer_init_timer(unsigned timer)
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int io_timer_set_rate(unsigned timer, unsigned rate)
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{
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/* Gather the channel bits that belong to the timer */
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int rv = EBUSY;
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/* Get the channel bits that belong to the timer */
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uint32_t channels = get_timer_channels(timer);
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/* Check ownership of PWM out */
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/* Check that all channels are either in PWM or Oneshot */
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if ((channels & channel_allocations[IOTimerChanMode_PWMOut]) != 0) {
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if ((channels & (channel_allocations[IOTimerChanMode_PWMOut] | channel_allocations[IOTimerChanMode_OneShot])) ==
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channels) {
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/* Change only a timer that is owned by pwm */
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/* Change only a timer that is owned by pwm or one shot */
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timer_set_rate(timer, rate);
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/* Request to use OneShot ?*/
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if (rate == 0) {
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/* Request to use OneShot
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*
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* We are here because ALL these channels were either PWM or Oneshot
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* Now they need to be Oneshot
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*/
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/* Did the allocation change */
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if (reallocate_channel_resources(channels, IOTimerChanMode_PWMOut, IOTimerChanMode_OneShot)) {
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io_timer_set_oneshot_mode(timer);
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}
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} else {
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/* Request to use PWM
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*
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* We are here because ALL these channels were either PWM or Oneshot
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* Now they need to be PWM
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*/
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if (reallocate_channel_resources(channels, IOTimerChanMode_OneShot, IOTimerChanMode_PWMOut)) {
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rPSC(timer) = (io_timers[timer].clock_freq / BOARD_PWM_FREQ) - 1;
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}
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timer_set_rate(timer, rate);
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}
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rv = OK;
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}
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return 0;
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return rv;
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}
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int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode,
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@ -504,18 +625,15 @@ int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode,
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uint32_t gpio = 0;
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uint32_t clearbits = CCMR_C1_RESET;
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uint32_t setbits = CCMR_C1_CAPTURE_INIT;
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uint32_t ccer_setbits = GTIM_CCER_CC1E;
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uint32_t ccer_setbits = CCER_C1_INIT;
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uint32_t dier_setbits = GTIM_DIER_CC1IE;
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/* figure out the GPIO config first */
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switch (mode) {
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case IOTimerChanMode_OneShot:
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io_timer_set_oneshot_mode(timer_io_channels[channel].timer_index);
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// intentional fallthrough
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case IOTimerChanMode_OneShot:
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case IOTimerChanMode_PWMOut:
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ccer_setbits = 0;
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dier_setbits = 0;
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@ -620,7 +738,7 @@ int io_timer_set_enable(bool state, io_timer_channel_mode_t mode, io_timer_chann
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memset(action_cache, 0, sizeof(action_cache));
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uint32_t dier_bit = state ? GTIM_DIER_CC1IE : 0;
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uint32_t ccer_bit = state ? GTIM_CCER_CC1E : 0;
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uint32_t ccer_bit = state ? CCER_C1_INIT : 0;
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switch (mode) {
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case IOTimerChanMode_NotUsed:
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@ -663,12 +781,12 @@ int io_timer_set_enable(bool state, io_timer_channel_mode_t mode, io_timer_chann
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uint32_t shifts = timer_io_channels[chan_index].timer_channel - 1;
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uint32_t timer = channels_timer(chan_index);
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action_cache[timer].base = io_timers[timer].base;
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action_cache[timer].ccer_clearbits |= GTIM_CCER_CC1E << (shifts * CCER_C1_NUM_BITS);
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action_cache[timer].ccer_clearbits |= CCER_C1_INIT << (shifts * CCER_C1_NUM_BITS);
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action_cache[timer].ccer_setbits |= ccer_bit << (shifts * CCER_C1_NUM_BITS);
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action_cache[timer].dier_clearbits |= GTIM_DIER_CC1IE << shifts;
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action_cache[timer].dier_setbits |= dier_bit << shifts;
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if ((state && mode == IOTimerChanMode_PWMOut) || (state && mode == IOTimerChanMode_OneShot)) {
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if ((state && (mode == IOTimerChanMode_PWMOut || mode == IOTimerChanMode_OneShot))) {
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action_cache[timer].gpio[shifts] = timer_io_channels[chan_index].gpio_out;
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}
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}
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@ -720,10 +838,10 @@ int io_timer_set_enable(bool state, io_timer_channel_mode_t mode, io_timer_chann
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int io_timer_set_ccr(unsigned channel, uint16_t value)
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{
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int rv = io_timer_validate_channel_index(channel);
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int mode = io_timer_get_channel_mode(channel);
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if (rv == 0) {
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if ((io_timer_get_channel_mode(channel) != IOTimerChanMode_PWMOut) &&
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(io_timer_get_channel_mode(channel) != IOTimerChanMode_OneShot)) {
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if ((mode != IOTimerChanMode_PWMOut) && (mode != IOTimerChanMode_OneShot)) {
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rv = -EIO;
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@ -731,17 +849,6 @@ int io_timer_set_ccr(unsigned channel, uint16_t value)
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/* configure the channel */
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// this hack won't work correctly in oneshot mode; would be OK if it just inverted the output
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#ifdef BOARD_PWM_DRIVE_ACTIVE_LOW
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unsigned period = rARR(channels_timer(channel));
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value = period - value;
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#endif
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if (value > 0) {
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value--;
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}
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// write PWM value into CCR preload register
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REG(channels_timer(channel), timer_io_channels[channel].ccr_offset) = value;
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}
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}
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@ -753,16 +860,12 @@ uint16_t io_channel_get_ccr(unsigned channel)
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{
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uint16_t value = 0;
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if (io_timer_validate_channel_index(channel) == 0 &&
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((io_timer_get_channel_mode(channel) == IOTimerChanMode_PWMOut) ||
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(io_timer_get_channel_mode(channel) == IOTimerChanMode_OneShot))) {
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value = REG(channels_timer(channel), timer_io_channels[channel].ccr_offset) + 1;
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#ifdef BOARD_PWM_DRIVE_ACTIVE_LOW
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unsigned period = rARR(channels_timer(channel));
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value = period - value;
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#endif
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if (io_timer_validate_channel_index(channel) == 0) {
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int mode = io_timer_get_channel_mode(channel);
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if ((mode == IOTimerChanMode_PWMOut) || (mode == IOTimerChanMode_OneShot)) {
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value = REG(channels_timer(channel), timer_io_channels[channel].ccr_offset);
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}
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}
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return value;
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