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https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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87 Commits
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| daa89ba30a |
@@ -47,7 +47,7 @@ pipeline {
|
||||
"ark_fmu-v6x_bootloader",
|
||||
"ark_fmu-v6x_default",
|
||||
"ark_pi6x_bootloader",
|
||||
"ark_pi6x_default"
|
||||
"ark_pi6x_default",
|
||||
"atl_mantis-edu_default",
|
||||
"av_x-v1_default",
|
||||
"bitcraze_crazyflie21_default",
|
||||
|
||||
Vendored
+6
-6
@@ -151,16 +151,16 @@ CONFIG:
|
||||
buildType: MinSizeRel
|
||||
settings:
|
||||
CONFIG: ark_can-rtk-gps_canbootloader
|
||||
ark_septentrio_gps_default:
|
||||
short: ark_septentrio_gps_default
|
||||
ark_septentrio-gps_default:
|
||||
short: ark_septentrio-gps_default
|
||||
buildType: MinSizeRel
|
||||
settings:
|
||||
CONFIG: ark_septentrio_gps_default
|
||||
ark_septentrio_gps_canbootloader:
|
||||
short: ark_septentrio_gps_canbootloader
|
||||
CONFIG: ark_septentrio-gps_default
|
||||
ark_septentrio-gps_canbootloader:
|
||||
short: ark_septentrio-gps_canbootloader
|
||||
buildType: MinSizeRel
|
||||
settings:
|
||||
CONFIG: ark_septentrio_gps_canbootloader
|
||||
CONFIG: ark_septentrio-gps_canbootloader
|
||||
ark_cannode_default:
|
||||
short: ark_cannode_default
|
||||
buildType: MinSizeRel
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
############################################################################
|
||||
#
|
||||
# Copyright (c) 2015 - 2020 PX4 Development Team. All rights reserved.
|
||||
# Copyright (c) 2015 - 2024 PX4 Development Team. All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
@@ -323,7 +323,32 @@ px4io_update:
|
||||
cp build/cubepilot_io-v2_default/cubepilot_io-v2_default.bin boards/cubepilot/cubeyellow/extras/cubepilot_io-v2_default.bin
|
||||
git status
|
||||
|
||||
bootloaders_update: ark_fmu-v6x_bootloader cuav_nora_bootloader cuav_x7pro_bootloader cubepilot_cubeorange_bootloader holybro_durandal-v1_bootloader holybro_kakuteh7_bootloader matek_h743_bootloader matek_h743-mini_bootloader matek_h743-slim_bootloader modalai_fc-v2_bootloader mro_ctrl-zero-classic_bootloader mro_ctrl-zero-h7_bootloader mro_ctrl-zero-h7-oem_bootloader mro_pixracerpro_bootloader px4_fmu-v6c_bootloader px4_fmu-v6u_bootloader px4_fmu-v6x_bootloader
|
||||
bootloaders_update: \
|
||||
ark_fmu-v6x_bootloader \
|
||||
ark_pi6x_bootloader \
|
||||
cuav_nora_bootloader \
|
||||
cuav_x7pro_bootloader \
|
||||
cubepilot_cubeorange_bootloader \
|
||||
cubepilot_cubeorangeplus_bootloader \
|
||||
hkust_nxt-dual_bootloader \
|
||||
hkust_nxt-v1_bootloader \
|
||||
holybro_durandal-v1_bootloader \
|
||||
holybro_kakuteh7_bootloader \
|
||||
holybro_kakuteh7mini_bootloader \
|
||||
holybro_kakuteh7v2_bootloader \
|
||||
matek_h743_bootloader \
|
||||
matek_h743-mini_bootloader \
|
||||
matek_h743-slim_bootloader \
|
||||
modalai_fc-v2_bootloader \
|
||||
mro_ctrl-zero-classic_bootloader \
|
||||
mro_ctrl-zero-h7_bootloader \
|
||||
mro_ctrl-zero-h7-oem_bootloader \
|
||||
mro_pixracerpro_bootloader \
|
||||
px4_fmu-v6c_bootloader \
|
||||
px4_fmu-v6u_bootloader \
|
||||
px4_fmu-v6x_bootloader \
|
||||
px4_fmu-v6xrt_bootloader \
|
||||
siyi_n7_bootloader
|
||||
git status
|
||||
|
||||
.PHONY: coverity_scan
|
||||
|
||||
@@ -24,7 +24,6 @@ param set-default FW_RR_P 0.085
|
||||
param set-default FW_W_EN 1
|
||||
|
||||
param set-default MIS_TAKEOFF_ALT 20
|
||||
param set-default MIS_DIST_1WP 2500
|
||||
|
||||
param set-default NAV_ACC_RAD 15
|
||||
param set-default NAV_DLL_ACT 2
|
||||
|
||||
@@ -24,7 +24,6 @@ param set-default FW_RR_P 0.085
|
||||
param set-default FW_W_EN 1
|
||||
|
||||
param set-default MIS_TAKEOFF_ALT 20
|
||||
param set-default MIS_DIST_1WP 2500
|
||||
|
||||
param set-default NAV_ACC_RAD 15
|
||||
param set-default NAV_DLL_ACT 2
|
||||
|
||||
@@ -24,7 +24,6 @@ param set-default FW_RR_P 0.085
|
||||
param set-default FW_W_EN 1
|
||||
|
||||
param set-default MIS_TAKEOFF_ALT 20
|
||||
param set-default MIS_DIST_1WP 2500
|
||||
|
||||
param set-default NAV_ACC_RAD 15
|
||||
param set-default NAV_DLL_ACT 2
|
||||
|
||||
@@ -25,7 +25,6 @@ param set-default FW_W_EN 1
|
||||
|
||||
param set-default MIS_LTRMIN_ALT 30
|
||||
param set-default MIS_TAKEOFF_ALT 20
|
||||
param set-default MIS_DIST_1WP 2500
|
||||
|
||||
param set-default NAV_ACC_RAD 15
|
||||
param set-default NAV_DLL_ACT 2
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# @name Monocopter SITL
|
||||
#
|
||||
|
||||
. ${R}etc/init.d/rc.fw_defaults
|
||||
|
||||
param set-default FW_LND_ANG 8
|
||||
|
||||
param set-default NPFG_PERIOD 12
|
||||
|
||||
param set-default FW_PR_P 0.9
|
||||
param set-default FW_PR_FF 0.5
|
||||
param set-default FW_PR_I 0.5
|
||||
param set-default TRIM_PITCH -0.15
|
||||
|
||||
param set-default FW_PSP_OFF 2
|
||||
param set-default FW_P_LIM_MIN -15
|
||||
|
||||
param set-default FW_RR_FF 0.5
|
||||
param set-default FW_RR_P 0.3
|
||||
param set-default FW_RR_I 0.5
|
||||
|
||||
param set-default FW_YR_FF 0.5
|
||||
param set-default FW_YR_P 0.6
|
||||
param set-default FW_YR_I 0.5
|
||||
|
||||
param set-default FW_SPOILERS_LND 0.4
|
||||
|
||||
param set-default FW_THR_MAX 0.6
|
||||
param set-default FW_THR_MIN 0.05
|
||||
param set-default FW_THR_TRIM 0.25
|
||||
|
||||
param set-default FW_T_CLMB_MAX 8
|
||||
param set-default FW_T_SINK_MAX 2.7
|
||||
param set-default FW_T_SINK_MIN 2.2
|
||||
|
||||
param set-default FW_W_EN 1
|
||||
|
||||
param set-default MIS_TAKEOFF_ALT 30
|
||||
|
||||
param set-default NAV_ACC_RAD 15
|
||||
param set-default NAV_DLL_ACT 2
|
||||
|
||||
param set-default RWTO_TKOFF 1
|
||||
|
||||
param set-default CA_AIRFRAME 1
|
||||
|
||||
param set-default CA_ROTOR_COUNT 1
|
||||
param set-default CA_ROTOR0_PX 0.3
|
||||
|
||||
param set-default CA_SV_CS_COUNT 6
|
||||
param set-default CA_SV_CS0_TRQ_R -0.5
|
||||
param set-default CA_SV_CS0_TYPE 1
|
||||
param set-default CA_SV_CS1_TRQ_R 0.5
|
||||
param set-default CA_SV_CS1_TYPE 2
|
||||
param set-default CA_SV_CS2_TRQ_P 1
|
||||
param set-default CA_SV_CS2_TYPE 3
|
||||
param set-default CA_SV_CS3_TRQ_Y 1
|
||||
param set-default CA_SV_CS3_TYPE 4
|
||||
param set-default CA_SV_CS4_TYPE 9
|
||||
param set-default CA_SV_CS5_TYPE 10
|
||||
param set-default PWM_MAIN_FUNC3 204
|
||||
param set-default PWM_MAIN_FUNC4 205
|
||||
param set-default PWM_MAIN_FUNC5 101
|
||||
param set-default PWM_MAIN_FUNC6 201
|
||||
param set-default PWM_MAIN_FUNC7 202
|
||||
param set-default PWM_MAIN_FUNC8 203
|
||||
param set-default PWM_MAIN_FUNC9 206
|
||||
param set-default PWM_MAIN_REV 256
|
||||
@@ -52,3 +52,4 @@ param set-default SIM_GZ_EC_MAX3 1000
|
||||
param set-default SIM_GZ_EC_MAX4 1000
|
||||
|
||||
param set-default MPC_THR_HOVER 0.60
|
||||
param set-default NAV_DLL_ACT 2
|
||||
|
||||
@@ -101,8 +101,9 @@ param set-default MPC_XY_VEL_I_ACC 4
|
||||
param set-default MPC_XY_VEL_D_ACC 0.1
|
||||
|
||||
param set-default NAV_ACC_RAD 5
|
||||
param set-default NAV_DLL_ACT 2
|
||||
|
||||
param set-default VT_FWD_THRUST_EN 4
|
||||
param set-default VT_F_TRANS_THR 0.75
|
||||
param set-default VT_F_TRANS_THR 0.3
|
||||
param set-default VT_TYPE 2
|
||||
param set-default FD_ESCS_EN 0
|
||||
|
||||
@@ -132,3 +132,5 @@ param set-default SIM_GZ_EC_MAX1 1100
|
||||
param set-default SIM_GZ_EC_MAX2 1100
|
||||
param set-default SIM_GZ_EC_MAX3 1100
|
||||
param set-default SIM_GZ_EC_MAX4 1100
|
||||
|
||||
param set-default NAV_DLL_ACT 2
|
||||
|
||||
@@ -67,6 +67,7 @@ px4_add_romfs_files(
|
||||
1061_gazebo-classic_r1_rover
|
||||
1062_flightgear_tf-r1
|
||||
1070_gazebo-classic_boat
|
||||
1090_gazebo-classic_monocopter
|
||||
|
||||
2507_gazebo-classic_cloudship
|
||||
|
||||
|
||||
@@ -84,6 +84,13 @@ if(CONFIG_MODULES_DIFFERENTIAL_DRIVE)
|
||||
)
|
||||
endif()
|
||||
|
||||
if(CONFIG_MODULES_ROVER_ACKERMANN)
|
||||
px4_add_romfs_files(
|
||||
rc.rover_ackermann_apps
|
||||
rc.rover_ackermann_defaults
|
||||
)
|
||||
endif()
|
||||
|
||||
if(CONFIG_MODULES_UUV_ATT_CONTROL)
|
||||
px4_add_romfs_files(
|
||||
rc.uuv_apps
|
||||
|
||||
@@ -66,7 +66,6 @@ param set-default MC_PITCHRATE_I 0.05
|
||||
param set-default MC_YAWRATE_MAX 20
|
||||
param set-default MC_AIRMODE 1
|
||||
|
||||
param set-default MIS_DIST_1WP 100
|
||||
param set-default MIS_TAKEOFF_ALT 15
|
||||
|
||||
param set-default MPC_XY_P 0.8
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# @name Generic ackermann rover
|
||||
#
|
||||
# @type Rover
|
||||
# @class Rover
|
||||
#
|
||||
# @board px4_fmu-v2 exclude
|
||||
# @board bitcraze_crazyflie exclude
|
||||
#
|
||||
|
||||
. ${R}etc/init.d/rc.rover_ackermann_defaults
|
||||
@@ -149,6 +149,12 @@ if(CONFIG_MODULES_DIFFERENTIAL_DRIVE)
|
||||
)
|
||||
endif()
|
||||
|
||||
if(CONFIG_MODULES_ROVER_ACKERMANN)
|
||||
px4_add_romfs_files(
|
||||
50010_ackermann_rover_generic
|
||||
)
|
||||
endif()
|
||||
|
||||
if(CONFIG_MODULES_UUV_ATT_CONTROL)
|
||||
px4_add_romfs_files(
|
||||
# [60000, 61000] (Unmanned) Underwater Robots
|
||||
|
||||
@@ -0,0 +1,11 @@
|
||||
#!/bin/sh
|
||||
# Standard apps for a ackermann drive rover.
|
||||
|
||||
# Start the attitude and position estimator.
|
||||
ekf2 start &
|
||||
|
||||
# Start rover ackermann drive controller.
|
||||
rover_ackermann start
|
||||
|
||||
# Start Land Detector.
|
||||
land_detector start rover
|
||||
@@ -0,0 +1,13 @@
|
||||
#!/bin/sh
|
||||
# Ackermann rover parameters.
|
||||
|
||||
set VEHICLE_TYPE rover_ackermann
|
||||
param set-default MAV_TYPE 10 # MAV_TYPE_GROUND_ROVER
|
||||
param set-default CA_AIRFRAME 5 # Rover (Ackermann)
|
||||
param set-default CA_R_REV 1 # Motor is assumed to be reversible
|
||||
param set-default EKF2_MAG_TYPE 1 # make sure magnetometer is fused even when not flying
|
||||
param set-default EKF2_GBIAS_INIT 0.01
|
||||
param set-default EKF2_ANGERR_INIT 0.01
|
||||
param set-default NAV_ACC_RAD 0.5 # Waypoint acceptance radius
|
||||
param set-default NAV_RCL_ACT 6 # Disarm on manual control loss
|
||||
param set-default COM_FAIL_ACT_T 1 # Delay before failsafe after rc loss
|
||||
@@ -41,6 +41,15 @@ then
|
||||
. ${R}etc/init.d/rc.rover_differential_apps
|
||||
fi
|
||||
|
||||
#
|
||||
# Ackermann Rover setup.
|
||||
#
|
||||
if [ $VEHICLE_TYPE = rover_ackermann ]
|
||||
then
|
||||
# Start ackermann drive rover apps.
|
||||
. ${R}etc/init.d/rc.rover_ackermann_apps
|
||||
fi
|
||||
|
||||
#
|
||||
# VTOL setup.
|
||||
#
|
||||
|
||||
@@ -123,6 +123,13 @@ else
|
||||
set PARAM_FILE /fs/mtd_params
|
||||
fi
|
||||
|
||||
# Check if /fs/mtd_params is a valid BSON file
|
||||
if ! bsondump docsize /fs/mtd_caldata
|
||||
then
|
||||
echo "New /fs/mtd_caldata size is:"
|
||||
bsondump docsize /fs/mtd_caldata
|
||||
fi
|
||||
|
||||
#
|
||||
# Load parameters.
|
||||
#
|
||||
|
||||
@@ -54,12 +54,21 @@ def extract_timer_from_channel(line, timer_names):
|
||||
|
||||
return None
|
||||
|
||||
def imxrt_is_dshot(line):
|
||||
|
||||
# NXP FlexPWM format format: initIOPWM(PWM::FlexPWM2),
|
||||
search = re.search('(initIOPWMDshot)', line, re.IGNORECASE)
|
||||
if search:
|
||||
return True
|
||||
|
||||
return False
|
||||
|
||||
def get_timer_groups(timer_config_file, verbose=False):
|
||||
with open(timer_config_file, 'r') as f:
|
||||
timer_config = f.read()
|
||||
|
||||
# timers
|
||||
dshot_support = {} # key: timer
|
||||
dshot_support = {str(i): False for i in range(16)}
|
||||
timers_start_marker = 'io_timers_t io_timers'
|
||||
timers_start = timer_config.find(timers_start_marker)
|
||||
if timers_start == -1:
|
||||
@@ -78,10 +87,9 @@ def get_timer_groups(timer_config_file, verbose=False):
|
||||
if timer_type == 'imxrt':
|
||||
if verbose: print('imxrt timer found')
|
||||
timer_names.append(timer)
|
||||
if imxrt_is_dshot(line):
|
||||
dshot_support[str(len(timers))] = True
|
||||
timers.append(str(len(timers)))
|
||||
dshot_support = {str(i): False for i in range(16)}
|
||||
for i in range(8): # First 8 channels support dshot
|
||||
dshot_support[str(i)] = True
|
||||
elif timer:
|
||||
if verbose: print('found timer def: {:}'.format(timer))
|
||||
dshot_support[timer] = 'DMA' in line
|
||||
|
||||
+1
-1
@@ -95,7 +95,7 @@ if [[ $INSTALL_SIM == "true" ]]; then
|
||||
|
||||
# java (jmavsim)
|
||||
sudo pacman -S --noconfirm --needed \
|
||||
ant
|
||||
ant \
|
||||
;
|
||||
|
||||
# Gazebo setup
|
||||
|
||||
@@ -1,5 +1,4 @@
|
||||
argcomplete
|
||||
argparse>=1.2
|
||||
cerberus
|
||||
coverage
|
||||
empy==3.3.4
|
||||
|
||||
+16
-1
@@ -66,6 +66,8 @@ elif [[ "${UBUNTU_RELEASE}" == "20.04" ]]; then
|
||||
echo "Ubuntu 20.04"
|
||||
elif [[ "${UBUNTU_RELEASE}" == "22.04" ]]; then
|
||||
echo "Ubuntu 22.04"
|
||||
elif [[ "${UBUNTU_RELEASE}" == "21.3" ]]; then
|
||||
echo "Linux Mint 21.3"
|
||||
fi
|
||||
|
||||
|
||||
@@ -146,7 +148,7 @@ if [[ $INSTALL_NUTTX == "true" ]]; then
|
||||
util-linux \
|
||||
vim-common \
|
||||
;
|
||||
if [[ "${UBUNTU_RELEASE}" == "20.04" || "${UBUNTU_RELEASE}" == "22.04" ]]; then
|
||||
if [[ "${UBUNTU_RELEASE}" == "20.04" || "${UBUNTU_RELEASE}" == "22.04" || "${UBUNTU_RELEASE}" == "21.3" ]]; then
|
||||
sudo DEBIAN_FRONTEND=noninteractive apt-get -y --quiet --no-install-recommends install \
|
||||
kconfig-frontends \
|
||||
;
|
||||
@@ -205,6 +207,8 @@ if [[ $INSTALL_SIM == "true" ]]; then
|
||||
java_version=13
|
||||
elif [[ "${UBUNTU_RELEASE}" == "22.04" ]]; then
|
||||
java_version=11
|
||||
elif [[ "${UBUNTU_RELEASE}" == "21.3" ]]; then
|
||||
java_version=11
|
||||
else
|
||||
java_version=14
|
||||
fi
|
||||
@@ -228,6 +232,17 @@ if [[ $INSTALL_SIM == "true" ]]; then
|
||||
echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/pkgs-osrf-archive-keyring.gpg] http://packages.osrfoundation.org/gazebo/ubuntu-stable $(lsb_release -cs) main" | sudo tee /etc/apt/sources.list.d/gazebo-stable.list > /dev/null
|
||||
sudo apt-get update -y --quiet
|
||||
|
||||
# Install Gazebo
|
||||
gazebo_packages="gz-garden"
|
||||
elif [[ "${UBUNTU_RELEASE}" == "21.3" ]]; then
|
||||
echo "Gazebo (Garden) will be installed"
|
||||
echo "Earlier versions will be removed"
|
||||
# Add Gazebo binary repository
|
||||
sudo wget https://packages.osrfoundation.org/gazebo.gpg -O /usr/share/keyrings/pkgs-osrf-archive-keyring.gpg
|
||||
echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/pkgs-osrf-archive-keyring.gpg] http://packages.osrfoundation.org/gazebo/ubuntu-stable jammy main" | sudo tee /etc/apt/sources.list.d/gazebo-stable.list > /dev/null
|
||||
|
||||
sudo apt-get update -y --quiet
|
||||
|
||||
# Install Gazebo
|
||||
gazebo_packages="gz-garden"
|
||||
else
|
||||
|
||||
Submodule Tools/simulation/gazebo-classic/sitl_gazebo-classic updated: da7206e057...cc4aed2096
Binary file not shown.
@@ -147,8 +147,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DHCPC=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_MONITOR=y
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
|
||||
Binary file not shown.
@@ -32,19 +32,10 @@ then
|
||||
param set-default SENS_TEMP_ID 2490378
|
||||
fi
|
||||
|
||||
param set-default EKF2_BARO_DELAY 39
|
||||
param set-default EKF2_BARO_NOISE 0.9
|
||||
param set-default EKF2_HGT_REF 0
|
||||
param set-default EKF2_MAG_DELAY 60
|
||||
param set-default EKF2_MAG_NOISE 0.06
|
||||
param set-default EKF2_MULTI_IMU 2
|
||||
param set-default EKF2_OF_CTRL 1
|
||||
param set-default EKF2_OF_DELAY 28
|
||||
param set-default EKF2_OF_N_MIN 0.05
|
||||
param set-default EKF2_RNG_A_HMAX 25
|
||||
param set-default EKF2_RNG_DELAY 105
|
||||
param set-default EKF2_RNG_NOISE 0.03
|
||||
param set-default EKF2_RNG_QLTY_T 0.1
|
||||
param set-default EKF2_RNG_SFE 0.03
|
||||
|
||||
param set-default SENS_FLOW_RATE 150
|
||||
|
||||
@@ -47,7 +47,7 @@
|
||||
#define GPIO_BTN_SAFETY /* PB15 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTB|GPIO_PIN15)
|
||||
|
||||
/* Safety LED */
|
||||
#define GPIO_LED_SAFETY /* PA1 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_LED_SAFETY /* PA1 */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
|
||||
|
||||
/* Tone alarm output. */
|
||||
#define TONE_ALARM_TIMER 2 /* timer 2 */
|
||||
|
||||
@@ -139,8 +139,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DHCPC=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
CONFIG_NETUTILS_TELNETD=y
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -97,9 +97,9 @@
|
||||
#define INTERFACE_USART_CONFIG "/dev/ttyS5,57600"
|
||||
#define BOOT_DELAY_ADDRESS 0x000001a0
|
||||
#define BOARD_TYPE 1013
|
||||
#define _FLASH_KBYTES (*(uint32_t *)0x1FF1E880)
|
||||
#define BOARD_FLASH_SECTORS (15)
|
||||
#define BOARD_FLASH_SIZE (_FLASH_KBYTES * 1024)
|
||||
#define BOARD_FLASH_SECTORS (14)
|
||||
#define BOARD_FLASH_SIZE (16 * 128 * 1024)
|
||||
#define APP_RESERVATION_SIZE (1 * 128 * 1024)
|
||||
|
||||
#define OSC_FREQ 16
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -15,7 +15,7 @@ param set-default SYS_AUTOSTART 4050
|
||||
param set-default SYS_HAS_MAG 0
|
||||
|
||||
# enable gravity fusion
|
||||
param set-default EKF2_IMU_CONTROL 7
|
||||
param set-default EKF2_IMU_CTRL 7
|
||||
|
||||
# the startup tune is not great on a binary output buzzer, so disable it
|
||||
param set-default CBRK_BUZZER 782090
|
||||
|
||||
Binary file not shown.
@@ -25,7 +25,7 @@ param set-default SYS_AUTOSTART 4050
|
||||
# use EKF2 without mag
|
||||
param set-default SYS_HAS_MAG 0
|
||||
# and enable gravity fusion
|
||||
param set-default EKF2_IMU_CONTROL 7
|
||||
param set-default EKF2_IMU_CTRL 7
|
||||
|
||||
# the startup tune is not great on a binary output buzzer, so disable it
|
||||
param set-default CBRK_BUZZER 782090
|
||||
|
||||
Binary file not shown.
@@ -25,7 +25,7 @@ param set-default SYS_AUTOSTART 4050
|
||||
# use EKF2 without mag
|
||||
param set-default SYS_HAS_MAG 0
|
||||
# and enable gravity fusion
|
||||
param set-default EKF2_IMU_CONTROL 7
|
||||
param set-default EKF2_IMU_CTRL 7
|
||||
|
||||
# the startup tune is not great on a binary output buzzer, so disable it
|
||||
param set-default CBRK_BUZZER 782090
|
||||
|
||||
Binary file not shown.
@@ -25,7 +25,7 @@ param set-default SYS_AUTOSTART 4050
|
||||
# use EKF2 without mag
|
||||
param set-default SYS_HAS_MAG 0
|
||||
# and enable gravity fusion
|
||||
param set-default EKF2_IMU_CONTROL 7
|
||||
param set-default EKF2_IMU_CTRL 7
|
||||
|
||||
# the startup tune is not great on a binary output buzzer, so disable it
|
||||
param set-default CBRK_BUZZER 782090
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -158,8 +158,8 @@ CONFIG_NETDEV_LATEINIT=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DHCPC=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_MONITOR=y
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
|
||||
@@ -158,8 +158,8 @@ CONFIG_NETDEV_LATEINIT=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DHCPC=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_MONITOR=y
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
|
||||
@@ -19,3 +19,4 @@ CONFIG_MODULES_VTOL_ATT_CONTROL=n
|
||||
CONFIG_EKF2_AUX_GLOBAL_POSITION=y
|
||||
# CONFIG_EKF2_WIND is not set
|
||||
CONFIG_MODULES_DIFFERENTIAL_DRIVE=y
|
||||
CONFIG_MODULES_ROVER_ACKERMANN=y
|
||||
|
||||
@@ -3,23 +3,25 @@
|
||||
# board specific defaults
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
# Mavlink ethernet (CFG 1000)
|
||||
param set-default MAV_2_CONFIG 1000
|
||||
param set-default MAV_2_BROADCAST 1
|
||||
param set-default MAV_2_MODE 0
|
||||
param set-default MAV_2_RADIO_CTL 0
|
||||
param set-default MAV_2_RATE 100000
|
||||
param set-default MAV_2_REMOTE_PRT 14550
|
||||
param set-default MAV_2_UDP_PRT 14550
|
||||
|
||||
param set-default SENS_EN_INA238 0
|
||||
param set-default SENS_EN_INA228 0
|
||||
param set-default SENS_EN_INA226 1
|
||||
|
||||
if ver hwbasecmp 008 009 00a 010 011
|
||||
then
|
||||
# Skynode: use the "custom participant" config for uxrce_dds_client
|
||||
# Skynode: use the "custom participant", IP=10.41.10.1 config for uxrce_dds_client
|
||||
param set-default UXRCE_DDS_PTCFG 2
|
||||
param set-default UXRCE_DDS_AG_IP 170461697
|
||||
param set-default UXRCE_DDS_CFG 1000
|
||||
else
|
||||
# Mavlink ethernet (CFG 1000)
|
||||
param set-default MAV_2_CONFIG 1000
|
||||
param set-default MAV_2_BROADCAST 1
|
||||
param set-default MAV_2_MODE 0
|
||||
param set-default MAV_2_RADIO_CTL 0
|
||||
param set-default MAV_2_RATE 100000
|
||||
param set-default MAV_2_REMOTE_PRT 14550
|
||||
param set-default MAV_2_UDP_PRT 14550
|
||||
fi
|
||||
|
||||
safety_button start
|
||||
|
||||
@@ -143,8 +143,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DHCPC=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_MONITOR=y
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
|
||||
@@ -143,8 +143,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DHCPC=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
CONFIG_NETUTILS_TELNETD=y
|
||||
|
||||
@@ -14,3 +14,5 @@ CONFIG_MODULES_MC_RATE_CONTROL=n
|
||||
CONFIG_MODULES_VTOL_ATT_CONTROL=n
|
||||
CONFIG_EKF2_AUX_GLOBAL_POSITION=y
|
||||
# CONFIG_EKF2_WIND is not set
|
||||
CONFIG_MODULES_DIFFERENTIAL_DRIVE=y
|
||||
CONFIG_MODULES_ROVER_ACKERMANN=y
|
||||
|
||||
@@ -8,7 +8,7 @@ CONFIG_DRIVERS_IMU_ANALOG_DEVICES_ADIS16448=n
|
||||
CONFIG_DRIVERS_IRLOCK=n
|
||||
CONFIG_MODULES_FW_AUTOTUNE_ATTITUDE_CONTROL=n
|
||||
CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=n
|
||||
CONFIG_MODULES_ROVER_POS_CONTROL=n
|
||||
CONFIG_MODULES_PAYLOAD_DELIVERER=n
|
||||
CONFIG_MODULES_SIMULATION_SIMULATOR_SIH=n
|
||||
CONFIG_BOARD_TESTING=y
|
||||
CONFIG_DRIVERS_DISTANCE_SENSOR_LIGHTWARE_LASER_SERIAL=y
|
||||
|
||||
@@ -48,7 +48,6 @@ CONFIG_MODULES_FW_POS_CONTROL=y
|
||||
CONFIG_MODULES_FW_RATE_CONTROL=y
|
||||
CONFIG_MODULES_GIMBAL=y
|
||||
CONFIG_MODULES_GYRO_CALIBRATION=y
|
||||
CONFIG_MODULES_GYRO_FFT=y
|
||||
CONFIG_MODULES_LAND_DETECTOR=y
|
||||
CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
|
||||
CONFIG_MODULES_LOAD_MON=y
|
||||
|
||||
Binary file not shown.
@@ -14,3 +14,4 @@ CONFIG_MODULES_VTOL_ATT_CONTROL=n
|
||||
CONFIG_EKF2_AUX_GLOBAL_POSITION=y
|
||||
# CONFIG_EKF2_WIND is not set
|
||||
CONFIG_MODULES_DIFFERENTIAL_DRIVE=y
|
||||
CONFIG_MODULES_ROVER_ACKERMANN=y
|
||||
|
||||
Binary file not shown.
@@ -14,3 +14,4 @@ CONFIG_MODULES_VTOL_ATT_CONTROL=n
|
||||
CONFIG_EKF2_AUX_GLOBAL_POSITION=y
|
||||
# CONFIG_EKF2_WIND is not set
|
||||
CONFIG_MODULES_DIFFERENTIAL_DRIVE=y
|
||||
CONFIG_MODULES_ROVER_ACKERMANN=y
|
||||
|
||||
Binary file not shown.
@@ -3,15 +3,6 @@
|
||||
# board specific defaults
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
# Mavlink ethernet (CFG 1000)
|
||||
param set-default MAV_2_CONFIG 1000
|
||||
param set-default MAV_2_BROADCAST 1
|
||||
param set-default MAV_2_MODE 0
|
||||
param set-default MAV_2_RADIO_CTL 0
|
||||
param set-default MAV_2_RATE 100000
|
||||
param set-default MAV_2_REMOTE_PRT 14550
|
||||
param set-default MAV_2_UDP_PRT 14550
|
||||
|
||||
# By disabling all 3 INA modules, we use the
|
||||
# i2c_launcher instead.
|
||||
param set-default SENS_EN_INA238 0
|
||||
@@ -20,8 +11,19 @@ param set-default SENS_EN_INA226 0
|
||||
|
||||
if ver hwbasecmp 009 010 011
|
||||
then
|
||||
# Skynode: use the "custom participant" config for uxrce_dds_client
|
||||
# Skynode: use the "custom participant", IP=10.41.10.1 config for uxrce_dds_client
|
||||
param set-default UXRCE_DDS_PTCFG 2
|
||||
param set-default UXRCE_DDS_AG_IP 170461697
|
||||
param set-default UXRCE_DDS_CFG 1000
|
||||
else
|
||||
# Mavlink ethernet (CFG 1000)
|
||||
param set-default MAV_2_CONFIG 1000
|
||||
param set-default MAV_2_BROADCAST 1
|
||||
param set-default MAV_2_MODE 0
|
||||
param set-default MAV_2_RADIO_CTL 0
|
||||
param set-default MAV_2_RATE 100000
|
||||
param set-default MAV_2_REMOTE_PRT 14550
|
||||
param set-default MAV_2_UDP_PRT 14550
|
||||
fi
|
||||
|
||||
safety_button start
|
||||
|
||||
@@ -147,8 +147,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DHCPC=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_MONITOR=y
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
|
||||
@@ -14,3 +14,4 @@ CONFIG_MODULES_VTOL_ATT_CONTROL=n
|
||||
CONFIG_EKF2_AUX_GLOBAL_POSITION=y
|
||||
# CONFIG_EKF2_WIND is not set
|
||||
CONFIG_MODULES_DIFFERENTIAL_DRIVE=y
|
||||
CONFIG_MODULES_ROVER_ACKERMANN=y
|
||||
|
||||
Binary file not shown.
@@ -28,6 +28,7 @@ CONFIG_ARMV7M_ITCM=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_ARM_MPU=y
|
||||
CONFIG_ARM_MPU_RESET=y
|
||||
CONFIG_BOARDCTL=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
CONFIG_BOARD_ASSERT_RESET_VALUE=0
|
||||
|
||||
@@ -267,6 +267,10 @@
|
||||
|
||||
// This is the ENET_1G interface.
|
||||
|
||||
/* Dshot Disambiguation *******************************************************/
|
||||
|
||||
#define IOMUX_DSHOT_DEFAULT (IOMUX_DRIVE_HIGHSTRENGTH | IOMUX_SLEW_FAST)
|
||||
|
||||
// Compile time selection
|
||||
#if defined(CONFIG_ETH0_PHY_TJA1103)
|
||||
# define BOARD_PHY_ADDR (18)
|
||||
|
||||
@@ -29,6 +29,7 @@ CONFIG_ARMV7M_ITCM=y
|
||||
CONFIG_ARMV7M_MEMCPY=y
|
||||
CONFIG_ARMV7M_USEBASEPRI=y
|
||||
CONFIG_ARM_MPU=y
|
||||
CONFIG_ARM_MPU_RESET=y
|
||||
CONFIG_BOARDCTL_RESET=y
|
||||
CONFIG_BOARD_ASSERT_RESET_VALUE=0
|
||||
CONFIG_BOARD_BOOTLOADER_FIXUP=y
|
||||
@@ -86,7 +87,6 @@ CONFIG_IMXRT_ENET=y
|
||||
CONFIG_IMXRT_FLEXCAN1=y
|
||||
CONFIG_IMXRT_FLEXCAN2=y
|
||||
CONFIG_IMXRT_FLEXCAN3=y
|
||||
CONFIG_IMXRT_FLEXIO1=y
|
||||
CONFIG_IMXRT_FLEXSPI2=y
|
||||
CONFIG_IMXRT_GPIO13_IRQ=y
|
||||
CONFIG_IMXRT_GPIO1_0_15_IRQ=y
|
||||
@@ -202,8 +202,8 @@ CONFIG_NETDEV_LATEINIT=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DHCPC=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_MONITOR=y
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
|
||||
@@ -683,7 +683,6 @@
|
||||
*(.text._ZN18MavlinkStreamDebug8get_sizeEv)
|
||||
*(.text._ZN12GPSDriverUBX7receiveEj)
|
||||
*(.text._ZN13BatteryStatus21parameter_update_pollEb)
|
||||
*(.text._ZN3Ekf26checkYawAngleObservabilityEv)
|
||||
*(.text._ZN3RTL18updateDatamanCacheEv)
|
||||
*(.text.__ieee754_sqrtf)
|
||||
*(.text._ZThn24_N18mag_bias_estimator16MagBiasEstimator3RunEv)
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
*(.text.board_autoled_on)
|
||||
*(.text.clock_timer)
|
||||
*(.text.exception_common)
|
||||
*(.text.flexio_irq_handler)
|
||||
*(.text.hrt_absolute_time)
|
||||
*(.text.hrt_call_enter)
|
||||
*(.text.hrt_tim_isr)
|
||||
|
||||
@@ -15,3 +15,4 @@ CONFIG_MODULES_VTOL_ATT_CONTROL=n
|
||||
CONFIG_EKF2_AUX_GLOBAL_POSITION=y
|
||||
# CONFIG_EKF2_WIND is not set
|
||||
CONFIG_MODULES_DIFFERENTIAL_DRIVE=y
|
||||
CONFIG_MODULES_ROVER_ACKERMANN=y
|
||||
|
||||
@@ -455,6 +455,7 @@
|
||||
#define RC_SERIAL_SINGLEWIRE 1 // Suport Single wire wiring
|
||||
#define RC_SERIAL_SWAP_RXTX 1 // Set Swap (but not supported in HW) to use Single wire
|
||||
#define RC_SERIAL_SWAP_USING_SINGLEWIRE 1 // Set to use Single wire swap as HW does not support swap
|
||||
#define BOARD_SUPPORTS_RC_SERIAL_PORT_OUTPUT
|
||||
|
||||
/* FLEXSPI4 */
|
||||
|
||||
|
||||
@@ -114,7 +114,7 @@ const struct clock_configuration_s g_initial_clkconfig = {
|
||||
.div = 1,
|
||||
.mux = ACMP_CLK_ROOT_OSC_RC_48M_DIV2,
|
||||
},
|
||||
.flexio1_clk_root =
|
||||
.flexio1_clk_root = /* 240 / 2 = 120Mhz */
|
||||
{
|
||||
.enable = 1,
|
||||
.div = 2,
|
||||
|
||||
@@ -104,9 +104,10 @@ const struct flexspi_nor_config_s g_flash_fast_config = {
|
||||
.busyBitPolarity = 0u,
|
||||
.lookupTable =
|
||||
{
|
||||
/* Read */// EEH+11H+32bit addr+20dummy cycles+ 4Bytes read data //200Mhz 18 dummy=10+8
|
||||
/* Read */// EEH+11H+32bit addr+20dummy cycles+ 4Bytes read data
|
||||
/* Macronix manual says 20 dummy cycles @ 200Mhz, FlexSPI peripheral Operand value needs to be 2N in DDR mode hence 0x28 */
|
||||
[0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), //0x871187ee,
|
||||
[0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04),//0xb3048b20,
|
||||
[0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x28),//0xb3288b20,
|
||||
[0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00), //0xa704,
|
||||
|
||||
/* Read status */
|
||||
|
||||
@@ -91,14 +91,14 @@
|
||||
|
||||
|
||||
constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
|
||||
initIOPWMDshot(PWM::FlexPWM1, PWM::Submodule0, GPIO_FLEXIO1_FLEXIO23_1, 23),
|
||||
initIOPWMDshot(PWM::FlexPWM1, PWM::Submodule1, GPIO_FLEXIO1_FLEXIO25_1, 25),
|
||||
initIOPWMDshot(PWM::FlexPWM1, PWM::Submodule2, GPIO_FLEXIO1_FLEXIO27_1, 27),
|
||||
initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule0, GPIO_FLEXIO1_FLEXIO06_1, 6),
|
||||
initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule1, GPIO_FLEXIO1_FLEXIO08_1, 8),
|
||||
initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule2, GPIO_FLEXIO1_FLEXIO10_1, 10),
|
||||
initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule3, GPIO_FLEXIO1_FLEXIO19_1, 19),
|
||||
initIOPWMDshot(PWM::FlexPWM3, PWM::Submodule0, GPIO_FLEXIO1_FLEXIO29_1, 29),
|
||||
initIOPWMDshot(PWM::FlexPWM1, PWM::Submodule0),
|
||||
initIOPWMDshot(PWM::FlexPWM1, PWM::Submodule1),
|
||||
initIOPWMDshot(PWM::FlexPWM1, PWM::Submodule2),
|
||||
initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule0),
|
||||
initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule1),
|
||||
initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule2),
|
||||
initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule3),
|
||||
initIOPWMDshot(PWM::FlexPWM3, PWM::Submodule0),
|
||||
initIOPWM(PWM::FlexPWM3, PWM::Submodule1),
|
||||
initIOPWM(PWM::FlexPWM3, PWM::Submodule3),
|
||||
initIOPWM(PWM::FlexPWM4, PWM::Submodule0),
|
||||
@@ -106,14 +106,14 @@ constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
|
||||
};
|
||||
|
||||
constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
|
||||
/* FMU_CH1 */ initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_23),
|
||||
/* FMU_CH2 */ initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_25),
|
||||
/* FMU_CH3 */ initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_B1_27),
|
||||
/* FMU_CH4 */ initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_06),
|
||||
/* FMU_CH5 */ initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_08),
|
||||
/* FMU_CH6 */ initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_B1_10),
|
||||
/* FMU_CH7 */ initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule3}, IOMUX::Pad::GPIO_EMC_B1_19),
|
||||
/* FMU_CH8 */ initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_29),
|
||||
/* FMU_CH1 */ initIOTimerChannelDshot(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_23, GPIO_FLEXIO1_FLEXIO23_1 | IOMUX_DSHOT_DEFAULT, 23),
|
||||
/* FMU_CH2 */ initIOTimerChannelDshot(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_25, GPIO_FLEXIO1_FLEXIO25_1 | IOMUX_DSHOT_DEFAULT, 25),
|
||||
/* FMU_CH3 */ initIOTimerChannelDshot(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_B1_27, GPIO_FLEXIO1_FLEXIO27_1 | IOMUX_DSHOT_DEFAULT, 27),
|
||||
/* FMU_CH4 */ initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_06, GPIO_FLEXIO1_FLEXIO06_1 | IOMUX_DSHOT_DEFAULT, 6),
|
||||
/* FMU_CH5 */ initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_08, GPIO_FLEXIO1_FLEXIO08_1 | IOMUX_DSHOT_DEFAULT, 8),
|
||||
/* FMU_CH6 */ initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_B1_10, GPIO_FLEXIO1_FLEXIO10_1 | IOMUX_DSHOT_DEFAULT, 10),
|
||||
/* FMU_CH7 */ initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule3}, IOMUX::Pad::GPIO_EMC_B1_19, GPIO_FLEXIO1_FLEXIO19_1 | IOMUX_DSHOT_DEFAULT, 19),
|
||||
/* FMU_CH8 */ initIOTimerChannelDshot(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_29, GPIO_FLEXIO1_FLEXIO29_1 | IOMUX_DSHOT_DEFAULT, 29),
|
||||
/* FMU_CH9 */ initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_31),
|
||||
/* FMU_CH10 */ initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule3}, IOMUX::Pad::GPIO_EMC_B1_21),
|
||||
/* FMU_CH11 */ initIOTimerChannel(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_00),
|
||||
|
||||
@@ -45,6 +45,7 @@ CONFIG_MODE_NAVIGATOR_VTOL_TAKEOFF=y
|
||||
CONFIG_MODULES_PAYLOAD_DELIVERER=y
|
||||
CONFIG_MODULES_RC_UPDATE=y
|
||||
CONFIG_MODULES_REPLAY=y
|
||||
CONFIG_MODULES_ROVER_ACKERMANN=y
|
||||
CONFIG_MODULES_ROVER_POS_CONTROL=y
|
||||
CONFIG_MODULES_SENSORS=y
|
||||
CONFIG_COMMON_SIMULATION=y
|
||||
|
||||
Binary file not shown.
@@ -50,7 +50,6 @@ CONFIG_MODULES_FW_POS_CONTROL=y
|
||||
CONFIG_MODULES_FW_RATE_CONTROL=y
|
||||
CONFIG_MODULES_GIMBAL=y
|
||||
CONFIG_MODULES_GYRO_CALIBRATION=y
|
||||
CONFIG_MODULES_GYRO_FFT=y
|
||||
CONFIG_MODULES_LAND_DETECTOR=y
|
||||
CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
|
||||
CONFIG_MODULES_LOAD_MON=y
|
||||
|
||||
@@ -141,8 +141,8 @@ CONFIG_NETDB_DNSCLIENT_ENTRIES=8
|
||||
CONFIG_NETDB_DNSSERVER_NOADDR=y
|
||||
CONFIG_NETDEV_PHY_IOCTL=y
|
||||
CONFIG_NETINIT_DNS=y
|
||||
CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DRIPADDR=0XC0A800FE
|
||||
CONFIG_NETINIT_DNSIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_DRIPADDR=0xA290AFE
|
||||
CONFIG_NETINIT_THREAD=y
|
||||
CONFIG_NETINIT_THREAD_PRIORITY=49
|
||||
CONFIG_NETUTILS_TELNETD=y
|
||||
|
||||
@@ -308,7 +308,7 @@ class MavrosMissionTest(MavrosTestCommon):
|
||||
self.assertTrue(res['pitch_error_std'] < 5.0, str(res))
|
||||
|
||||
# TODO: fix by excluding initial heading init and reset preflight
|
||||
self.assertTrue(res['yaw_error_std'] < 13.0, str(res))
|
||||
self.assertTrue(res['yaw_error_std'] < 15.0, str(res))
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
|
||||
@@ -178,6 +178,7 @@ set(msg_files
|
||||
RcParameterMap.msg
|
||||
RegisterExtComponentReply.msg
|
||||
RegisterExtComponentRequest.msg
|
||||
RoverAckermannGuidanceStatus.msg
|
||||
Rpm.msg
|
||||
RtlStatus.msg
|
||||
RtlTimeEstimate.msg
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
uint64 timestamp # time since system start (microseconds)
|
||||
|
||||
float32 actual_speed # [m/s] Rover ground speed
|
||||
float32 desired_speed # [m/s] Rover desired ground speed
|
||||
float32 lookahead_distance # [m] Lookahead distance of pure the pursuit controller
|
||||
float32 heading_error # [deg] Heading error of the pure pursuit controller
|
||||
float32 pid_throttle_integral # [-1, 1] Integral of the PID for the normalized throttle to control the rover speed during missions
|
||||
float32 crosstrack_error # [m] Shortest distance from the vehicle to the path
|
||||
|
||||
# TOPICS rover_ackermann_guidance_status
|
||||
@@ -11,7 +11,7 @@ float32[4] q_d # Desired quaternion for quaternion control
|
||||
|
||||
# For clarification: For multicopters thrust_body[0] and thrust[1] are usually 0 and thrust[2] is the negative throttle demand.
|
||||
# For fixed wings thrust_x is the throttle demand and thrust_y, thrust_z will usually be zero.
|
||||
float32[3] thrust_body # Normalized thrust command in body NED frame [-1,1]
|
||||
float32[3] thrust_body # Normalized thrust command in body FRD frame [-1,1]
|
||||
|
||||
bool reset_integral # Reset roll/pitch/yaw integrals (navigation logic change)
|
||||
|
||||
|
||||
@@ -62,6 +62,11 @@ public:
|
||||
{
|
||||
Node **p;
|
||||
|
||||
// Don't allow duplicates to be inserted
|
||||
if (find(node_name)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (_top == nullptr) {
|
||||
p = &_top;
|
||||
|
||||
|
||||
Submodule platforms/nuttx/NuttX/nuttx updated: 0f401a6062...6fbb26eb52
@@ -306,7 +306,7 @@ void
|
||||
jump_to_app()
|
||||
{
|
||||
const uint32_t *app_base = (const uint32_t *)APP_LOAD_ADDRESS;
|
||||
const uint32_t *vec_base = (const uint32_t *)app_base + APP_VECTOR_OFFSET;
|
||||
const uint32_t *vec_base = (const uint32_t *)((const uint32_t)app_base + APP_VECTOR_OFFSET);
|
||||
|
||||
/*
|
||||
* We refuse to program the first word of the app until the upload is marked
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
#include "imxrt_clockconfig.h"
|
||||
|
||||
#include <nvic.h>
|
||||
#include <mpu.h>
|
||||
#include <lib/systick.h>
|
||||
#include <lib/flash_cache.h>
|
||||
|
||||
@@ -396,7 +397,7 @@ flash_func_sector_size(unsigned sector)
|
||||
}
|
||||
|
||||
/* imxRT uses Flash lib, not up_progmem so let's stub it here */
|
||||
up_progmem_ispageerased(unsigned sector)
|
||||
ssize_t up_progmem_ispageerased(unsigned sector)
|
||||
{
|
||||
const uint32_t bytes_per_sector = flash_func_sector_size(sector);
|
||||
uint32_t *address = (uint32_t *)(IMXRT_FLEXSPI1_CIPHER_BASE + (sector * bytes_per_sector));
|
||||
@@ -431,9 +432,13 @@ flash_func_erase_sector(unsigned sector, bool force)
|
||||
return;
|
||||
}
|
||||
|
||||
if (force || flash_func_is_sector_blank(sector) != 0) {
|
||||
if (force || up_progmem_ispageerased(sector) != 0) {
|
||||
|
||||
struct flexspi_nor_config_s *pConfig = &g_bootConfig;
|
||||
|
||||
const uint32_t bytes_per_sector = flash_func_sector_size(sector);
|
||||
uint32_t *address = (uint32_t *)(IMXRT_FLEXSPI1_CIPHER_BASE + (sector * bytes_per_sector));
|
||||
|
||||
uintptr_t offset = ((uintptr_t) address) - IMXRT_FLEXSPI1_CIPHER_BASE;
|
||||
irqstate_t flags;
|
||||
flags = enter_critical_section();
|
||||
@@ -577,6 +582,21 @@ led_toggle(unsigned led)
|
||||
void
|
||||
arch_do_jump(const uint32_t *app_base)
|
||||
{
|
||||
/* The MPU configuration after booting has ITCM set to MPU_RASR_AP_RORO
|
||||
* We add this overlaping region to allow the Application to copy code into
|
||||
* the ITCM when it is booted. With CONFIG_ARM_MPU_RESET defined. The mpu
|
||||
* init will clear any added regions (after the copy)
|
||||
*/
|
||||
|
||||
mpu_configure_region(IMXRT_ITCM_BASE, 256 * 1024,
|
||||
/* Instruction access Enabled */
|
||||
MPU_RASR_AP_RWRW | /* P:RW U:RW */
|
||||
MPU_RASR_TEX_NOR /* Normal */
|
||||
/* Not Cacheable */
|
||||
/* Not Bufferable */
|
||||
/* Not Shareable */
|
||||
/* No Subregion disable */
|
||||
);
|
||||
|
||||
/* extract the stack and entrypoint from the app vector table and go */
|
||||
uint32_t stacktop = app_base[APP_VECTOR_OFFSET_WORDS];
|
||||
|
||||
@@ -74,6 +74,11 @@ bool SerialImpl::configure()
|
||||
int speed;
|
||||
|
||||
switch (_baudrate) {
|
||||
case 0:
|
||||
// special case, if baudrate is 0 it hangs entire system
|
||||
PX4_ERR("baudrate not specified");
|
||||
return false;
|
||||
|
||||
case 9600: speed = B9600; break;
|
||||
|
||||
case 19200: speed = B19200; break;
|
||||
|
||||
@@ -33,145 +33,454 @@
|
||||
****************************************************************************/
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/micro_hal.h>
|
||||
#include <px4_platform_common/log.h>
|
||||
#include <imxrt_flexio.h>
|
||||
#include <hardware/imxrt_flexio.h>
|
||||
#include <imxrt_periphclks.h>
|
||||
#include <px4_arch/dshot.h>
|
||||
#include <px4_arch/io_timer.h>
|
||||
#include <drivers/drv_dshot.h>
|
||||
#include <stdio.h>
|
||||
#include "barriers.h"
|
||||
|
||||
#include "arm_internal.h"
|
||||
|
||||
#define FLEXIO_BASE IMXRT_FLEXIO1_BASE
|
||||
#define FLEXIO_PREQ 120000000
|
||||
#define DSHOT_TIMERS FLEXIO_SHIFTBUFNIS_COUNT
|
||||
#define DSHOT_THROTTLE_POSITION 5u
|
||||
#define DSHOT_TELEMETRY_POSITION 4u
|
||||
#define NIBBLES_SIZE 4u
|
||||
#define DSHOT_NUMBER_OF_NIBBLES 3u
|
||||
|
||||
#if defined(IOMUX_PULL_UP_47K)
|
||||
#define IOMUX_PULL_UP IOMUX_PULL_UP_47K
|
||||
#endif
|
||||
|
||||
static const uint32_t gcr_decode[32] = {
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||
0x0, 0x9, 0xA, 0xB, 0x0, 0xD, 0xE, 0xF,
|
||||
0x0, 0x0, 0x2, 0x3, 0x0, 0x5, 0x6, 0x7,
|
||||
0x0, 0x0, 0x8, 0x1, 0x0, 0x4, 0xC, 0x0
|
||||
};
|
||||
|
||||
uint32_t erpms[DSHOT_TIMERS];
|
||||
|
||||
typedef enum {
|
||||
DSHOT_START = 0,
|
||||
DSHOT_12BIT_FIFO,
|
||||
DSHOT_12BIT_TRANSFERRED,
|
||||
DSHOT_TRANSMIT_COMPLETE,
|
||||
BDSHOT_RECEIVE,
|
||||
BDSHOT_RECEIVE_COMPLETE,
|
||||
} dshot_state;
|
||||
|
||||
typedef struct dshot_handler_t {
|
||||
bool init;
|
||||
uint32_t data_seg1;
|
||||
uint32_t irq_data;
|
||||
dshot_state state;
|
||||
bool bdshot;
|
||||
uint32_t raw_response;
|
||||
uint16_t erpm;
|
||||
uint32_t crc_error_cnt;
|
||||
uint32_t frame_error_cnt;
|
||||
uint32_t no_response_cnt;
|
||||
uint32_t last_no_response_cnt;
|
||||
} dshot_handler_t;
|
||||
|
||||
#define BDSHOT_OFFLINE_COUNT 400 // If there are no responses for 400 setpoints ESC is offline
|
||||
|
||||
static dshot_handler_t dshot_inst[DSHOT_TIMERS] = {};
|
||||
|
||||
struct flexio_dev_s *flexio_s;
|
||||
static uint32_t dshot_tcmp;
|
||||
static uint32_t bdshot_tcmp;
|
||||
static uint32_t dshot_mask;
|
||||
static uint32_t bdshot_recv_mask;
|
||||
static uint32_t bdshot_parsed_recv_mask;
|
||||
|
||||
static inline uint32_t flexio_getreg32(uint32_t offset)
|
||||
{
|
||||
return getreg32(FLEXIO_BASE + offset);
|
||||
}
|
||||
|
||||
static inline void flexio_modifyreg32(unsigned int offset,
|
||||
uint32_t clearbits,
|
||||
uint32_t setbits)
|
||||
{
|
||||
modifyreg32(FLEXIO_BASE + offset, clearbits, setbits);
|
||||
}
|
||||
|
||||
static inline void flexio_putreg32(uint32_t value, uint32_t offset)
|
||||
{
|
||||
putreg32(value, FLEXIO_BASE + offset);
|
||||
}
|
||||
|
||||
static inline void enable_shifter_status_interrupts(uint32_t mask)
|
||||
{
|
||||
flexio_modifyreg32(IMXRT_FLEXIO_SHIFTSIEN_OFFSET, 0, mask);
|
||||
}
|
||||
|
||||
static inline void disable_shifter_status_interrupts(uint32_t mask)
|
||||
{
|
||||
flexio_modifyreg32(IMXRT_FLEXIO_SHIFTSIEN_OFFSET, mask, 0);
|
||||
}
|
||||
|
||||
static inline uint32_t get_shifter_status_flags(void)
|
||||
{
|
||||
return flexio_getreg32(IMXRT_FLEXIO_SHIFTSTAT_OFFSET);
|
||||
}
|
||||
|
||||
static inline void clear_shifter_status_flags(uint32_t mask)
|
||||
{
|
||||
flexio_putreg32(mask, IMXRT_FLEXIO_SHIFTSTAT_OFFSET);
|
||||
}
|
||||
|
||||
static inline void enable_timer_status_interrupts(uint32_t mask)
|
||||
{
|
||||
flexio_modifyreg32(IMXRT_FLEXIO_TIMIEN_OFFSET, 0, mask);
|
||||
}
|
||||
|
||||
static inline void disable_timer_status_interrupts(uint32_t mask)
|
||||
{
|
||||
flexio_modifyreg32(IMXRT_FLEXIO_TIMIEN_OFFSET, mask, 0);
|
||||
}
|
||||
|
||||
static inline uint32_t get_timer_status_flags(void)
|
||||
{
|
||||
return flexio_getreg32(IMXRT_FLEXIO_TIMSTAT_OFFSET);
|
||||
}
|
||||
|
||||
static inline void clear_timer_status_flags(uint32_t mask)
|
||||
{
|
||||
flexio_putreg32(mask, IMXRT_FLEXIO_TIMSTAT_OFFSET);
|
||||
}
|
||||
|
||||
static void flexio_dshot_output(uint32_t channel, uint32_t pin, uint32_t timcmp, bool inverted)
|
||||
{
|
||||
/* Disable Shifter */
|
||||
flexio_putreg32(0, IMXRT_FLEXIO_SHIFTCTL0_OFFSET + channel * 0x4);
|
||||
|
||||
/* No start bit, stop bit low */
|
||||
flexio_putreg32(FLEXIO_SHIFTCFG_INSRC(FLEXIO_SHIFTER_INPUT_FROM_PIN) |
|
||||
FLEXIO_SHIFTCFG_PWIDTH(0) |
|
||||
FLEXIO_SHIFTCFG_SSTOP(FLEXIO_SHIFTER_STOP_BIT_LOW) |
|
||||
FLEXIO_SHIFTCFG_SSTART(FLEXIO_SHIFTER_START_BIT_DISABLED_LOAD_DATA_ON_ENABLE),
|
||||
IMXRT_FLEXIO_SHIFTCFG0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Transmit mode, output to FXIO pin, inverted output for bdshot */
|
||||
flexio_putreg32(FLEXIO_SHIFTCTL_TIMSEL(channel) |
|
||||
FLEXIO_SHIFTCTL_TIMPOL(FLEXIO_SHIFTER_TIMER_POLARITY_ON_POSITIVE) |
|
||||
FLEXIO_SHIFTCTL_PINCFG(FLEXIO_PIN_CONFIG_OUTPUT) |
|
||||
FLEXIO_SHIFTCTL_PINSEL(pin) |
|
||||
FLEXIO_SHIFTCTL_PINPOL(inverted) |
|
||||
FLEXIO_SHIFTCTL_SMOD(FLEXIO_SHIFTER_MODE_TRANSMIT),
|
||||
IMXRT_FLEXIO_SHIFTCTL0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Start transmitting on trigger, disable on compare */
|
||||
flexio_putreg32(FLEXIO_TIMCFG_TIMOUT(FLEXIO_TIMER_OUTPUT_ONE_NOT_AFFECTED_BY_RESET) |
|
||||
FLEXIO_TIMCFG_TIMDEC(FLEXIO_TIMER_DEC_SRC_ON_FLEX_IO_CLOCK_SHIFT_TIMER_OUTPUT) |
|
||||
FLEXIO_TIMCFG_TIMRST(FLEXIO_TIMER_RESET_NEVER) |
|
||||
FLEXIO_TIMCFG_TIMDIS(FLEXIO_TIMER_DISABLE_ON_TIMER_COMPARE) |
|
||||
FLEXIO_TIMCFG_TIMENA(FLEXIO_TIMER_ENABLE_ON_TRIGGER_HIGH) |
|
||||
FLEXIO_TIMCFG_TSTOP(FLEXIO_TIMER_STOP_BIT_DISABLED) |
|
||||
FLEXIO_TIMCFG_TSTART(FLEXIO_TIMER_START_BIT_DISABLED),
|
||||
IMXRT_FLEXIO_TIMCFG0_OFFSET + channel * 0x4);
|
||||
|
||||
flexio_putreg32(timcmp, IMXRT_FLEXIO_TIMCMP0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Baud mode, Trigger on shifter write */
|
||||
flexio_putreg32(FLEXIO_TIMCTL_TRGSEL((4 * channel) + 1) |
|
||||
FLEXIO_TIMCTL_TRGPOL(FLEXIO_TIMER_TRIGGER_POLARITY_ACTIVE_LOW) |
|
||||
FLEXIO_TIMCTL_TRGSRC(FLEXIO_TIMER_TRIGGER_SOURCE_INTERNAL) |
|
||||
FLEXIO_TIMCTL_PINCFG(FLEXIO_PIN_CONFIG_OUTPUT_DISABLED) |
|
||||
FLEXIO_TIMCTL_PINSEL(0) |
|
||||
FLEXIO_TIMCTL_PINPOL(FLEXIO_PIN_ACTIVE_LOW) |
|
||||
FLEXIO_TIMCTL_TIMOD(FLEXIO_TIMER_MODE_DUAL8_BIT_BAUD_BIT),
|
||||
IMXRT_FLEXIO_TIMCTL0_OFFSET + channel * 0x4);
|
||||
|
||||
}
|
||||
|
||||
static int flexio_irq_handler(int irq, void *context, void *arg)
|
||||
{
|
||||
uint32_t flags = get_shifter_status_flags();
|
||||
uint32_t channel;
|
||||
|
||||
uint32_t flags = flexio_s->ops->get_shifter_status_flags(flexio_s);
|
||||
uint32_t instance;
|
||||
for (channel = 0; flags && channel < DSHOT_TIMERS; channel++) {
|
||||
if (flags & (1 << channel)) {
|
||||
disable_shifter_status_interrupts(1 << channel);
|
||||
|
||||
for (instance = 0; flags && instance < DSHOT_TIMERS; instance++) {
|
||||
if (flags & (1 << instance)) {
|
||||
flexio_s->ops->disable_shifter_status_interrupts(flexio_s, (1 << instance));
|
||||
flexio_s->ops->disable_timer_status_interrupts(flexio_s, (1 << instance));
|
||||
if (dshot_inst[channel].state == DSHOT_START) {
|
||||
dshot_inst[channel].state = DSHOT_12BIT_FIFO;
|
||||
flexio_putreg32(dshot_inst[channel].irq_data, IMXRT_FLEXIO_SHIFTBUF0_OFFSET + channel * 0x4);
|
||||
|
||||
if (dshot_inst[instance].irq_data != 0) {
|
||||
uint32_t buf_adr = flexio_s->ops->get_shifter_buffer_address(flexio_s, FLEXIO_SHIFTER_BUFFER, instance);
|
||||
putreg32(dshot_inst[instance].irq_data, IMXRT_FLEXIO1_BASE + buf_adr);
|
||||
dshot_inst[instance].irq_data = 0;
|
||||
} else if (dshot_inst[channel].state == BDSHOT_RECEIVE) {
|
||||
dshot_inst[channel].state = BDSHOT_RECEIVE_COMPLETE;
|
||||
dshot_inst[channel].raw_response = flexio_getreg32(IMXRT_FLEXIO_SHIFTBUFBIS0_OFFSET + channel * 0x4);
|
||||
|
||||
bdshot_recv_mask |= (1 << channel);
|
||||
|
||||
if (bdshot_recv_mask == dshot_mask) {
|
||||
// Received telemetry on all channels
|
||||
// Schedule workqueue?
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
flags = get_timer_status_flags();
|
||||
|
||||
for (channel = 0; flags; (channel = (channel + 1) % DSHOT_TIMERS)) {
|
||||
flags = get_timer_status_flags();
|
||||
|
||||
if (flags & (1 << channel)) {
|
||||
clear_timer_status_flags(1 << channel);
|
||||
|
||||
if (dshot_inst[channel].state == DSHOT_12BIT_FIFO) {
|
||||
dshot_inst[channel].state = DSHOT_12BIT_TRANSFERRED;
|
||||
|
||||
} else if (!dshot_inst[channel].bdshot && dshot_inst[channel].state == DSHOT_12BIT_TRANSFERRED) {
|
||||
dshot_inst[channel].state = DSHOT_TRANSMIT_COMPLETE;
|
||||
|
||||
} else if (dshot_inst[channel].bdshot && dshot_inst[channel].state == DSHOT_12BIT_TRANSFERRED) {
|
||||
disable_shifter_status_interrupts(1 << channel);
|
||||
dshot_inst[channel].state = BDSHOT_RECEIVE;
|
||||
|
||||
/* Transmit done, disable timer and reconfigure to receive*/
|
||||
flexio_putreg32(0x0, IMXRT_FLEXIO_TIMCTL0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Input data from pin, no start/stop bit*/
|
||||
flexio_putreg32(FLEXIO_SHIFTCFG_INSRC(FLEXIO_SHIFTER_INPUT_FROM_PIN) |
|
||||
FLEXIO_SHIFTCFG_PWIDTH(0) |
|
||||
FLEXIO_SHIFTCFG_SSTOP(FLEXIO_SHIFTER_STOP_BIT_DISABLE) |
|
||||
FLEXIO_SHIFTCFG_SSTART(FLEXIO_SHIFTER_START_BIT_DISABLED_LOAD_DATA_ON_SHIFT),
|
||||
IMXRT_FLEXIO_SHIFTCFG0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Shifter receive mdoe, on FXIO pin input */
|
||||
flexio_putreg32(FLEXIO_SHIFTCTL_TIMSEL(channel) |
|
||||
FLEXIO_SHIFTCTL_TIMPOL(FLEXIO_SHIFTER_TIMER_POLARITY_ON_POSITIVE) |
|
||||
FLEXIO_SHIFTCTL_PINCFG(FLEXIO_PIN_CONFIG_OUTPUT_DISABLED) |
|
||||
FLEXIO_SHIFTCTL_PINSEL(timer_io_channels[channel].dshot.flexio_pin) |
|
||||
FLEXIO_SHIFTCTL_PINPOL(FLEXIO_PIN_ACTIVE_LOW) |
|
||||
FLEXIO_SHIFTCTL_SMOD(FLEXIO_SHIFTER_MODE_RECEIVE),
|
||||
IMXRT_FLEXIO_SHIFTCTL0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Make sure there no shifter flags high from transmission */
|
||||
clear_shifter_status_flags(1 << channel);
|
||||
|
||||
/* Enable on pin transition, resychronize through reset on rising edge */
|
||||
flexio_putreg32(FLEXIO_TIMCFG_TIMOUT(FLEXIO_TIMER_OUTPUT_ONE_AFFECTED_BY_RESET) |
|
||||
FLEXIO_TIMCFG_TIMDEC(FLEXIO_TIMER_DEC_SRC_ON_FLEX_IO_CLOCK_SHIFT_TIMER_OUTPUT) |
|
||||
FLEXIO_TIMCFG_TIMRST(FLEXIO_TIMER_RESET_ON_TIMER_PIN_RISING_EDGE) |
|
||||
FLEXIO_TIMCFG_TIMDIS(FLEXIO_TIMER_DISABLE_ON_TIMER_COMPARE) |
|
||||
FLEXIO_TIMCFG_TIMENA(FLEXIO_TIMER_ENABLE_ON_TRIGGER_BOTH_EDGE) |
|
||||
FLEXIO_TIMCFG_TSTOP(FLEXIO_TIMER_STOP_BIT_ENABLE_ON_TIMER_DISABLE) |
|
||||
FLEXIO_TIMCFG_TSTART(FLEXIO_TIMER_START_BIT_ENABLED),
|
||||
IMXRT_FLEXIO_TIMCFG0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Enable on pin transition, resychronize through reset on rising edge */
|
||||
flexio_putreg32(bdshot_tcmp, IMXRT_FLEXIO_TIMCMP0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Trigger on FXIO pin transition, Baud mode */
|
||||
flexio_putreg32(FLEXIO_TIMCTL_TRGSEL(2 * timer_io_channels[channel].dshot.flexio_pin) |
|
||||
FLEXIO_TIMCTL_TRGPOL(FLEXIO_TIMER_TRIGGER_POLARITY_ACTIVE_HIGH) |
|
||||
FLEXIO_TIMCTL_TRGSRC(FLEXIO_TIMER_TRIGGER_SOURCE_INTERNAL) |
|
||||
FLEXIO_TIMCTL_PINCFG(FLEXIO_PIN_CONFIG_OUTPUT_DISABLED) |
|
||||
FLEXIO_TIMCTL_PINSEL(0) |
|
||||
FLEXIO_TIMCTL_PINPOL(FLEXIO_PIN_ACTIVE_LOW) |
|
||||
FLEXIO_TIMCTL_TIMOD(FLEXIO_TIMER_MODE_DUAL8_BIT_BAUD_BIT),
|
||||
IMXRT_FLEXIO_TIMCTL0_OFFSET + channel * 0x4);
|
||||
|
||||
/* Enable shifter interrupt for receiving data */
|
||||
enable_shifter_status_interrupts(1 << channel);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
int up_dshot_init(uint32_t channel_mask, unsigned dshot_pwm_freq)
|
||||
|
||||
int up_dshot_init(uint32_t channel_mask, unsigned dshot_pwm_freq, bool enable_bidirectional_dshot)
|
||||
{
|
||||
uint32_t timer_compare;
|
||||
/* Calculate dshot timings based on dshot_pwm_freq */
|
||||
dshot_tcmp = 0x2F00 | (((FLEXIO_PREQ / (dshot_pwm_freq * 3) / 2)) & 0xFF);
|
||||
bdshot_tcmp = 0x2900 | (((FLEXIO_PREQ / (dshot_pwm_freq * 5 / 4) / 2) - 1) & 0xFF);
|
||||
|
||||
if (dshot_pwm_freq == 150000) {
|
||||
timer_compare = 0x2F8A;
|
||||
/* Clock FlexIO peripheral */
|
||||
imxrt_clockall_flexio1();
|
||||
|
||||
} else if (dshot_pwm_freq == 300000) {
|
||||
timer_compare = 0x2F45;
|
||||
/* Reset FlexIO peripheral */
|
||||
flexio_modifyreg32(IMXRT_FLEXIO_CTRL_OFFSET, 0,
|
||||
FLEXIO_CTRL_SWRST_MASK);
|
||||
flexio_putreg32(0, IMXRT_FLEXIO_CTRL_OFFSET);
|
||||
|
||||
} else if (dshot_pwm_freq == 600000) {
|
||||
timer_compare = 0x2F22;
|
||||
/* Initialize FlexIO peripheral */
|
||||
flexio_modifyreg32(IMXRT_FLEXIO_CTRL_OFFSET,
|
||||
(FLEXIO_CTRL_DOZEN_MASK |
|
||||
FLEXIO_CTRL_DBGE_MASK |
|
||||
FLEXIO_CTRL_FASTACC_MASK |
|
||||
FLEXIO_CTRL_FLEXEN_MASK),
|
||||
(FLEXIO_CTRL_DBGE(1) |
|
||||
FLEXIO_CTRL_FASTACC(1) |
|
||||
FLEXIO_CTRL_FLEXEN(0)));
|
||||
|
||||
} else if (dshot_pwm_freq == 1200000) {
|
||||
timer_compare = 0x2F11;
|
||||
|
||||
} else {
|
||||
// Not supported Dshot frequency
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Init FlexIO peripheral */
|
||||
|
||||
flexio_s = imxrt_flexio_initialize(1);
|
||||
/* FlexIO IRQ handling */
|
||||
up_enable_irq(IMXRT_IRQ_FLEXIO1);
|
||||
irq_attach(IMXRT_IRQ_FLEXIO1, flexio_irq_handler, flexio_s);
|
||||
irq_attach(IMXRT_IRQ_FLEXIO1, flexio_irq_handler, 0);
|
||||
|
||||
dshot_mask = 0x0;
|
||||
|
||||
for (unsigned channel = 0; (channel_mask != 0) && (channel < DSHOT_TIMERS); channel++) {
|
||||
if (channel_mask & (1 << channel)) {
|
||||
uint8_t timer = timer_io_channels[channel].timer_index;
|
||||
|
||||
if (io_timers[timer].dshot.pinmux == 0) { // board does not configure dshot on this pin
|
||||
if (timer_io_channels[channel].dshot.pinmux == 0) { // board does not configure dshot on this pin
|
||||
continue;
|
||||
}
|
||||
|
||||
imxrt_config_gpio(io_timers[timer].dshot.pinmux);
|
||||
imxrt_config_gpio(timer_io_channels[channel].dshot.pinmux | IOMUX_PULL_UP);
|
||||
|
||||
struct flexio_shifter_config_s shft_cfg;
|
||||
shft_cfg.timer_select = channel;
|
||||
shft_cfg.timer_polarity = FLEXIO_SHIFTER_TIMER_POLARITY_ON_POSITIVE;
|
||||
shft_cfg.pin_config = FLEXIO_PIN_CONFIG_OUTPUT;
|
||||
shft_cfg.pin_select = io_timers[timer].dshot.flexio_pin;
|
||||
shft_cfg.pin_polarity = FLEXIO_PIN_ACTIVE_HIGH;
|
||||
shft_cfg.shifter_mode = FLEXIO_SHIFTER_MODE_TRANSMIT;
|
||||
shft_cfg.parallel_width = 0;
|
||||
shft_cfg.input_source = FLEXIO_SHIFTER_INPUT_FROM_PIN;
|
||||
shft_cfg.shifter_stop = FLEXIO_SHIFTER_STOP_BIT_LOW;
|
||||
shft_cfg.shifter_start = FLEXIO_SHIFTER_START_BIT_DISABLED_LOAD_DATA_ON_ENABLE;
|
||||
dshot_inst[channel].bdshot = enable_bidirectional_dshot;
|
||||
|
||||
flexio_s->ops->set_shifter_config(flexio_s, channel, &shft_cfg);
|
||||
|
||||
struct flexio_timer_config_s tmr_cfg;
|
||||
tmr_cfg.trigger_select = (4 * channel) + 1;
|
||||
tmr_cfg.trigger_polarity = FLEXIO_TIMER_TRIGGER_POLARITY_ACTIVE_LOW;
|
||||
tmr_cfg.trigger_source = FLEXIO_TIMER_TRIGGER_SOURCE_INTERNAL;
|
||||
tmr_cfg.pin_config = FLEXIO_PIN_CONFIG_OUTPUT_DISABLED;
|
||||
tmr_cfg.pin_select = 0;
|
||||
tmr_cfg.pin_polarity = FLEXIO_PIN_ACTIVE_LOW;
|
||||
tmr_cfg.timer_mode = FLEXIO_TIMER_MODE_DUAL8_BIT_BAUD_BIT;
|
||||
tmr_cfg.timer_output = FLEXIO_TIMER_OUTPUT_ONE_NOT_AFFECTED_BY_RESET;
|
||||
tmr_cfg.timer_decrement = FLEXIO_TIMER_DEC_SRC_ON_FLEX_IO_CLOCK_SHIFT_TIMER_OUTPUT;
|
||||
tmr_cfg.timer_reset = FLEXIO_TIMER_RESET_NEVER;
|
||||
tmr_cfg.timer_disable = FLEXIO_TIMER_DISABLE_ON_TIMER_COMPARE;
|
||||
tmr_cfg.timer_enable = FLEXIO_TIMER_ENABLE_ON_TRIGGER_HIGH;
|
||||
tmr_cfg.timer_stop = FLEXIO_TIMER_STOP_BIT_DISABLED;
|
||||
tmr_cfg.timer_start = FLEXIO_TIMER_START_BIT_DISABLED;
|
||||
tmr_cfg.timer_compare = timer_compare;
|
||||
flexio_s->ops->set_timer_config(flexio_s, channel, &tmr_cfg);
|
||||
flexio_dshot_output(channel, timer_io_channels[channel].dshot.flexio_pin, dshot_tcmp, dshot_inst[channel].bdshot);
|
||||
|
||||
dshot_inst[channel].init = true;
|
||||
|
||||
// Mask channel to be active on dshot
|
||||
dshot_mask |= (1 << channel);
|
||||
}
|
||||
}
|
||||
|
||||
flexio_s->ops->enable(flexio_s, true);
|
||||
flexio_modifyreg32(IMXRT_FLEXIO_CTRL_OFFSET, 0,
|
||||
FLEXIO_CTRL_FLEXEN_MASK);
|
||||
|
||||
return channel_mask;
|
||||
}
|
||||
|
||||
void up_bdshot_erpm(void)
|
||||
{
|
||||
uint32_t value;
|
||||
uint32_t data;
|
||||
uint32_t csum_data;
|
||||
uint8_t exponent;
|
||||
uint16_t period;
|
||||
uint16_t erpm;
|
||||
|
||||
bdshot_parsed_recv_mask = 0;
|
||||
|
||||
// Decode each individual channel
|
||||
for (uint8_t channel = 0; (channel < DSHOT_TIMERS); channel++) {
|
||||
if (bdshot_recv_mask & (1 << channel)) {
|
||||
value = ~dshot_inst[channel].raw_response & 0xFFFFF;
|
||||
|
||||
/* if lowest significant isn't 1 we've got a framing error */
|
||||
if (value & 0x1) {
|
||||
/* Decode RLL */
|
||||
value = (value ^ (value >> 1));
|
||||
|
||||
/* Decode GCR */
|
||||
data = gcr_decode[value & 0x1fU];
|
||||
data |= gcr_decode[(value >> 5U) & 0x1fU] << 4U;
|
||||
data |= gcr_decode[(value >> 10U) & 0x1fU] << 8U;
|
||||
data |= gcr_decode[(value >> 15U) & 0x1fU] << 12U;
|
||||
|
||||
/* Calculate checksum */
|
||||
csum_data = data;
|
||||
csum_data = csum_data ^ (csum_data >> 8U);
|
||||
csum_data = csum_data ^ (csum_data >> NIBBLES_SIZE);
|
||||
|
||||
if ((csum_data & 0xFU) != 0xFU) {
|
||||
dshot_inst[channel].crc_error_cnt++;
|
||||
|
||||
} else {
|
||||
data = (data >> 4) & 0xFFF;
|
||||
|
||||
if (data == 0xFFF) {
|
||||
erpm = 0;
|
||||
|
||||
} else {
|
||||
exponent = ((data >> 9U) & 0x7U); /* 3 bit: exponent */
|
||||
period = (data & 0x1ffU); /* 9 bit: period base */
|
||||
period = period << exponent; /* Period in usec */
|
||||
erpm = ((1000000U * 60U / 100U + period / 2U) / period);
|
||||
}
|
||||
|
||||
dshot_inst[channel].erpm = erpm;
|
||||
bdshot_parsed_recv_mask |= (1 << channel);
|
||||
dshot_inst[channel].last_no_response_cnt = dshot_inst[channel].no_response_cnt;
|
||||
}
|
||||
|
||||
} else {
|
||||
dshot_inst[channel].frame_error_cnt++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
int up_bdshot_get_erpm(uint8_t channel, int *erpm)
|
||||
{
|
||||
if (bdshot_parsed_recv_mask & (1 << channel)) {
|
||||
*erpm = (int)dshot_inst[channel].erpm;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
int up_bdshot_channel_status(uint8_t channel)
|
||||
{
|
||||
if (channel < DSHOT_TIMERS) {
|
||||
return ((dshot_inst[channel].no_response_cnt - dshot_inst[channel].last_no_response_cnt) < BDSHOT_OFFLINE_COUNT);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
void up_bdshot_status(void)
|
||||
{
|
||||
|
||||
for (uint8_t channel = 0; (channel < DSHOT_TIMERS); channel++) {
|
||||
|
||||
if (dshot_inst[channel].init) {
|
||||
PX4_INFO("Channel %i %s Last erpm %i value", channel, up_bdshot_channel_status(channel) ? "online" : "offline",
|
||||
dshot_inst[channel].erpm);
|
||||
PX4_INFO("CRC errors Frame error No response");
|
||||
PX4_INFO("%10lu %11lu %11lu", dshot_inst[channel].crc_error_cnt, dshot_inst[channel].frame_error_cnt,
|
||||
dshot_inst[channel].no_response_cnt);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void up_dshot_trigger(void)
|
||||
{
|
||||
uint32_t buf_adr;
|
||||
// Calc data now since we're not event driven
|
||||
if (bdshot_recv_mask != 0x0) {
|
||||
up_bdshot_erpm();
|
||||
}
|
||||
|
||||
for (uint8_t motor_number = 0; (motor_number < DSHOT_TIMERS); motor_number++) {
|
||||
if (dshot_inst[motor_number].init && dshot_inst[motor_number].data_seg1 != 0) {
|
||||
buf_adr = flexio_s->ops->get_shifter_buffer_address(flexio_s, FLEXIO_SHIFTER_BUFFER, motor_number);
|
||||
putreg32(dshot_inst[motor_number].data_seg1, IMXRT_FLEXIO1_BASE + buf_adr);
|
||||
clear_timer_status_flags(0xFF);
|
||||
|
||||
for (uint8_t channel = 0; (channel < DSHOT_TIMERS); channel++) {
|
||||
if (dshot_inst[channel].bdshot && (bdshot_recv_mask & (1 << channel)) == 0) {
|
||||
dshot_inst[channel].no_response_cnt++;
|
||||
}
|
||||
|
||||
if (dshot_inst[channel].init && dshot_inst[channel].data_seg1 != 0) {
|
||||
flexio_putreg32(dshot_inst[channel].data_seg1, IMXRT_FLEXIO_SHIFTBUF0_OFFSET + channel * 0x4);
|
||||
}
|
||||
}
|
||||
|
||||
flexio_s->ops->clear_timer_status_flags(flexio_s, 0xFF);
|
||||
flexio_s->ops->enable_shifter_status_interrupts(flexio_s, 0xFF);
|
||||
bdshot_recv_mask = 0x0;
|
||||
|
||||
clear_timer_status_flags(0xFF);
|
||||
enable_shifter_status_interrupts(0xFF);
|
||||
enable_timer_status_interrupts(0xFF);
|
||||
}
|
||||
|
||||
/* Expand packet from 16 bits 48 to get T0H and T1H timing */
|
||||
uint64_t dshot_expand_data(uint16_t packet)
|
||||
{
|
||||
unsigned int mask;
|
||||
@@ -197,16 +506,22 @@ uint64_t dshot_expand_data(uint16_t packet)
|
||||
* bit 12 - dshot telemetry enable/disable
|
||||
* bits 13-16 - XOR checksum
|
||||
**/
|
||||
void dshot_motor_data_set(unsigned motor_number, uint16_t throttle, bool telemetry)
|
||||
void dshot_motor_data_set(unsigned channel, uint16_t throttle, bool telemetry)
|
||||
{
|
||||
if (motor_number < DSHOT_TIMERS && dshot_inst[motor_number].init) {
|
||||
if (channel < DSHOT_TIMERS && dshot_inst[channel].init) {
|
||||
uint16_t csum_data;
|
||||
uint16_t packet = 0;
|
||||
uint16_t checksum = 0;
|
||||
|
||||
packet |= throttle << DSHOT_THROTTLE_POSITION;
|
||||
packet |= ((uint16_t)telemetry & 0x01) << DSHOT_TELEMETRY_POSITION;
|
||||
|
||||
uint16_t csum_data = packet;
|
||||
if (dshot_inst[channel].bdshot) {
|
||||
csum_data = ~packet;
|
||||
|
||||
} else {
|
||||
csum_data = packet;
|
||||
}
|
||||
|
||||
/* XOR checksum calculation */
|
||||
csum_data >>= NIBBLES_SIZE;
|
||||
@@ -219,8 +534,20 @@ void dshot_motor_data_set(unsigned motor_number, uint16_t throttle, bool telemet
|
||||
packet |= (checksum & 0x0F);
|
||||
|
||||
uint64_t dshot_expanded = dshot_expand_data(packet);
|
||||
dshot_inst[motor_number].data_seg1 = (uint32_t)(dshot_expanded & 0xFFFFFF);
|
||||
dshot_inst[motor_number].irq_data = (uint32_t)(dshot_expanded >> 24);
|
||||
|
||||
dshot_inst[channel].data_seg1 = (uint32_t)(dshot_expanded & 0xFFFFFF);
|
||||
dshot_inst[channel].irq_data = (uint32_t)(dshot_expanded >> 24);
|
||||
dshot_inst[channel].state = DSHOT_START;
|
||||
|
||||
if (dshot_inst[channel].bdshot) {
|
||||
|
||||
flexio_putreg32(0x0, IMXRT_FLEXIO_TIMCTL0_OFFSET + channel * 0x4);
|
||||
disable_shifter_status_interrupts(1 << channel);
|
||||
|
||||
flexio_dshot_output(channel, timer_io_channels[channel].dshot.flexio_pin, dshot_tcmp, dshot_inst[channel].bdshot);
|
||||
|
||||
clear_timer_status_flags(0xFF);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -87,7 +87,6 @@ typedef struct io_timers_t {
|
||||
uint32_t clock_register; /* SIM_SCGCn */
|
||||
uint32_t clock_bit; /* SIM_SCGCn bit pos */
|
||||
uint32_t vectorno; /* IRQ number */
|
||||
dshot_conf_t dshot;
|
||||
} io_timers_t;
|
||||
|
||||
typedef struct io_timers_channel_mapping_element_t {
|
||||
@@ -112,6 +111,7 @@ typedef struct timer_io_channels_t {
|
||||
uint8_t sub_module; /* 0 based sub module offset */
|
||||
uint8_t sub_module_bits; /* LDOK and CLDOK bits */
|
||||
uint8_t timer_channel; /* Unused */
|
||||
dshot_conf_t dshot;
|
||||
} timer_io_channels_t;
|
||||
|
||||
#define SM0 0
|
||||
|
||||
@@ -36,7 +36,7 @@ add_subdirectory(../imxrt/adc adc)
|
||||
add_subdirectory(../imxrt/board_critmon board_critmon)
|
||||
add_subdirectory(../imxrt/board_hw_info board_hw_info)
|
||||
add_subdirectory(../imxrt/board_reset board_reset)
|
||||
#add_subdirectory(../imxrt/dshot dshot)
|
||||
add_subdirectory(../imxrt/dshot dshot)
|
||||
add_subdirectory(../imxrt/hrt hrt)
|
||||
add_subdirectory(../imxrt/led_pwm led_pwm)
|
||||
add_subdirectory(../imxrt/io_pins io_pins)
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
/****************************************************************************
|
||||
*
|
||||
* Copyright (c) 2023 PX4 Development Team. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name PX4 nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
#pragma once
|
||||
|
||||
|
||||
#include "../../../imxrt/include/px4_arch/dshot.h"
|
||||
@@ -41,6 +41,7 @@
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include "dshot.h"
|
||||
|
||||
#pragma once
|
||||
__BEGIN_DECLS
|
||||
@@ -110,6 +111,7 @@ typedef struct timer_io_channels_t {
|
||||
uint8_t sub_module; /* 0 based sub module offset */
|
||||
uint8_t sub_module_bits; /* LDOK and CLDOK bits */
|
||||
uint8_t timer_channel; /* Unused */
|
||||
dshot_conf_t dshot;
|
||||
} timer_io_channels_t;
|
||||
|
||||
#define SM0 0
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user