* Support for armv7-m_dcache control via parameter
The FORCE_F7_DCACHE parameter can be set to
0 - (default) if Eratta exits turn dcache off else leave it on
1 - Force it off
2 - Force it on
At boot the system will disable the d-cache if the silicon
has the 1259864 Data corruption in a sequence of Write-Through
stores and loads eratta.
Post nsh script execution the FORCE_F7_DCACHE paramater
will be used to set the d-cache to the state indicated
above.
I2C bus chaged I2C0 is external, I2C1 internal
Added BMM150 on I2C1 @ Addr 0x100
Added BMP280 on I2C1 @ Addr 0x76
UART0 (/dev/ttyS1) now used at Telem 2
Chip select added for W25X40CLUXIG Calibration EE prom
Driver is not added at this time
The cause of the stack detection fault is because of the
level of nesting in the start up script. We need to
determine the worst case configuration and set the
bar there.
This fault occurred some 42 calls deep due to script
calling script (repeat).
The HW stack check requires as a margin of 204 bytes. That is
ISR HW stacking of CPU(8) FPU(18) registers and SW stacking of
CPU(11) and FPU(16) registers. Total CPU(19) registers is
68 bytes and the total FPU(34) registers is 136 bytes. On
a system with a separate ISR stack This only needs to be 104
so there is 100 bytes of headroom. But as coded the detection
will give a false positive detection and fault. This does not
mean that the stack will be corrupted.
Adjustments to that stack can have no effect due to rounding.
A stack size of 2608 and 2616 can yield the exact same size stack.
So even when the failure is due to a 4 byte overflow, it can take
greater than a 16 bytes increase to fix it. Because the final
stack size is calculated with an 8 byte alignment after a 4 byte
decrease. So 2624 becomes 2620 at runtime and will boot
with SYS_AUTOSTART=4001.
Rate changes were doing an asynchronous register reload via the EGR_UG. This could extend a PWM pulse up to 2X.
This fix removes the asynchronous update. The net effect is the the rate change will occur on the next counter expiration. The worst case is the rate change is delayed by 20 Ms.
- see 1259864 Data corruption in a sequence of Write-Through stores and loads
- if we can be certain this sequence won't occur in PX4 then the d-cache will be re-enabled
usleep range was up to 2147 Seconds
Per open group: The rand() function shall compute a
sequence of pseudo-random integers in the range
[0, {RAND_MAX}] with a period of at least 2^32
{RAND_MAX} Maximum value returned by rand();
at least 32767.
/* Maximum value returned by rand(). Must be a minimum of 32767. */
#define RAND_MAX INT_MAX
and
#define INT_MAX 2147483647
* The build is built with SPI4. At run time the signal GPIO_8266_GPIO2 it tested. If it is low the SPI4 is configured. If it is high SPI4 is not configured.
* board_common: Add Notion of Board has bus manifest
Upstream changes defer the board reset based on the vaule of
CONFIG_BOARD_RESET_ON_ASSERT
0 (or not defined) Do not reset on assert
>= 1 reset if assertion is in an interrupt handler or the idle task
>= 2 on any asertion.
up_assert is called from up_hardfault or an asertion failure.
Part 1 of up_assert will call out to the board_crashdump
Part 2 on return from board_crashdump will then perform
the reset.
board_crashdump needs a chunk of ram to save the complete
context in. It uses &_sdata which is the lowest memory and
it will corrupt that memeory. We can therfore can not allow
return to the OS, as it could depend on that area of RAM.
So all boards need to do a reset at the end of board_crashdump
This updating of the driver setting is for EMI issue with GPS and FCC.
With this setting the clock is sinusoidal
N.B. sd_bench fails on SanDISK HC, but Passes SanDISK **HC1** and
Kingston cards.
****Use HC1 or Kingston cards!***
Testing done on SanDISK HC all failed sd_bench with Drive/Slew other
than default and _PIN_OUTPUT_FAST|_PIN_OUTPUT_HIGHDRIVE
_PIN_OUTPUT_FAST|_PIN_OUTPUT_HIGHDRIVE Square noisy, pass SanDISK HC
_PIN_OUTPUT_FAST|_PIN_OUTPUT_LOWDRIVE Square noisy, pass SanDISK HC
_PIN_OUTPUT_HIGHDRIVE|_PIN_OUTPUT_SLOW sinusoidal fail SanDISK HC, pass SanDISK HC1
_PIN_OUTPUT_LOWDRIVE |_PIN_OUTPUT_SLOW sinusoidal fail SanDISK HC, pass SanDISK HC1
_PIN_OUTPUT_SLOW sinusoidal fail SanDISK HC, pass SanDISK HC1
David Sidrane