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stm32 drv_io_timer: Prevent glitch on PWM outputs (#11453)

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Rate changes were doing an asynchronous register reload via the EGR_UG. This could extend a PWM pulse up to 2X.

This fix removes the asynchronous update. The net effect is the the rate change will occur on the next counter expiration. The worst case is the rate change is delayed by 20 Ms.
This commit is contained in:
David Sidrane 2019-02-18 08:08:04 -08:00 committed by Daniel Agar
parent b01e470ff9
commit 0705d6c807
1 changed files with 1 additions and 4 deletions
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5
src/drivers/stm32/drv_io_timer.c
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@ -461,12 +461,9 @@ static int allocate_channel(unsigned channel, io_timer_channel_mode_t mode)
static int timer_set_rate(unsigned timer, unsigned rate)
{
/* configure the timer to update at the desired rate */
rARR(timer) = (BOARD_PWM_FREQ / rate) - 1;
/* generate an update event; reloads the counter and all registers */
rEGR(timer) = GTIM_EGR_UG;
rARR(timer) = (BOARD_PWM_FREQ / rate) - 1;
return 0;
}