From 0705d6c807f99dbf413cf47d65f6e4444db30840 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 18 Feb 2019 08:08:04 -0800 Subject: [PATCH] stm32 drv_io_timer: Prevent glitch on PWM outputs (#11453) Rate changes were doing an asynchronous register reload via the EGR_UG. This could extend a PWM pulse up to 2X. This fix removes the asynchronous update. The net effect is the the rate change will occur on the next counter expiration. The worst case is the rate change is delayed by 20 Ms. --- src/drivers/stm32/drv_io_timer.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/drivers/stm32/drv_io_timer.c b/src/drivers/stm32/drv_io_timer.c index 2c1634e633..4f654e8a67 100644 --- a/src/drivers/stm32/drv_io_timer.c +++ b/src/drivers/stm32/drv_io_timer.c @@ -461,12 +461,9 @@ static int allocate_channel(unsigned channel, io_timer_channel_mode_t mode) static int timer_set_rate(unsigned timer, unsigned rate) { - /* configure the timer to update at the desired rate */ - rARR(timer) = (BOARD_PWM_FREQ / rate) - 1; - /* generate an update event; reloads the counter and all registers */ - rEGR(timer) = GTIM_EGR_UG; + rARR(timer) = (BOARD_PWM_FREQ / rate) - 1; return 0; }