Recent upsteam NuttX changes needed by PX4 added sem_[wait|post]
in the stm32_flash driver.
UAVCAN Bootloaders do not use the OS's scheduler etal.
This commit nops the sem_[wait|post] with linker magic.
Which precludes the linking the nuttx scheduler in the
bootloader build.
PX4 contrib from <jose.souza@intel.com>
1) stm32: Fix erase sector number for microcontrolers with
more than 11 sectors
Erase a sector from the second bank cause the bit 4 of SNB being set
but never unsed, so trying to erase a sector from the first bank
was acually eraseing a sector from the second bank.
2) stm32: Make up_progmem thread safe
Writing to a flash sector while starting the erase of other sector
have a undefined behavior so lets add a [staticaly initalized]
semaphore and syncronize access to Flash registers.
3) Add workaround for flash data cache corruption on
read-while-write
This is a know hardware issue on some STM32 see the errata
of your model and if you make use of both memory banks you
should enable it.
4) Greg's cleanup
5) PX4 clean up
stm32_flash:Need conditional on non F4 targets
* Order patch application
Per discussion with @demarchi this PR adds ordering to the
patch application.
This alos add some encoding
00000 series - is for px4 non up streamable changes
60000 (bp) series - is for back ports
90000 series - is for wip that shold make it upstream
* Restore 00010-workarround-for-flash-data-cache-corruption
Extract this from the 90000-wip-inflight-to-upstream.patch
and orders it.
* Moved upstreamed 0dbf44e flash fix to bp patch
* Moved upstreamed 5481087 cdcacm fix to bp patch
* Moved upstreamed ec85425 STM32F7 copy paste errors to bp patch
* Moved upstreamed 20e7237 HSI should not be turned off to bp patch
* Moved upstreamed ca895b9 Adding missing CONFIG_ prefix to bp patch
* Moved upstreamed 169b398 STM32: Fixes the bkp reference counter issue to bp patch
* Moved upstreamed 550d259 STM32F7: Fixes the bkp reference counter issue to bp patch
* Moved upstreamed 02825f3 STM32F3X: Add missing STM32_BKP_BASE to bp patch
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Renamed for ordering and classification
* Order Patches by Name
This reverts commit 22738b1213fff704d288ec84976fa84ff9535aba.
The command was added due to a lack of my understanding of how the pwm command can be used.
The command is not needed as the all flag can be used or a proper
mask WHIHOUT -g
fmu task mode_pwm
pwm rate -a -r 50 -d /dev/pwm_output0
pwm arm
pwm test -a -p 500
fmu task mode_pwm
pwm oneshot -a -d /dev/pwm_output0 is the same as pwm oneshot -m 0xff -d /dev/pwm_output0
pwm arm
pwm test -a -p 500
Since the Onshot<->PWM mode is changed based on rate. The
this signale the higher layers that the operation is invalid
test case:
fmu task mode_pwm2cap2
pwm oneshot -m 0xf -g 0 -d /dev/pwm_output0
should fail, because all the channels in the group are
not in the same mode.
1) Updated copyright
2) Defined BOARD overrideable BOARD_PWM_FREQ and BOARD_ONSHOT_FREQ
Not recogmended but allow experimentation
3) Solved the support for BOARD_PWM_DRIVE_ACTIVE_LOW using
the Polarity control bits as apposed to the negation of
the ARR.
4) Added a cache for getting a timers channels. This is static
and benifits from the qucik response.
5) Added a function to realocate all channes in a given timer
from one mode to another.
6) Removed the frequecy table in favor of the intended use of the
channel mode set. At it is the way to determine the mode of a
channel. Or in onshot's case a timers's complete set channels.
7) Added 2 lowlevel mode changing functions:
io_timer_set_oneshot_mode and io_timer_set_PWM_mode
that encapsalate the changes in mode to one place
in the code.
8) Added io_timer_trigger (the up_pwm_update) with low
latancy timer to time in updating.
9) io_timer_set_rate - use sets to enforce all or none
rules for switching PWM<->OneShot.
Onshot is entered using the very approriate rate of 0.
Only deltas will change the HW state.
1) Define IOTimerChanMode_OneShot
2) Added detailed commnent on .clock_freq and how it is used
3) Added single additional API point in support of Onshot mode
io_timer_trigger - That trigger all timer's channels in Oneshot
mode to fire the oneshots with updated values.
1) Validate timer paramater before using it.
2) Allow rate of 0 to enter Oneshot mode
At first blush this seamed like a hack, but at Mark
pointed out to me, Onshot PWM does not have a rate
So this is a realy a clever and beautiful simplification
on his part!
3) Exposes up_pwm_update that runs io_timer_trigger
Which trigger all timer's channels in Oneshot mode to
fire the oneshots with updated values.
The fmu now support the commandline option to be run as a task
or off a work queue.
This reverts the board_config.h changes from commit
e33af23122f5ee3030bb9745bbbf616b24c2a14a.
Conflicts:
src/drivers/px4fmu/fmu.cpp
change fmu to task
increase fmu_servo task priority to max and enable true oneshot
use lowest FMU priority which minimizes jitter
constrain oneshot updates to control group 0 events
* Backport:stm32f7: stm32_allocateheap: allow use DTCM memory for heap
Back port of upstrem contrib by Jussi Kivilinna <jussi.kivilinna@haltian.com>
stm32f7: stm32_allocateheap: allow use DTCM memory for heap
STM32F7 has up to 128KiB of DTCM memory that is currently left unused.
This patch adds DTCM to main heap if CONFIG_STM32F7_DTCMEXCLUDE is not enabled.
* px4fmu-v5_default:Enable inclusion of the DTCM in the heap
CONFIG_MM_REGIONS=3 adds the DTCM region to the heap.
