HACK to enable actuators in HITL

Mixers get loaded on normal output modules
the first actuator_outputs instance gets sent
to the simulator. No lockdown but the rest of
HIL stays.

.ci/Jenkinsfile-hardware

@@ -809,6 +809,9 @@ void runTests() {
   sh './Tools/HIL/run_nsh_cmd.py --device `find /dev/serial -name *usb-*` --cmd "top once"'
   sh './Tools/HIL/run_nsh_cmd.py --device `find /dev/serial -name *usb-*` --cmd "work_queue status"'
 
+  sh './Tools/HIL/run_nsh_cmd.py --device `find /dev/serial -name *usb-*` --cmd "ostest"'
+  sh './Tools/HIL/reboot.py --device `find /dev/serial -name *usb-*`' // reboot after ostest
+
   sh './Tools/HIL/run_nsh_cmd.py --device `find /dev/serial -name *usb-*` --cmd "commander_tests" || true'
   sh './Tools/HIL/run_nsh_cmd.py --device `find /dev/serial -name *usb-*` --cmd "controllib_test"'
   sh './Tools/HIL/run_nsh_cmd.py --device `find /dev/serial -name *usb-*` --cmd "lightware_laser_test"'

.vscode/settings.json

@@ -126,8 +126,6 @@
         },
         "search.showLineNumbers": true,
         "telemetry.enableTelemetry": false,
-        "terminal.integrated.copyOnSelection": true,
-        "terminal.integrated.rightClickBehavior": "paste",
         "terminal.integrated.scrollback": 5000,
         "window.title": "${dirty} ${activeEditorMedium}${separator}${rootName}",
         "workbench.editor.highlightModifiedTabs": true,

Makefile

@@ -331,7 +331,7 @@ px4io_update: px4_io-v2_default cubepilot_io-v2_default
 	cp build/cubepilot_io-v2_default/cubepilot_io-v2_default.bin boards/cubepilot/cubeyellow/extras/cubepilot_io-v2_default.bin
 	git status
 
-bootloaders_update: cuav_nora_bootloader cuav_x7pro_bootloader cubepilot_cubeorange_bootloader holybro_durandal-v1_bootloader matek_h743_bootloader matek_h743-mini_bootloader matek_h743-slim_bootloader modalai_fc-v2_bootloader mro_ctrl-zero-classic_bootloader mro_ctrl-zero-h7_bootloader mro_ctrl-zero-h7-oem_bootloader mro_pixracerpro_bootloader px4_fmu-v6u_bootloader px4_fmu-v6x_bootloader
+bootloaders_update: cuav_nora_bootloader cuav_x7pro_bootloader cubepilot_cubeorange_bootloader holybro_durandal-v1_bootloader holybro_kakuteh7_bootloader matek_h743_bootloader matek_h743-mini_bootloader matek_h743-slim_bootloader modalai_fc-v2_bootloader mro_ctrl-zero-classic_bootloader mro_ctrl-zero-h7_bootloader mro_ctrl-zero-h7-oem_bootloader mro_pixracerpro_bootloader px4_fmu-v6c_bootloader px4_fmu-v6u_bootloader px4_fmu-v6x_bootloader
 	git status
 
 .PHONY: coverity_scan

ROMFS/cannode/CMakeLists.txt

@@ -32,4 +32,3 @@
 ############################################################################
 
 add_subdirectory(init.d)
-add_subdirectory(mixers)

ROMFS/cannode/init.d/CMakeLists.txt

@@ -33,5 +33,4 @@
 
 px4_add_romfs_files(
 	rcS
-	rc.output_defaults
 )

ROMFS/cannode/init.d/rc.output_defaults

@@ -1,32 +0,0 @@
-#!/bin/sh
-#
-# UGV default parameters.
-#
-# NOTE: Script variables are declared/initialized/unset in the rcS script.
-#
-
-#
-# Enable servo output on pins 3 and 4 (steering and thrust)
-# but also include 1+2 as they form together one output group
-# and need to be set together.
-#
-set PWM_OUT 12
-
-#
-# PWM Hz - 50 Hz is the normal rate in RC cars, higher rates
-# may damage analog servos.
-#
-set PWM_MAIN_RATE 50
-
-#
-# This is the gimbal pass mixer.
-#
-set MIXER_AUX pass
-set PWM_AUX_OUT 12
-
-param set-default PWM_MAIN_DISARM 1500
-param set-default PWM_MAIN_MAX 2000
-param set-default PWM_MAIN_MIN 1000
-
-# Set mixer
-set MIXER IO_pass_ucan

ROMFS/cannode/init.d/rcS

@@ -65,8 +65,8 @@ unset BOARD_RC_DEFAULTS
 #
 # Start system state indicator.
 #
-#rgbled start -X -q
-#rgbled_ncp5623c start -X -q
+rgbled start -X -q
+rgbled_ncp5623c start -X -q
 
 #
 # board sensors: rc.sensors
@@ -86,10 +86,10 @@ unset BOARD_RC_SENSORS
 . ${R}etc/init.d/rc.serial
 
 # Check for flow sensor
-#if param compare SENS_EN_PX4FLOW 1
-#then
-#	px4flow start -X &
-#fi
+if param compare SENS_EN_PX4FLOW 1
+then
+	px4flow start -X &
+fi
 
-#uavcannode start
+uavcannode start
 unset R

ROMFS/cannode/mixers/CMakeLists.txt

@@ -1,36 +0,0 @@
-############################################################################
-#
-#   Copyright (c) 2018 PX4 Development Team. All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name PX4 nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-px4_add_romfs_files(
-	IO_pass_ucan.main.mix
-)

ROMFS/cannode/mixers/IO_pass_ucan.main.mix

@@ -1,12 +0,0 @@
-Passthrough mixer for PX4IO
-============================
-
-This file defines passthrough mixers suitable for testing.
-
-Channel group 0, channels 0-7 are passed directly through to the outputs.
-
-M: 1
-S: 0 0  10000  10000      0 -10000  10000
-
-M: 1
-S: 0 1  10000  10000      0 -10000  10000

ROMFS/px4fmu_common/init.d-posix/airframes/10019_omnicopter

@@ -0,0 +1,101 @@
+#!/bin/sh
+#
+# @name 6DoF Omnicopter SITL
+#
+# @type Quadrotor Wide
+#
+# @maintainer Jaeyoung Lim <jalim@ethz.ch>
+#
+
+. ${R}etc/init.d/rc.mc_defaults
+
+param set-default SYS_CTRL_ALLOC 1
+
+
+param set-default CA_AIRFRAME 0
+
+param set-default CA_ROTOR_COUNT 8
+param set-default CA_R_REV 255
+
+param set-default CA_ROTOR0_PX 0.14435
+param set-default CA_ROTOR0_PY -0.14435
+param set-default CA_ROTOR0_PZ -0.14435
+param set-default CA_ROTOR0_KM 0.05 # CCW
+param set-default CA_ROTOR0_AX -0.788675
+param set-default CA_ROTOR0_AY -0.211325
+param set-default CA_ROTOR0_AZ -0.57735
+
+param set-default CA_ROTOR1_PX -0.14435
+param set-default CA_ROTOR1_PY -0.14435
+param set-default CA_ROTOR1_PZ -0.14435
+param set-default CA_ROTOR1_KM 0.05
+param set-default CA_ROTOR1_AX 0.211325
+param set-default CA_ROTOR1_AY -0.788675
+param set-default CA_ROTOR1_AZ 0.57735
+
+param set-default CA_ROTOR2_PX 0.14435
+param set-default CA_ROTOR2_PY 0.14435
+param set-default CA_ROTOR2_PZ -0.14435
+param set-default CA_ROTOR2_KM 0.05
+param set-default CA_ROTOR2_AX -0.211325
+param set-default CA_ROTOR2_AY 0.788675
+param set-default CA_ROTOR2_AZ 0.57735
+
+param set-default CA_ROTOR3_PX -0.14435
+param set-default CA_ROTOR3_PY 0.14435
+param set-default CA_ROTOR3_PZ -0.14435
+param set-default CA_ROTOR3_KM 0.05
+param set-default CA_ROTOR3_AX 0.788675
+param set-default CA_ROTOR3_AY 0.211325
+param set-default CA_ROTOR3_AZ -0.57735
+
+param set-default CA_ROTOR4_PX 0.14435
+param set-default CA_ROTOR4_PY -0.14435
+param set-default CA_ROTOR4_PZ 0.14435
+param set-default CA_ROTOR4_KM 0.05
+param set-default CA_ROTOR4_AX 0.788675
+param set-default CA_ROTOR4_AY 0.211325
+param set-default CA_ROTOR4_AZ -0.57735
+
+param set-default CA_ROTOR5_PX -0.14435
+param set-default CA_ROTOR5_PY -0.14435
+param set-default CA_ROTOR5_PZ 0.14435
+param set-default CA_ROTOR5_KM 0.05
+param set-default CA_ROTOR5_AX -0.211325
+param set-default CA_ROTOR5_AY 0.788675
+param set-default CA_ROTOR5_AZ 0.57735
+
+param set-default CA_ROTOR6_PX 0.14435
+param set-default CA_ROTOR6_PY 0.14435
+param set-default CA_ROTOR6_PZ 0.14435
+param set-default CA_ROTOR6_KM 0.05
+param set-default CA_ROTOR6_AX 0.211325
+param set-default CA_ROTOR6_AY -0.788675
+param set-default CA_ROTOR6_AZ 0.57735
+
+param set-default CA_ROTOR7_PX -0.14435
+param set-default CA_ROTOR7_PY 0.14435
+param set-default CA_ROTOR7_PZ 0.14435
+param set-default CA_ROTOR7_KM 0.05
+param set-default CA_ROTOR7_AX -0.788675
+param set-default CA_ROTOR7_AY -0.211325
+param set-default CA_ROTOR7_AZ -0.57735
+
+param set-default PWM_MAIN_FUNC1 101
+param set-default PWM_MAIN_FUNC2 102
+param set-default PWM_MAIN_FUNC3 103
+param set-default PWM_MAIN_FUNC4 104
+param set-default PWM_MAIN_FUNC5 105
+param set-default PWM_MAIN_FUNC6 106
+param set-default PWM_MAIN_FUNC7 107
+param set-default PWM_MAIN_FUNC8 108
+
+# disable MC desaturation which improves attitude tracking
+param set-default CA_METHOD 0
+
+# disable attitude failure detection
+param set-default FD_FAIL_P 0
+param set-default FD_FAIL_R 0
+
+set MIXER skip
+set MIXER_AUX none

ROMFS/px4fmu_common/init.d-posix/airframes/10040_quadx

@@ -0,0 +1,23 @@
+#!/bin/sh
+#
+# @name QuadrotorX SITL for SIH
+#
+# @type Quadrotor
+#
+# @maintainer Romain Chiappinelli <romain.chiap@gmail.com>
+#
+
+. ${R}etc/init.d/rc.mc_defaults
+
+set MIXER quad_x
+
+# disable some checks to allow to fly:
+# - with usb
+param set-default CBRK_USB_CHK 197848
+# - without real battery
+param set-default CBRK_SUPPLY_CHK 894281
+# - without safety switch
+param set-default COM_PREARM_MODE 0
+param set-default CBRK_IO_SAFETY 22027
+
+param set SIH_VEHICLE_TYPE 0

ROMFS/px4fmu_common/init.d-posix/airframes/10041_airplane

@@ -0,0 +1,33 @@
+#!/bin/sh
+#
+# @name Plane SITL for SIH
+#
+# @type Plane
+#
+# @maintainer Romain Chiappinelli <romain.chiap@gmail.com>
+
+. ${R}etc/init.d/rc.fw_defaults
+
+set MIXER AERT
+
+# disable some checks to allow to fly:
+# - with usb
+param set-default CBRK_USB_CHK 197848
+# - without real battery
+param set-default CBRK_SUPPLY_CHK 894281
+# - without safety switch
+param set-default COM_PREARM_MODE 0
+param set-default CBRK_IO_SAFETY 22027
+
+param set-default BAT_N_CELLS 3
+
+param set SIH_T_MAX 6.0
+param set SIH_MASS 0.3
+param set SIH_IXX 0.00402
+param set SIH_IYY 0.0144
+param set SIH_IZZ 0.0177
+param set SIH_IXZ 0.00046
+param set SIH_KDV 0.2
+
+param set SIH_VEHICLE_TYPE 1 	# sih as fixed wing
+param set RWTO_TKOFF 1  # enable takeoff from runway (as opposed to launched)

ROMFS/px4fmu_common/init.d-posix/airframes/10042_xvert

@@ -0,0 +1,45 @@
+#!/bin/sh
+#
+# @name SIH Tailsitter Duo
+#
+# @type VTOL
+#
+# @maintainer Romain Chiappinelli <romain.chiap@gmail.com>
+
+. ${R}etc/init.d/rc.vtol_defaults
+
+param set-default VT_ELEV_MC_LOCK 0
+param set-default VT_TYPE 0
+param set-default VT_FW_DIFTHR_EN 1
+param set-default VT_FW_DIFTHR_SC 0.3
+param set-default MPC_MAN_Y_MAX 60
+param set-default MC_PITCH_P 5
+
+param set-default MAV_TYPE 19
+set MAV_TYPE 19
+set MIXER vtol_tailsitter_duo_sat
+
+# disable some checks to allow to fly:
+# - with usb
+param set-default CBRK_USB_CHK 197848
+# - without real battery
+param set-default CBRK_SUPPLY_CHK 894281
+# - without safety switch
+param set-default COM_PREARM_MODE 0
+param set-default CBRK_IO_SAFETY 22027
+
+param set-default BAT_N_CELLS 3
+
+param set SIH_T_MAX 2.0
+param set SIH_Q_MAX 0.0165
+param set SIH_MASS 0.2
+# IXX and IZZ are inverted from the thesis as the body frame is pitched by 90 deg
+param set SIH_IXX 0.00354
+param set SIH_IYY 0.000625
+param set SIH_IZZ 0.00300
+param set SIH_IXZ 0.0
+param set SIH_KDV 0.2
+param set SIH_L_ROLL 0.145
+
+# sih as tailsitter
+param set SIH_VEHICLE_TYPE 2

ROMFS/px4fmu_common/init.d-posix/airframes/CMakeLists.txt

@@ -35,8 +35,12 @@ px4_add_romfs_files(
 	10016_iris
 	10017_iris_ctrlalloc
 	10018_iris_foggy_lidar
+	10019_omnicopter
 	10020_if750a
 	10030_px4vision
+	10040_quadx
+	10041_airplane
+	10042_xvert
 	1010_iris_opt_flow
 	1010_iris_opt_flow.post
 	1011_iris_irlock

ROMFS/px4fmu_common/init.d-posix/px4-rc.mavlink

@@ -30,3 +30,12 @@ mavlink start -x -u $udp_onboard_payload_port_local -r 4000 -f -m onboard -o $ud
 
 # Onboard link to gimbal
 mavlink start -x -u $udp_onboard_gimbal_port_local -r 400000 -m gimbal -o $udp_onboard_gimbal_port_remote
+
+# To display for SIH sitl
+if [ "$SIM_MODE" = "sihsim" ]; then
+	udp_sihsim_port_local=$((19450+px4_instance))
+	udp_sihsim_port_remote=$((19410+px4_instance))
+	mavlink start -x -u $udp_sihsim_port_local -r 400000 -m custom -o $udp_sihsim_port_remote
+	mavlink stream -r 200 -s HIL_ACTUATOR_CONTROLS -u  $udp_sihsim_port_local
+	mavlink stream -r 25 -s HIL_STATE_QUATERNION -u  $udp_sihsim_port_local
+fi

ROMFS/px4fmu_common/init.d-posix/rcS

@@ -154,6 +154,8 @@ param set-default SDLOG_DIRS_MAX 7
 
 param set-default TRIG_INTERFACE 3
 
+param set-default SYS_FAILURE_EN 1
+
 # Adapt timeout parameters if simulation runs faster or slower than realtime.
 if [ -n "$PX4_SIM_SPEED_FACTOR" ]; then
 	COM_DL_LOSS_T_LONGER=$(echo "$PX4_SIM_SPEED_FACTOR * 10" | bc)
@@ -202,8 +204,11 @@ param set IMU_INTEG_RATE 250
 . px4-rc.params
 
 dataman start
+# start sih in sih_sim mode, otherwise simulator module
+if [ "$SIM_MODE" = "sihsim" ]; then
+	sih start
 # only start the simulator if not in replay mode, as both control the lockstep time
-if ! replay tryapplyparams
+elif ! replay tryapplyparams
 then
   . px4-rc.simulator
 fi

ROMFS/px4fmu_common/init.d/CMakeLists.txt

@@ -55,5 +55,4 @@ px4_add_romfs_files(
 	rc.vehicle_setup
 	rc.vtol_apps
 	rc.vtol_defaults
-	rc.output_defaults
 )

ROMFS/px4fmu_common/init.d/airframes/22222_generic_output

@@ -1,21 +0,0 @@
-#!/bin/sh
-#
-# @name Generic Output
-#
-# @maintainer
-#
-# @board bitcraze_crazyflie exclude
-#
-
-. ${R}etc/init.d/rc.output_defaults
-
-
-# Provide ESC a constant 1500 us pulse
-param set-default PWM_MAIN_DISARM 1500
-param set-default PWM_MAIN_MAX 2000
-param set-default PWM_MAIN_MIN 1000
-
-# Set mixer
-set MIXER IO_pass
-
-set PWM_OUT 12

ROMFS/px4fmu_common/init.d/airframes/CMakeLists.txt

@@ -147,7 +147,7 @@ px4_add_romfs_files(
 	18001_TF-B1
 
 	# [22000, 22999] Reserve for custom models
-	22222_generic_output
+
 	24001_dodeca_cox
 
 	50000_generic_ground_vehicle

ROMFS/px4fmu_common/init.d/rc.interface

@@ -188,16 +188,7 @@ then
 
 	if [ $MIXER_AUX_FILE != none ]
 	then
-		# Append aux mixer to main device.
-		if param greater SYS_HITL 0
-		then
-			if mixer append ${OUTPUT_DEV} ${MIXER_AUX_FILE}
-			then
-				echo "INFO  [init] Mixer: ${MIXER_AUX_FILE} appended to ${OUTPUT_DEV}"
-			else
-				echo "ERROR  [init] Failed appending mixer: ${MIXER_AUX_FILE}"
-			fi
-		fi
+		# Enable actuators in HITL
 		if [ -e $OUTPUT_AUX_DEV -a $OUTPUT_MODE != hil ]
 		then
 			if mixer load ${OUTPUT_AUX_DEV} ${MIXER_AUX_FILE}

ROMFS/px4fmu_common/init.d/rc.output_defaults

@@ -1,25 +0,0 @@
-#!/bin/sh
-#
-# UGV default parameters.
-#
-# NOTE: Script variables are declared/initialized/unset in the rcS script.
-#
-
-#
-# Enable servo output on pins 3 and 4 (steering and thrust)
-# but also include 1+2 as they form together one output group
-# and need to be set together.
-#
-set PWM_OUT 12
-
-#
-# PWM Hz - 50 Hz is the normal rate in RC cars, higher rates
-# may damage analog servos.
-#
-set PWM_MAIN_RATE 50
-
-#
-# This is the gimbal pass mixer.
-#
-set MIXER_AUX pass
-set PWM_AUX_OUT 12

Tools/HIL/run_nsh_cmd.py

@@ -95,7 +95,7 @@ def do_nsh_cmd(port_url, baudrate, cmd):
 
 
     timeout_start = time.monotonic()
-    timeout = 240 # 4 minutes
+    timeout = 600 # 10 minutes
 
     return_code = 0
 

Tools/flash_nxp/flash_ucan.jlink

@@ -1,7 +0,0 @@
-if SWD
-speed 1000
-r
-loadbin /Users/landon/git/px4/build/nxp_ucans32k146_nxp_demo/deploy/34.bin,0x6000
-r
-g
-q

Tools/flash_nxp/flash_ucan.sh

@@ -1,3 +0,0 @@
-#!/bin/zsh
-
-JLinkExe -device S32K146 -CommandFile /Users/landon/git/px4/Tools/flash_nxp/flash_ucan.jlink

Tools/jmavsim_run.sh

@@ -5,12 +5,13 @@ set -e
 SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
 cd "$SCRIPT_DIR/jMAVSim"
 
-tcp_port=4560
+port=4560
 extra_args=
 baudrate=921600
 device=
 ip="127.0.0.1"
-while getopts ":b:d:p:qsr:f:i:loat" opt; do
+protocol="tcp"
+while getopts ":b:d:u:p:qsr:f:i:loat" opt; do
 	case $opt in
 		b)
 			baudrate=$OPTARG
@@ -18,11 +19,14 @@ while getopts ":b:d:p:qsr:f:i:loat" opt; do
 		d)
 			device="$OPTARG"
 			;;
+		u)
+			protocol="udp"
+			;;
 		i)
 			ip="$OPTARG"
 			;;
 		p)
-			tcp_port=$OPTARG
+			port=$OPTARG
 			;;
 		q)
 			extra_args="$extra_args -qgc"
@@ -53,7 +57,11 @@ while getopts ":b:d:p:qsr:f:i:loat" opt; do
 done
 
 if [ "$device" == "" ]; then
-	device="-tcp $ip:$tcp_port"
+	if [ "$protocol" == "tcp" ]; then
+		device="-tcp $ip:$port"
+	else
+		device="-udp $port"
+	fi
 else
 	device="-serial $device $baudrate"
 fi

Tools/sitl_run.sh

@@ -74,6 +74,9 @@ if [ "$model" == "" ] || [ "$model" == "none" ]; then
 	if [ "$program" == "jsbsim" ]; then
 		echo "empty model, setting rascal as default for jsbsim"
 		model="rascal"
+	elif [ "$program" == "sihsim" ]; then
+		echo "empty model, setting quadx as default for sihsim"
+		model="quadx"
 	else
 		echo "empty model, setting iris as default"
 		model="iris"
@@ -214,6 +217,12 @@ elif [ "$program" == "jsbsim" ] && [ -z "$no_sim" ]; then
 	fi
 	"${build_path}/build_jsbsim_bridge/jsbsim_bridge" ${model} -s "${src_path}/Tools/jsbsim_bridge/scene/${world}.xml" 2> /dev/null &
 	JSBSIM_PID=$!
+elif [ "$program" == "sihsim" ] && [ ! -n "$no_sim" ]; then
+	export SIM_MODE="sihsim"
+	if [ "$model" != "airplane" ] && [ "$model" != "quadx" ] && [ "$model" != "xvert" ]; then
+		echo "Model ${model} not compatible with with sih. sih supports [quadx,airplane,xvert]."
+		exit 1
+	fi
 fi
 
 pushd "$rootfs" >/dev/null

boards/airmind/mindpx-v2/nuttx-config/nsh/defconfig

@@ -130,8 +130,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDIO_BLOCKSETUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
@@ -174,7 +173,7 @@ CONFIG_STM32_SPI1=y
 CONFIG_STM32_SPI2=y
 CONFIG_STM32_SPI4=y
 CONFIG_STM32_SPI4_DMA=y
-CONFIG_STM32_SPI4_DMA_BUFFER=1024
+CONFIG_STM32_SPI4_DMA_BUFFER=512
 CONFIG_STM32_SPI_DMA=y
 CONFIG_STM32_SPI_DMATHRESHOLD=8
 CONFIG_STM32_TIM10=y

boards/ark/can-flow/nuttx-config/nsh/defconfig

@@ -105,8 +105,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/ark/can-gps/nuttx-config/nsh/defconfig

@@ -107,8 +107,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/ark/can-rtk-gps/nuttx-config/nsh/defconfig

@@ -107,8 +107,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/ark/cannode/nuttx-config/nsh/defconfig

@@ -107,8 +107,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/atl/mantis-edu/nuttx-config/nsh/defconfig

@@ -140,8 +140,7 @@ CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_MODE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/av/x-v1/nuttx-config/nsh/defconfig

@@ -162,8 +162,7 @@ CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_MODE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/bitcraze/crazyflie/nuttx-config/nsh/defconfig

@@ -126,8 +126,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/bitcraze/crazyflie21/nuttx-config/nsh/defconfig

@@ -125,8 +125,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/cuav/can-gps-v1/nuttx-config/nsh/defconfig

@@ -108,8 +108,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/cuav/nora/nuttx-config/nsh/defconfig

@@ -139,8 +139,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/cuav/nora/nuttx-config/scripts/script.ld

@@ -111,6 +111,7 @@ MEMORY
 {
 	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
 	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
 	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
 	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
 	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
@@ -186,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > AXI_SRAM AT > FLASH
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);

boards/cuav/x7pro/nuttx-config/nsh/defconfig

@@ -60,6 +60,7 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_FIFO_SIZE=0
 CONFIG_DEV_PIPE_MAXSIZE=1024
 CONFIG_DEV_PIPE_SIZE=70
+CONFIG_DISABLE_MQUEUE=y
 CONFIG_EXAMPLES_CALIB_UDELAY=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FAT_DMAMEMORY=y
@@ -138,8 +139,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/cuav/x7pro/nuttx-config/scripts/script.ld

@@ -111,6 +111,7 @@ MEMORY
 {
 	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
 	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
 	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
 	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
 	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
@@ -186,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > AXI_SRAM AT > FLASH
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);

boards/cuav/x7pro/nuttx-config/test/defconfig

@@ -0,0 +1,245 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_DISABLE_ENVIRON is not set
+# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_MMCSD_HAVE_CARDDETECT is not set
+# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set
+# CONFIG_MMCSD_MMCSUPPORT is not set
+# CONFIG_MMCSD_SPI is not set
+# CONFIG_NSH_DISABLEBG is not set
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLE_DF is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXIT is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_ITEF is not set
+# CONFIG_NSH_DISABLE_LOOPS is not set
+# CONFIG_NSH_DISABLE_MKFATFS is not set
+# CONFIG_NSH_DISABLE_SEMICOLON is not set
+# CONFIG_NSH_DISABLE_TIME is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD_CUSTOM=y
+CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/cuav/x7pro/nuttx-config"
+CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
+CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32H743XI=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_INTERRUPTSTACK=512
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_BASEPRI_WAR=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_MEMCPY=y
+CONFIG_ARMV7M_USEBASEPRI=y
+CONFIG_ARM_MPU_EARLY_RESET=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_CRASHDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=95150
+CONFIG_BOARD_RESET_ON_ASSERT=2
+CONFIG_BUILTIN=y
+CONFIG_C99_BOOL8=y
+CONFIG_CDCACM=y
+CONFIG_CDCACM_IFLOWCONTROL=y
+CONFIG_CDCACM_PRODUCTID=0x004c
+CONFIG_CDCACM_PRODUCTSTR="PX4 CUAV X7Pro"
+CONFIG_CDCACM_RXBUFSIZE=600
+CONFIG_CDCACM_TXBUFSIZE=12000
+CONFIG_CDCACM_VENDORID=0x3163
+CONFIG_CDCACM_VENDORSTR="CUAV"
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_HARDFAULT_ALERT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEFAULT_SMALL=y
+CONFIG_DEV_FIFO_SIZE=0
+CONFIG_DEV_PIPE_MAXSIZE=1024
+CONFIG_DEV_PIPE_SIZE=70
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_EXAMPLES_CALIB_UDELAY=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_FAT_DMAMEMORY=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FAT_LFN=y
+CONFIG_FAT_LFN_ALIAS_HASH=y
+CONFIG_FDCLONE_STDIO=y
+CONFIG_FS_BINFS=y
+CONFIG_FS_CROMFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FATTIME=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_INCLUDE_PROGMEM=y
+CONFIG_FS_PROCFS_MAX_TASKS=64
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_FS_ROMFS=y
+CONFIG_GRAN=y
+CONFIG_GRAN_INTR=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2C_RESET=y
+CONFIG_IDLETHREAD_STACKSIZE=750
+CONFIG_LIBC_LONG_LONG=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_MEMSET_64BIT=y
+CONFIG_MEMSET_OPTSPEED=y
+CONFIG_MMCSD=y
+CONFIG_MMCSD_SDIO=y
+CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y
+CONFIG_MM_REGIONS=4
+CONFIG_MTD=y
+CONFIG_MTD_BYTE_WRITE=y
+CONFIG_MTD_PARTITION=y
+CONFIG_MTD_PROGMEM=y
+CONFIG_MTD_RAMTRON=y
+CONFIG_NAME_MAX=40
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_ARGCAT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_CMDPARMS=y
+CONFIG_NSH_CROMFSETC=y
+CONFIG_NSH_DISABLE_IFCONFIG=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_DISABLE_TELNETD=y
+CONFIG_NSH_LINELEN=128
+CONFIG_NSH_MAXARGUMENTS=15
+CONFIG_NSH_NESTDEPTH=8
+CONFIG_NSH_QUOTE=y
+CONFIG_NSH_ROMFSETC=y
+CONFIG_NSH_ROMFSSECTSIZE=128
+CONFIG_NSH_STRERROR=y
+CONFIG_NSH_VARS=y
+CONFIG_OTG_ID_GPIO_DISABLE=y
+CONFIG_PIPES=y
+CONFIG_PREALLOC_TIMERS=50
+CONFIG_PRIORITY_INHERITANCE=y
+CONFIG_PTHREAD_MUTEX_ROBUST=y
+CONFIG_PTHREAD_STACK_MIN=512
+CONFIG_RAMTRON_SETSPEED=y
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_RTC_DATETIME=y
+CONFIG_SCHED_ATEXIT=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_HPWORKPRIORITY=249
+CONFIG_SCHED_HPWORKSTACKSIZE=1280
+CONFIG_SCHED_INSTRUMENTATION=y
+CONFIG_SCHED_INSTRUMENTATION_EXTERNAL=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_LPWORKPRIORITY=50
+CONFIG_SCHED_LPWORKSTACKSIZE=1632
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SDMMC1_SDIO_PULLUP=y
+CONFIG_SEM_PREALLOCHOLDERS=32
+CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
+CONFIG_SERIAL_TERMIOS=y
+CONFIG_SIG_DEFAULT=y
+CONFIG_SIG_SIGALRM_ACTION=y
+CONFIG_SIG_SIGUSR1_ACTION=y
+CONFIG_SIG_SIGUSR2_ACTION=y
+CONFIG_SIG_SIGWORK=4
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=30
+CONFIG_START_MONTH=11
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STM32H7_ADC1=y
+CONFIG_STM32H7_ADC3=y
+CONFIG_STM32H7_BBSRAM=y
+CONFIG_STM32H7_BBSRAM_FILES=5
+CONFIG_STM32H7_BDMA=y
+CONFIG_STM32H7_BKPSRAM=y
+CONFIG_STM32H7_DMA1=y
+CONFIG_STM32H7_DMA2=y
+CONFIG_STM32H7_DMACAPABLE=y
+CONFIG_STM32H7_FLOWCONTROL_BROKEN=y
+CONFIG_STM32H7_I2C1=y
+CONFIG_STM32H7_I2C2=y
+CONFIG_STM32H7_I2C3=y
+CONFIG_STM32H7_I2C4=y
+CONFIG_STM32H7_I2C_DYNTIMEO=y
+CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP=10
+CONFIG_STM32H7_OTGFS=y
+CONFIG_STM32H7_PROGMEM=y
+CONFIG_STM32H7_RTC=y
+CONFIG_STM32H7_RTC_HSECLOCK=y
+CONFIG_STM32H7_RTC_MAGIC_REG=1
+CONFIG_STM32H7_SAVE_CRASHDUMP=y
+CONFIG_STM32H7_SDMMC1=y
+CONFIG_STM32H7_SERIALBRK_BSDCOMPAT=y
+CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
+CONFIG_STM32H7_SPI1=y
+CONFIG_STM32H7_SPI1_DMA=y
+CONFIG_STM32H7_SPI1_DMA_BUFFER=1024
+CONFIG_STM32H7_SPI2=y
+CONFIG_STM32H7_SPI4=y
+CONFIG_STM32H7_SPI4_DMA=y
+CONFIG_STM32H7_SPI4_DMA_BUFFER=1024
+CONFIG_STM32H7_SPI5=y
+CONFIG_STM32H7_SPI6=y
+CONFIG_STM32H7_SPI6_DMA=y
+CONFIG_STM32H7_SPI6_DMA_BUFFER=1024
+CONFIG_STM32H7_SPI_DMA=y
+CONFIG_STM32H7_TIM12=y
+CONFIG_STM32H7_TIM15=y
+CONFIG_STM32H7_TIM1=y
+CONFIG_STM32H7_TIM3=y
+CONFIG_STM32H7_TIM4=y
+CONFIG_STM32H7_TIM5=y
+CONFIG_STM32H7_TIM8=y
+CONFIG_STM32H7_UART4=y
+CONFIG_STM32H7_UART7=y
+CONFIG_STM32H7_UART8=y
+CONFIG_STM32H7_USART1=y
+CONFIG_STM32H7_USART2=y
+CONFIG_STM32H7_USART6=y
+CONFIG_STM32H7_USART_BREAKS=y
+CONFIG_STM32H7_USART_INVERT=y
+CONFIG_STM32H7_USART_SINGLEWIRE=y
+CONFIG_STM32H7_USART_SWAP=y
+CONFIG_SYSTEM_CDCACM=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=24
+CONFIG_TESTING_OSTEST=y
+CONFIG_TESTING_OSTEST_FPUTESTDISABLE=y
+CONFIG_TESTING_OSTEST_STACKSIZE=10240
+CONFIG_TTY_SIGINT=y
+CONFIG_TTY_SIGTSTP=y
+CONFIG_UART4_BAUD=57600
+CONFIG_UART4_RXBUFSIZE=600
+CONFIG_UART4_TXBUFSIZE=1500
+CONFIG_UART7_BAUD=57600
+CONFIG_UART7_RXBUFSIZE=600
+CONFIG_UART7_SERIAL_CONSOLE=y
+CONFIG_UART7_TXBUFSIZE=1500
+CONFIG_UART8_BAUD=57600
+CONFIG_UART8_RXBUFSIZE=600
+CONFIG_UART8_TXBUFSIZE=1500
+CONFIG_USART1_BAUD=57600
+CONFIG_USART1_RXBUFSIZE=600
+CONFIG_USART1_TXBUFSIZE=1500
+CONFIG_USART2_BAUD=57600
+CONFIG_USART2_IFLOWCONTROL=y
+CONFIG_USART2_OFLOWCONTROL=y
+CONFIG_USART2_RXBUFSIZE=600
+CONFIG_USART2_TXBUFSIZE=1500
+CONFIG_USART6_BAUD=57600
+CONFIG_USART6_IFLOWCONTROL=y
+CONFIG_USART6_OFLOWCONTROL=y
+CONFIG_USART6_RXBUFSIZE=600
+CONFIG_USART6_TXBUFSIZE=1500
+CONFIG_USBDEV=y
+CONFIG_USBDEV_BUSPOWERED=y
+CONFIG_USBDEV_MAXPOWER=500
+CONFIG_USEC_PER_TICK=1000
+CONFIG_USERMAIN_STACKSIZE=2944
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WATCHDOG=y

boards/cubepilot/cubeorange/nuttx-config/nsh/defconfig

@@ -140,8 +140,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/cubepilot/cubeorange/nuttx-config/scripts/script.ld

@@ -187,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > AXI_SRAM AT > FLASH
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);

boards/cubepilot/cubeorange/nuttx-config/test/defconfig

@@ -60,6 +60,7 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_FIFO_SIZE=0
 CONFIG_DEV_PIPE_MAXSIZE=1024
 CONFIG_DEV_PIPE_SIZE=70
+CONFIG_DISABLE_MQUEUE=y
 CONFIG_EXAMPLES_CALIB_UDELAY=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FAT_DMAMEMORY=y
@@ -138,8 +139,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
@@ -197,6 +197,9 @@ CONFIG_STM32H7_USART_SWAP=y
 CONFIG_SYSTEM_CDCACM=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=24
+CONFIG_TESTING_OSTEST=y
+CONFIG_TESTING_OSTEST_FPUTESTDISABLE=y
+CONFIG_TESTING_OSTEST_STACKSIZE=10240
 CONFIG_TTY_SIGINT=y
 CONFIG_TTY_SIGTSTP=y
 CONFIG_UART4_BAUD=57600

boards/cubepilot/cubeyellow/nuttx-config/nsh/defconfig

@@ -141,8 +141,7 @@ CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_MODE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/diatone/mamba-f405-mk2/nuttx-config/nsh/defconfig

@@ -120,8 +120,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y
@@ -158,7 +157,7 @@ CONFIG_STM32_SERIALBRK_BSDCOMPAT=y
 CONFIG_STM32_SERIAL_DISABLE_REORDERING=y
 CONFIG_STM32_SPI1=y
 CONFIG_STM32_SPI1_DMA=y
-CONFIG_STM32_SPI1_DMA_BUFFER=1024
+CONFIG_STM32_SPI1_DMA_BUFFER=512
 CONFIG_STM32_SPI2=y
 CONFIG_STM32_SPI2_DMA=y
 CONFIG_STM32_SPI3=y

boards/freefly/can-rtk-gps/nuttx-config/nsh/defconfig

@@ -122,8 +122,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/holybro/can-gps-v1/nuttx-config/nsh/defconfig

@@ -108,8 +108,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/holybro/durandal-v1/nuttx-config/nsh/defconfig

@@ -140,8 +140,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/holybro/durandal-v1/nuttx-config/scripts/script.ld

@@ -109,16 +109,17 @@
 
 MEMORY
 {
-	itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
-	flash (rx)  : ORIGIN = 0x08020000, LENGTH = 1920K
-	dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
-	dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
-	sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
-	sram1 (rwx) : ORIGIN = 0x30000000, LENGTH =  128K
-	sram2 (rwx) : ORIGIN = 0x30020000, LENGTH =  128K
-	sram3 (rwx) : ORIGIN = 0x30040000, LENGTH =   32K
-	sram4 (rwx) : ORIGIN = 0x38000000, LENGTH =   64K
-	bbram (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
+	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
+	SRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K /* D2 domain AHB bus */
+	SRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K /* D3 domain */
+	BKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
 }
 
 OUTPUT_ARCH(arm)
@@ -156,7 +157,7 @@ SECTIONS
 		*(.gnu.linkonce.r.*)
 		_etext = ABSOLUTE(.);
 
-	} > flash
+	} > FLASH
 
 	/*
 	 * Init functions (static constructors and the like)
@@ -165,17 +166,17 @@ SECTIONS
 		_sinit = ABSOLUTE(.);
 		KEEP(*(.init_array .init_array.*))
 		_einit = ABSOLUTE(.);
-	} > flash
+	} > FLASH
 
 
 	.ARM.extab : {
 		*(.ARM.extab*)
-	} > flash
+	} > FLASH
 
 	__exidx_start = ABSOLUTE(.);
 	.ARM.exidx : {
 		*(.ARM.exidx*)
-	} > flash
+	} > FLASH
 	__exidx_end = ABSOLUTE(.);
 
 	_eronly = ABSOLUTE(.);
@@ -186,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -195,7 +201,7 @@ SECTIONS
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = ABSOLUTE(.);
-	} > sram
+	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
 
@@ -204,7 +210,7 @@ SECTIONS
 		*(.sram4)
 		. = ALIGN(4);
 		_sram4_heap_start = ABSOLUTE(.);
-	} > sram4
+	} > SRAM4
 
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }

boards/holybro/kakutef7/nuttx-config/nsh/defconfig

@@ -140,8 +140,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/holybro/kakuteh7/nuttx-config/nsh/defconfig

@@ -139,8 +139,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/holybro/kakuteh7/nuttx-config/scripts/script.ld

@@ -109,16 +109,17 @@
 
 MEMORY
 {
-	itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
-	flash (rx)  : ORIGIN = 0x08020000, LENGTH = 1792K /* params in last sector */
-	dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
-	dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
-	sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
-	sram1 (rwx) : ORIGIN = 0x30000000, LENGTH =  128K
-	sram2 (rwx) : ORIGIN = 0x30020000, LENGTH =  128K
-	sram3 (rwx) : ORIGIN = 0x30040000, LENGTH =   32K
-	sram4 (rwx) : ORIGIN = 0x38000000, LENGTH =   64K
-	bbram (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1792K /* params in last sector */
+
+	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
+	SRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K /* D2 domain AHB bus */
+	SRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K /* D3 domain */
+	BKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
 }
 
 OUTPUT_ARCH(arm)
@@ -156,7 +157,7 @@ SECTIONS
 		*(.gnu.linkonce.r.*)
 		_etext = ABSOLUTE(.);
 
-	} > flash
+	} > FLASH
 
 	/*
 	 * Init functions (static constructors and the like)
@@ -165,17 +166,17 @@ SECTIONS
 		_sinit = ABSOLUTE(.);
 		KEEP(*(.init_array .init_array.*))
 		_einit = ABSOLUTE(.);
-	} > flash
+	} > FLASH
 
 
 	.ARM.extab : {
 		*(.ARM.extab*)
-	} > flash
+	} > FLASH
 
 	__exidx_start = ABSOLUTE(.);
 	.ARM.exidx : {
 		*(.ARM.exidx*)
-	} > flash
+	} > FLASH
 	__exidx_end = ABSOLUTE(.);
 
 	_eronly = ABSOLUTE(.);
@@ -186,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -195,7 +201,7 @@ SECTIONS
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = ABSOLUTE(.);
-	} > sram
+	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
 
@@ -204,7 +210,7 @@ SECTIONS
 		*(.sram4)
 		. = ALIGN(4);
 		_sram4_heap_start = ABSOLUTE(.);
-	} > sram4
+	} > SRAM4
 
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }

boards/holybro/pix32v5/nuttx-config/nsh/defconfig

@@ -140,8 +140,7 @@ CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_MODE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/matek/gnss-m9n-f4/nuttx-config/nsh/defconfig

@@ -126,8 +126,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_PASSTHRU_UBLOX=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/matek/h743-mini/nuttx-config/nsh/defconfig

@@ -126,8 +126,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/matek/h743-mini/nuttx-config/scripts/script.ld

@@ -1,7 +1,7 @@
 /****************************************************************************
  * scripts/script.ld
  *
- *   Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2020 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  *
@@ -34,7 +34,7 @@
  *
  ****************************************************************************/
 
-/* The Durandal-v1 uses an STM32H743II has 2048Kb of main FLASH memory.
+/* The board uses an STM32H743II and has 2048Kb of main FLASH memory.
  * The flash memory is partitioned into a User Flash memory and a System
  * Flash memory. Each of these memories has two banks:
  *
@@ -59,8 +59,8 @@
  *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
  *      ST programmed value: System bootloader at 0x1FF0:0000
  *
- * The Durandal has a Swtich on board, the BOOT0 pin is at ground so by default,
- * the STM32 will boot to address 0x0800:0000 in FLASH unless the swiutch is
+ * There's a switch on board, the BOOT0 pin is at ground so by default,
+ * the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is
  * drepresed, then the boot will be from 0x1FF0:0000
  *
  * The STM32H743ZI also has 1024Kb of data SRAM.
@@ -109,16 +109,17 @@
 
 MEMORY
 {
-	itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
-	flash (rx)  : ORIGIN = 0x08020000, LENGTH = 1920K
-	dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
-	dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
-	sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
-	sram1 (rwx) : ORIGIN = 0x30000000, LENGTH =  128K
-	sram2 (rwx) : ORIGIN = 0x30020000, LENGTH =  128K
-	sram3 (rwx) : ORIGIN = 0x30040000, LENGTH =   32K
-	sram4 (rwx) : ORIGIN = 0x38000000, LENGTH =   64K
-	bbram (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
+	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
+	SRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K /* D2 domain AHB bus */
+	SRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K /* D3 domain */
+	BKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
 }
 
 OUTPUT_ARCH(arm)
@@ -156,7 +157,7 @@ SECTIONS
 		*(.gnu.linkonce.r.*)
 		_etext = ABSOLUTE(.);
 
-	} > flash
+	} > FLASH
 
 	/*
 	 * Init functions (static constructors and the like)
@@ -165,17 +166,17 @@ SECTIONS
 		_sinit = ABSOLUTE(.);
 		KEEP(*(.init_array .init_array.*))
 		_einit = ABSOLUTE(.);
-	} > flash
+	} > FLASH
 
 
 	.ARM.extab : {
 		*(.ARM.extab*)
-	} > flash
+	} > FLASH
 
 	__exidx_start = ABSOLUTE(.);
 	.ARM.exidx : {
 		*(.ARM.exidx*)
-	} > flash
+	} > FLASH
 	__exidx_end = ABSOLUTE(.);
 
 	_eronly = ABSOLUTE(.);
@@ -186,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -195,7 +201,7 @@ SECTIONS
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = ABSOLUTE(.);
-	} > sram
+	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
 
@@ -204,7 +210,7 @@ SECTIONS
 		*(.sram4)
 		. = ALIGN(4);
 		_sram4_heap_start = ABSOLUTE(.);
-	} > sram4
+	} > SRAM4
 
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }

boards/matek/h743-slim/nuttx-config/nsh/defconfig

@@ -130,8 +130,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/matek/h743-slim/nuttx-config/scripts/script.ld

@@ -34,7 +34,7 @@
  *
  ****************************************************************************/
 
-/* The Durandal-v1 uses an STM32H743II has 2048Kb of main FLASH memory.
+/* The board uses an STM32H743II and has 2048Kb of main FLASH memory.
  * The flash memory is partitioned into a User Flash memory and a System
  * Flash memory. Each of these memories has two banks:
  *
@@ -59,8 +59,8 @@
  *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
  *      ST programmed value: System bootloader at 0x1FF0:0000
  *
- * The Durandal has a Swtich on board, the BOOT0 pin is at ground so by default,
- * the STM32 will boot to address 0x0800:0000 in FLASH unless the swiutch is
+ * There's a switch on board, the BOOT0 pin is at ground so by default,
+ * the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is
  * drepresed, then the boot will be from 0x1FF0:0000
  *
  * The STM32H743ZI also has 1024Kb of data SRAM.
@@ -109,16 +109,17 @@
 
 MEMORY
 {
-	itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
-	flash (rx)  : ORIGIN = 0x08020000, LENGTH = 1920K
-	dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
-	dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
-	sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
-	sram1 (rwx) : ORIGIN = 0x30000000, LENGTH =  128K
-	sram2 (rwx) : ORIGIN = 0x30020000, LENGTH =  128K
-	sram3 (rwx) : ORIGIN = 0x30040000, LENGTH =   32K
-	sram4 (rwx) : ORIGIN = 0x38000000, LENGTH =   64K
-	bbram (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
+	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
+	SRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K /* D2 domain AHB bus */
+	SRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K /* D3 domain */
+	BKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
 }
 
 OUTPUT_ARCH(arm)
@@ -156,7 +157,7 @@ SECTIONS
 		*(.gnu.linkonce.r.*)
 		_etext = ABSOLUTE(.);
 
-	} > flash
+	} > FLASH
 
 	/*
 	 * Init functions (static constructors and the like)
@@ -165,17 +166,17 @@ SECTIONS
 		_sinit = ABSOLUTE(.);
 		KEEP(*(.init_array .init_array.*))
 		_einit = ABSOLUTE(.);
-	} > flash
+	} > FLASH
 
 
 	.ARM.extab : {
 		*(.ARM.extab*)
-	} > flash
+	} > FLASH
 
 	__exidx_start = ABSOLUTE(.);
 	.ARM.exidx : {
 		*(.ARM.exidx*)
-	} > flash
+	} > FLASH
 	__exidx_end = ABSOLUTE(.);
 
 	_eronly = ABSOLUTE(.);
@@ -186,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -195,7 +201,7 @@ SECTIONS
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = ABSOLUTE(.);
-	} > sram
+	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
 
@@ -204,7 +210,7 @@ SECTIONS
 		*(.sram4)
 		. = ALIGN(4);
 		_sram4_heap_start = ABSOLUTE(.);
-	} > sram4
+	} > SRAM4
 
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }

boards/matek/h743/nuttx-config/nsh/defconfig

@@ -127,8 +127,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/matek/h743/nuttx-config/scripts/script.ld

@@ -34,7 +34,7 @@
  *
  ****************************************************************************/
 
-/* The Durandal-v1 uses an STM32H743II has 2048Kb of main FLASH memory.
+/* The board uses an STM32H743II and has 2048Kb of main FLASH memory.
  * The flash memory is partitioned into a User Flash memory and a System
  * Flash memory. Each of these memories has two banks:
  *
@@ -59,8 +59,8 @@
  *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
  *      ST programmed value: System bootloader at 0x1FF0:0000
  *
- * The Durandal has a Swtich on board, the BOOT0 pin is at ground so by default,
- * the STM32 will boot to address 0x0800:0000 in FLASH unless the swiutch is
+ * There's a switch on board, the BOOT0 pin is at ground so by default,
+ * the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is
  * drepresed, then the boot will be from 0x1FF0:0000
  *
  * The STM32H743ZI also has 1024Kb of data SRAM.
@@ -109,16 +109,17 @@
 
 MEMORY
 {
-	itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
-	flash (rx)  : ORIGIN = 0x08020000, LENGTH = 1920K
-	dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
-	dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
-	sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
-	sram1 (rwx) : ORIGIN = 0x30000000, LENGTH =  128K
-	sram2 (rwx) : ORIGIN = 0x30020000, LENGTH =  128K
-	sram3 (rwx) : ORIGIN = 0x30040000, LENGTH =   32K
-	sram4 (rwx) : ORIGIN = 0x38000000, LENGTH =   64K
-	bbram (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
+	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
+	SRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K /* D2 domain AHB bus */
+	SRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K /* D3 domain */
+	BKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
 }
 
 OUTPUT_ARCH(arm)
@@ -156,7 +157,7 @@ SECTIONS
 		*(.gnu.linkonce.r.*)
 		_etext = ABSOLUTE(.);
 
-	} > flash
+	} > FLASH
 
 	/*
 	 * Init functions (static constructors and the like)
@@ -165,17 +166,17 @@ SECTIONS
 		_sinit = ABSOLUTE(.);
 		KEEP(*(.init_array .init_array.*))
 		_einit = ABSOLUTE(.);
-	} > flash
+	} > FLASH
 
 
 	.ARM.extab : {
 		*(.ARM.extab*)
-	} > flash
+	} > FLASH
 
 	__exidx_start = ABSOLUTE(.);
 	.ARM.exidx : {
 		*(.ARM.exidx*)
-	} > flash
+	} > FLASH
 	__exidx_end = ABSOLUTE(.);
 
 	_eronly = ABSOLUTE(.);
@@ -186,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -195,7 +201,7 @@ SECTIONS
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = ABSOLUTE(.);
-	} > sram
+	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
 
@@ -204,7 +210,7 @@ SECTIONS
 		*(.sram4)
 		. = ALIGN(4);
 		_sram4_heap_start = ABSOLUTE(.);
-	} > sram4
+	} > SRAM4
 
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }

boards/modalai/fc-v1/nuttx-config/nsh/defconfig

@@ -138,8 +138,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC2_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/modalai/fc-v2/nuttx-config/nsh/defconfig

@@ -140,8 +140,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC2_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/modalai/fc-v2/nuttx-config/scripts/script.ld

@@ -109,16 +109,17 @@
 
 MEMORY
 {
-	itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
-	flash (rx)  : ORIGIN = 0x08020000, LENGTH = 1920K
-	dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
-	dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
-	sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
-	sram1 (rwx) : ORIGIN = 0x30000000, LENGTH =  128K
-	sram2 (rwx) : ORIGIN = 0x30020000, LENGTH =  128K
-	sram3 (rwx) : ORIGIN = 0x30040000, LENGTH =   32K
-	sram4 (rwx) : ORIGIN = 0x38000000, LENGTH =   64K
-	bbram (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
+	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
+	SRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K /* D2 domain AHB bus */
+	SRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K /* D3 domain */
+	BKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
 }
 
 OUTPUT_ARCH(arm)
@@ -157,7 +158,7 @@ SECTIONS
 		*(.gnu.linkonce.r.*)
 		_etext = ABSOLUTE(.);
 
-	} > flash
+	} > FLASH
 
 	/*
 	 * Init functions (static constructors and the like)
@@ -166,17 +167,17 @@ SECTIONS
 		_sinit = ABSOLUTE(.);
 		KEEP(*(.init_array .init_array.*))
 		_einit = ABSOLUTE(.);
-	} > flash
+	} > FLASH
 
 
 	.ARM.extab : {
 		*(.ARM.extab*)
-	} > flash
+	} > FLASH
 
 	__exidx_start = ABSOLUTE(.);
 	.ARM.exidx : {
 		*(.ARM.exidx*)
-	} > flash
+	} > FLASH
 	__exidx_end = ABSOLUTE(.);
 
 	_eronly = ABSOLUTE(.);
@@ -187,7 +188,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -196,7 +202,7 @@ SECTIONS
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = ABSOLUTE(.);
-	} > sram
+	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
 
@@ -205,7 +211,7 @@ SECTIONS
 		*(.sram4)
 		. = ALIGN(4);
 		_sram4_heap_start = ABSOLUTE(.);
-	} > sram4
+	} > SRAM4
 
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }

boards/mro/ctrl-zero-classic/nuttx-config/nsh/defconfig

@@ -141,8 +141,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/mro/ctrl-zero-classic/nuttx-config/scripts/script.ld

@@ -187,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > AXI_SRAM AT > FLASH
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -199,6 +204,7 @@ SECTIONS
 	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
+
 	.sram4_reserve (NOLOAD) :
 	{
 		*(.sram4)
@@ -206,7 +212,6 @@ SECTIONS
 		_sram4_heap_start = ABSOLUTE(.);
 	} > SRAM4
 
-
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }
 	.stabstr 0 : { *(.stabstr) }
@@ -220,13 +225,4 @@ SECTIONS
 	.debug_line 0 : { *(.debug_line) }
 	.debug_pubnames 0 : { *(.debug_pubnames) }
 	.debug_aranges 0 : { *(.debug_aranges) }
-
-	.ramfunc : {
-		_sramfuncs = .;
-		*(.ramfunc  .ramfunc.*)
-		. = ALIGN(4);
-		_eramfuncs = .;
-	} > ITCM_RAM AT > FLASH
-
-	_framfuncs = LOADADDR(.ramfunc);
 }

boards/mro/ctrl-zero-f7-oem/nuttx-config/nsh/defconfig

@@ -139,8 +139,7 @@ CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_MODE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/mro/ctrl-zero-f7/nuttx-config/nsh/defconfig

@@ -139,8 +139,7 @@ CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_MODE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/mro/ctrl-zero-h7-oem/nuttx-config/nsh/defconfig

@@ -141,8 +141,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/mro/ctrl-zero-h7-oem/nuttx-config/scripts/script.ld

@@ -187,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > AXI_SRAM AT > FLASH
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -199,6 +204,7 @@ SECTIONS
 	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
+
 	.sram4_reserve (NOLOAD) :
 	{
 		*(.sram4)
@@ -206,7 +212,6 @@ SECTIONS
 		_sram4_heap_start = ABSOLUTE(.);
 	} > SRAM4
 
-
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }
 	.stabstr 0 : { *(.stabstr) }
@@ -220,13 +225,4 @@ SECTIONS
 	.debug_line 0 : { *(.debug_line) }
 	.debug_pubnames 0 : { *(.debug_pubnames) }
 	.debug_aranges 0 : { *(.debug_aranges) }
-
-	.ramfunc : {
-		_sramfuncs = .;
-		*(.ramfunc  .ramfunc.*)
-		. = ALIGN(4);
-		_eramfuncs = .;
-	} > ITCM_RAM AT > FLASH
-
-	_framfuncs = LOADADDR(.ramfunc);
 }

boards/mro/ctrl-zero-h7/nuttx-config/nsh/defconfig

@@ -141,8 +141,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/mro/ctrl-zero-h7/nuttx-config/scripts/script.ld

@@ -187,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > AXI_SRAM AT > FLASH
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);
@@ -199,6 +204,7 @@ SECTIONS
 	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
+
 	.sram4_reserve (NOLOAD) :
 	{
 		*(.sram4)
@@ -206,7 +212,6 @@ SECTIONS
 		_sram4_heap_start = ABSOLUTE(.);
 	} > SRAM4
 
-
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }
 	.stabstr 0 : { *(.stabstr) }
@@ -220,13 +225,4 @@ SECTIONS
 	.debug_line 0 : { *(.debug_line) }
 	.debug_pubnames 0 : { *(.debug_pubnames) }
 	.debug_aranges 0 : { *(.debug_aranges) }
-
-	.ramfunc : {
-		_sramfuncs = .;
-		*(.ramfunc  .ramfunc.*)
-		. = ALIGN(4);
-		_eramfuncs = .;
-	} > ITCM_RAM AT > FLASH
-
-	_framfuncs = LOADADDR(.ramfunc);
 }

boards/mro/pixracerpro/nuttx-config/nsh/defconfig

@@ -139,8 +139,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y

boards/mro/pixracerpro/nuttx-config/scripts/script.ld

@@ -111,6 +111,7 @@ MEMORY
 {
 	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
 	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
 	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
 	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
 	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
@@ -186,7 +187,12 @@ SECTIONS
 		*(.gnu.linkonce.d.*)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	} > AXI_SRAM AT > FLASH
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
 
 	.bss : {
 		_sbss = ABSOLUTE(.);

boards/mro/pixracerpro/src/board_config.h

@@ -86,9 +86,9 @@
 #define DIRECT_PWM_OUTPUT_CHANNELS  8
 
 /* Power supply control and monitoring GPIOs */
-#define GPIO_nPOWER_IN_A                /* PB5 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_POWER_IN_A                 /* PB5 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN5)
 
-#define GPIO_nVDD_BRICK1_VALID          GPIO_nPOWER_IN_A /* Brick 1 Is Chosen */
+#define GPIO_VDD_BRICK1_VALID           GPIO_POWER_IN_A /* Brick 1 Is Chosen */
 #define BOARD_NUMBER_BRICKS             1
 
 #define GPIO_VDD_3V3_SPEKTRUM_POWER_EN  /* PE4  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN4)
@@ -143,7 +143,7 @@
  */
 #define BOARD_ADC_USB_CONNECTED (px4_arch_gpioread(GPIO_OTGFS_VBUS))
 #define BOARD_ADC_USB_VALID     BOARD_ADC_USB_CONNECTED
-#define BOARD_ADC_BRICK_VALID   (!px4_arch_gpioread(GPIO_nVDD_BRICK1_VALID))
+#define BOARD_ADC_BRICK_VALID   (px4_arch_gpioread(GPIO_VDD_BRICK1_VALID))
 
 #define BOARD_NUM_IO_TIMERS 3
 #define BOARD_DMA_ALLOC_POOL_SIZE 5120 /* This board provides a DMA pool and APIs */
@@ -160,7 +160,7 @@
 		GPIO_CAN2_SILENT_S0,              \
 		GPIO_LEVEL_SHIFTER_OE,            \
 		GPIO_PWM_VOLT_SEL,                \
-		GPIO_nPOWER_IN_A,                 \
+		GPIO_POWER_IN_A,                  \
 		GPIO_VDD_3V3_SPEKTRUM_POWER_EN,   \
 		PX4_GPIO_PIN_OFF(GPIO_SDMMC1_D0), \
 		PX4_GPIO_PIN_OFF(GPIO_SDMMC1_D1), \

boards/mro/x21-777/nuttx-config/nsh/defconfig

@@ -139,8 +139,7 @@ CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_MODE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
@@ -199,9 +198,9 @@ CONFIG_SYSTEM_CDCACM=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=24
 CONFIG_UART4_BAUD=57600
-CONFIG_UART4_RXBUFSIZE=600
-CONFIG_UART4_RXDMA=y
-CONFIG_UART4_TXBUFSIZE=1500
+CONFIG_UART4_RXBUFSIZE=1200
+CONFIG_UART4_RXDMA=n
+CONFIG_UART4_TXBUFSIZE=1200
 CONFIG_UART7_BAUD=57600
 CONFIG_UART7_RXBUFSIZE=600
 CONFIG_UART7_SERIAL_CONSOLE=y
@@ -226,10 +225,10 @@ CONFIG_USART3_RXBUFSIZE=600
 CONFIG_USART3_RXDMA=y
 CONFIG_USART3_TXBUFSIZE=3000
 CONFIG_USART6_BAUD=57600
-CONFIG_USART6_RXBUFSIZE=600
-CONFIG_USART6_RXDMA=y
-CONFIG_USART6_TXBUFSIZE=1500
-CONFIG_USART6_TXDMA=y
+CONFIG_USART6_RXBUFSIZE=1200
+CONFIG_USART6_RXDMA=n
+CONFIG_USART6_TXBUFSIZE=1200
+CONFIG_USART6_TXDMA=n
 CONFIG_USBDEV=y
 CONFIG_USBDEV_BUSPOWERED=y
 CONFIG_USBDEV_MAXPOWER=500

boards/mro/x21/nuttx-config/nsh/defconfig

@@ -131,8 +131,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDIO_BLOCKSETUP=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
@@ -172,7 +171,7 @@ CONFIG_STM32_SERIALBRK_BSDCOMPAT=y
 CONFIG_STM32_SERIAL_DISABLE_REORDERING=y
 CONFIG_STM32_SPI1=y
 CONFIG_STM32_SPI1_DMA=y
-CONFIG_STM32_SPI1_DMA_BUFFER=1024
+CONFIG_STM32_SPI1_DMA_BUFFER=512
 CONFIG_STM32_SPI2=y
 CONFIG_STM32_SPI_DMA=y
 CONFIG_STM32_SPI_DMATHRESHOLD=8

boards/nxp/fmuk66-e/nuttx-config/nsh/defconfig

@@ -187,8 +187,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/nxp/fmuk66-e/nuttx-config/socketcan/defconfig

@@ -187,8 +187,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y

boards/nxp/fmuk66-v3/init/rc.board_defaults

@@ -9,11 +9,3 @@ param set-default BAT1_A_PER_V 15.391030303
 rgbled_pwm start
 safety_button start
 
-# pre-arm stuff
-param set-default SYS_CTRL_ALLOC 1
-param set-default COM_PREARM_MODE 2
-
-# Cyphal stuff
-ifup can0
-cyphal start
-elm_lighting_module

boards/nxp/fmuk66-v3/nuttx-config/nsh/defconfig

@@ -185,8 +185,7 @@ CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SEM_NNESTPRIO=8
-CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y