Update platforms/nuttx/src/bootloader/stm/stm32_common/main.c

stm32 bootloader: use STM32_CPUCLK_FREQUENCY for systick_mhz
boards: ark fpv fix current adc
2026-05-28 19:10:04 +08:00 · 2024-11-19 12:19:19 -05:00 · 2024-11-19 12:19:19 -05:00 · 2024-11-19 12:19:19 -05:00 · 2024-11-19 12:19:19 -05:00 · 2024-11-19 12:19:19 -05:00
460 changed files with 9407 additions and 11205 deletions
@@ -46,6 +46,8 @@ pipeline {
                     "ark_cannode_default",
                     "ark_fmu-v6x_bootloader",
                     "ark_fmu-v6x_default",
+                     "ark_fpv_bootloader",
+                     "ark_fpv_default",
                     "ark_pi6x_bootloader",
                     "ark_pi6x_default",
                     "atl_mantis-edu_default",
@@ -15,7 +15,6 @@
 	"extensions": [
 		"chiehyu.vscode-astyle",
 		"dan-c-underwood.arm",
-		"editorconfig.editorconfig",
 		"fredericbonnet.cmake-test-adapter",
 		"github.vscode-pull-request-github",
 		"marus25.cortex-debug",
@@ -1,7 +1,7 @@
 root = true

 [*]
-insert_final_newline = true
+insert_final_newline = false

 [{*.{c,cpp,cc,h,hpp},CMakeLists.txt,Kconfig}]
 indent_style = tab
@@ -23,7 +23,6 @@ jobs:
          "shellcheck_all",
          "NO_NINJA_BUILD=1 px4_fmu-v5_default",
          "NO_NINJA_BUILD=1 px4_sitl_default",
-          "px4_sitl_allyes",
          "airframe_metadata",
          "module_documentation",
          "parameters_metadata",
@@ -151,16 +151,16 @@ CONFIG:
      buildType: MinSizeRel
      settings:
        CONFIG: ark_can-rtk-gps_canbootloader
-    ark_septentrio-gps_default:
-      short: ark_septentrio-gps_default
+    ark_septentrio_gps_default:
+      short: ark_septentrio_gps_default
      buildType: MinSizeRel
      settings:
-        CONFIG: ark_septentrio-gps_default
-    ark_septentrio-gps_canbootloader:
-      short: ark_septentrio-gps_canbootloader
+        CONFIG: ark_septentrio_gps_default
+    ark_septentrio_gps_canbootloader:
+      short: ark_septentrio_gps_canbootloader
      buildType: MinSizeRel
      settings:
-        CONFIG: ark_septentrio-gps_canbootloader
+        CONFIG: ark_septentrio_gps_canbootloader
    ark_cannode_default:
      short: ark_cannode_default
      buildType: MinSizeRel
@@ -181,6 +181,16 @@ CONFIG:
      buildType: MinSizeRel
      settings:
        CONFIG: ark_fmu-v6x_default
+    ark_fpv_bootloader:
+      short: ark_fpv_bootloader
+      buildType: MinSizeRel
+      settings:
+        CONFIG: ark_fpv_bootloader
+    ark_fpv_default:
+      short: ark_fpv_default
+      buildType: MinSizeRel
+      settings:
+        CONFIG: ark_fpv_default
    ark_pi6x_bootloader:
      short: ark_pi6x_bootloader
      buildType: MinSizeRel
@@ -4,7 +4,6 @@
    "recommendations": [
        "chiehyu.vscode-astyle",
        "dan-c-underwood.arm",
-        "editorconfig.editorconfig",
        "fredericbonnet.cmake-test-adapter",
        "github.vscode-pull-request-github",
        "marus25.cortex-debug",
@@ -15,7 +15,6 @@
        "cmake.buildDirectory": "${workspaceFolder}/build/${variant:CONFIG}",
        "cmake.configureOnOpen": true,
        "cmake.ctest.parallelJobs": 1,
-        "cmake.options.statusBarVisibility": "compact",
        "cmake.skipConfigureIfCachePresent": true,
        "cmakeExplorer.buildDir": "${workspaceFolder}/build/px4_sitl_test",
        "cmakeExplorer.parallelJobs": 1,
@@ -325,6 +325,7 @@ px4io_update:

 bootloaders_update: \
 	ark_fmu-v6x_bootloader \
+	ark_fpv_bootloader \
 	ark_pi6x_bootloader \
 	cuav_nora_bootloader \
 	cuav_x7pro_bootloader \
@@ -24,6 +24,8 @@ param set-default CBRK_SUPPLY_CHK 894281
 # - without safety switch
 param set-default CBRK_IO_SAFETY 22027

+param set-default BAT_N_CELLS 3
+
 param set-default SIH_T_MAX 6
 param set-default SIH_MASS 0.3
 param set-default SIH_IXX 0.00402
@@ -33,6 +33,8 @@ param set-default CBRK_SUPPLY_CHK 894281
 # - without safety switch
 param set-default CBRK_IO_SAFETY 22027

+param set-default BAT_N_CELLS 3
+
 param set-default SIH_T_MAX 2
 param set-default SIH_Q_MAX 0.0165
 param set-default SIH_MASS 0.2
@@ -24,6 +24,7 @@ param set-default FW_RR_P 0.085
 param set-default FW_W_EN 1

 param set-default MIS_TAKEOFF_ALT 20
+param set-default MIS_DIST_1WP 2500

 param set-default NAV_ACC_RAD 15
 param set-default NAV_DLL_ACT 2
@@ -24,6 +24,7 @@ param set-default FW_RR_P 0.085
 param set-default FW_W_EN 1

 param set-default MIS_TAKEOFF_ALT 20
+param set-default MIS_DIST_1WP 2500

 param set-default NAV_ACC_RAD 15
 param set-default NAV_DLL_ACT 2
@@ -24,6 +24,7 @@ param set-default FW_RR_P 0.085
 param set-default FW_W_EN 1

 param set-default MIS_TAKEOFF_ALT 20
+param set-default MIS_DIST_1WP 2500

 param set-default NAV_ACC_RAD 15
 param set-default NAV_DLL_ACT 2
@@ -25,6 +25,7 @@ param set-default FW_W_EN 1

 param set-default MIS_LTRMIN_ALT 30
 param set-default MIS_TAKEOFF_ALT 20
+param set-default MIS_DIST_1WP 2500

 param set-default NAV_ACC_RAD 15
 param set-default NAV_DLL_ACT 2
@@ -52,4 +52,3 @@ param set-default SIM_GZ_EC_MAX3 1000
 param set-default SIM_GZ_EC_MAX4 1000

 param set-default MPC_THR_HOVER 0.60
-param set-default NAV_DLL_ACT 2
@@ -101,9 +101,8 @@ param set-default MPC_XY_VEL_I_ACC 4
 param set-default MPC_XY_VEL_D_ACC 0.1

 param set-default NAV_ACC_RAD 5
-param set-default NAV_DLL_ACT 2

 param set-default VT_FWD_THRUST_EN 4
-param set-default VT_F_TRANS_THR 0.3
+param set-default VT_F_TRANS_THR 0.75
 param set-default VT_TYPE 2
 param set-default FD_ESCS_EN 0
@@ -132,5 +132,3 @@ param set-default SIM_GZ_EC_MAX1 1100
 param set-default SIM_GZ_EC_MAX2 1100
 param set-default SIM_GZ_EC_MAX3 1100
 param set-default SIM_GZ_EC_MAX4 1100
-
-param set-default NAV_DLL_ACT 2
@@ -84,13 +84,6 @@ if(CONFIG_MODULES_DIFFERENTIAL_DRIVE)
 	)
 endif()

-if(CONFIG_MODULES_ROVER_ACKERMANN)
-	px4_add_romfs_files(
-		rc.rover_ackermann_apps
-		rc.rover_ackermann_defaults
-	)
-endif()
-
 if(CONFIG_MODULES_UUV_ATT_CONTROL)
 	px4_add_romfs_files(
 		rc.uuv_apps
@@ -44,6 +44,8 @@ param set-default CBRK_SUPPLY_CHK 894281
 # - without safety switch
 param set-default CBRK_IO_SAFETY 22027

+param set-default BAT_N_CELLS 3
+
 param set SIH_T_MAX 6
 param set SIH_MASS 0.3
 param set SIH_IXX 0.00402
@@ -62,6 +62,8 @@ param set-default CBRK_SUPPLY_CHK 894281
 # - without safety switch
 param set-default CBRK_IO_SAFETY 22027

+param set-default BAT_N_CELLS 3
+
 param set SIH_T_MAX 2.0
 param set SIH_Q_MAX 0.0165
 param set SIH_MASS 0.2
@@ -66,6 +66,7 @@ param set-default MC_PITCHRATE_I 0.05
 param set-default MC_YAWRATE_MAX 20
 param set-default MC_AIRMODE 1

+param set-default MIS_DIST_1WP 100
 param set-default MIS_TAKEOFF_ALT 15

 param set-default MPC_XY_P 0.8
@@ -1,12 +0,0 @@
-#!/bin/sh
-#
-# @name Generic ackermann rover
-#
-# @type Rover
-# @class Rover
-#
-# @board px4_fmu-v2 exclude
-# @board bitcraze_crazyflie exclude
-#
-
-. ${R}etc/init.d/rc.rover_ackermann_defaults
@@ -149,12 +149,6 @@ if(CONFIG_MODULES_DIFFERENTIAL_DRIVE)
 	)
 endif()

-if(CONFIG_MODULES_ROVER_ACKERMANN)
-	px4_add_romfs_files(
-		50010_ackermann_rover_generic
-	)
-endif()
-
 if(CONFIG_MODULES_UUV_ATT_CONTROL)
 	px4_add_romfs_files(
 		# [60000, 61000] (Unmanned) Underwater Robots
@@ -1,11 +0,0 @@
-#!/bin/sh
-# Standard apps for a ackermann drive rover.
-
-# Start the attitude and position estimator.
-ekf2 start &
-
-# Start rover ackermann drive controller.
-rover_ackermann start
-
-# Start Land Detector.
-land_detector start rover
@@ -1,13 +0,0 @@
-#!/bin/sh
-# Ackermann rover parameters.
-
-set VEHICLE_TYPE rover_ackermann
-param set-default MAV_TYPE 10 # MAV_TYPE_GROUND_ROVER
-param set-default CA_AIRFRAME 5 # Rover (Ackermann)
-param set-default CA_R_REV 1 # Motor is assumed to be reversible
-param set-default EKF2_MAG_TYPE 1 # make sure magnetometer is fused even when not flying
-param set-default EKF2_GBIAS_INIT 0.01
-param set-default EKF2_ANGERR_INIT 0.01
-param set-default NAV_ACC_RAD 0.5 # Waypoint acceptance radius
-param set-default NAV_RCL_ACT 6 # Disarm on manual control loss
-param set-default COM_FAIL_ACT_T 1 # Delay before failsafe after rc loss
@@ -138,12 +138,6 @@ then
 	adis16507 -S start
 fi

-# SCH16T spi external IMU
-if param compare -s SENS_EN_SCH16T 1
-then
-	sch16t -S start
-fi
-
 # Eagle Tree airspeed sensor external I2C
 if param compare -s SENS_EN_ETSASPD 1
 then
@@ -41,15 +41,6 @@ then
 	. ${R}etc/init.d/rc.rover_differential_apps
 fi

-#
-# Ackermann Rover setup.
-#
-if [ $VEHICLE_TYPE = rover_ackermann ]
-then
-	# Start ackermann drive rover apps.
-	. ${R}etc/init.d/rc.rover_ackermann_apps
-fi
-
 #
 # VTOL setup.
 #
@@ -36,12 +36,6 @@ set SDCARD_FORMAT no
 set STARTUP_TUNE 1
 set VEHICLE_TYPE none

-# Airframe parameter versioning
-# Value set to 1 by default but can optionally be overridden in the airframe configuration startup script.
-# Airframe maintainers can ensure a reset to the airframe defaults during an update by increasing by one.
-# e.g. add line "set PARAM_DEFAULTS_VER 2" in your airframe file to build the first update that enfoces a reset.
-set PARAM_DEFAULTS_VER 1
-
 #
 # Print full system version.
 #
@@ -129,13 +123,6 @@ else
 		set PARAM_FILE /fs/mtd_params
 	fi

-	# Check if /fs/mtd_params is a valid BSON file
-	if ! bsondump docsize /fs/mtd_caldata
-	then
-		echo "New /fs/mtd_caldata size is:"
-		bsondump docsize /fs/mtd_caldata
-	fi
-
 	#
 	# Load parameters.
 	#
@@ -188,11 +175,13 @@ else
 		netman update -i eth0
 	fi

-	# To trigger a parameter reset during boot SYS_AUTCONFIG was set to 1 before
+	#
+	# If the airframe has been previously reset SYS_AUTCONFIG will have been set to 1 and other params will be reset on the next boot.
+	#
 	if param greater SYS_AUTOCONFIG 0
 	then
-		# Reset parameters except airframe, parameter version, RC calibration, sensor calibration, flight modes, total flight time, flight UUID
-		param reset_all SYS_AUTOSTART SYS_PARAM_VER RC* CAL_* COM_FLTMODE* LND_FLIGHT* TC_* COM_FLIGHT*
+		# Reset params except Airframe, RC calibration, sensor calibration, flight modes, total flight time, and next flight UUID.
+		param reset_all SYS_AUTOSTART RC* CAL_* COM_FLTMODE* LND_FLIGHT* TC_* COM_FLIGHT*
 	fi

 	#
@@ -237,17 +226,6 @@ else
 	fi
 	unset AUTOSTART_PATH

-	# Check parameter version and reset upon airframe configuration version mismatch.
-	# Reboot required because "param reset_all" would reset all "param set" lines from airframe.
-	if ! param compare SYS_PARAM_VER ${PARAM_DEFAULTS_VER}
-	then
-		echo "Switched to different parameter version. Resetting parameters."
-		param set SYS_PARAM_VER ${PARAM_DEFAULTS_VER}
-		param set SYS_AUTOCONFIG 1
-		param save
-		reboot
-	fi
-
 	#
 	# Start the tone_alarm driver.
 	# Needs to be started after the parameters are loaded (for CBRK_BUZZER).
@@ -613,7 +591,6 @@ unset LOGGER_ARGS
 unset LOGGER_BUF
 unset PARAM_FILE
 unset PARAM_BACKUP_FILE
-unset PARAM_DEFAULTS_VER
 unset RC_INPUT_ARGS
 unset SDCARD_AVAILABLE
 unset SDCARD_EXT_PATH
@@ -3,20 +3,22 @@
 FILE=$1
 DIR=$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )

-CHECK_FAILED=$(${DIR}/fix_code_style.sh --dry-run --formatted $FILE)
-if [ -n "$CHECK_FAILED" ]; then
-	${DIR}/fix_code_style.sh --quiet < $FILE > $FILE.pretty
+if [ -f "$FILE" ]; then
+	CHECK_FAILED=$(${DIR}/fix_code_style.sh --dry-run --formatted $FILE)
+	if [ -n "$CHECK_FAILED" ]; then
+		${DIR}/fix_code_style.sh --quiet < $FILE > $FILE.pretty

-	echo -e 'Formatting issue found in' $FILE
-	echo
-	git --no-pager diff --no-index --minimal --histogram --color=always $FILE $FILE.pretty | grep -vE -e "^.{,4}diff.*\.pretty.{,3}$" -e "^.{,4}--- a/.*$" -e "^.{,4}\+\+\+ b/.*$" -e "^.{,5}@@ .* @@.*$" -e "^.{,4}index .{10}\.\."
-	rm -f $FILE.pretty
-	echo
+		echo -e 'Formatting issue found in' $FILE
+		echo
+		git --no-pager diff --no-index --minimal --histogram --color=always $FILE $FILE.pretty | grep -vE -e "^.{,4}diff.*\.pretty.{,3}$" -e "^.{,4}--- a/.*$" -e "^.{,4}\+\+\+ b/.*$" -e "^.{,5}@@ .* @@.*$" -e "^.{,4}index .{10}\.\."
+		rm -f $FILE.pretty
+		echo

-	if [[ $PX4_ASTYLE_FIX -eq 1 ]]; then
-		${DIR}/fix_code_style.sh $FILE
-	else
-		echo 'to fix automatically run "make format" or "./Tools/astyle/fix_code_style.sh' $FILE'"'
-		exit 1
+		if [[ $PX4_ASTYLE_FIX -eq 1 ]]; then
+			${DIR}/fix_code_style.sh $FILE
+		else
+			echo 'to fix automatically run "make format" or "./Tools/astyle/fix_code_style.sh' $FILE'"'
+			exit 1
+		fi
 	fi
 fi
@@ -31,4 +31,4 @@ exec find boards msg src platforms test \
    -path src/lib/cdrstream/rosidl -prune -o \
    -path src/modules/zenoh/zenoh-pico -prune -o \
    -path boards/modalai/voxl2/libfc-sensor-api -prune -o \
-    \( -type f \( -name "*.c" -o -name "*.h" -o -name "*.cpp" -o -name "*.hpp" \) -print \) | grep $PATTERN
+    -type f \( -name "*.c" -o -name "*.h" -o -name "*.cpp" -o -name "*.hpp" \) | grep $PATTERN
@@ -6,7 +6,7 @@ function check_git_submodule {
 if [[ -f $1"/.git" || -d $1"/.git" ]]; then

 	# always update within CI environment or configuring withing VSCode CMake where you can't interact
-	if [ "$CI" == "true" ] || [ -n "${VSCODE_PID+set}" ] || [ -n "${CLION_IDE+set}" ]; then
+	if [ "$CI" == "true" ] || [ -n "${VSCODE_PID+set}" ]; then
 		git submodule --quiet sync --recursive -- $1
 		git submodule --quiet update --init --recursive --jobs=8 -- $1  || true
 		git submodule --quiet sync --recursive -- $1
@@ -34,41 +34,33 @@ def extract_timer(line):
    if search:
        return search.group(1), 'generic'

-    # NXP FlexPWM format format: initIOPWM(PWM::FlexPWM2),
-    search = re.search('PWM::Flex([0-9a-zA-Z_]+)..PWM::Submodule([0-9])[,\)]', line, re.IGNORECASE)
+    # nxp rt1062 format: initIOPWM(PWM::FlexPWM2),
+    search = re.search('PWM::Flex([0-9a-zA-Z_]+)[,\)]', line, re.IGNORECASE)
    if search:
-        return (search.group(1) + '_' +  search.group(2)), 'imxrt'
+        return search.group(1), 'imxrt'

    return None, 'unknown'

-def extract_timer_from_channel(line, timer_names):
+def extract_timer_from_channel(line, num_channels_already_found):
    # Try format: initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel1}, {GPIO::PortA, GPIO::Pin0}),
    search = re.search('Timer::([0-9a-zA-Z_]+), ', line, re.IGNORECASE)
    if search:
        return search.group(1)

-    # NXP FlexPWM format: initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_B0_06),
-    search = re.search('PWM::(PWM[0-9]+).*PWM::Submodule([0-9])', line, re.IGNORECASE)
+    # nxp rt1062 format: initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_B0_06),
+    search = re.search('PWM::(PWM[0-9]+)[_,\)]', line, re.IGNORECASE)
    if search:
-        return str(timer_names.index((search.group(1) + '_' +  search.group(2))))
+        # imxrt uses a 1:1 timer group to channel association
+        return str(num_channels_already_found)

    return None

-def imxrt_is_dshot(line):
-
-    # NXP FlexPWM format format: initIOPWM(PWM::FlexPWM2),
-    search = re.search('(initIOPWMDshot)', line, re.IGNORECASE)
-    if search:
-        return True
-
-    return False
-
 def get_timer_groups(timer_config_file, verbose=False):
    with open(timer_config_file, 'r') as f:
        timer_config = f.read()

    # timers
-    dshot_support = {str(i): False for i in range(16)}
+    dshot_support = {} # key: timer
    timers_start_marker = 'io_timers_t io_timers'
    timers_start = timer_config.find(timers_start_marker)
    if timers_start == -1:
@@ -77,7 +69,6 @@ def get_timer_groups(timer_config_file, verbose=False):
    open_idx, close_idx = find_matching_brackets(('{', '}'), timer_config, verbose)
    timers_str = timer_config[open_idx:close_idx]
    timers = []
-    timer_names = []
    for line in timers_str.splitlines():
        line = line.strip()
        if len(line) == 0 or line.startswith('//'):
@@ -86,11 +77,14 @@ def get_timer_groups(timer_config_file, verbose=False):

        if timer_type == 'imxrt':
            if verbose: print('imxrt timer found')
-            timer_names.append(timer)
-            if imxrt_is_dshot(line):
-                dshot_support[str(len(timers))] = True
-            timers.append(str(len(timers)))
-        elif timer:
+            max_num_channels = 16 # Just add a fixed number of timers
+            timers = [str(i) for i in range(max_num_channels)]
+            dshot_support = {str(i): False for i in range(max_num_channels)}
+            for i in range(8): # First 8 channels support dshot
+                dshot_support[str(i)] = True
+            break
+
+        if timer:
            if verbose: print('found timer def: {:}'.format(timer))
            dshot_support[timer] = 'DMA' in line
            timers.append(timer)
@@ -117,7 +111,7 @@ def get_timer_groups(timer_config_file, verbose=False):
            continue

        if verbose: print('--'+line+'--')
-        timer = extract_timer_from_channel(line, timer_names)
+        timer = extract_timer_from_channel(line, len(channel_timers))

        if timer:
            if verbose: print('Found timer: {:} in channel line {:}'.format(timer, line))
@@ -15,7 +15,7 @@ class ModuleDocumentation(object):
    # TOC in https://github.com/PX4/PX4-user_guide/blob/main/en/SUMMARY.md
    valid_categories = ['driver', 'estimator', 'controller', 'system',
                        'communication', 'command', 'template', 'simulation', 'autotune']
-    valid_subcategories = ['', 'camera', 'distance_sensor', 'imu', 'ins', 'airspeed_sensor',
+    valid_subcategories = ['', 'distance_sensor', 'imu', 'ins', 'airspeed_sensor',
                           'magnetometer', 'baro', 'optical_flow', 'rpm_sensor', 'transponder']

    max_line_length = 80 # wrap lines that are longer than this
@@ -95,7 +95,7 @@ if [[ $INSTALL_SIM == "true" ]]; then

 	# java (jmavsim)
 	sudo pacman -S --noconfirm --needed \
-		ant \
+		ant
 		;

 	# Gazebo setup
@@ -1,4 +1,5 @@
 argcomplete
+argparse>=1.2
 cerberus
 coverage
 empy==3.3.4
@@ -66,8 +66,6 @@ elif [[ "${UBUNTU_RELEASE}" == "20.04" ]]; then
 	echo "Ubuntu 20.04"
 elif [[ "${UBUNTU_RELEASE}" == "22.04" ]]; then
 	echo "Ubuntu 22.04"
-elif [[ "${UBUNTU_RELEASE}" == "21.3" ]]; then
-	echo "Linux Mint 21.3"
 fi


@@ -148,7 +146,7 @@ if [[ $INSTALL_NUTTX == "true" ]]; then
 		util-linux \
 		vim-common \
 		;
-	if [[ "${UBUNTU_RELEASE}" == "20.04" || "${UBUNTU_RELEASE}" == "22.04" || "${UBUNTU_RELEASE}" == "21.3" ]]; then
+	if [[ "${UBUNTU_RELEASE}" == "20.04" || "${UBUNTU_RELEASE}" == "22.04" ]]; then
 		sudo DEBIAN_FRONTEND=noninteractive apt-get -y --quiet --no-install-recommends install \
 		kconfig-frontends \
 		;
@@ -207,8 +205,6 @@ if [[ $INSTALL_SIM == "true" ]]; then
 		java_version=13
 	elif [[ "${UBUNTU_RELEASE}" == "22.04" ]]; then
 		java_version=11
-	elif [[ "${UBUNTU_RELEASE}" == "21.3" ]]; then
-		java_version=11
 	else
 		java_version=14
 	fi
@@ -232,17 +228,6 @@ if [[ $INSTALL_SIM == "true" ]]; then
 		echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/pkgs-osrf-archive-keyring.gpg] http://packages.osrfoundation.org/gazebo/ubuntu-stable $(lsb_release -cs) main" | sudo tee /etc/apt/sources.list.d/gazebo-stable.list > /dev/null
 		sudo apt-get update -y --quiet

-		# Install Gazebo
-		gazebo_packages="gz-garden"
-	elif [[ "${UBUNTU_RELEASE}" == "21.3" ]]; then
-		echo "Gazebo (Garden) will be installed"
-		echo "Earlier versions will be removed"
-		# Add Gazebo binary repository
-		sudo wget https://packages.osrfoundation.org/gazebo.gpg -O /usr/share/keyrings/pkgs-osrf-archive-keyring.gpg
-		echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/pkgs-osrf-archive-keyring.gpg] http://packages.osrfoundation.org/gazebo/ubuntu-stable jammy main" | sudo tee /etc/apt/sources.list.d/gazebo-stable.list > /dev/null
-
-		sudo apt-get update -y --quiet
-
 		# Install Gazebo
 		gazebo_packages="gz-garden"
 	else
@@ -10,9 +10,9 @@ CONFIG_COMMON_BAROMETERS=y
 CONFIG_DRIVERS_BATT_SMBUS=y
 CONFIG_DRIVERS_CAMERA_CAPTURE=y
 CONFIG_DRIVERS_CAMERA_TRIGGER=y
-CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
 CONFIG_COMMON_DISTANCE_SENSOR=y
+CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_DRIVERS_GPS=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM20948=y
 CONFIG_DRIVERS_IMU_INVENSENSE_MPU6000=y
@@ -6,7 +6,6 @@
 param set-default CBRK_IO_SAFETY 0
 param set-default CANNODE_SUB_MBD 1
 param set-default CANNODE_SUB_RTCM 1
-param set-default GPS_1_GNSS 63
 param set-default MBE_ENABLE 1
 param set-default SENS_IMU_CLPNOTI 0

@@ -47,7 +47,7 @@
 #define GPIO_BTN_SAFETY       /* PB15 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTB|GPIO_PIN15)

 /* Safety LED */
-#define GPIO_LED_SAFETY       /* PA1  */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_LED_SAFETY       /* PA1  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)

 /* Tone alarm output. */
 #define TONE_ALARM_TIMER             2    /* timer 2 */
@@ -14,7 +14,6 @@ CONFIG_DRIVERS_DSHOT=y
 CONFIG_DRIVERS_GPS=y
 CONFIG_COMMON_HYGROMETERS=y
 CONFIG_DRIVERS_IMU_ANALOG_DEVICES_ADIS16448=y
-CONFIG_DRIVERS_IMU_ANALOG_DEVICES_ADIS16507=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM20948=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM42688P=y
 CONFIG_DRIVERS_IRLOCK=y
@@ -8,11 +8,11 @@ CONFIG_BOARD_SERIAL_TEL2="/dev/ttyS4"
 CONFIG_BOARD_SERIAL_TEL3="/dev/ttyS1"
 CONFIG_BOARD_SERIAL_TEL4="/dev/ttyS3"
 CONFIG_DRIVERS_ADC_BOARD_ADC=y
+CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_DRIVERS_BAROMETER_BMP388=y
 CONFIG_DRIVERS_BATT_SMBUS=y
 CONFIG_DRIVERS_CAMERA_CAPTURE=y
 CONFIG_DRIVERS_CAMERA_TRIGGER=y
-CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
 CONFIG_COMMON_DISTANCE_SENSOR=y
 CONFIG_DRIVERS_DSHOT=y
@@ -22,7 +22,6 @@ CONFIG_DRIVERS_IMU_ANALOG_DEVICES_ADIS16507=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM42688P=y
 CONFIG_DRIVERS_IMU_INVENSENSE_IIM42652=y
 CONFIG_DRIVERS_IMU_INVENSENSE_IIM42653=y
-CONFIG_DRIVERS_IMU_MURATA_SCH16T=y
 CONFIG_COMMON_LIGHT=y
 CONFIG_COMMON_MAGNETOMETER=y
 CONFIG_COMMON_OPTICAL_FLOW=y
@@ -59,7 +58,6 @@ CONFIG_MODULES_LOGGER=y
 CONFIG_MODULES_MAG_BIAS_ESTIMATOR=y
 CONFIG_MODULES_MANUAL_CONTROL=y
 CONFIG_MODULES_MAVLINK=y
-CONFIG_MAVLINK_DIALECT="development"
 CONFIG_MODULES_MC_ATT_CONTROL=y
 CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=y
 CONFIG_MODULES_MC_HOVER_THRUST_ESTIMATOR=y
@@ -147,8 +147,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETINIT_DHCPC=y
 CONFIG_NETINIT_DNS=y
-CONFIG_NETINIT_DNSIPADDR=0xA290AFE
-CONFIG_NETINIT_DRIPADDR=0xA290AFE
+CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
+CONFIG_NETINIT_DRIPADDR=0XC0A800FE
 CONFIG_NETINIT_MONITOR=y
 CONFIG_NETINIT_THREAD=y
 CONFIG_NETINIT_THREAD_PRIORITY=49
@@ -1,30 +1,29 @@
 CONFIG_BOARD_TOOLCHAIN="arm-none-eabi"
 CONFIG_BOARD_ARCHITECTURE="cortex-m7"
-CONFIG_BOARD_SERIAL_URT6="/dev/ttyS5"
-CONFIG_BOARD_SERIAL_GPS1="/dev/ttyS2"
-CONFIG_BOARD_SERIAL_TEL1="/dev/ttyS0"
-CONFIG_BOARD_SERIAL_TEL2="/dev/ttyS1"
-CONFIG_BOARD_SERIAL_TEL3="/dev/ttyS3"
-CONFIG_BOARD_SERIAL_TEL4="/dev/ttyS6"
-CONFIG_BOARD_SERIAL_RC="/dev/ttyS4"
+CONFIG_BOARD_SERIAL_GPS1="/dev/ttyS0"
+CONFIG_BOARD_SERIAL_TEL3="/dev/ttyS1"
+CONFIG_BOARD_SERIAL_TEL4="/dev/ttyS3"
+CONFIG_BOARD_SERIAL_TEL2="/dev/ttyS4"
+CONFIG_BOARD_SERIAL_RC="/dev/ttyS5"
+CONFIG_BOARD_SERIAL_TEL1="/dev/ttyS6"
 CONFIG_DRIVERS_ADC_BOARD_ADC=y
-CONFIG_DRIVERS_BAROMETER_DPS310=y
+CONFIG_DRIVERS_BAROMETER_BMP388=y
+CONFIG_DRIVERS_CDCACM_AUTOSTART=y
+CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
+CONFIG_COMMON_DISTANCE_SENSOR=y
+CONFIG_DRIVERS_DISTANCE_SENSOR_VL53L0X=y
 CONFIG_DRIVERS_DSHOT=y
 CONFIG_DRIVERS_GPS=y
-CONFIG_DRIVERS_IMU_BOSCH_BMI088=y
-CONFIG_DRIVERS_IMU_BOSCH_BMI270=y
-CONFIG_COMMON_INS=y
+CONFIG_DRIVERS_HEATER=y
+CONFIG_DRIVERS_IMU_INVENSENSE_IIM42653=y
+CONFIG_DRIVERS_IMU_MURATA_SCH16T=y
+CONFIG_COMMON_LIGHT=y
 CONFIG_COMMON_MAGNETOMETER=y
-CONFIG_DRIVERS_OSD_ATXXXX=y
-CONFIG_DRIVERS_PPS_CAPTURE=y
 CONFIG_DRIVERS_PWM_OUT=y
 CONFIG_COMMON_RC=y
-CONFIG_DRIVERS_RC_INPUT=y
-CONFIG_DRIVERS_TAP_ESC=y
-CONFIG_COMMON_TELEMETRY=y
 CONFIG_DRIVERS_UAVCAN=y
-CONFIG_BOARD_UAVCAN_INTERFACES=1
-CONFIG_MODULES_ATTITUDE_ESTIMATOR_Q=y
+CONFIG_BOARD_UAVCAN_TIMER_OVERRIDE=2
+CONFIG_MODULES_AIRSPEED_SELECTOR=y
 CONFIG_MODULES_BATTERY_STATUS=y
 CONFIG_MODULES_COMMANDER=y
 CONFIG_MODULES_CONTROL_ALLOCATOR=y
@@ -33,53 +32,43 @@ CONFIG_MODULES_EKF2=y
 CONFIG_MODULES_ESC_BATTERY=y
 CONFIG_MODULES_EVENTS=y
 CONFIG_MODULES_FLIGHT_MODE_MANAGER=y
-CONFIG_MODULES_FW_ATT_CONTROL=y
-CONFIG_MODULES_FW_AUTOTUNE_ATTITUDE_CONTROL=y
-CONFIG_MODULES_FW_POS_CONTROL=y
-CONFIG_MODULES_FW_RATE_CONTROL=y
 CONFIG_MODULES_GYRO_CALIBRATION=y
 CONFIG_MODULES_GYRO_FFT=y
 CONFIG_MODULES_LAND_DETECTOR=y
 CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
 CONFIG_MODULES_LOAD_MON=y
-CONFIG_MODULES_LOCAL_POSITION_ESTIMATOR=y
 CONFIG_MODULES_LOGGER=y
 CONFIG_MODULES_MAG_BIAS_ESTIMATOR=y
 CONFIG_MODULES_MANUAL_CONTROL=y
 CONFIG_MODULES_MAVLINK=y
+CONFIG_MAVLINK_DIALECT="development"
 CONFIG_MODULES_MC_ATT_CONTROL=y
 CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=y
 CONFIG_MODULES_MC_HOVER_THRUST_ESTIMATOR=y
 CONFIG_MODULES_MC_POS_CONTROL=y
 CONFIG_MODULES_MC_RATE_CONTROL=y
 CONFIG_MODULES_NAVIGATOR=y
-CONFIG_MODULES_PAYLOAD_DELIVERER=y
 CONFIG_MODULES_RC_UPDATE=y
-CONFIG_MODULES_ROVER_POS_CONTROL=y
 CONFIG_MODULES_SENSORS=y
-CONFIG_MODULES_TEMPERATURE_COMPENSATION=y
 CONFIG_MODULES_UXRCE_DDS_CLIENT=y
-CONFIG_MODULES_VTOL_ATT_CONTROL=y
 CONFIG_SYSTEMCMDS_ACTUATOR_TEST=y
+CONFIG_SYSTEMCMDS_BSONDUMP=y
 CONFIG_SYSTEMCMDS_DMESG=y
-CONFIG_SYSTEMCMDS_DUMPFILE=y
-CONFIG_SYSTEMCMDS_FAILURE=y
-CONFIG_SYSTEMCMDS_GPIO=y
 CONFIG_SYSTEMCMDS_HARDFAULT_LOG=y
 CONFIG_SYSTEMCMDS_I2CDETECT=y
+CONFIG_SYSTEMCMDS_LED_CONTROL=y
+CONFIG_SYSTEMCMDS_MFT=y
+CONFIG_SYSTEMCMDS_MTD=y
 CONFIG_SYSTEMCMDS_NSHTERM=y
 CONFIG_SYSTEMCMDS_PARAM=y
 CONFIG_SYSTEMCMDS_PERF=y
 CONFIG_SYSTEMCMDS_REBOOT=y
 CONFIG_SYSTEMCMDS_SD_BENCH=y
 CONFIG_SYSTEMCMDS_SD_STRESS=y
-CONFIG_SYSTEMCMDS_SERIAL_PASSTHRU=y
-CONFIG_SYSTEMCMDS_SERIAL_TEST=y
 CONFIG_SYSTEMCMDS_SYSTEM_TIME=y
 CONFIG_SYSTEMCMDS_TOP=y
 CONFIG_SYSTEMCMDS_TOPIC_LISTENER=y
 CONFIG_SYSTEMCMDS_TUNE_CONTROL=y
 CONFIG_SYSTEMCMDS_UORB=y
-CONFIG_SYSTEMCMDS_USB_CONNECTED=y
 CONFIG_SYSTEMCMDS_VER=y
 CONFIG_SYSTEMCMDS_WORK_QUEUE=y
@@ -1,10 +1,10 @@
 {
-    "board_id": 1166,
-    "magic": "PX4FWv1",
-    "description": "Firmware for the MicoAir743 board",
+    "board_id": 59,
+    "magic": "ARKFPVFWv1",
+    "description": "Firmware for the ARKFPV board",
    "image": "",
    "build_time": 0,
-    "summary": "MicoAir743",
+    "summary": "ARKFPV",
    "version": "0.1",
    "image_size": 0,
    "image_maxsize": 1835008,
@@ -0,0 +1,37 @@
+#!/bin/sh
+#
+# board specific defaults
+#------------------------------------------------------------------------------
+
+# transision from params file to flash-based params (2022-08)
+if [ -f $PARAM_FILE ]
+then
+	param load $PARAM_FILE
+	param save
+	# create a backup
+	mv $PARAM_FILE ${PARAM_FILE}.bak
+	reboot
+fi
+
+# TODO: Tune the following parameters
+param set-default SENS_EN_THERMAL 1
+param set-default SENS_IMU_TEMP 10.0
+#param set-default SENS_IMU_TEMP_FF 0.0
+#param set-default SENS_IMU_TEMP_I 0.025
+#param set-default SENS_IMU_TEMP_P 1.0
+
+if ver hwtypecmp ARKFPV000
+then
+	param set-default SENS_TEMP_ID 3014666
+fi
+
+param set-default BAT1_V_DIV 21.0
+
+param set-default RC_CRSF_PRT_CFG 300
+param set-default RC_SBUS_PRT_CFG 0
+
+param set-default IMU_GYRO_DNF_EN 3
+
+# Single IMU
+param set-default EKF2_MULTI_IMU 0
+param set-default SENS_IMU_MODE 1
@@ -0,0 +1,18 @@
+#!/bin/sh
+#
+# ARKFPV specific board sensors init
+#------------------------------------------------------------------------------
+
+board_adc start
+
+if ver hwtypecmp ARKFPV000
+then
+	# Internal SPI bus IIM42653
+	iim42653 -R 14 -s -b 1 start
+fi
+
+# Internal magnetometer on I2C
+iis2mdc -R 0 -I -b 4 start
+
+# Internal Baro on I2C
+bmp388 -I -b 2 start
@@ -0,0 +1,17 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+config BOARD_HAS_PROBES
+	bool "Board provides GPIO or other Hardware for signaling to timing analyze."
+	default y
+	---help---
+		This board provides GPIO FMU-CH1-5, CAP1-6 as PROBE_1-11 to provide timing signals from selected drivers.
+
+config BOARD_USE_PROBES
+	bool "Enable the use the board provided FMU-CH1-5, CAP1-6 as PROBE_1-11"
+	default n
+	depends on BOARD_HAS_PROBES
+
+	---help---
+		Select to use GPIO FMU-CH1-5, CAP1-6  to provide timing signals from selected drivers.
@@ -7,15 +7,16 @@
 #
 # CONFIG_DEV_CONSOLE is not set
 # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_DISABLE_PTHREAD is not set
 # CONFIG_SPI_EXCHANGE is not set
 # CONFIG_STM32H7_SYSCFG is not set
 CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD_CUSTOM=y
-CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/micoair/h743/nuttx-config"
+CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/ark/fpv/nuttx-config"
 CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
-CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
+CONFIG_ARCH_BOARD_CUSTOM_NAME="ark"
 CONFIG_ARCH_CHIP="stm32h7"
-CONFIG_ARCH_CHIP_STM32H743VI=y
+CONFIG_ARCH_CHIP_STM32H743II=y
 CONFIG_ARCH_CHIP_STM32H7=y
 CONFIG_ARCH_INTERRUPTSTACK=768
 CONFIG_ARMV7M_BASEPRI_WAR=y
@@ -31,12 +32,12 @@ CONFIG_BOARD_LOOPSPERMSEC=95150
 CONFIG_BOARD_RESET_ON_ASSERT=2
 CONFIG_CDCACM=y
 CONFIG_CDCACM_IFLOWCONTROL=y
-CONFIG_CDCACM_PRODUCTID=0x004b
-CONFIG_CDCACM_PRODUCTSTR="MicoAir743"
+CONFIG_CDCACM_PRODUCTID=0x003B
+CONFIG_CDCACM_PRODUCTSTR="ARK BL FPV.x"
 CONFIG_CDCACM_RXBUFSIZE=600
 CONFIG_CDCACM_TXBUFSIZE=12000
-CONFIG_CDCACM_VENDORID=0x3162
-CONFIG_CDCACM_VENDORSTR="MicoAir"
+CONFIG_CDCACM_VENDORID=0x3185
+CONFIG_CDCACM_VENDORSTR="ARK"
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEBUG_TCBINFO=y
@@ -55,10 +56,12 @@ CONFIG_LIBC_STRERROR=y
 CONFIG_MEMSET_64BIT=y
 CONFIG_MEMSET_OPTSPEED=y
 CONFIG_PREALLOC_TIMERS=50
+CONFIG_PTHREAD_MUTEX_ROBUST=y
 CONFIG_PTHREAD_STACK_MIN=512
 CONFIG_RAM_SIZE=245760
 CONFIG_RAM_START=0x20010000
 CONFIG_RAW_BINARY=y
+CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y
 CONFIG_SIG_SIGUSR1_ACTION=y
@@ -70,15 +73,22 @@ CONFIG_START_MONTH=11
 CONFIG_STDIO_BUFFER_SIZE=32
 CONFIG_STM32H7_BKPSRAM=y
 CONFIG_STM32H7_DMA1=y
+CONFIG_STM32H7_DMA2=y
 CONFIG_STM32H7_OTGFS=y
 CONFIG_STM32H7_PROGMEM=y
+CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
 CONFIG_STM32H7_TIM1=y
+CONFIG_STM32H7_UART7=y
 CONFIG_SYSTEMTICK_HOOK=y
 CONFIG_SYSTEM_CDCACM=y
 CONFIG_TASK_NAME_SIZE=24
 CONFIG_TTY_SIGINT=y
 CONFIG_TTY_SIGINT_CHAR=0x03
 CONFIG_TTY_SIGTSTP=y
+CONFIG_UART7_RXBUFSIZE=512
+CONFIG_UART7_RXDMA=y
+CONFIG_UART7_TXBUFSIZE=512
+CONFIG_UART7_TXDMA=y
 CONFIG_USBDEV=y
 CONFIG_USBDEV_BUSPOWERED=y
 CONFIG_USBDEV_MAXPOWER=500
@@ -1,7 +1,7 @@
 /************************************************************************************
- * nuttx-configs/px4_fmu-v6u/include/board.h
+ * nuttx-configs/px4_fmu-v6x/include/board.h
 *
- *   Copyright (C) 2016-2019 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016-2024 Gregory Nutt. All rights reserved.
 *   Authors: David Sidrane <david.sidrane@nscdg.com>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -32,8 +32,8 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/
-#ifndef __NUTTX_CONFIG_MICOAIR743_INCLUDE_BOARD_H
-#define __NUTTX_CONFIG_MICOAIR743_INCLUDE_BOARD_H
+#ifndef __NUTTX_CONFIG_PX4_FMU_V6X_INCLUDE_BOARD_H
+#define __NUTTX_CONFIG_PX4_FMU_V6X_INCLUDE_BOARD_H

 /************************************************************************************
 * Included Files
@@ -55,17 +55,17 @@
 ************************************************************************************/

 /* Clocking *************************************************************************/
-/* The MicoAir743  board provides the following clock sources:
+/* The px4_fmu-v6X  board provides the following clock sources:
 *
- *   X1: 8 MHz crystal for HSE
+ *   X1: 16 MHz crystal for HSE
 *
 * So we have these clock source available within the STM32
 *
- *   HSI: 64 MHz RC factory-trimmed
- *   HSE:  8 MHz crystal for HSE
+ *   HSI: 16 MHz RC factory-trimmed
+ *   HSE: 16 MHz crystal for HSE
 */

-#define STM32_BOARD_XTAL        8000000ul
+#define STM32_BOARD_XTAL        16000000ul

 #define STM32_HSI_FREQUENCY     16000000ul
 #define STM32_LSI_FREQUENCY     32000
@@ -74,7 +74,7 @@

 /* Main PLL Configuration.
 *
- * PLL source is HSE = 8,000,000
+ * PLL source is HSE = 16,000,000
 *
 * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
 * Subject to:
@@ -99,11 +99,11 @@

 /* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
 *
- *   PLL1_VCO = (8,000,000 / 1) * 120 = 960 MHz
+ *   PLL1_VCO = (16,000,000 / 1) * 40 = 640 MHz
 *
- *   PLL1P = PLL1_VCO/2  = 960 MHz / 2   = 480 MHz
- *   PLL1Q = PLL1_VCO/4  = 960 MHz / 4   = 240 MHz
- *   PLL1R = PLL1_VCO/8  = 960 MHz / 8   = 120 MHz
+ *   PLL1P = PLL1_VCO/2  = 640 MHz / 2   = 320 MHz
+ *   PLL1Q = PLL1_VCO/4  = 640 MHz / 4   = 160 MHz
+ *   PLL1R = PLL1_VCO/8  = 640 MHz / 8   = 80 MHz
 */

 #define STM32_PLLCFG_PLL1CFG    (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
@@ -112,12 +112,12 @@
 				 RCC_PLLCFGR_DIVQ1EN | \
 				 RCC_PLLCFGR_DIVR1EN)
 #define STM32_PLLCFG_PLL1M       RCC_PLLCKSELR_DIVM1(1)
-#define STM32_PLLCFG_PLL1N       RCC_PLL1DIVR_N1(120)
+#define STM32_PLLCFG_PLL1N       RCC_PLL1DIVR_N1(40)
 #define STM32_PLLCFG_PLL1P       RCC_PLL1DIVR_P1(2)
 #define STM32_PLLCFG_PLL1Q       RCC_PLL1DIVR_Q1(4)
 #define STM32_PLLCFG_PLL1R       RCC_PLL1DIVR_R1(8)

-#define STM32_VCO1_FREQUENCY     ((STM32_HSE_FREQUENCY / 1) * 120)
+#define STM32_VCO1_FREQUENCY     ((STM32_HSE_FREQUENCY / 1) * 40)
 #define STM32_PLL1P_FREQUENCY    (STM32_VCO1_FREQUENCY / 2)
 #define STM32_PLL1Q_FREQUENCY    (STM32_VCO1_FREQUENCY / 4)
 #define STM32_PLL1R_FREQUENCY    (STM32_VCO1_FREQUENCY / 8)
@@ -129,13 +129,13 @@
 				  RCC_PLLCFGR_DIVP2EN | \
 				  RCC_PLLCFGR_DIVQ2EN | \
 				  RCC_PLLCFGR_DIVR2EN)
-#define STM32_PLLCFG_PLL2M       RCC_PLLCKSELR_DIVM2(2)
+#define STM32_PLLCFG_PLL2M       RCC_PLLCKSELR_DIVM2(4)
 #define STM32_PLLCFG_PLL2N       RCC_PLL2DIVR_N2(48)
 #define STM32_PLLCFG_PLL2P       RCC_PLL2DIVR_P2(2)
 #define STM32_PLLCFG_PLL2Q       RCC_PLL2DIVR_Q2(2)
 #define STM32_PLLCFG_PLL2R       RCC_PLL2DIVR_R2(2)

-#define STM32_VCO2_FREQUENCY     ((STM32_HSE_FREQUENCY / 2) * 48)
+#define STM32_VCO2_FREQUENCY     ((STM32_HSE_FREQUENCY / 4) * 48)
 #define STM32_PLL2P_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
 #define STM32_PLL2Q_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
 #define STM32_PLL2R_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
@@ -145,13 +145,13 @@
 #define STM32_PLLCFG_PLL3CFG    (RCC_PLLCFGR_PLL3VCOSEL_WIDE | \
 				 RCC_PLLCFGR_PLL3RGE_4_8_MHZ | \
 				 RCC_PLLCFGR_DIVQ3EN)
-#define STM32_PLLCFG_PLL3M      RCC_PLLCKSELR_DIVM3(2)
+#define STM32_PLLCFG_PLL3M      RCC_PLLCKSELR_DIVM3(4)
 #define STM32_PLLCFG_PLL3N      RCC_PLL3DIVR_N3(48)
 #define STM32_PLLCFG_PLL3P      RCC_PLL3DIVR_P3(2)
 #define STM32_PLLCFG_PLL3Q      RCC_PLL3DIVR_Q3(4)
 #define STM32_PLLCFG_PLL3R      RCC_PLL3DIVR_R3(2)

-#define STM32_VCO3_FREQUENCY    ((STM32_HSE_FREQUENCY / 2) * 48)
+#define STM32_VCO3_FREQUENCY    ((STM32_HSE_FREQUENCY / 4) * 48)
 #define STM32_PLL3P_FREQUENCY   (STM32_VCO3_FREQUENCY / 2)
 #define STM32_PLL3Q_FREQUENCY   (STM32_VCO3_FREQUENCY / 4)
 #define STM32_PLL3R_FREQUENCY   (STM32_VCO3_FREQUENCY / 2)
@@ -167,7 +167,7 @@
 /* Configure Clock Assignments */

 /* AHB clock (HCLK) is SYSCLK/2 (240 MHz max)
- * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 240
+ * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 160
 */

 #define STM32_RCC_D1CFGR_HPRE   RCC_D1CFGR_HPRE_SYSCLKd2        /* HCLK  = SYSCLK / 2 */
@@ -175,22 +175,22 @@
 #define STM32_HCLK_FREQUENCY    (STM32_CPUCLK_FREQUENCY / 2)    /* HCLK in D2, HCLK4 in D3 */
 #define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY            /* same as above, to satisfy compiler */

-/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */
+/* APB1 clock (PCLK1) is HCLK/2 (80 MHz) */

 #define STM32_RCC_D2CFGR_D2PPRE1  RCC_D2CFGR_D2PPRE1_HCLKd2       /* PCLK1 = HCLK / 2 */
 #define STM32_PCLK1_FREQUENCY     (STM32_HCLK_FREQUENCY/2)

-/* APB2 clock (PCLK2) is HCLK/2 (120 MHz) */
+/* APB2 clock (PCLK2) is HCLK/2 (80 MHz) */

 #define STM32_RCC_D2CFGR_D2PPRE2  RCC_D2CFGR_D2PPRE2_HCLKd2       /* PCLK2 = HCLK / 2 */
 #define STM32_PCLK2_FREQUENCY     (STM32_HCLK_FREQUENCY/2)

-/* APB3 clock (PCLK3) is HCLK/2 (120 MHz) */
+/* APB3 clock (PCLK3) is HCLK/2 (80 MHz) */

 #define STM32_RCC_D1CFGR_D1PPRE   RCC_D1CFGR_D1PPRE_HCLKd2        /* PCLK3 = HCLK / 2 */
 #define STM32_PCLK3_FREQUENCY     (STM32_HCLK_FREQUENCY/2)

-/* APB4 clock (PCLK4) is HCLK/4 (120 MHz) */
+/* APB4 clock (PCLK4) is HCLK/4 (80 MHz) */

 #define STM32_RCC_D3CFGR_D3PPRE   RCC_D3CFGR_D3PPRE_HCLKd2       /* PCLK4 = HCLK / 2 */
 #define STM32_PCLK4_FREQUENCY     (STM32_HCLK_FREQUENCY/2)
@@ -248,9 +248,9 @@

 /* ADC 1 2 3 clock source */

-#define STM32_RCC_D3CCIPR_ADCSEL     RCC_D3CCIPR_ADCSEL_PLL2
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2

-/* FDCAN 1 clock source */
+/* FDCAN 1 2 clock source */

 #define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */

@@ -280,21 +280,21 @@

 /* SDMMC definitions ********************************************************/

-/* Init 480kHz, freq = PLL1Q/(2*div)  div =  PLL1Q/(2*freq) */
+/* Init 400kHz, freq = PLL1Q/(2*div)  div =  PLL1Q/(2*freq) */

 #define STM32_SDMMC_INIT_CLKDIV     (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)

-/* 20 MHz Max for now - more reliable on some boards than 25 MHz
- * 20 MHz = PLL1Q/(2*div), div =  PLL1Q/(2*freq), div = 6 = 240 / 40
+/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div =  PLL1Q/(2*freq)
+ * div = 4.8 = 240 / 50, So round up to 5 for default speed 24 MB/s
 */

 #if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA)
-#  define STM32_SDMMC_MMCXFR_CLKDIV   (6 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#  define STM32_SDMMC_MMCXFR_CLKDIV   (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #else
 #  define STM32_SDMMC_MMCXFR_CLKDIV   (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #endif
 #if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA)
-#  define STM32_SDMMC_SDXFR_CLKDIV    (6 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#  define STM32_SDMMC_SDXFR_CLKDIV    (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #else
 #  define STM32_SDMMC_SDXFR_CLKDIV    (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #endif
@@ -302,8 +302,18 @@
 #define STM32_SDMMC_CLKCR_EDGE      STM32_SDMMC_CLKCR_NEGEDGE

 /* LED definitions ******************************************************************/
-/* The board has two, LED_GREEN a Green LED and LED_BLUE a Blue LED,
- * that can be controlled by software.
+/* The ARKV6X board has three, LED_GREEN a Green LED, LED_BLUE a Blue LED and
+ * LED_RED a Red LED, that can be controlled by software.
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
+ * The following definitions are used to access individual LEDs.
+ */
+
+/* LED index values for use with board_userled() */
+
+/* LED definitions ******************************************************************/
+/* The px4_fmu-v6x board has three, LED_GREEN a Green LED, LED_BLUE a Blue LED and
+ * LED_RED a Red LED, that can be controlled by software.
 *
 * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
 * The following definitions are used to access individual LEDs.
@@ -353,74 +363,145 @@

 /* Alternate function pin selections ************************************************/

-#define GPIO_USART1_RX   GPIO_USART1_RX_2   /* PA10 */
-#define GPIO_USART1_TX   GPIO_USART1_TX_2   /* PA9  */
+#define GPIO_USART1_RX   GPIO_USART1_RX_3   /* PB7 */
+#define GPIO_USART1_TX   GPIO_USART1_TX_3   /* PB6 */

-#define GPIO_USART2_RX   GPIO_USART2_RX_1   /* PA3  */
-#define GPIO_USART2_TX   GPIO_USART2_TX_1   /* PA2  */
+#define GPIO_USART2_RX   GPIO_USART2_RX_1   /* PA3 */
+#define GPIO_USART2_TX   GPIO_USART2_TX_2   /* PD5 */

-#define GPIO_USART3_RX   GPIO_USART3_RX_3   /* PD9  */
-#define GPIO_USART3_TX   GPIO_USART3_TX_3   /* PD8  */
+#define GPIO_USART3_RX   GPIO_USART3_RX_3   /* PD9   */
+#define GPIO_USART3_TX   GPIO_USART3_TX_3   /* PD8   */

-#define GPIO_UART4_RX    GPIO_UART4_RX_2    /* PA1  */
-#define GPIO_UART4_TX    GPIO_UART4_TX_2    /* PA0  */
+#define GPIO_UART4_RX    GPIO_UART4_RX_6    /* PH14 */
+#define GPIO_UART4_TX    GPIO_UART4_TX_6    /* PH13 */

-#define GPIO_USART6_RX   GPIO_USART6_RX_1   /* PC7  */
+#define GPIO_UART5_RX    GPIO_UART5_RX_3    /* PD2  */
+#define GPIO_UART5_TX    GPIO_UART5_TX_3    /* PC12 */
+// GPIO_UART5_RTS  No remap                 /* PC8  */
+//#define GPIO_UART5_CTS   (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN9|GPIO_PULLDOWN)    /* PC9  */
+
+#define GPIO_USART6_RX   GPIO_USART6_RX_1   /* PC7 */
 #define GPIO_USART6_TX   GPIO_USART6_TX_1   /* PC6  */

-#define GPIO_UART7_RX    GPIO_UART7_RX_3    /* PE7  */
+#define GPIO_UART7_RX    GPIO_UART7_RX_4    /* PF6  */
 #define GPIO_UART7_TX    GPIO_UART7_TX_3    /* PE8  */
-
-
-#define GPIO_UART8_RX    GPIO_UART8_RX_1    /* PE0  */
-#define GPIO_UART8_TX    GPIO_UART8_TX_1    /* PE1  */
+#define GPIO_UART7_RTS   GPIO_UART7_RTS_2   /* PF8  */
+#define GPIO_UART7_CTS   (GPIO_UART7_CTS_1 | GPIO_PULLDOWN)   /* PE10 */


 /* CAN
 *
 * CAN1 is routed to transceiver.
 */
-
-#define GPIO_CAN1_RX     GPIO_CAN1_RX_2      /* PB8  */
-#define GPIO_CAN1_TX     GPIO_CAN1_TX_2      /* PB9  */
+#define GPIO_CAN1_RX     GPIO_CAN1_RX_3     /* PD0  */
+#define GPIO_CAN1_TX     GPIO_CAN1_TX_3     /* PD1  */

 /* SPI
+ * SPI1 is sensors1
+ * SPI2 is sensors2
+ * SPI3 is sensors3
+ * SPI4 is Not Used
+ * SPI5 is Not Used
+ * SPI6 is EXTERNAL1
 *
-
 */

 #define ADJ_SLEW_RATE(p) (((p) & ~GPIO_SPEED_MASK) | (GPIO_SPEED_2MHz))

-#define GPIO_SPI1_MISO   GPIO_SPI1_MISO_1               /* PA6  */
-#define GPIO_SPI1_MOSI   GPIO_SPI1_MOSI_1               /* PA7  */
-#define GPIO_SPI1_SCK    ADJ_SLEW_RATE(GPIO_SPI1_SCK_1) /* PA5 */
-
-#define GPIO_SPI2_MISO   GPIO_SPI2_MISO_2               /* PC2  */
-#define GPIO_SPI2_MOSI   GPIO_SPI2_MOSI_3               /* PC3 */
-#define GPIO_SPI2_SCK    ADJ_SLEW_RATE(GPIO_SPI2_SCK_5) /* PD3  */
-
+#define GPIO_SPI1_MISO   GPIO_SPI1_MISO_3               /* PG9  */
+#define GPIO_SPI1_MOSI   GPIO_SPI1_MOSI_2               /* PB5  */
+#define GPIO_SPI1_SCK    ADJ_SLEW_RATE(GPIO_SPI1_SCK_1) /* PA5  */

+#define GPIO_SPI6_MISO   GPIO_SPI6_MISO_2               /* PA6  */
+#define GPIO_SPI6_MOSI   GPIO_SPI6_MOSI_1               /* PG14 */
+#define GPIO_SPI6_SCK    ADJ_SLEW_RATE(GPIO_SPI6_SCK_3) /* PB3  */

 /* I2C
 *
-
+ *   The optional _GPIO configurations allow the I2C driver to manually
+ *   reset the bus to clear stuck slaves.  They match the pin configuration,
+ *   but are normally-high GPIOs.
 *
 */

-#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1       /* PB6  */
-#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1       /* PB7  */
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2       /* PB8  */
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2       /* PB9  */

-#define GPIO_I2C1_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
-#define GPIO_I2C1_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_I2C1_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_I2C1_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)

-#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1       /* PB10 */
-#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1       /* PB11 */
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2       /* PF1 */
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2       /* PF0 */

-#define GPIO_I2C2_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
-#define GPIO_I2C2_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN11)
+#define GPIO_I2C2_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN1)
+#define GPIO_I2C2_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN0)

+#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2       /* PF14 */
+#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2       /* PF15 */
+
+#define GPIO_I2C4_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN14)
+#define GPIO_I2C4_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN15)
+
+/* SDMMC2
+ *
+ *      VDD 3.3
+ *      GND
+ *      SDMMC2_CK                           PD6
+ *      SDMMC2_CMD                          PD7
+ *      SDMMC2_D0                           PB14
+ *      SDMMC2_D1                           PB15
+ *      SDMMC2_D2                           PG11
+ *      SDMMC2_D3                           PB4
+ */
+
+#define GPIO_SDMMC2_CK   GPIO_SDMMC2_CK_1  /* PD6 */
+#define GPIO_SDMMC2_CMD  GPIO_SDMMC2_CMD_1 /* PD7 */
+//      GPIO_SDMMC2_D0   No Remap          /* PB14 */
+//      GPIO_SDMMC2_D1   No Remap          /* PB15 */
+#define GPIO_SDMMC2_D2   GPIO_SDMMC2_D2_1  /* PG11 */
+//      GPIO_SDMMC2_D3    No Remap         /* PB4 */
+
+/* USB
+ *
+ *      OTG_FS_DM                           PA11
+ *      OTG_FS_DP                           PA12
+ *      VBUS                                PA9
+ */
+
+
+/* Board provides GPIO or other Hardware for signaling to timing analyzer */
+
+#if defined(CONFIG_BOARD_USE_PROBES)
+# include "stm32_gpio.h"
+# define PROBE_N(n) (1<<((n)-1))
+# define PROBE_1    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTI|GPIO_PIN0)   /* PI0 AUX1 */
+# define PROBE_2    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN12)  /* PH12 AUX2 */
+# define PROBE_3    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN11)  /* PH11 AUX3 */
+# define PROBE_4    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN10)  /* PH10 AUX4 */
+# define PROBE_5    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN13)  /* PD13 AUX5 */
+# define PROBE_6    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN14)  /* PD14 AUX6 */
+# define PROBE_7    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN6)   /* PH6  AUX7 */
+# define PROBE_8    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN9)   /* PH9  AUX8 */
+
+# define PROBE_INIT(mask) \
+	do { \
+		if ((mask)& PROBE_N(1)) { stm32_configgpio(PROBE_1); } \
+		if ((mask)& PROBE_N(2)) { stm32_configgpio(PROBE_2); } \
+		if ((mask)& PROBE_N(3)) { stm32_configgpio(PROBE_3); } \
+		if ((mask)& PROBE_N(4)) { stm32_configgpio(PROBE_4); } \
+		if ((mask)& PROBE_N(5)) { stm32_configgpio(PROBE_5); } \
+		if ((mask)& PROBE_N(6)) { stm32_configgpio(PROBE_6); } \
+		if ((mask)& PROBE_N(7)) { stm32_configgpio(PROBE_7); } \
+		if ((mask)& PROBE_N(8)) { stm32_configgpio(PROBE_8); } \
+		if ((mask)& PROBE_N(9)) { stm32_configgpio(PROBE_9); } \
+	} while(0)
+
+# define PROBE(n,s)  do {stm32_gpiowrite(PROBE_##n,(s));}while(0)
+# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true)
+#else
 # define PROBE_INIT(mask)
 # define PROBE(n,s)
 # define PROBE_MARK(n)
+#endif

-#endif  /*__NUTTX_CONFIG_MICOAIR743_INCLUDE_BOARD_H  */
+#endif  /*__NUTTX_CONFIG_PX4_FMU_V6X_INCLUDE_BOARD_H  */
@@ -0,0 +1,108 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2024 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#pragma once
+
+// DMAMUX1 Using at most 8 Channels on DMA1 --------   Assigned
+//                                                     V
+
+// Timer 4 Channel 1                               /* DMA1:29 TIM4CH1 */
+
+#define DMAMAP_SPI1_RX    DMAMAP_DMA12_SPI1RX_0   /* 1 DMA1:37 IIM-42653 */
+#define DMAMAP_SPI1_TX    DMAMAP_DMA12_SPI1TX_0   /* 2 DMA1:38 IIM-42653 */
+
+//#define DMAMAP_SPI2_RX    DMAMAP_DMA12_SPI2RX_0  /* 3 DMA1:39 ICM-42688-P */
+//#define DMAMAP_SPI2_TX    DMAMAP_DMA12_SPI2TX_0  /* 4 DMA1:40 ICM-42688-P */
+
+#define DMAMAP_USART1_RX  DMAMAP_DMA12_USART1RX_0 /*  DMA1:41  GPS1 */
+#define DMAMAP_USART1_TX  DMAMAP_DMA12_USART1TX_0 /*  DMA1:42  GPS1 */
+
+//#define DMAMAP_USART3_RX  DMAMAP_DMA12_USART3RX_0 /*  DMA1:45 DEBUG */
+//#define DMAMAP_USART3_TX  DMAMAP_DMA12_USART3TX_0 /*  DMA1:46 DEBUG */
+
+// Timer 8 Channel 1                               /* DMA1:47 TIM8CH1 */
+// Timer 8 Channel 2                               /* DMA1:48 TIM8CH2 */
+// Timer 8 Channel 3                               /* DMA1:49 TIM8CH3 */
+// Timer 8 Channel 4                               /* DMA1:50 TIM8CH4 */
+
+// Timer 5 Channel 1                               /* DMA1:55 TIM5CH1 */
+// Timer 5 Channel 2                               /* DMA1:56 TIM5CH2 */
+// Timer 5 Channel 3                               /* DMA1:57 TIM5CH3 */
+// Timer 5 Channel 4                               /* DMA1:58 TIM5CH4 */
+
+// #define DMAMAP_UART4_RX   DMAMAP_DMA12_UART4RX_0  /*  DMA1:63 UART4 */
+// #define DMAMAP_UART4_TX   DMAMAP_DMA12_UART4TX_0  /*  DMA1:64 UART4 */
+
+#define DMAMAP_USART6_RX  DMAMAP_DMA12_USART6RX_0 /* 5 DMA1:71 RC */
+// #define DMAMAP_USART6_TX  DMAMAP_DMA12_USART6TX_0 /* 6 DMA1:72 RC */
+
+// Assigned in timer_config.cpp
+
+// Timer 4                                          /* 7 DMA1:32 TIM4UP */
+// Timer 5                                          /* 8 DMA1:50 TIM5UP */
+
+// DMAMUX2 Using at most 8 Channels on DMA2 --------   Assigned
+//                                                     V
+
+// Timer 4 Channel 1                               /* DMA2:29 TIM4CH1 */
+
+#define DMAMAP_USART2_RX  DMAMAP_DMA12_USART2RX_1   /* 3 DMA2:43 TELEM3 */
+#define DMAMAP_USART2_TX  DMAMAP_DMA12_USART2TX_1   /* 4 DMA2:44 TELEM3 */
+
+#define DMAMAP_USART3_RX  DMAMAP_DMA12_USART3RX_1   /* 3 DMA2:45 DEBUG */
+#define DMAMAP_USART3_TX  DMAMAP_DMA12_USART3TX_1   /* 4 DMA2:46 DEBUG */
+
+// Timer 8 Channel 1                                 /* DMA2:47 TIM8CH1 */
+// Timer 8 Channel 2                                 /* DMA2:48 TIM8CH2 */
+// Timer 8 Channel 3                                 /* DMA2:49 TIM8CH3 */
+// Timer 8 Channel 4                                 /* DMA2:50 TIM8CH4 */
+
+// Timer 5 Channel 1                                 /* DMA2:55 TIM5CH1 */
+// Timer 5 Channel 2                                 /* DMA2:56 TIM5CH2 */
+// Timer 5 Channel 3                                 /* DMA2:57 TIM5CH3 */
+// Timer 5 Channel 4                                 /* DMA2:58 TIM5CH4 */
+
+//#define DMAMAP_SPI3_RX    DMAMAP_DMA12_SPI3RX_1     /* 1 DMA2:61 BMI088 */
+//#define DMAMAP_SPI3_TX    DMAMAP_DMA12_SPI3TX_1     /* 2 DMA2:62 BMI088 */
+
+#define DMAMAP_UART5_RX   DMAMAP_DMA12_UART5RX_1    /* 5 DMA2:65 TELEM2 */
+#define DMAMAP_UART5_TX   DMAMAP_DMA12_UART5TX_1    /* 6 DMA2:66 TELEM2 */
+
+#define DMAMAP_UART7_RX   DMAMAP_DMA12_UART7RX_1    /* 7 DMA1:79 TELEM1 */
+#define DMAMAP_UART7_TX   DMAMAP_DMA12_UART7TX_1    /* 8 DMA1:80 TELEM1 */
+
+// DMAMUX2 Using at most 8 Channels on BDMA --------   Assigned
+//                                                     V
+
+#define DMAMAP_SPI6_RX    DMAMAP_BDMA_SPI6_RX       /* 1 BDMA:11 SPI J11 */
+#define DMAMAP_SPI6_TX    DMAMAP_BDMA_SPI6_TX       /* 2 BDMA:12 SPI J11 */
@@ -5,7 +5,6 @@
 # You can then do "make savedefconfig" to generate a new defconfig file that includes your
 # modifications.
 #
-# CONFIG_DEV_CONSOLE is not set
 # CONFIG_DISABLE_ENVIRON is not set
 # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
 # CONFIG_DISABLE_PTHREAD is not set
@@ -23,11 +22,12 @@
 # CONFIG_NSH_DISABLE_ECHO is not set
 # CONFIG_NSH_DISABLE_ENV is not set
 # CONFIG_NSH_DISABLE_EXEC is not set
-# CONFIG_NSH_DISABLE_EXIT is not set
 # CONFIG_NSH_DISABLE_EXPORT is not set
 # CONFIG_NSH_DISABLE_FREE is not set
 # CONFIG_NSH_DISABLE_GET is not set
 # CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_IFUPDOWN is not set
 # CONFIG_NSH_DISABLE_ITEF is not set
 # CONFIG_NSH_DISABLE_KILL is not set
 # CONFIG_NSH_DISABLE_LOOPS is not set
@@ -36,7 +36,6 @@
 # CONFIG_NSH_DISABLE_MKFATFS is not set
 # CONFIG_NSH_DISABLE_MOUNT is not set
 # CONFIG_NSH_DISABLE_MV is not set
-# CONFIG_NSH_DISABLE_PRINTF is not set
 # CONFIG_NSH_DISABLE_PS is not set
 # CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set
 # CONFIG_NSH_DISABLE_PWD is not set
@@ -46,6 +45,7 @@
 # CONFIG_NSH_DISABLE_SET is not set
 # CONFIG_NSH_DISABLE_SLEEP is not set
 # CONFIG_NSH_DISABLE_SOURCE is not set
+# CONFIG_NSH_DISABLE_TELNETD is not set
 # CONFIG_NSH_DISABLE_TEST is not set
 # CONFIG_NSH_DISABLE_TIME is not set
 # CONFIG_NSH_DISABLE_UMOUNT is not set
@@ -53,11 +53,11 @@
 # CONFIG_NSH_DISABLE_USLEEP is not set
 CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD_CUSTOM=y
-CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/micoair/h743/nuttx-config"
+CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/ark/fpv/nuttx-config"
 CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
-CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
+CONFIG_ARCH_BOARD_CUSTOM_NAME="ark"
 CONFIG_ARCH_CHIP="stm32h7"
-CONFIG_ARCH_CHIP_STM32H743VI=y
+CONFIG_ARCH_CHIP_STM32H743II=y
 CONFIG_ARCH_CHIP_STM32H7=y
 CONFIG_ARCH_INTERRUPTSTACK=768
 CONFIG_ARCH_STACKDUMP=y
@@ -67,23 +67,26 @@ CONFIG_ARMV7M_DTCM=y
 CONFIG_ARMV7M_ICACHE=y
 CONFIG_ARMV7M_MEMCPY=y
 CONFIG_ARMV7M_USEBASEPRI=y
+CONFIG_ARM_MPU_EARLY_RESET=y
 CONFIG_BOARDCTL_RESET=y
 CONFIG_BOARD_ASSERT_RESET_VALUE=0
 CONFIG_BOARD_CRASHDUMP=y
-CONFIG_BOARD_LOOPSPERMSEC=95150
+CONFIG_BOARD_LOOPSPERMSEC=95751
 CONFIG_BOARD_RESET_ON_ASSERT=2
 CONFIG_BUILTIN=y
 CONFIG_CDCACM=y
-CONFIG_CDCACM_PRODUCTID=0x0036
-CONFIG_CDCACM_PRODUCTSTR="MicoAir743"
+CONFIG_CDCACM_IFLOWCONTROL=y
+CONFIG_CDCACM_PRODUCTID=0x003B
+CONFIG_CDCACM_PRODUCTSTR="ARK FPV.x"
 CONFIG_CDCACM_RXBUFSIZE=600
 CONFIG_CDCACM_TXBUFSIZE=12000
-CONFIG_CDCACM_VENDORID=0x1B8C
-CONFIG_CDCACM_VENDORSTR="MicoAir"
+CONFIG_CDCACM_VENDORID=0x3185
+CONFIG_CDCACM_VENDORSTR="ARK"
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_HARDFAULT_ALERT=y
 CONFIG_DEBUG_MEMFAULT=y
 CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_TCBINFO=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_FIFO_SIZE=0
 CONFIG_DEV_PIPE_MAXSIZE=1024
@@ -112,8 +115,6 @@ CONFIG_I2C_RESET=y
 CONFIG_IDLETHREAD_STACKSIZE=750
 CONFIG_INIT_ENTRYPOINT="nsh_main"
 CONFIG_INIT_STACKSIZE=3194
-CONFIG_IOB_NBUFFERS=24
-CONFIG_IOB_NCHAINS=24
 CONFIG_LIBC_FLOATINGPOINT=y
 CONFIG_LIBC_LONG_LONG=y
 CONFIG_LIBC_MAX_EXITFUNS=1
@@ -123,8 +124,12 @@ CONFIG_MEMSET_OPTSPEED=y
 CONFIG_MMCSD=y
 CONFIG_MMCSD_SDIO=y
 CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y
-CONFIG_MM_IOB=y
 CONFIG_MM_REGIONS=4
+CONFIG_MTD=y
+CONFIG_MTD_BYTE_WRITE=y
+CONFIG_MTD_PARTITION=y
+CONFIG_MTD_PROGMEM=y
+CONFIG_MTD_RAMTRON=y
 CONFIG_NAME_MAX=40
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_ARGCAT=y
@@ -145,9 +150,14 @@ CONFIG_PREALLOC_TIMERS=50
 CONFIG_PRIORITY_INHERITANCE=y
 CONFIG_PTHREAD_MUTEX_ROBUST=y
 CONFIG_PTHREAD_STACK_MIN=512
+CONFIG_RAMTRON_EMULATE_PAGE_SHIFT=5
+CONFIG_RAMTRON_EMULATE_SECTOR_SHIFT=5
+CONFIG_RAMTRON_SETSPEED=y
 CONFIG_RAM_SIZE=245760
 CONFIG_RAM_START=0x20010000
 CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
 CONFIG_RTC_DATETIME=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_SCHED_HPWORKPRIORITY=249
@@ -159,8 +169,9 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
-CONFIG_SDMMC1_SDIO_PULLUP=y
+CONFIG_SDMMC2_SDIO_PULLUP=y
 CONFIG_SEM_PREALLOCHOLDERS=32
+CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
 CONFIG_SIG_SIGALRM_ACTION=y
@@ -181,31 +192,37 @@ CONFIG_STM32H7_DMA1=y
 CONFIG_STM32H7_DMA2=y
 CONFIG_STM32H7_DMACAPABLE=y
 CONFIG_STM32H7_FLASH_OVERRIDE_I=y
+CONFIG_STM32H7_FLOWCONTROL_BROKEN=y
 CONFIG_STM32H7_I2C1=y
 CONFIG_STM32H7_I2C2=y
+CONFIG_STM32H7_I2C4=y
 CONFIG_STM32H7_I2C_DYNTIMEO=y
 CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP=10
 CONFIG_STM32H7_OTGFS=y
 CONFIG_STM32H7_PROGMEM=y
 CONFIG_STM32H7_RTC=y
-CONFIG_STM32H7_RTC_HSECLOCK=y
+CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y
 CONFIG_STM32H7_RTC_MAGIC_REG=1
 CONFIG_STM32H7_SAVE_CRASHDUMP=y
-CONFIG_STM32H7_SDMMC1=y
+CONFIG_STM32H7_SDMMC2=y
 CONFIG_STM32H7_SERIALBRK_BSDCOMPAT=y
 CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
 CONFIG_STM32H7_SPI1=y
-CONFIG_STM32H7_SPI2=y
-CONFIG_STM32H7_SPI2_DMA=y
-CONFIG_STM32H7_SPI2_DMA_BUFFER=4096
-CONFIG_STM32H7_SPI_DMATHRESHOLD=8
+CONFIG_STM32H7_SPI1_DMA=y
+CONFIG_STM32H7_SPI1_DMA_BUFFER=1024
+CONFIG_STM32H7_SPI6=y
+CONFIG_STM32H7_SPI6_DMA=y
+CONFIG_STM32H7_SPI6_DMA_BUFFER=1024
 CONFIG_STM32H7_TIM1=y
+CONFIG_STM32H7_TIM2=y
 CONFIG_STM32H7_TIM3=y
 CONFIG_STM32H7_TIM4=y
+CONFIG_STM32H7_TIM5=y
 CONFIG_STM32H7_TIM8=y
+CONFIG_STM32H7_TIM12=y
 CONFIG_STM32H7_UART4=y
+CONFIG_STM32H7_UART5=y
 CONFIG_STM32H7_UART7=y
-CONFIG_STM32H7_UART8=y
 CONFIG_STM32H7_USART1=y
 CONFIG_STM32H7_USART2=y
 CONFIG_STM32H7_USART3=y
@@ -220,22 +237,39 @@ CONFIG_TASK_NAME_SIZE=24
 CONFIG_UART4_BAUD=57600
 CONFIG_UART4_RXBUFSIZE=600
 CONFIG_UART4_TXBUFSIZE=1500
+CONFIG_UART5_IFLOWCONTROL=y
+CONFIG_UART5_OFLOWCONTROL=y
+CONFIG_UART5_RXDMA=y
+CONFIG_UART5_RXBUFSIZE=600
+CONFIG_UART5_TXBUFSIZE=10000
+CONFIG_UART5_TXDMA=y
 CONFIG_UART7_BAUD=57600
+CONFIG_UART7_IFLOWCONTROL=y
+CONFIG_UART7_OFLOWCONTROL=y
 CONFIG_UART7_RXBUFSIZE=600
-CONFIG_UART7_TXBUFSIZE=1500
-CONFIG_UART8_BAUD=57600
-CONFIG_UART8_RXBUFSIZE=600
-CONFIG_UART8_TXBUFSIZE=1500
+CONFIG_UART7_RXDMA=y
+CONFIG_UART7_TXBUFSIZE=3000
+CONFIG_UART7_TXDMA=y
 CONFIG_USART1_BAUD=57600
+CONFIG_USART1_RXDMA=y
+CONFIG_USART1_TXDMA=y
 CONFIG_USART1_RXBUFSIZE=600
 CONFIG_USART1_TXBUFSIZE=1500
 CONFIG_USART2_BAUD=57600
+CONFIG_USART2_RXDMA=y
+CONFIG_USART2_TXDMA=y
 CONFIG_USART2_RXBUFSIZE=600
 CONFIG_USART2_TXBUFSIZE=1500
 CONFIG_USART3_BAUD=57600
-CONFIG_USART3_RXBUFSIZE=600
+CONFIG_USART3_RXBUFSIZE=180
+CONFIG_USART3_RXDMA=y
+CONFIG_USART3_SERIAL_CONSOLE=y
 CONFIG_USART3_TXBUFSIZE=1500
+CONFIG_USART3_TXDMA=y
 CONFIG_USART6_BAUD=57600
+CONFIG_USART6_RXDMA=y
+CONFIG_USART6_RXBUFSIZE=600
+CONFIG_USART6_TXBUFSIZE=1500
 CONFIG_USART6_RXBUFSIZE=600
 CONFIG_USART6_TXBUFSIZE=1500
 CONFIG_USBDEV=y
@@ -1,7 +1,7 @@
 /****************************************************************************
 * scripts/script.ld
 *
- *   Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016, 2024 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 *
@@ -34,7 +34,7 @@
 *
 ****************************************************************************/

-/* The Durandal-v1 uses an STM32H743II has 2048Kb of main FLASH memory.
+/* The ARKV6X uses an STM32H743II has 2048Kb of main FLASH memory.
 * The flash memory is partitioned into a User Flash memory and a System
 * Flash memory. Each of these memories has two banks:
 *
@@ -59,11 +59,11 @@
 *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
 *      ST programmed value: System bootloader at 0x1FF0:0000
 *
- * The Durandal has a Swtich on board, the BOOT0 pin is at ground so by default,
- * the STM32 will boot to address 0x0800:0000 in FLASH unless the swiutch is
- * drepresed, then the boot will be from 0x1FF0:0000
+ * The ARKV6X has a test point on board, the BOOT0 pin is at ground so by
+ * default, the STM32 will boot to address 0x0800:0000 in FLASH unless the test
+ * point is pulled to 3.3V.then the boot will be from 0x1FF0:0000
 *
- * The STM32H743ZI also has 1024Kb of data SRAM.
+ * The STM32H743II also has 1024Kb of data SRAM.
 * SRAM is split up into several blocks and into three power domains:
 *
 *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with
@@ -105,12 +105,14 @@
 * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
 * where the code expects to begin execution by jumping to the entry point in
 * the 0x0800:0000 address range.
+ *
+ * The bootloader uses the first sector of the flash, which is 128K in length.
 */

 MEMORY
 {
 	itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
-	flash (rx)  : ORIGIN = 0x08000000, LENGTH = 2048K
+	flash (rx)  : ORIGIN = 0x08000000, LENGTH =  128K
 	dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
 	dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
 	sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
@@ -1,7 +1,7 @@
 /****************************************************************************
 * scripts/script.ld
 *
- *   Copyright (C) 2020 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016, 2024 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 *
@@ -34,7 +34,7 @@
 *
 ****************************************************************************/

-/* The board uses an STM32H743II and has 2048Kb of main FLASH memory.
+/* The ARKV6X uses an STM32H743II has 2048Kb of main FLASH memory.
 * The flash memory is partitioned into a User Flash memory and a System
 * Flash memory. Each of these memories has two banks:
 *
@@ -59,11 +59,11 @@
 *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
 *      ST programmed value: System bootloader at 0x1FF0:0000
 *
- * There's a switch on board, the BOOT0 pin is at ground so by default,
- * the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is
- * drepresed, then the boot will be from 0x1FF0:0000
+ * The ARKV6X has a test point on board, the BOOT0 pin is at ground so by
+ * default, the STM32 will boot to address 0x0800:0000 in FLASH unless the test
+ * point is pulled to 3.3V.then the boot will be from 0x1FF0:0000
 *
- * The STM32H743ZI also has 1024Kb of data SRAM.
+ * The STM32H743II also has 1024Kb of data SRAM.
 * SRAM is split up into several blocks and into three power domains:
 *
 *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with
@@ -110,7 +110,7 @@
 MEMORY
 {
 	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
-	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1792K
+	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1792K /* params in last sector */

 	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
 	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
@@ -132,6 +132,7 @@ ENTRY(_stext)
 */
 EXTERN(abort)
 EXTERN(_bootdelay_signature)
+EXTERN(board_get_manifest)

 SECTIONS
 {
@@ -1,6 +1,6 @@
 ############################################################################
 #
-#   Copyright (c) 2021 PX4 Development Team. All rights reserved.
+#   Copyright (c) 2016 PX4 Development Team. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
@@ -31,25 +31,34 @@
 #
 ############################################################################
 if("${PX4_BOARD_LABEL}" STREQUAL  "bootloader")
+	add_compile_definitions(BOOTLOADER)
 	add_library(drivers_board
 		bootloader_main.c
+		init.c
 		usb.c
+		timer_config.cpp
 	)
 	target_link_libraries(drivers_board
 		PRIVATE
-			nuttx_arch
-			nuttx_drivers
+			nuttx_arch # sdio
+			nuttx_drivers # sdio
+			px4_layer #gpio
+			arch_io_pins # iotimer
 			bootloader
 	)
 	target_include_directories(drivers_board PRIVATE ${PX4_SOURCE_DIR}/platforms/nuttx/src/bootloader/common)

 else()
 	add_library(drivers_board
+		can.c
 		i2c.cpp
 		init.c
 		led.c
+		mtd.cpp
 		sdio.c
 		spi.cpp
+		spix_sync.c
+		spix_sync.h
 		timer_config.cpp
 		usb.c
 	)
@@ -60,9 +69,9 @@ else()
 			arch_io_pins
 			arch_spi
 			arch_board_hw_info
-			drivers__led
-			nuttx_arch
-			nuttx_drivers
+			drivers__led # drv_led_start
+			nuttx_arch # sdio
+			nuttx_drivers # sdio
 			px4_layer
 	)
 endif()
@@ -0,0 +1,397 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2016-2024 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file board_config.h
+ *
+ * ARK FPV internal definitions
+ */
+
+#pragma once
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+
+#include <stm32_gpio.h>
+
+/****************************************************************************************************
+ * Definitions
+ ****************************************************************************************************/
+
+#undef TRACE_PINS
+
+/* Configuration ************************************************************************************/
+
+#  define BOARD_HAS_USB_VALID           1
+#  define BOARD_HAS_NBAT_V              1
+#  define BOARD_HAS_NBAT_I              1
+
+/* PX4FMU GPIOs ***********************************************************************************/
+
+/* Trace Clock and D0-D3 are available on the trace connector
+ *
+ * TRACECLK PE2  - Dedicated       - Trace Connector Pin 1
+ * TRACED0  PE3  - nLED_RED        - Trace Connector Pin 3
+ * TRACED1  PE4  - nLED_GREEN      - Trace Connector Pin 5
+ * TRACED2  PE5  - nLED_BLUE       - Trace Connector Pin 7
+ * TRACED3  PE6  - nARMED          - Trace Connector Pin 8
+
+ */
+
+/* LEDs are driven with push open drain to support Anode to 5V or 3.3V or used as TRACE0-2 */
+
+#if !defined(TRACE_PINS)
+#  define GPIO_nLED_RED        /* PE3 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
+#  define GPIO_nLED_GREEN      /* PE4 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4)
+#  define GPIO_nLED_BLUE       /* PE5 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN5)
+
+#  define BOARD_HAS_CONTROL_STATUS_LEDS      1
+#  define BOARD_OVERLOAD_LED     LED_RED
+#  define BOARD_ARMED_STATE_LED  LED_BLUE
+
+#else
+
+#  define GPIO_TRACECLK1 (GPIO_TRACECLK |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2)
+#  define GPIO_TRACED0   (GPIO_TRACED0_2|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3)
+#  define GPIO_TRACED1   (GPIO_TRACED1_2|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4)
+#  define GPIO_TRACED2   (GPIO_TRACED2_2|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5)
+#  define GPIO_TRACED3   (GPIO_TRACED3_2|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6)
+//#define GPIO_TRACESWO                        //(GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
+
+#  undef  BOARD_HAS_CONTROL_STATUS_LEDS
+#  undef  BOARD_OVERLOAD_LED
+#  undef  BOARD_ARMED_STATE_LED
+
+#  define GPIO_nLED_RED    GPIO_TRACED0
+#  define GPIO_nLED_GREEN  GPIO_TRACED1
+#  define GPIO_nLED_BLUE   GPIO_TRACED2
+#  define GPIO_nARMED      GPIO_TRACED3
+#  define GPIO_nARMED_INIT GPIO_TRACED3
+#endif
+
+/* SPI */
+
+#define SPI6_nRESET_EXTERNAL1       /* PF10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTF|GPIO_PIN10)
+#define SPI6_RESET(on_true)          px4_arch_gpiowrite(SPI6_nRESET_EXTERNAL1, !(on_true))
+
+/* I2C busses */
+
+/* Devices on the onboard buses.
+ *
+ * Note that these are unshifted addresses.
+ */
+#define PX4_I2C_OBDEV_SE050         0x48
+
+/*
+ * ADC channels
+ *
+ * These are the channel numbers of the ADCs of the microcontroller that
+ * can be used by the Px4 Firmware in the adc driver
+ */
+
+/* ADC defines to be used in sensors.cpp to read from a particular channel */
+
+#define ADC1_CH(n)                  (n)
+
+/* N.B. there is no offset mapping needed for ADC3 because */
+#define ADC3_CH(n)                  (n)
+
+/* We are only use ADC3 for REV/VER.
+ * ADC3_6V6 and ADC3_3V3 are mapped back to ADC1
+ * To do this We are relying on PC2_C, PC3_C being connected to PC2, PC3
+ * respectively by the SYSCFG_PMCR default of setting for PC3SO PC2SO PA1SO
+ * PA0SO of 0.
+ *
+ *  0 Analog switch closed (pads are connected through the analog switch)
+ *
+ * So ADC3_INP0 is GPIO_ADC123_INP12
+ *    ADC3_INP1 is GPIO_ADC12_INP13
+ */
+
+/* Define GPIO pins used as ADC N.B. Channel numbers must match below  */
+
+#define PX4_ADC_GPIO  \
+	/* PA0  */  GPIO_ADC1_INP16,   \
+	/* PA4  */  GPIO_ADC12_INP18,  \
+	/* PB0  */  GPIO_ADC12_INP9,   \
+	/* PB1  */  GPIO_ADC12_INP5,   \
+	/* PC2  */  GPIO_ADC123_INP12, \
+	/* PC3  */  GPIO_ADC12_INP13,  \
+	/* PF12 */  GPIO_ADC1_INP6,    \
+	/* PH3  */  GPIO_ADC3_INP14,   \
+	/* PH4  */  GPIO_ADC3_INP15
+
+/* Define Channel numbers must match above GPIO pin IN(n)*/
+#define ADC_BATTERY_VOLTAGE_CHANNEL        	/* PB0 */  ADC1_CH(9)
+#define ADC_BATTERY_CURRENT_CHANNEL        	/* PC2 */  ADC3_CH(12)
+#define ADC_SCALED_12V_CHANNEL	     		/* PA4 */  ADC1_CH(18)
+#define ADC_SCALED_VDD_3V3_SENSORS_CHANNEL     /* PA0 */  ADC1_CH(16)
+#define ADC_SCALED_V5_CHANNEL                   /* PB1 */  ADC1_CH(5)
+#define ADC_HW_VER_SENSE_CHANNEL                /* PH3 */  ADC3_CH(14)
+#define ADC_HW_REV_SENSE_CHANNEL                /* PH4 */  ADC3_CH(15)
+
+#define ADC_CHANNELS \
+	((1 << ADC_BATTERY_VOLTAGE_CHANNEL)         | \
+	 (1 << ADC_BATTERY_CURRENT_CHANNEL)         | \
+	 (1 << ADC_SCALED_VDD_3V3_SENSORS_CHANNEL)  | \
+	 (1 << ADC_SCALED_V5_CHANNEL)               | \
+	 (1 << ADC_SCALED_12V_CHANNEL))
+
+
+#define BOARD_BATTERY1_V_DIV	 (21.0f) // (20k + 1k) / 1k = 21
+
+#define ADC_SCALED_PAYLOAD_SENSE ADC_SCALED_12V_CHANNEL
+
+/* HW has to large of R termination on ADC todo:change when HW value is chosen */
+
+#define HW_REV_VER_ADC_BASE STM32_ADC3_BASE
+
+#define SYSTEM_ADC_BASE STM32_ADC1_BASE
+
+/* HW has to large of R termination on ADC todo:change when HW value is chosen */
+#define BOARD_ADC_OPEN_CIRCUIT_V     (5.6f)
+
+/* HW Version and Revision drive signals Default to 1 to detect */
+#define BOARD_HAS_HW_SPLIT_VERSIONING
+
+#define GPIO_HW_VER_REV_DRIVE  /* PG0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN0)
+#define GPIO_HW_REV_SENSE      /* PH4 */  GPIO_ADC3_INP15
+#define GPIO_HW_VER_SENSE      /* PH3 */  GPIO_ADC3_INP14
+#define HW_INFO_INIT_PREFIX    "ARKFPV"
+
+#define BOARD_NUM_SPI_CFG_HW_VERSIONS 2
+//                 Base/FMUM
+#define ARKFPV_0   HW_FMUM_ID(0x0) // ARKFPV,     Sensor Set  Rev 0
+#define ARKFPV_1   HW_FMUM_ID(0x1) // ARKFPV,     Sensor Set  Rev 1
+
+#define UAVCAN_NUM_IFACES_RUNTIME  1
+
+/* HEATER
+ * PWM in future
+ */
+#define GPIO_HEATER_OUTPUT   /* PB10  T2CH3 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
+#define HEATER_OUTPUT_EN(on_true)	       px4_arch_gpiowrite(GPIO_HEATER_OUTPUT, (on_true))
+
+/* PE6 is nARMED
+ *  The GPIO will be set as input while not armed HW will have external HW Pull UP.
+ *  While armed it shall be configured at a GPIO OUT set LOW
+ */
+#if !defined(TRACE_PINS)
+#define GPIO_nARMED_INIT     /* PE6 */  (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN6)
+#define GPIO_nARMED          /* PE6 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN6)
+#define BOARD_INDICATE_EXTERNAL_LOCKOUT_STATE(enabled)  px4_arch_configgpio((enabled) ? GPIO_nARMED : GPIO_nARMED_INIT)
+#define BOARD_GET_EXTERNAL_LOCKOUT_STATE() px4_arch_gpioread(GPIO_nARMED)
+#endif
+
+/* PWM
+ */
+#define DIRECT_PWM_OUTPUT_CHANNELS   9
+
+#define GPIO_FMU_CH1                    /* PI0  */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTI|GPIO_PIN0)
+#define GPIO_FMU_CH2                    /* PH12 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTH|GPIO_PIN12)
+#define GPIO_FMU_CH3                    /* PH11 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTH|GPIO_PIN11)
+#define GPIO_FMU_CH4                    /* PH10 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTH|GPIO_PIN10)
+#define GPIO_FMU_CH5                    /* PI5  */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTI|GPIO_PIN5)
+#define GPIO_FMU_CH6                    /* PI6  */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTI|GPIO_PIN6)
+#define GPIO_FMU_CH7                    /* PI7  */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTI|GPIO_PIN7)
+#define GPIO_FMU_CH8                    /* PI2  */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTI|GPIO_PIN2)
+#define GPIO_FMU_CH9                    /* PD12 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTD|GPIO_PIN12)
+
+#define GPIO_SPIX_SYNC                  /* PE9  */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTE|GPIO_PIN9)
+
+/* Power supply control and monitoring GPIOs */
+
+#define GPIO_VDD_5V_PGOOD         	/* PF13 */ (GPIO_INPUT |GPIO_FLOAT|GPIO_PORTF|GPIO_PIN13)
+#define GPIO_VDD_12V_PGOOD	 	/* PE15 */ (GPIO_INPUT |GPIO_FLOAT|GPIO_PORTE|GPIO_PIN15)
+#define GPIO_5V_ON_BATTERY	 	/* PG1  */ (GPIO_INPUT |GPIO_FLOAT|GPIO_PORTG|GPIO_PIN1)
+#define GPIO_VDD_12V_EN			/* PG4  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN4)
+
+#define GPIO_VDD_3V3_SD_CARD_EN         /* PC13 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN13)
+
+
+#define BOARD_NUMBER_BRICKS             1
+
+/* Define True logic Power Control in arch agnostic form */
+
+#define VDD_3V3_SD_CARD_EN(on_true)        px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
+#define PAYLOAD_POWER_EN(on_true)          px4_arch_gpiowrite(GPIO_VDD_12V_EN, (on_true))
+
+/* USB OTG FS
+ *
+ * PA9  OTG_FS_VBUS VBUS sensing
+ */
+#define GPIO_OTGFS_VBUS         /* PA9 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN9)
+
+#define FLASH_BASED_PARAMS
+
+/* High-resolution timer */
+#define HRT_TIMER               3  /* use timer3 for the HRT */
+#define HRT_TIMER_CHANNEL       1 /* use capture/compare channel 1 */
+
+/* RC Serial port */
+
+#define RC_SERIAL_PORT                     "/dev/ttyS4"
+
+/* PWM input driver. Use FMU AUX5 pins attached to timer4 channel 2 */
+#define PWMIN_TIMER                       4
+#define PWMIN_TIMER_CHANNEL    /* T4C2 */ 2
+#define GPIO_PWM_IN            /* PD13 */ GPIO_TIM4_CH2IN_2
+
+#define SDIO_SLOTNO                    0  /* Only one slot */
+#define SDIO_MINOR                     0
+
+/* SD card bringup does not work if performed on the IDLE thread because it
+ * will cause waiting.  Use either:
+ *
+ *  CONFIG_BOARDCTL=y, OR
+ *  CONFIG_BOARD_INITIALIZE=y && CONFIG_BOARD_INITTHREAD=y
+ */
+
+#if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_BOARDCTL) && \
+   !defined(CONFIG_BOARD_INITTHREAD)
+#  warning SDIO initialization cannot be perfomed on the IDLE thread
+#endif
+
+/* By Providing BOARD_ADC_USB_CONNECTED (using the px4_arch abstraction)
+ * this board support the ADC system_power interface, and therefore
+ * provides the true logic GPIO BOARD_ADC_xxxx macros.
+ */
+#define BOARD_ADC_USB_CONNECTED (px4_arch_gpioread(GPIO_OTGFS_VBUS))
+
+/* ARKFPV never powers off the Servo rail */
+
+#define BOARD_ADC_SERVO_VALID     (1)
+
+#define BOARD_ADC_BRICK_VALID   (px4_arch_gpioread(GPIO_VDD_5V_PGOOD))
+#define BOARD_GPIO_PAYOLOAD_V_VALID (px4_arch_gpioread(GPIO_VDD_12V_PGOOD))
+
+/* This board provides a DMA pool and APIs */
+#define BOARD_DMA_ALLOC_POOL_SIZE 5120
+
+/* This board provides the board_on_reset interface */
+
+#define BOARD_HAS_ON_RESET 1
+
+#if defined(TRACE_PINS)
+#define GPIO_TRACE                          \
+	GPIO_TRACECLK1,                           \
+	GPIO_TRACED0,                             \
+	GPIO_TRACED1,                             \
+	GPIO_TRACED2,                             \
+	GPIO_TRACED3
+#else
+#define GPIO_TRACE (GPIO_OUTPUT|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN2)
+#endif
+
+#define PX4_GPIO_INIT_LIST { \
+		GPIO_TRACE,                       \
+		PX4_ADC_GPIO,                     \
+		GPIO_HW_VER_REV_DRIVE,            \
+		GPIO_CAN1_TX,                     \
+		GPIO_CAN1_RX,                     \
+		GPIO_HEATER_OUTPUT,               \
+		GPIO_VDD_5V_PGOOD,                \
+		GPIO_VDD_12V_PGOOD,               \
+		GPIO_VDD_12V_EN,                  \
+		GPIO_5V_ON_BATTERY,               \
+		GPIO_VDD_3V3_SD_CARD_EN,          \
+		GPIO_nARMED_INIT,                 \
+		SPI6_nRESET_EXTERNAL1,            \
+		GPIO_FMU_CH1,     	          \
+		GPIO_FMU_CH2,     	          \
+		GPIO_FMU_CH3,     	          \
+		GPIO_FMU_CH4,     	          \
+		GPIO_FMU_CH5,     	          \
+		GPIO_FMU_CH6,     	          \
+		GPIO_FMU_CH7,     	          \
+		GPIO_FMU_CH8,     	          \
+		GPIO_FMU_CH9,     	          \
+		GPIO_SPIX_SYNC                    \
+	}
+
+#define BOARD_ENABLE_CONSOLE_BUFFER
+
+#define BOARD_NUM_IO_TIMERS  3
+#define BOARD_SPIX_SYNC_FREQ 32000
+
+__BEGIN_DECLS
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public data
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO-based MMC/SD card support
+ *
+ ****************************************************************************/
+
+int stm32_sdio_initialize(void);
+
+/****************************************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
+ *
+ ****************************************************************************************************/
+
+extern void stm32_spiinitialize(void);
+
+extern void stm32_usbinitialize(void);
+
+extern void board_peripheral_reset(int ms);
+
+#include <px4_platform_common/board_common.h>
+
+#endif /* __ASSEMBLY__ */
+
+__END_DECLS
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2021 PX4 Development Team. All rights reserved.
+ *   Copyright (c) 2022 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -46,6 +46,7 @@
 #include <stm32_uart.h>
 #include <arch/board/board.h>
 #include "arm_internal.h"
+#include <px4_platform/gpio.h>
 #include <px4_platform_common/init.h>

 extern int sercon_main(int c, char **argv);
@@ -54,6 +55,15 @@ __EXPORT void board_on_reset(int status) {}

 __EXPORT void stm32_boardinitialize(void)
 {
+	/* configure pins */
+	const uint32_t list[] = PX4_GPIO_INIT_LIST;
+
+	for (size_t gpio = 0; gpio < arraySize(list); gpio++) {
+		if (list[gpio] != 0) {
+			px4_arch_configgpio(list[gpio]);
+		}
+	}
+
 	/* configure USB interfaces */
 	stm32_usbinitialize();
 }
@@ -0,0 +1,140 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file can.c
+ *
+ * Board-specific CAN functions.
+ */
+
+#if !defined(CONFIG_CAN)
+
+#include <stdint.h>
+
+#include "board_config.h"
+
+
+__EXPORT
+uint16_t board_get_can_interfaces(void)
+{
+	uint16_t enabled_interfaces = 0x3;
+
+	enabled_interfaces &= ~(1 << 1);
+
+	return enabled_interfaces;
+}
+
+#else
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "arm_internal.h"
+
+#include "chip.h"
+#include "stm32_can.h"
+#include "board_config.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+
+#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
+#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#  undef CONFIG_STM32_CAN2
+#endif
+
+#ifdef CONFIG_STM32_CAN1
+#  define CAN_PORT 1
+#else
+#  define CAN_PORT 2
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+int can_devinit(void);
+
+/************************************************************************************
+ * Name: can_devinit
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/can.
+ *
+ ************************************************************************************/
+
+int can_devinit(void)
+{
+	static bool initialized = false;
+	struct can_dev_s *can;
+	int ret;
+
+	/* Check if we have already initialized */
+
+	if (!initialized) {
+		/* Call stm32_caninitialize() to get an instance of the CAN interface */
+
+		can = stm32_caninitialize(CAN_PORT);
+
+		if (can == NULL) {
+			canerr("ERROR:  Failed to get CAN interface\n");
+			return -ENODEV;
+		}
+
+		/* Register the CAN driver at "/dev/can0" */
+
+		ret = can_register("/dev/can0", can);
+
+		if (ret < 0) {
+			canerr("ERROR: can_register failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Now we are initialized */
+
+		initialized = true;
+	}
+
+	return OK;
+}
+#endif /* CONFIG_CAN */
@@ -1,37 +1,12 @@
-/****************************************************************************
+/*
+ * hw_config.h
 *
- *   Copyright (C) 2021 PX4 Development Team. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name PX4 nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
+ *  Created on: May 17, 2015
+ *      Author: david_s5
+ */

-#pragma once
+#ifndef HW_CONFIG_H_
+#define HW_CONFIG_H_

 /****************************************************************************
 * 10-8--2016:
@@ -94,14 +69,15 @@

 //#define USE_VBUS_PULL_DOWN
 #define INTERFACE_USART                1
-#define INTERFACE_USART_CONFIG         "/dev/ttyS0,115200"
+#define INTERFACE_USART_CONFIG         "/dev/ttyS6,921600"
 #define BOOT_DELAY_ADDRESS             0x000001a0
-#define BOARD_TYPE                     1166
+#define BOARD_TYPE                     59
+#define _FLASH_KBYTES                  (*(uint32_t *)0x1FF1E880)
 #define BOARD_FLASH_SECTORS            (14)
-#define BOARD_FLASH_SIZE               (16 * 128 * 1024)
-#define APP_RESERVATION_SIZE 	       (1 * 128 * 1024)
+#define BOARD_FLASH_SIZE               (_FLASH_KBYTES * 1024)
+#define APP_RESERVATION_SIZE           (1 * 128 * 1024)

-#define OSC_FREQ                       8
+#define OSC_FREQ                       16

 #define BOARD_PIN_LED_ACTIVITY         GPIO_nLED_BLUE // BLUE
 #define BOARD_PIN_LED_BOOTLOADER       GPIO_nLED_GREEN // GREEN
@@ -110,6 +86,22 @@

 #define SERIAL_BREAK_DETECT_DISABLED   1

+/*
+ * Uncommenting this allows to force the bootloader through
+ * a PWM output pin. As this can accidentally initialize
+ * an ESC prematurely, it is not recommended. This feature
+ * has not been used and hence defaults now to off.
+ *
+ * # define BOARD_FORCE_BL_PIN_OUT         (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN14)
+ * # define BOARD_FORCE_BL_PIN_IN          (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN11)
+ *
+ * # define BOARD_POWER_PIN_OUT           (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4)
+ * # define BOARD_POWER_ON                 1
+ * # define BOARD_POWER_OFF                0
+ * # undef  BOARD_POWER_PIN_RELEASE        // Leave pin enabling Power - un comment to release (disable power)
+ *
+*/
+
 #if !defined(ARCH_SN_MAX_LENGTH)
 # define ARCH_SN_MAX_LENGTH 12
 #endif
@@ -133,3 +125,5 @@
 #ifndef BOOT_DEVICES_FILTER_ONUSB
 #  define BOOT_DEVICES_FILTER_ONUSB USB0_DEV|SERIAL0_DEV|SERIAL1_DEV
 #endif
+
+#endif /* HW_CONFIG_H_ */
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (C) 2021 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2022 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -36,4 +36,5 @@
 constexpr px4_i2c_bus_t px4_i2c_buses[I2C_BUS_MAX_BUS_ITEMS] = {
 	initI2CBusExternal(1),
 	initI2CBusInternal(2),
+	initI2CBusInternal(4),
 };
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2021 PX4 Development Team. All rights reserved.
+ *   Copyright (c) 2012-2022 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -34,21 +34,35 @@
 /**
 * @file init.c
 *
- * FMU-specific early startup code. This file implements the
+ * ARKFMU-specific early startup code.  This file implements the
 * board_app_initialize() function that is called early by nsh during startup.
 *
 * Code here is run before the rcS script is invoked; it should start required
- * subsystems and perform board-specific initialisation.
+ * subsystems and perform board-specific initialization.
 */

-#include "board_config.h"
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/

-#include <syslog.h>
+#include "board_config.h"
+#include "spix_sync.h"
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include <debug.h>
+#include <errno.h>

 #include <nuttx/config.h>
 #include <nuttx/board.h>
+#include <nuttx/spi/spi.h>
 #include <nuttx/sdio.h>
 #include <nuttx/mmcsd.h>
+#include <nuttx/analog/adc.h>
+#include <nuttx/mm/gran.h>
+#include <chip.h>
+#include <stm32_uart.h>
 #include <arch/board/board.h>
 #include "arm_internal.h"

@@ -57,19 +71,35 @@
 #include <systemlib/px4_macros.h>
 #include <px4_arch/io_timer.h>
 #include <px4_platform_common/init.h>
+#include <px4_platform_common/px4_manifest.h>
 #include <px4_platform/gpio.h>
+#include <px4_platform/board_determine_hw_info.h>
 #include <px4_platform/board_dma_alloc.h>

 # if defined(FLASH_BASED_PARAMS)
 #  include <parameters/flashparams/flashfs.h>
 #endif

+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/*
+ * Ideally we'd be able to get these from arm_internal.h,
+ * but since we want to be able to disable the NuttX use
+ * of leds for system indication at will and there is no
+ * separate switch, we need to build independent of the
+ * CONFIG_ARCH_LEDS configuration switch.
+ */
 __BEGIN_DECLS
 extern void led_init(void);
 extern void led_on(int led);
 extern void led_off(int led);
 __END_DECLS

+
 /************************************************************************************
 * Name: board_peripheral_reset
 *
@@ -78,7 +108,24 @@ __END_DECLS
 ************************************************************************************/
 __EXPORT void board_peripheral_reset(int ms)
 {
-	UNUSED(ms);
+	/* set the peripheral rails off */
+
+	PAYLOAD_POWER_EN(false);
+	board_control_spi_sensors_power(false, 0xffff);
+	SPI6_RESET(true);
+
+	/* wait for the peripheral rail to reach GND */
+	usleep(ms * 1000);
+	syslog(LOG_DEBUG, "reset done, %d ms\n", ms);
+
+	/* re-enable power */
+
+	/* switch the peripheral rail back on */
+	board_control_spi_sensors_power(true, 0xffff);
+	PAYLOAD_POWER_EN(true);
+
+	/* Release SPI6 Reset */
+	SPI6_RESET(false);
 }

 /************************************************************************************
@@ -112,22 +159,23 @@ __EXPORT void board_on_reset(int status)
 *   and mapped but before any devices have been initialized.
 *
 ************************************************************************************/
-__EXPORT void stm32_boardinitialize(void)
+
+__EXPORT void
+stm32_boardinitialize(void)
 {
-	/* Reset PWM first thing */
-	board_on_reset(-1);
+	board_on_reset(-1); /* Reset PWM first thing */

 	/* configure LEDs */
+
 	board_autoled_initialize();

 	/* configure pins */
+
 	const uint32_t gpio[] = PX4_GPIO_INIT_LIST;
 	px4_gpio_init(gpio, arraySize(gpio));

-	/* configure SPI interfaces */
-	stm32_spiinitialize();
-
 	/* configure USB interfaces */
+
 	stm32_usbinitialize();

 }
@@ -143,43 +191,35 @@ __EXPORT void stm32_boardinitialize(void)
 * Input Parameters:
 *   arg - The boardctl() argument is passed to the board_app_initialize()
 *         implementation without modification.  The argument has no
- *         meaning to NuttX;
+ *         meaning to NuttX; the meaning of the argument is a contract
+ *         between the board-specific initalization logic and the the
+ *         matching application logic.  The value cold be such things as a
+ *         mode enumeration value, a set of DIP switch switch settings, a
+ *         pointer to configuration data read from a file or serial FLASH,
+ *         or whatever you would like to do with it.  Every implementation
+ *         should accept zero/NULL as a default configuration.
 *
 * Returned Value:
 *   Zero (OK) is returned on success; a negated errno value is returned on
 *   any failure to indicate the nature of the failure.
 *
 ****************************************************************************/
+
 __EXPORT int board_app_initialize(uintptr_t arg)
 {
+	/* Power on Interfaces */
+	PAYLOAD_POWER_EN(true);
+
+	SPI6_RESET(false);
+
 	/* Need hrt running before using the ADC */
+
 	px4_platform_init();

-	/* configure the DMA allocator */
-	if (board_dma_alloc_init() < 0) {
-		syslog(LOG_ERR, "[boot] DMA alloc FAILED\n");
-	}
+	// Use the default HW_VER_REV(0x0,0x0) for Ramtron

-	/* initial LED state */
-	drv_led_start();
-	led_off(LED_RED);
-	led_off(LED_BLUE);
+	stm32_spiinitialize();

-	if (board_hardfault_init(2, true) != 0) {
-		led_on(LED_BLUE);
-	}
-
-#ifdef CONFIG_MMCSD
-	int ret = stm32_sdio_initialize();
-
-	if (ret != OK) {
-		led_on(LED_BLUE);
-		return ret;
-	}
-
-#endif
-
-// TODO：internal flash store parameters
 #if defined(FLASH_BASED_PARAMS)
 	static sector_descriptor_t params_sector_map[] = {
 		{15, 128 * 1024, 0x081E0000},
@@ -191,13 +231,69 @@ __EXPORT int board_app_initialize(uintptr_t arg)

 	if (result != OK) {
 		syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
+		led_on(LED_AMBER);
+	}
+
+#endif // FLASH_BASED_PARAMS
+
+	/* Configure the HW based on the manifest */
+
+	px4_platform_configure();
+
+	if (OK == board_determine_hw_info()) {
+		syslog(LOG_INFO, "[boot] Rev 0x%1x : Ver 0x%1x %s\n", board_get_hw_revision(), board_get_hw_version(),
+		       board_get_hw_type_name());
+
+	} else {
+		syslog(LOG_ERR, "[boot] Failed to read HW revision and version\n");
+	}
+
+	/* Configure the Actual SPI interfaces (after we determined the HW version)  */
+
+	stm32_spiinitialize();
+
+	board_spi_reset(10, 0xffff);
+
+	/* Configure the DMA allocator */
+
+	if (board_dma_alloc_init() < 0) {
+		syslog(LOG_ERR, "[boot] DMA alloc FAILED\n");
+	}
+
+#if defined(SERIAL_HAVE_RXDMA)
+	// set up the serial DMA polling at 1ms intervals for received bytes that have not triggered a DMA event.
+	static struct hrt_call serial_dma_call;
+	hrt_call_every(&serial_dma_call, 1000, 1000, (hrt_callout)stm32_serial_dma_poll, NULL);
+#endif
+
+	/* initial LED state */
+	drv_led_start();
+	led_off(LED_RED);
+	led_on(LED_GREEN); // Indicate Power.
+	led_off(LED_BLUE);
+
+	if (board_hardfault_init(2, true) != 0) {
 		led_on(LED_RED);
 	}

-#endif
+	// Ensure Power is off for > 10 mS
+	usleep(15 * 1000);
+	VDD_3V3_SD_CARD_EN(true);
+	usleep(500 * 1000);

-	/* Configure the HW based on the manifest */
-	px4_platform_configure();
+#ifdef CONFIG_MMCSD
+	int ret = stm32_sdio_initialize();
+
+	if (ret != OK) {
+		led_on(LED_RED);
+		return ret;
+	}
+
+#endif /* CONFIG_MMCSD */
+
+	/* Configure the SPIX_SYNC output */
+	spix_sync_servo_init(BOARD_SPIX_SYNC_FREQ);
+	spix_sync_servo_set(0, 150);

 	return OK;
 }
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2021 PX4 Development Team. All rights reserved.
+ *   Copyright (c) 2013 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -34,7 +34,7 @@
 /**
 * @file led.c
 *
- * LED backend.
+ * ARKFMU LED backend.
 */

 #include <px4_platform_common/px4_config.h>
@@ -62,16 +62,32 @@ extern void led_off(int led);
 extern void led_toggle(int led);
 __END_DECLS

-#  define xlat(p) (p)
+#ifdef CONFIG_ARCH_LEDS
+static bool nuttx_owns_leds = true;
+//                                B  R  S  G
+//                                0  1  2  3
+static const uint8_t xlatpx4[] = {1, 2, 4, 0};
+#  define xlat(p) xlatpx4[(p)]
 static uint32_t g_ledmap[] = {
 	GPIO_nLED_GREEN,   // Indexed by BOARD_LED_GREEN
 	GPIO_nLED_BLUE,    // Indexed by BOARD_LED_BLUE
 	GPIO_nLED_RED,     // Indexed by BOARD_LED_RED
 };

+#else
+
+#  define xlat(p) (p)
+static uint32_t g_ledmap[] = {
+	GPIO_nLED_BLUE,                     // Indexed by LED_BLUE
+	GPIO_nLED_RED,                      // Indexed by LED_RED, LED_AMBER
+	0,                                  // Indexed by LED_SAFETY (defaulted to an input)
+	GPIO_nLED_GREEN,                    // Indexed by LED_GREEN
+};
+
+#endif
+
 __EXPORT void led_init(void)
 {
-	/* Configure LED GPIOs for output */
 	for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
 		if (g_ledmap[l] != 0) {
 			stm32_configgpio(g_ledmap[l]);
@@ -82,6 +98,7 @@ __EXPORT void led_init(void)
 static void phy_set_led(int led, bool state)
 {
 	/* Drive Low to switch on */
+
 	if (g_ledmap[led] != 0) {
 		stm32_gpiowrite(g_ledmap[led], !state);
 	}
@@ -97,7 +114,6 @@ static bool phy_get_led(int led)
 	return false;
 }

-
 __EXPORT void led_on(int led)
 {
 	phy_set_led(xlat(led), true);
@@ -112,3 +128,107 @@ __EXPORT void led_toggle(int led)
 {
 	phy_set_led(xlat(led), !phy_get_led(xlat(led)));
 }
+
+#ifdef CONFIG_ARCH_LEDS
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+	led_init();
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+	if (!nuttx_owns_leds) {
+		return;
+	}
+
+	switch (led) {
+	default:
+		break;
+
+	case LED_HEAPALLOCATE:
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_IRQSENABLED:
+		phy_set_led(BOARD_LED_BLUE, false);
+		phy_set_led(BOARD_LED_GREEN, true);
+		break;
+
+	case LED_STACKCREATED:
+		phy_set_led(BOARD_LED_GREEN, true);
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_INIRQ:
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_SIGNAL:
+		phy_set_led(BOARD_LED_GREEN, true);
+		break;
+
+	case LED_ASSERTION:
+		phy_set_led(BOARD_LED_RED, true);
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_PANIC:
+		phy_set_led(BOARD_LED_RED, true);
+		break;
+
+	case LED_IDLE : /* IDLE */
+		phy_set_led(BOARD_LED_RED, true);
+		break;
+	}
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+	if (!nuttx_owns_leds) {
+		return;
+	}
+
+	switch (led) {
+	default:
+		break;
+
+	case LED_SIGNAL:
+		phy_set_led(BOARD_LED_GREEN, false);
+		break;
+
+	case LED_INIRQ:
+		phy_set_led(BOARD_LED_BLUE, false);
+		break;
+
+	case LED_ASSERTION:
+		phy_set_led(BOARD_LED_RED, false);
+		phy_set_led(BOARD_LED_BLUE, false);
+		break;
+
+	case LED_PANIC:
+		phy_set_led(BOARD_LED_RED, false);
+		break;
+
+	case LED_IDLE : /* IDLE */
+		phy_set_led(BOARD_LED_RED, false);
+		break;
+	}
+}
+
+#endif /* CONFIG_ARCH_LEDS */
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2024 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2024 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -31,24 +31,25 @@
 *
 ****************************************************************************/

-#pragma once
+#include <nuttx/config.h>
+#include <board_config.h>

-#include "../Common.hpp"
+#include <nuttx/spi/spi.h>
+#include <px4_platform_common/px4_manifest.h>

-#include <uORB/Subscription.hpp>
-#include <uORB/SubscriptionMultiArray.hpp>
-#include <uORB/topics/logger_status.h>
-
-class LoggerChecks : public HealthAndArmingCheckBase
-{
-public:
-	LoggerChecks();
-	~LoggerChecks() = default;
-
-	void checkAndReport(const Context &context, Report &reporter) override;
-
-private:
-	uORB::Subscription _logger_status_sub{ORB_ID::logger_status};
-	const param_t _param_sdlog_mode_handle;
-	int32_t _sdlog_mode = -1;
+static const px4_mft_entry_s mft_mft = {
+	.type = MFT,
+	.pmft = (void *) system_query_manifest,
 };
+
+static const px4_mft_s mft = {
+	.nmft = 1,
+	.mfts = {
+		&mft_mft,
+	}
+};
+
+const px4_mft_s *board_get_manifest(void)
+{
+	return &mft;
+}
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (C) 2021 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2024 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -35,16 +35,23 @@
 #include <drivers/drv_sensor.h>
 #include <nuttx/spi/spi.h>

-
-constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
-	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(DRV_OSD_DEVTYPE_ATXXXX, SPI::CS{GPIO::PortB, GPIO::Pin12}),
+constexpr px4_spi_bus_all_hw_t px4_spi_buses_all_hw[BOARD_NUM_SPI_CFG_HW_VERSIONS] = {
+	initSPIFmumID(ARKFPV_0, {
+		initSPIBus(SPI::Bus::SPI1, {
+			initSPIDevice(DRV_IMU_DEVTYPE_IIM42653, SPI::CS{GPIO::PortI, GPIO::Pin9}, SPI::DRDY{GPIO::PortF, GPIO::Pin2}),
+		}, {GPIO::PortI, GPIO::Pin11}),
+		initSPIBusExternal(SPI::Bus::SPI6, {
+			initSPIConfigExternal(SPI::CS{GPIO::PortI, GPIO::Pin10}, SPI::DRDY{GPIO::PortD, GPIO::Pin11})
+		}),
 	}),
-	initSPIBus(SPI::Bus::SPI2, {
-		initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::PortD, GPIO::Pin5}),
-		initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::PortD, GPIO::Pin4}),
-		initSPIDevice(DRV_IMU_DEVTYPE_BMI270, SPI::CS{GPIO::PortA, GPIO::Pin15}),
+	initSPIFmumID(ARKFPV_1, { // Placeholder
+		initSPIBus(SPI::Bus::SPI1, {
+			initSPIDevice(DRV_IMU_DEVTYPE_IIM42653, SPI::CS{GPIO::PortI, GPIO::Pin9}, SPI::DRDY{GPIO::PortF, GPIO::Pin2}),
+		}, {GPIO::PortI, GPIO::Pin11}),
+		initSPIBusExternal(SPI::Bus::SPI6, {
+			initSPIConfigExternal(SPI::CS{GPIO::PortI, GPIO::Pin10}, SPI::DRDY{GPIO::PortD, GPIO::Pin11})
+		}),
 	}),
 };

-static constexpr bool unused = validateSPIConfig(px4_spi_buses);
+static constexpr bool unused = validateSPIConfig(px4_spi_buses_all_hw);
@@ -0,0 +1,309 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2023 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Airmind nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+* @file spix_sync.c
+*
+*
+*/
+
+#include <px4_platform_common/px4_config.h>
+
+#include <board_config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <ctype.h>
+
+
+#include <perf/perf_counter.h>
+#include <systemlib/err.h>
+#include <systemlib/px4_macros.h>
+
+#include <px4_arch/io_timer.h>
+
+#include "spix_sync.h"
+
+#define REG(_tmr, _reg) (*(volatile uint32_t *)(spix_sync_timers[_tmr].base + _reg))
+
+#define rCR1(_tmr)      REG(_tmr, STM32_GTIM_CR1_OFFSET)
+#define rCR2(_tmr)      REG(_tmr, STM32_GTIM_CR2_OFFSET)
+#define rSMCR(_tmr)     REG(_tmr, STM32_GTIM_SMCR_OFFSET)
+#define rDIER(_tmr)     REG(_tmr, STM32_GTIM_DIER_OFFSET)
+#define rSR(_tmr)       REG(_tmr, STM32_GTIM_SR_OFFSET)
+#define rEGR(_tmr)      REG(_tmr, STM32_GTIM_EGR_OFFSET)
+#define rCCMR1(_tmr)    REG(_tmr, STM32_GTIM_CCMR1_OFFSET)
+#define rCCMR2(_tmr)    REG(_tmr, STM32_GTIM_CCMR2_OFFSET)
+#define rCCER(_tmr)     REG(_tmr, STM32_GTIM_CCER_OFFSET)
+#define rCNT(_tmr)      REG(_tmr, STM32_GTIM_CNT_OFFSET)
+#define rPSC(_tmr)      REG(_tmr, STM32_GTIM_PSC_OFFSET)
+#define rARR(_tmr)      REG(_tmr, STM32_GTIM_ARR_OFFSET)
+#define rCCR1(_tmr)     REG(_tmr, STM32_GTIM_CCR1_OFFSET)
+#define rCCR2(_tmr)     REG(_tmr, STM32_GTIM_CCR2_OFFSET)
+#define rCCR3(_tmr)     REG(_tmr, STM32_GTIM_CCR3_OFFSET)
+#define rCCR4(_tmr)     REG(_tmr, STM32_GTIM_CCR4_OFFSET)
+#define rDCR(_tmr)      REG(_tmr, STM32_GTIM_DCR_OFFSET)
+#define rDMAR(_tmr)     REG(_tmr, STM32_GTIM_DMAR_OFFSET)
+#define rBDTR(_tmr)     REG(_tmr, STM32_ATIM_BDTR_OFFSET)
+
+#define BOARD_SPIX_SYNC_PWM_FREQ 1024000
+
+unsigned
+spix_sync_timer_get_period(unsigned timer)
+{
+	return (rARR(timer));
+}
+
+static void spix_sync_timer_init_timer(unsigned timer, unsigned rate)
+{
+	if (spix_sync_timers[timer].base) {
+
+		irqstate_t flags = px4_enter_critical_section();
+
+		/* enable the timer clock before we try to talk to it */
+
+		modifyreg32(spix_sync_timers[timer].clock_register, 0, spix_sync_timers[timer].clock_bit);
+
+		/* disable and configure the timer */
+		rCR1(timer) = 0;
+		rCR2(timer) = 0;
+		rSMCR(timer) = 0;
+		rDIER(timer) = 0;
+		rCCER(timer) = 0;
+		rCCMR1(timer) = 0;
+		rCCMR2(timer) = 0;
+		rCCR1(timer) = 0;
+		rCCR2(timer) = 0;
+		rCCR3(timer) = 0;
+		rCCR4(timer) = 0;
+		rCCER(timer) = 0;
+		rDCR(timer) = 0;
+
+		if ((spix_sync_timers[timer].base == STM32_TIM1_BASE) || (spix_sync_timers[timer].base == STM32_TIM8_BASE)) {
+
+			/* master output enable = on */
+
+			rBDTR(timer) = ATIM_BDTR_MOE;
+		}
+
+		/* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
+		 * then configure the timer to free-run at 1MHz.
+		 * Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
+		 */
+
+		rPSC(timer) = (spix_sync_timers[timer].clock_freq / BOARD_SPIX_SYNC_PWM_FREQ) - 1;
+
+		/* configure the timer to update at the desired rate */
+
+		rARR(timer) = (BOARD_SPIX_SYNC_PWM_FREQ / rate) - 1;
+
+		/* generate an update event; reloads the counter and all registers */
+		rEGR(timer) = GTIM_EGR_UG;
+
+		px4_leave_critical_section(flags);
+	}
+
+}
+
+void spix_sync_channel_init(unsigned channel)
+{
+	/* Only initialize used channels */
+
+	if (spix_sync_channels[channel].timer_channel) {
+
+		unsigned timer = spix_sync_channels[channel].timer_index;
+
+		/* configure the GPIO first */
+		px4_arch_configgpio(spix_sync_channels[channel].gpio_out);
+
+		uint16_t polarity = spix_sync_channels[channel].masks;
+
+		/* configure the channel */
+		switch (spix_sync_channels[channel].timer_channel) {
+		case 1:
+			rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE;
+			rCCER(timer) |= polarity | GTIM_CCER_CC1E;
+			break;
+
+		case 2:
+			rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE;
+			rCCER(timer) |= polarity | GTIM_CCER_CC2E;
+			break;
+
+		case 3:
+			rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE;
+			rCCER(timer) |= polarity | GTIM_CCER_CC3E;
+			break;
+
+		case 4:
+			rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE;
+			rCCER(timer) |= polarity | GTIM_CCER_CC4E;
+			break;
+		}
+	}
+}
+
+int
+spix_sync_servo_set(unsigned channel, uint8_t  cvalue)
+{
+	if (channel >= arraySize(spix_sync_channels)) {
+		return -1;
+	}
+
+	unsigned timer = spix_sync_channels[channel].timer_index;
+
+	/* test timer for validity */
+	if ((spix_sync_timers[timer].base == 0) ||
+	    (spix_sync_channels[channel].gpio_out == 0)) {
+		return -1;
+	}
+
+	unsigned period = spix_sync_timer_get_period(timer);
+
+	unsigned value = (unsigned)cvalue * period / 255;
+
+	/* configure the channel */
+	if (value > 0) {
+		value--;
+	}
+
+
+	switch (spix_sync_channels[channel].timer_channel) {
+	case 1:
+		rCCR1(timer) = value;
+		break;
+
+	case 2:
+		rCCR2(timer) = value;
+		break;
+
+	case 3:
+		rCCR3(timer) = value;
+		break;
+
+	case 4:
+		rCCR4(timer) = value;
+		break;
+
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+unsigned spix_sync_servo_get(unsigned channel)
+{
+	if (channel >= 3) {
+		return 0;
+	}
+
+	unsigned timer = spix_sync_channels[channel].timer_index;
+	uint16_t value = 0;
+
+	/* test timer for validity */
+	if ((spix_sync_timers[timer].base == 0) ||
+	    (spix_sync_channels[channel].timer_channel == 0)) {
+		return 0;
+	}
+
+	/* configure the channel */
+	switch (spix_sync_channels[channel].timer_channel) {
+	case 1:
+		value = rCCR1(timer);
+		break;
+
+	case 2:
+		value = rCCR2(timer);
+		break;
+
+	case 3:
+		value = rCCR3(timer);
+		break;
+
+	case 4:
+		value = rCCR4(timer);
+		break;
+	}
+
+	unsigned period = spix_sync_timer_get_period(timer);
+	return ((value + 1) * 255 / period);
+}
+
+int spix_sync_servo_init(unsigned rate)
+{
+	/* do basic timer initialisation first */
+	for (unsigned i = 0; i < arraySize(spix_sync_timers); i++) {
+		spix_sync_timer_init_timer(i, rate);
+	}
+
+	/* now init channels */
+	for (unsigned i = 0; i < arraySize(spix_sync_channels); i++) {
+		spix_sync_channel_init(i);
+	}
+
+	spix_sync_servo_arm(true);
+	return OK;
+}
+
+void
+spix_sync_servo_deinit(void)
+{
+	/* disable the timers */
+	spix_sync_servo_arm(false);
+}
+void
+spix_sync_servo_arm(bool armed)
+{
+	/* iterate timers and arm/disarm appropriately */
+	for (unsigned i = 0; i < arraySize(spix_sync_timers); i++) {
+		if (spix_sync_timers[i].base != 0) {
+			if (armed) {
+				/* force an update to preload all registers */
+				rEGR(i) = GTIM_EGR_UG;
+
+				/* arm requires the timer be enabled */
+				rCR1(i) |= GTIM_CR1_CEN | GTIM_CR1_ARPE;
+
+			} else {
+				rCR1(i) = 0;
+			}
+		}
+	}
+}
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2021 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2023 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -31,6 +31,12 @@
 *
 ****************************************************************************/

-#pragma once
-#define DMAMAP_SPI2_RX    DMAMAP_DMA12_SPI2RX_0 /* DMA1:39 */
-#define DMAMAP_SPI2_TX    DMAMAP_DMA12_SPI2TX_0 /* DMA1:40 */
+__BEGIN_DECLS
+void spix_sync_channel_init(unsigned channel);
+int spix_sync_servo_set(unsigned channel, uint8_t  value);
+unsigned spix_sync_servo_get(unsigned channel);
+int spix_sync_servo_init(unsigned rate);
+void spix_sync_servo_deinit(void);
+void spix_sync_servo_arm(bool armed);
+unsigned spix_sync_timer_get_period(unsigned timer);
+__END_DECLS
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (C) 2021 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -33,24 +33,54 @@

 #include <px4_arch/io_timer_hw_description.h>

+/* Timer allocation
+ *
+ * TIM5_CH4  T FMU_CH1
+ * TIM5_CH3  T FMU_CH2
+ * TIM5_CH2  T FMU_CH3
+ * TIM5_CH1  T FMU_CH4
+ *
+ * TIM8_CH1  T FMU_CH5
+ * TIM8_CH2  T FMU_CH6
+ * TIM8_CH3  T FMU_CH7
+ * TIM8_CH4  T FMU_CH8
+ *
+ * TIM4_CH1  T FMU_CH9
+ *
+ * TIM1_CH1  T SPIX_SYNC              > Pulse or GPIO strobe
+ *
+ * TIM2_CH3  T HEATER                 > PWM OUT or GPIO
+ *
+ * TIM3_CH1  T HRT_TIMER
+ *
+ */
+
 constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
-	initIOTimer(Timer::Timer1, DMA{DMA::Index1}),
-	initIOTimer(Timer::Timer3, DMA{DMA::Index1}),
+	initIOTimer(Timer::Timer5, DMA{DMA::Index1}),
+	initIOTimer(Timer::Timer8, DMA{DMA::Index1}),
 	initIOTimer(Timer::Timer4, DMA{DMA::Index1}),
 };

 constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
-	initIOTimerChannel(io_timers, {Timer::Timer1, Timer::Channel4}, {GPIO::PortE, GPIO::Pin14}),
-	initIOTimerChannel(io_timers, {Timer::Timer1, Timer::Channel3}, {GPIO::PortE, GPIO::Pin13}),
-	initIOTimerChannel(io_timers, {Timer::Timer1, Timer::Channel2}, {GPIO::PortE, GPIO::Pin11}),
-	initIOTimerChannel(io_timers, {Timer::Timer1, Timer::Channel1}, {GPIO::PortE, GPIO::Pin9}),
-	initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel4}, {GPIO::PortB, GPIO::Pin1}),
-	initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel3}, {GPIO::PortB, GPIO::Pin0}),
+	initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel4}, {GPIO::PortI, GPIO::Pin0}),
+	initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel3}, {GPIO::PortH, GPIO::Pin12}),
+	initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel2}, {GPIO::PortH, GPIO::Pin11}),
+	initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel1}, {GPIO::PortH, GPIO::Pin10}),
+	initIOTimerChannel(io_timers, {Timer::Timer8, Timer::Channel1}, {GPIO::PortI, GPIO::Pin5}),
+	initIOTimerChannel(io_timers, {Timer::Timer8, Timer::Channel2}, {GPIO::PortI, GPIO::Pin6}),
+	initIOTimerChannel(io_timers, {Timer::Timer8, Timer::Channel3}, {GPIO::PortI, GPIO::Pin7}),
+	initIOTimerChannel(io_timers, {Timer::Timer8, Timer::Channel4}, {GPIO::PortI, GPIO::Pin2}),
 	initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel1}, {GPIO::PortD, GPIO::Pin12}),
-	initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel2}, {GPIO::PortD, GPIO::Pin13}),
-	initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel3}, {GPIO::PortD, GPIO::Pin14}),
-	initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel4}, {GPIO::PortD, GPIO::Pin15}),
 };

 constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
 	initIOTimerChannelMapping(io_timers, timer_io_channels);
+
+
+constexpr io_timers_t spix_sync_timers[MAX_SPIX_SYNC_TIMERS] = {
+	initIOTimer(Timer::Timer1),
+};
+
+constexpr timer_io_channels_t spix_sync_channels[MAX_SPIX_SYNC_TIMERS] = {
+	initIOTimerChannel(spix_sync_timers, {Timer::Timer1, Timer::Channel1}, {GPIO::PortE, GPIO::Pin9}),
+};
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (C) 2021 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2016 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -37,17 +37,43 @@
 * Board-specific USB functions.
 */

-#include "board_config.h"
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
 #include <nuttx/usb/usbdev.h>
 #include <nuttx/usb/usbdev_trace.h>
+
+#include "arm_internal.h"
+#include <chip.h>
+#include <stm32_gpio.h>
 #include <stm32_otg.h>
-#include <debug.h>
+#include "board_config.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/

 /************************************************************************************
 * Name: stm32_usbinitialize
 *
 * Description:
- *   Called to setup USB-related GPIO pins for the board.
+ *   Called to setup USB-related GPIO pins for the ARKFMU board.
 *
 ************************************************************************************/

@@ -72,6 +98,7 @@ __EXPORT void stm32_usbinitialize(void)
 *   while the USB is suspended.
 *
 ************************************************************************************/
+
 __EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
 	uinfo("resume: %d\n", resume);
@@ -7,9 +7,10 @@ CONFIG_BOARD_SERIAL_TEL4="/dev/ttyS2"
 CONFIG_BOARD_SERIAL_RC="/dev/ttyS4"
 CONFIG_DRIVERS_ADC_BOARD_ADC=y
 CONFIG_DRIVERS_BAROMETER_BMP388=y
-CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
+CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_DRIVERS_DISTANCE_SENSOR_BROADCOM_AFBRS50=y
+CONFIG_DRIVERS_DISTANCE_SENSOR_VL53L0X=y
 CONFIG_DRIVERS_DSHOT=y
 CONFIG_DRIVERS_GPS=y
 CONFIG_DRIVERS_HEATER=y
@@ -40,7 +41,6 @@ CONFIG_MODULES_LOGGER=y
 CONFIG_MODULES_MAG_BIAS_ESTIMATOR=y
 CONFIG_MODULES_MANUAL_CONTROL=y
 CONFIG_MODULES_MAVLINK=y
-CONFIG_MAVLINK_DIALECT="development"
 CONFIG_MODULES_MC_ATT_CONTROL=y
 CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=y
 CONFIG_MODULES_MC_HOVER_THRUST_ESTIMATOR=y
@@ -14,6 +14,7 @@
 # CONFIG_MMCSD_SPI is not set
 # CONFIG_NSH_DISABLEBG is not set
 # CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLE_ARP is not set
 # CONFIG_NSH_DISABLE_CAT is not set
 # CONFIG_NSH_DISABLE_CD is not set
 # CONFIG_NSH_DISABLE_CP is not set
@@ -36,6 +37,7 @@
 # CONFIG_NSH_DISABLE_MKFATFS is not set
 # CONFIG_NSH_DISABLE_MOUNT is not set
 # CONFIG_NSH_DISABLE_MV is not set
+# CONFIG_NSH_DISABLE_NSLOOKUP is not set
 # CONFIG_NSH_DISABLE_PS is not set
 # CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set
 # CONFIG_NSH_DISABLE_PWD is not set
@@ -115,6 +117,8 @@ CONFIG_I2C_RESET=y
 CONFIG_IDLETHREAD_STACKSIZE=750
 CONFIG_INIT_ENTRYPOINT="nsh_main"
 CONFIG_INIT_STACKSIZE=3194
+CONFIG_IOB_NBUFFERS=24
+CONFIG_IOB_THROTTLE=0
 CONFIG_LIBC_FLOATINGPOINT=y
 CONFIG_LIBC_LONG_LONG=y
 CONFIG_LIBC_MAX_EXITFUNS=1
@@ -1,13 +1,13 @@
 CONFIG_BOARD_TOOLCHAIN="arm-none-eabi"
 CONFIG_BOARD_ARCHITECTURE="cortex-m4"
 CONFIG_BOARD_ROMFSROOT="cannode"
+CONFIG_BOARD_NO_HELP=y
 CONFIG_BOARD_CONSTRAINED_MEMORY=y
 CONFIG_DRIVERS_BAROMETER_BMP388=y
 CONFIG_DRIVERS_BOOTLOADERS=y
 CONFIG_DRIVERS_GPS=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM42688P=y
 CONFIG_DRIVERS_MAGNETOMETER_BOSCH_BMM150=y
-CONFIG_DRIVERS_MAGNETOMETER_ST_IIS2MDC=y
 CONFIG_DRIVERS_SAFETY_BUTTON=y
 CONFIG_DRIVERS_TONE_ALARM=y
 CONFIG_BOARD_UAVCAN_INTERFACES=1
@@ -8,7 +8,4 @@ icm42688p -R 0 -s start

 bmp388 -I -b 1 start

-if ! iis2mdc -R 4 -I -b 1 start
-then
-	bmm150 -I -b 1 start
-fi
+bmm150 -I -b 1 start
@@ -47,7 +47,7 @@
 #define GPIO_BTN_SAFETY       /* PB15 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTB|GPIO_PIN15)

 /* Safety LED */
-#define GPIO_LED_SAFETY       /* PA1  */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_LED_SAFETY       /* PA1  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)

 /* Tone alarm output. */
 #define TONE_ALARM_TIMER             2    /* timer 2 */
@@ -139,8 +139,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETINIT_DHCPC=y
 CONFIG_NETINIT_DNS=y
-CONFIG_NETINIT_DNSIPADDR=0xA290AFE
-CONFIG_NETINIT_DRIPADDR=0xA290AFE
+CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
+CONFIG_NETINIT_DRIPADDR=0XC0A800FE
 CONFIG_NETINIT_THREAD=y
 CONFIG_NETINIT_THREAD_PRIORITY=49
 CONFIG_NETUTILS_TELNETD=y
@@ -14,6 +14,7 @@ CONFIG_DRIVERS_GPS=y
 CONFIG_DRIVERS_IMU_ANALOG_DEVICES_ADIS16448=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM20948=y
 CONFIG_DRIVERS_IMU_INVENSENSE_MPU9250=y
+CONFIG_DRIVERS_LINUX_PWM_OUT=y
 CONFIG_DRIVERS_MAGNETOMETER_HMC5883=y
 CONFIG_DRIVERS_RC_INPUT=y
 CONFIG_DRIVERS_SMART_BATTERY_BATMON=y
@@ -3,8 +3,8 @@ CONFIG_BOARD_ARCHITECTURE="cortex-m4"
 CONFIG_BOARD_CONSTRAINED_FLASH=y
 CONFIG_BOARD_CONSTRAINED_MEMORY=y
 CONFIG_BOARD_COMPILE_DEFINITIONS="-Wno-narrowing"
-CONFIG_DRIVERS_BAROMETER_LPS25H=y
 CONFIG_DRIVERS_CDCACM_AUTOSTART=y
+CONFIG_DRIVERS_BAROMETER_LPS25H=y
 CONFIG_DRIVERS_DISTANCE_SENSOR_VL53L0X=y
 CONFIG_DRIVERS_GPS=y
 CONFIG_DRIVERS_IMU_INVENSENSE_MPU9250=y
@@ -7,10 +7,10 @@ CONFIG_BOARD_SERIAL_TEL2="/dev/ttyS3"
 CONFIG_DRIVERS_ADC_ADS1115=y
 CONFIG_DRIVERS_ADC_BOARD_ADC=y
 CONFIG_COMMON_BAROMETERS=y
+CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_DRIVERS_BATT_SMBUS=y
 CONFIG_DRIVERS_CAMERA_CAPTURE=y
 CONFIG_DRIVERS_CAMERA_TRIGGER=y
-CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
 CONFIG_COMMON_DISTANCE_SENSOR=y
 CONFIG_DRIVERS_DSHOT=y
@@ -39,6 +39,7 @@ CONFIG_DRIVERS_TONE_ALARM=y
 CONFIG_DRIVERS_UAVCAN=y
 CONFIG_BOARD_UAVCAN_TIMER_OVERRIDE=2
 CONFIG_MODULES_AIRSPEED_SELECTOR=y
+CONFIG_MODULES_ATTITUDE_ESTIMATOR_Q=y
 CONFIG_MODULES_BATTERY_STATUS=y
 CONFIG_MODULES_CAMERA_FEEDBACK=y
 CONFIG_MODULES_COMMANDER=y
@@ -57,6 +58,7 @@ CONFIG_MODULES_GYRO_CALIBRATION=y
 CONFIG_MODULES_LAND_DETECTOR=y
 CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
 CONFIG_MODULES_LOAD_MON=y
+CONFIG_MODULES_LOCAL_POSITION_ESTIMATOR=y
 CONFIG_MODULES_LOGGER=y
 CONFIG_MODULES_MAG_BIAS_ESTIMATOR=y
 CONFIG_MODULES_MANUAL_CONTROL=y
@@ -68,6 +70,7 @@ CONFIG_MODULES_MC_POS_CONTROL=y
 CONFIG_MODULES_MC_RATE_CONTROL=y
 CONFIG_MODULES_NAVIGATOR=y
 CONFIG_MODULES_RC_UPDATE=y
+CONFIG_MODULES_ROVER_POS_CONTROL=y
 CONFIG_MODULES_SENSORS=y
 CONFIG_MODULES_SIMULATION_SIMULATOR_SIH=y
 CONFIG_MODULES_TEMPERATURE_COMPENSATION=y
@@ -95,3 +98,4 @@ CONFIG_SYSTEMCMDS_UORB=y
 CONFIG_SYSTEMCMDS_USB_CONNECTED=y
 CONFIG_SYSTEMCMDS_VER=y
 CONFIG_SYSTEMCMDS_WORK_QUEUE=y
+CONFIG_EXAMPLES_FAKE_GPS=y
@@ -6,11 +6,11 @@ CONFIG_BOARD_SERIAL_TEL1="/dev/ttyS1"
 CONFIG_BOARD_SERIAL_TEL2="/dev/ttyS3"
 CONFIG_DRIVERS_ADC_ADS1115=y
 CONFIG_DRIVERS_ADC_BOARD_ADC=y
+CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_COMMON_BAROMETERS=y
 CONFIG_DRIVERS_BATT_SMBUS=y
 CONFIG_DRIVERS_CAMERA_CAPTURE=y
 CONFIG_DRIVERS_CAMERA_TRIGGER=y
-CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
 CONFIG_COMMON_DISTANCE_SENSOR=y
 CONFIG_DRIVERS_DSHOT=y
@@ -194,6 +194,12 @@

 #define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */

+/* UART clock selection */
+/* reset to default to overwrite any changes done by any bootloader */
+
+#define STM32_RCC_D2CCIP2R_USART234578_SEL RCC_D2CCIP2R_USART234578SEL_RCC
+#define STM32_RCC_D2CCIP2R_USART16_SEL     RCC_D2CCIP2R_USART16SEL_RCC
+
 /* FLASH wait states */
 #define BOARD_FLASH_WAITSTATES 2

@@ -195,6 +195,12 @@

 #define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2     /* ADC 1 2 3 clock source */

+/* UART clock selection */
+/* reset to default to overwrite any changes done by any bootloader */
+
+#define STM32_RCC_D2CCIP2R_USART234578_SEL RCC_D2CCIP2R_USART234578SEL_RCC
+#define STM32_RCC_D2CCIP2R_USART16_SEL     RCC_D2CCIP2R_USART16SEL_RCC
+
 /* FLASH wait states */
 #define BOARD_FLASH_WAITSTATES 2

@@ -15,6 +15,7 @@ CONFIG_DRIVERS_IMU_ANALOG_DEVICES_ADIS16448=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM20948=y
 CONFIG_DRIVERS_IMU_INVENSENSE_MPU9250=y
 CONFIG_DRIVERS_IMU_ST_LSM9DS1=y
+CONFIG_DRIVERS_LINUX_PWM_OUT=y
 CONFIG_DRIVERS_MAGNETOMETER_HMC5883=y
 CONFIG_DRIVERS_MAGNETOMETER_LSM9DS1_MAG=y
 CONFIG_DRIVERS_RC_INPUT=y
@@ -29,12 +29,14 @@ CONFIG_BOARD_INITTHREAD_PRIORITY=254
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=95150
 CONFIG_BOARD_RESET_ON_ASSERT=2
+CONFIG_C99_BOOL8=y
 CONFIG_CDCACM=y
 CONFIG_CDCACM_IFLOWCONTROL=y
 CONFIG_CDCACM_PRODUCTID=0x004b
 CONFIG_CDCACM_PRODUCTSTR="HKUST UAV NxtPX4"
 CONFIG_CDCACM_RXBUFSIZE=600
 CONFIG_CDCACM_TXBUFSIZE=12000
+#TODO：ally for VENDOR ID in the future
 CONFIG_CDCACM_VENDORID=0x3162
 CONFIG_CDCACM_VENDORSTR="Matek"
 CONFIG_DEBUG_FULLOPT=y
@@ -75,15 +77,15 @@ CONFIG_STM32H7_OTGFS=y
 CONFIG_STM32H7_PROGMEM=y
 CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
 CONFIG_STM32H7_TIM1=y
-CONFIG_STM32H7_USART6=y
+CONFIG_STM32H7_USART6=y #debug port, can be modified to UART8
+CONFIG_USART6_RXBUFSIZE=600
+CONFIG_USART6_TXBUFSIZE=300
 CONFIG_SYSTEMTICK_HOOK=y
 CONFIG_SYSTEM_CDCACM=y
 CONFIG_TASK_NAME_SIZE=24
 CONFIG_TTY_SIGINT=y
 CONFIG_TTY_SIGINT_CHAR=0x03
 CONFIG_TTY_SIGTSTP=y
-CONFIG_USART6_RXBUFSIZE=600
-CONFIG_USART6_TXBUFSIZE=300
 CONFIG_USBDEV=y
 CONFIG_USBDEV_BUSPOWERED=y
 CONFIG_USBDEV_MAXPOWER=500
@@ -73,6 +73,7 @@ CONFIG_BOARD_CRASHDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=95150
 CONFIG_BOARD_RESET_ON_ASSERT=2
 CONFIG_BUILTIN=y
+CONFIG_C99_BOOL8=y
 CONFIG_CDCACM=y
 CONFIG_CDCACM_IFLOWCONTROL=y
 CONFIG_CDCACM_PRODUCTID=0x0036
@@ -81,10 +82,12 @@ CONFIG_CDCACM_RXBUFSIZE=600
 CONFIG_CDCACM_TXBUFSIZE=12000
 CONFIG_CDCACM_VENDORID=0x1B8C
 CONFIG_CDCACM_VENDORSTR="Matek"
+CONFIG_CLOCK_MONOTONIC=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_HARDFAULT_ALERT=y
 CONFIG_DEBUG_MEMFAULT=y
 CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_TCBINFO=n
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_FIFO_SIZE=0
 CONFIG_DEV_PIPE_MAXSIZE=1024
@@ -111,10 +114,10 @@ CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_I2C=y
 CONFIG_I2C_RESET=y
 CONFIG_IDLETHREAD_STACKSIZE=750
-CONFIG_INIT_ENTRYPOINT="nsh_main"
-CONFIG_INIT_STACKSIZE=3194
 CONFIG_IOB_NBUFFERS=24
 CONFIG_IOB_NCHAINS=24
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=3194
 CONFIG_LIBC_FLOATINGPOINT=y
 CONFIG_LIBC_LONG_LONG=y
 CONFIG_LIBC_MAX_EXITFUNS=1
@@ -126,6 +129,7 @@ CONFIG_MMCSD_SDIO=y
 CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y
 CONFIG_MM_IOB=y
 CONFIG_MM_REGIONS=4
+# Avaible in Dual Version TODO: MTD IO error
 CONFIG_MTD=y
 CONFIG_MTD_BYTE_WRITE=y
 CONFIG_MTD_PARTITION=y
@@ -160,6 +164,7 @@ CONFIG_RAW_BINARY=y
 CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_READLINE_TABCOMPLETION=y
 CONFIG_RTC_DATETIME=y
+CONFIG_SCHED_ATEXIT=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_SCHED_HPWORKPRIORITY=249
 CONFIG_SCHED_HPWORKSTACKSIZE=1280
@@ -170,6 +175,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
 CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
@@ -185,7 +191,7 @@ CONFIG_START_MONTH=11
 CONFIG_STDIO_BUFFER_SIZE=256
 CONFIG_STM32H7_ADC1=y
 CONFIG_STM32H7_ADC2=y
-CONFIG_STM32H7_ADC3=y
+CONFIG_STM32H7_ADC3=y #should always enable otherwsie got ADC timeout error this is for tempreature compenstae
 CONFIG_STM32H7_BBSRAM=y
 CONFIG_STM32H7_BBSRAM_FILES=5
 CONFIG_STM32H7_BDMA=y
@@ -206,28 +212,40 @@ CONFIG_STM32H7_RTC_HSECLOCK=y
 CONFIG_STM32H7_RTC_MAGIC_REG=1
 CONFIG_STM32H7_SAVE_CRASHDUMP=y
 CONFIG_STM32H7_SDMMC1=y
+CONFIG_STM32H7_SDMMC1_DMA=y
+CONFIG_STM32H7_SDMMC1_DMA_BUFFER=1024
 CONFIG_STM32H7_SERIALBRK_BSDCOMPAT=y
 CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
 CONFIG_STM32H7_SPI1=y
+# CONFIG_STM32H7_SPI1_DMA=y
+# CONFIG_STM32H7_SPI1_DMA_BUFFER=1024
 CONFIG_STM32H7_SPI2=y
 CONFIG_STM32H7_SPI2_DMA=y
 CONFIG_STM32H7_SPI2_DMA_BUFFER=4096
 CONFIG_STM32H7_SPI3=y
+# CONFIG_STM32H7_SPI3_DMA=y
+# CONFIG_STM32H7_SPI3_DMA_BUFFER=1024
 CONFIG_STM32H7_SPI4=y
+# CONFIG_STM32H7_SPI4_DMA=y
+# CONFIG_STM32H7_SPI4_DMA_BUFFER=1024
+CONFIG_STM32H7_SPI_DMA=y
 CONFIG_STM32H7_SPI_DMATHRESHOLD=8
 CONFIG_STM32H7_TIM1=y
 CONFIG_STM32H7_TIM2=y
 CONFIG_STM32H7_TIM3=y
 CONFIG_STM32H7_TIM4=y
+# CONFIG_STM32H7_TIM5=y
+# CONFIG_STM32H7_TIM6=y
+# CONFIG_STM32H7_TIM7=y
 CONFIG_STM32H7_TIM8=y
-CONFIG_STM32H7_UART4=y
-CONFIG_STM32H7_UART5=y
-CONFIG_STM32H7_UART7=y
-CONFIG_STM32H7_UART8=y
-CONFIG_STM32H7_USART1=y
-CONFIG_STM32H7_USART2=y
-CONFIG_STM32H7_USART3=y
-CONFIG_STM32H7_USART6=y
+CONFIG_STM32H7_USART1=y #ttyS0
+CONFIG_STM32H7_USART2=y #ttyS1
+CONFIG_STM32H7_USART3=y #ttyS2
+CONFIG_STM32H7_UART4=y #ttyS3
+CONFIG_STM32H7_UART5=y #ttyS4
+CONFIG_STM32H7_USART6=y #ttyS5 NC
+CONFIG_STM32H7_UART7=y #ttyS6
+CONFIG_STM32H7_UART8=y #ttyS7
 CONFIG_STM32H7_USART_BREAKS=y
 CONFIG_STM32H7_USART_INVERT=y
 CONFIG_STM32H7_USART_SINGLEWIRE=y
@@ -235,20 +253,6 @@ CONFIG_STM32H7_USART_SWAP=y
 CONFIG_SYSTEM_CDCACM=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=24
-CONFIG_UART4_BAUD=921600
-CONFIG_UART4_RXBUFSIZE=3000
-CONFIG_UART4_RXDMA=y
-CONFIG_UART4_TXBUFSIZE=3000
-CONFIG_UART4_TXDMA=y
-CONFIG_UART5_BAUD=57600
-CONFIG_UART5_RXBUFSIZE=600
-CONFIG_UART5_TXBUFSIZE=1500
-CONFIG_UART7_BAUD=57600
-CONFIG_UART7_RXBUFSIZE=600
-CONFIG_UART7_TXBUFSIZE=3000
-CONFIG_UART8_BAUD=57600
-CONFIG_UART8_RXBUFSIZE=600
-CONFIG_UART8_TXBUFSIZE=3000
 CONFIG_USART1_BAUD=57600
 CONFIG_USART1_RXBUFSIZE=600
 CONFIG_USART1_TXBUFSIZE=1500
@@ -258,12 +262,27 @@ CONFIG_USART2_TXBUFSIZE=3000
 CONFIG_USART3_BAUD=57600
 CONFIG_USART3_RXBUFSIZE=180
 CONFIG_USART3_TXBUFSIZE=1500
+CONFIG_UART4_BAUD=921600
+CONFIG_UART4_RXBUFSIZE=3000
+CONFIG_UART4_TXBUFSIZE=3000
+CONFIG_UART4_RXDMA=y
+CONFIG_UART4_TXDMA=y
+CONFIG_UART5_BAUD=57600
+CONFIG_UART5_RXBUFSIZE=600
+CONFIG_UART5_TXBUFSIZE=1500
 CONFIG_USART6_BAUD=57600
 CONFIG_USART6_RXBUFSIZE=180
 CONFIG_USART6_SERIAL_CONSOLE=y
+CONFIG_UART7_BAUD=57600
+CONFIG_UART7_RXBUFSIZE=600
+CONFIG_UART7_TXBUFSIZE=3000
+CONFIG_UART8_BAUD=57600
+CONFIG_UART8_RXBUFSIZE=600
+CONFIG_UART8_TXBUFSIZE=3000
 CONFIG_USBDEV=y
 CONFIG_USBDEV_BUSPOWERED=y
 CONFIG_USBDEV_MAXPOWER=500
 CONFIG_USEC_PER_TICK=1000
+CONFIG_USERMAIN_STACKSIZE=2944
 CONFIG_WATCHDOG=y
 CONFIG_WQUEUE_NOTIFIER=y
@@ -17,25 +17,32 @@ CONFIG_COMMON_DISTANCE_SENSOR=y
 CONFIG_DRIVERS_DSHOT=y
 CONFIG_DRIVERS_GPS=y
 CONFIG_DRIVERS_IMU_BOSCH_BMI088=y
+CONFIG_DRIVERS_IMU_INVENSENSE_MPU6500=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM20602=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM42688P=y
-CONFIG_DRIVERS_IMU_INVENSENSE_MPU6500=y
+CONFIG_DRIVERS_MAGNETOMETER_QMC5883L=y
+CONFIG_DRIVERS_BAROMETER_BMP388=y
 CONFIG_DRIVERS_IRLOCK=y
 CONFIG_COMMON_LIGHT=y
 CONFIG_COMMON_MAGNETOMETER=y
 CONFIG_COMMON_OPTICAL_FLOW=y
 CONFIG_DRIVERS_PWM_OUT=y
+CONFIG_DRIVERS_PWM_OUT_SIM=y
 CONFIG_DRIVERS_RC_INPUT=y
 CONFIG_DRIVERS_ROBOCLAW=y
+CONFIG_DRIVERS_RPM=y
 CONFIG_COMMON_TELEMETRY=y
 CONFIG_DRIVERS_TONE_ALARM=y
-CONFIG_MODULES_ATTITUDE_ESTIMATOR_Q=y
+#CONFIG_DRIVERS_UAVCAN=y
+#CONFIG_BOARD_UAVCAN_INTERFACES=1
+#CONFIG_MODULES_AIRSPEED_SELECTOR=y
 CONFIG_MODULES_BATTERY_STATUS=y
 CONFIG_MODULES_CAMERA_FEEDBACK=y
 CONFIG_MODULES_COMMANDER=y
 CONFIG_MODULES_CONTROL_ALLOCATOR=y
 CONFIG_MODULES_DATAMAN=y
 CONFIG_MODULES_EKF2=y
+CONFIG_MODULES_ATTITUDE_ESTIMATOR_Q=y
 CONFIG_MODULES_ESC_BATTERY=y
 CONFIG_MODULES_EVENTS=y
 CONFIG_MODULES_FLIGHT_MODE_MANAGER=y
@@ -43,13 +50,13 @@ CONFIG_MODULES_FW_ATT_CONTROL=y
 CONFIG_MODULES_FW_AUTOTUNE_ATTITUDE_CONTROL=y
 CONFIG_MODULES_FW_POS_CONTROL=y
 CONFIG_MODULES_FW_RATE_CONTROL=y
-CONFIG_MODULES_GIMBAL=y
+# CONFIG_MODULES_FW_POS_CONTROL_L1=y
+CONFIG_MODULES_LOCAL_POSITION_ESTIMATOR=y
 CONFIG_MODULES_GYRO_CALIBRATION=y
 CONFIG_MODULES_GYRO_FFT=y
 CONFIG_MODULES_LAND_DETECTOR=y
 CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
 CONFIG_MODULES_LOAD_MON=y
-CONFIG_MODULES_LOCAL_POSITION_ESTIMATOR=y
 CONFIG_MODULES_LOGGER=y
 CONFIG_MODULES_MAG_BIAS_ESTIMATOR=y
 CONFIG_MODULES_MANUAL_CONTROL=y
@@ -59,15 +66,18 @@ CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=y
 CONFIG_MODULES_MC_HOVER_THRUST_ESTIMATOR=y
 CONFIG_MODULES_MC_POS_CONTROL=y
 CONFIG_MODULES_MC_RATE_CONTROL=y
+CONFIG_MODULES_CONTROL_ALLOCATOR=y
 CONFIG_MODULES_NAVIGATOR=y
 CONFIG_MODULES_RC_UPDATE=y
 CONFIG_MODULES_ROVER_POS_CONTROL=y
-CONFIG_MODULES_SENSORS=y
-CONFIG_MODULES_TEMPERATURE_COMPENSATION=y
 CONFIG_MODULES_UXRCE_DDS_CLIENT=y
+CONFIG_MODULES_SENSORS=y
+CONFIG_MODULES_SIH=y
+CONFIG_MODULES_TEMPERATURE_COMPENSATION=y
+CONFIG_MODULES_GIMBAL=y
 CONFIG_MODULES_VTOL_ATT_CONTROL=y
-CONFIG_SYSTEMCMDS_ACTUATOR_TEST=y
 CONFIG_SYSTEMCMDS_BL_UPDATE=y
+CONFIG_SYSTEMCMDS_ACTUATOR_TEST=y
 CONFIG_SYSTEMCMDS_DMESG=y
 CONFIG_SYSTEMCMDS_DUMPFILE=y
 CONFIG_SYSTEMCMDS_GPIO=y
@@ -75,9 +85,13 @@ CONFIG_SYSTEMCMDS_HARDFAULT_LOG=y
 CONFIG_SYSTEMCMDS_I2CDETECT=y
 CONFIG_SYSTEMCMDS_LED_CONTROL=y
 CONFIG_SYSTEMCMDS_MFT=y
+CONFIG_SYSTEMCMDS_MIXER=y
+CONFIG_SYSTEMCMDS_MOTOR_TEST=y
+#CONFIG_SYSTEMCMDS_MTD=y
 CONFIG_SYSTEMCMDS_NSHTERM=y
 CONFIG_SYSTEMCMDS_PARAM=y
 CONFIG_SYSTEMCMDS_PERF=y
+CONFIG_SYSTEMCMDS_PWM=y
 CONFIG_SYSTEMCMDS_REBOOT=y
 CONFIG_SYSTEMCMDS_SD_BENCH=y
 CONFIG_SYSTEMCMDS_SD_STRESS=y
@@ -29,12 +29,14 @@ CONFIG_BOARD_INITTHREAD_PRIORITY=254
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=95150
 CONFIG_BOARD_RESET_ON_ASSERT=2
+CONFIG_C99_BOOL8=y
 CONFIG_CDCACM=y
 CONFIG_CDCACM_IFLOWCONTROL=y
 CONFIG_CDCACM_PRODUCTID=0x004b
 CONFIG_CDCACM_PRODUCTSTR="HKUST UAV NxtPX4"
 CONFIG_CDCACM_RXBUFSIZE=600
 CONFIG_CDCACM_TXBUFSIZE=12000
+#TODO：ally for VENDOR ID in the future
 CONFIG_CDCACM_VENDORID=0x3162
 CONFIG_CDCACM_VENDORSTR="Matek"
 CONFIG_DEBUG_FULLOPT=y
@@ -73,6 +73,7 @@ CONFIG_BOARD_CRASHDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=95150
 CONFIG_BOARD_RESET_ON_ASSERT=2
 CONFIG_BUILTIN=y
+CONFIG_C99_BOOL8=y
 CONFIG_CDCACM=y
 CONFIG_CDCACM_IFLOWCONTROL=y
 CONFIG_CDCACM_PRODUCTID=0x0036
@@ -81,10 +82,12 @@ CONFIG_CDCACM_RXBUFSIZE=600
 CONFIG_CDCACM_TXBUFSIZE=12000
 CONFIG_CDCACM_VENDORID=0x1B8C
 CONFIG_CDCACM_VENDORSTR="Matek"
+CONFIG_CLOCK_MONOTONIC=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_HARDFAULT_ALERT=y
 CONFIG_DEBUG_MEMFAULT=y
 CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_TCBINFO=n
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_FIFO_SIZE=0
 CONFIG_DEV_PIPE_MAXSIZE=1024
@@ -111,10 +114,10 @@ CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_I2C=y
 CONFIG_I2C_RESET=y
 CONFIG_IDLETHREAD_STACKSIZE=750
-CONFIG_INIT_ENTRYPOINT="nsh_main"
-CONFIG_INIT_STACKSIZE=3194
 CONFIG_IOB_NBUFFERS=24
 CONFIG_IOB_NCHAINS=24
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=3194
 CONFIG_LIBC_FLOATINGPOINT=y
 CONFIG_LIBC_LONG_LONG=y
 CONFIG_LIBC_MAX_EXITFUNS=1
@@ -126,6 +129,12 @@ CONFIG_MMCSD_SDIO=y
 CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y
 CONFIG_MM_IOB=y
 CONFIG_MM_REGIONS=4
+# Avaible in Dual Version
+# CONFIG_MTD=y
+# CONFIG_MTD_BYTE_WRITE=y
+# CONFIG_MTD_PARTITION=y
+# CONFIG_MTD_PROGMEM=y
+# CONFIG_MTD_RAMTRON=y
 CONFIG_NAME_MAX=40
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_ARGCAT=y
@@ -146,12 +155,14 @@ CONFIG_PREALLOC_TIMERS=50
 CONFIG_PRIORITY_INHERITANCE=y
 CONFIG_PTHREAD_MUTEX_ROBUST=y
 CONFIG_PTHREAD_STACK_MIN=512
+CONFIG_RAMTRON_SETSPEED=y
 CONFIG_RAM_SIZE=245760
 CONFIG_RAM_START=0x20010000
 CONFIG_RAW_BINARY=y
 CONFIG_READLINE_CMD_HISTORY=y
 CONFIG_READLINE_TABCOMPLETION=y
 CONFIG_RTC_DATETIME=y
+CONFIG_SCHED_ATEXIT=y
 CONFIG_SCHED_HPWORK=y
 CONFIG_SCHED_HPWORKPRIORITY=249
 CONFIG_SCHED_HPWORKSTACKSIZE=1280
@@ -162,6 +173,7 @@ CONFIG_SCHED_LPWORK=y
 CONFIG_SCHED_LPWORKPRIORITY=50
 CONFIG_SCHED_LPWORKSTACKSIZE=1632
 CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
 CONFIG_SDMMC1_SDIO_PULLUP=y
 CONFIG_SEM_PREALLOCHOLDERS=32
 CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
@@ -177,7 +189,7 @@ CONFIG_START_MONTH=11
 CONFIG_STDIO_BUFFER_SIZE=256
 CONFIG_STM32H7_ADC1=y
 CONFIG_STM32H7_ADC2=y
-CONFIG_STM32H7_ADC3=y
+CONFIG_STM32H7_ADC3=y #should always enable otherwsie got ADC timeout error this is for tempreature compenstae
 CONFIG_STM32H7_BBSRAM=y
 CONFIG_STM32H7_BBSRAM_FILES=5
 CONFIG_STM32H7_BDMA=y
@@ -198,6 +210,8 @@ CONFIG_STM32H7_RTC_HSECLOCK=y
 CONFIG_STM32H7_RTC_MAGIC_REG=1
 CONFIG_STM32H7_SAVE_CRASHDUMP=y
 CONFIG_STM32H7_SDMMC1=y
+CONFIG_STM32H7_SDMMC1_DMA=y
+CONFIG_STM32H7_SDMMC1_DMA_BUFFER=1024
 CONFIG_STM32H7_SERIALBRK_BSDCOMPAT=y
 CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
 CONFIG_STM32H7_SPI1=y
@@ -209,18 +223,19 @@ CONFIG_STM32H7_SPI2_DMA_BUFFER=4096
 CONFIG_STM32H7_SPI3=y
 CONFIG_STM32H7_SPI3_DMA=y
 CONFIG_STM32H7_SPI3_DMA_BUFFER=1024
+CONFIG_STM32H7_SPI_DMA=y
 CONFIG_STM32H7_SPI_DMATHRESHOLD=8
 CONFIG_STM32H7_TIM1=y
 CONFIG_STM32H7_TIM3=y
 CONFIG_STM32H7_TIM4=y
 CONFIG_STM32H7_TIM5=y
 CONFIG_STM32H7_TIM8=y
-CONFIG_STM32H7_UART4=y
-CONFIG_STM32H7_UART5=y
-CONFIG_STM32H7_UART7=y
-CONFIG_STM32H7_USART1=y
-CONFIG_STM32H7_USART2=y
-CONFIG_STM32H7_USART3=y
+CONFIG_STM32H7_USART1=y #ttyS0
+CONFIG_STM32H7_USART2=y #ttyS1
+CONFIG_STM32H7_USART3=y #ttyS2
+CONFIG_STM32H7_UART4=y #ttyS3
+CONFIG_STM32H7_UART5=y #ttyS4
+CONFIG_STM32H7_UART7=y #ttyS5
 CONFIG_STM32H7_USART_BREAKS=y
 CONFIG_STM32H7_USART_INVERT=y
 CONFIG_STM32H7_USART_SINGLEWIRE=y
@@ -228,15 +243,6 @@ CONFIG_STM32H7_USART_SWAP=y
 CONFIG_SYSTEM_CDCACM=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=24
-CONFIG_UART4_BAUD=921600
-CONFIG_UART4_RXBUFSIZE=3000
-CONFIG_UART4_TXBUFSIZE=1200
-CONFIG_UART5_BAUD=57600
-CONFIG_UART5_RXBUFSIZE=600
-CONFIG_UART5_TXBUFSIZE=1500
-CONFIG_UART7_BAUD=57600
-CONFIG_UART7_RXBUFSIZE=600
-CONFIG_UART7_TXBUFSIZE=3000
 CONFIG_USART1_BAUD=57600
 CONFIG_USART1_RXBUFSIZE=600
 CONFIG_USART1_TXBUFSIZE=1500
@@ -247,9 +253,20 @@ CONFIG_USART3_BAUD=57600
 CONFIG_USART3_RXBUFSIZE=180
 CONFIG_USART3_SERIAL_CONSOLE=y
 CONFIG_USART3_TXBUFSIZE=1500
+CONFIG_UART4_BAUD=921600
+CONFIG_UART4_RXBUFSIZE=3000
+CONFIG_UART4_TXBUFSIZE=1200
+CONFIG_UART5_BAUD=57600
+CONFIG_UART5_RXBUFSIZE=600
+CONFIG_UART5_TXBUFSIZE=1500
+CONFIG_UART7_BAUD=57600
+CONFIG_UART7_RXBUFSIZE=600
+CONFIG_UART7_TXBUFSIZE=3000
 CONFIG_USBDEV=y
 CONFIG_USBDEV_BUSPOWERED=y
 CONFIG_USBDEV_MAXPOWER=500
 CONFIG_USEC_PER_TICK=1000
+CONFIG_USERMAIN_STACKSIZE=2944
+CONFIG_USER_ENTRYPOINT="nsh_main"
 CONFIG_WATCHDOG=y
 CONFIG_WQUEUE_NOTIFIER=y
@@ -15,7 +15,7 @@ param set-default SYS_AUTOSTART 4050
 param set-default SYS_HAS_MAG 0

 # enable gravity fusion
-param set-default EKF2_IMU_CTRL 7
+param set-default EKF2_IMU_CONTROL 7

 # the startup tune is not great on a binary output buzzer, so disable it
 param set-default CBRK_BUZZER 782090
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Jacob Dahl	8017135965	Update platforms/nuttx/src/bootloader/stm/stm32_common/main.c	2024-11-19 12:19:19 -05:00
alexklimaj	eb76cc6001	stm32 bootloader: use STM32_CPUCLK_FREQUENCY for systick_mhz	2024-11-19 12:19:19 -05:00
alexklimaj	15dd55e86a	boards: ark fpv fix current adc	2024-11-19 12:19:19 -05:00
Alex Klimaj	4798b6b631	boards: ark fpv change bootloader uart to telem1 (#23898 )	2024-11-19 12:19:19 -05:00
Alex Klimaj	b8e7237317	boards: ark fpv add SCH16T (#23883 ) * boards: ark fpv add SCH16T * boards: ark fpv fix spi6	2024-11-19 12:19:19 -05:00
Alex Klimaj	510d6a1f70	boards: new ARK FPV FC (#23830 ) * add new payload power switch (RC_MAP_PAY_SW)	2024-11-19 12:19:19 -05:00
Alexis Guijarro	4817c0618a	mRo boards: Fix for USART clock selection (#23524 )	2024-11-06 12:20:00 -08:00
QiTao Weng	e85ffa0991	Add airspeed message to uxrce dds topics (#23847 ) Co-authored-by: Weng <q350w358@ENGR-GQT56X3-X.home.ku.edu>	2024-11-04 19:18:29 -09:00
Silvan Fuhrer	aa25964942	Navigator: land: set lat/lon fields of triplet to NAN if global position is not valid Signed-off-by: Silvan Fuhrer <silvan@auterion.com>	2024-10-31 13:34:45 +01:00
Julian Oes	53dda3576b	boards: add Septentrio GNSS drivers to 6XRT	2024-10-29 19:58:01 +13:00
Julian Oes	31582270ae	boards: add Sepentrio GNSS drivers to 6C and 6X	2024-10-29 19:58:01 +13:00
Jacob Dahl	93eef0c787	set file descriptor to -1 after close()	2024-10-01 13:13:18 -04:00
alexklimaj	dd5e81470c	failure detector use per index esc current	2024-09-30 15:45:56 -04:00
Mathieu Bresciani	1d06f62399	fix VehicleCommand.msg syntax	2024-09-30 15:28:24 -04:00
Daniel Agar	f5f7dfc45e	commander: ignore REQUEST_CAMERA_INFORMATION - add answer command logging	2024-09-30 15:28:24 -04:00
Ramon Roche	cf1c03e412	drivers/gnss/septentrio: disable default assignment of GPS1	2024-09-25 06:54:51 -07:00
Ramon Roche	30e763b678	Commander: lock down mav sys and comp id - keeps them as local params at init - only allow to set at init	2024-08-27 15:27:32 -04:00
Julian Oes	fe26cdebc0	stm32h7: Reset USART clock selection (#23498 ) (#23516 ) This resets the USARTs' clock source selection to the default, in case it has been changed by the bootloader. This is required if booting from the ArduPilot bootloader which happens to reset the clock selection to PLL. Without this fix, UARTs (including the console) is garbled, so presumably at an invalid baudrate.	2024-08-09 10:25:19 +12:00
Silvan Fuhrer	631f36b1ee	TECS: reduce default of FW_T_SPD_STD to reduce airspeed measurement delay Signed-off-by: Silvan Fuhrer <silvan@auterion.com>	2024-08-07 17:45:20 +02:00
Beat Küng	96cddf5ed1	fix metadata.cmake: add missing paths to json & xml parameter outputs (#23464 )	2024-08-07 08:39:43 +02:00
chiara-septentrio	5216453b39	drivers/gnss/septentrio : 1.15-compatible extracted septentrio driver, with new features and fixes (#23386 ) Co-authored-by: Chiara de Saint Giniez <chiarastginiez@gmail.com>	2024-07-25 11:39:38 -04:00
David Sidrane	3dc97908db	spracing_h7extreme:rcc Tack upstream name fix	2024-07-15 13:52:44 +02:00
Matthias Grob	762d87285c	Jankinsfile-compile: add missing comma after `ark_pi6x_default`	2024-07-15 13:52:44 +02:00
Matthias Grob	5216d5c569	SubscriptionInterval: move updated, update, copy function to a cpp file Saves 17.3 kilobytes of flash 😮	2024-07-15 11:31:52 +02:00
Matthias Grob	920005a235	uORB: SubscriptionInterval fix timestamp wrapping when initializing less than the interval time after boot (#23384 ) * SubscriptionInterval: ensure _last_update is never before timer start	2024-07-11 16:36:55 +02:00
Peter van der Perk	50dd011c5e	Update NuttX Backports: stm32h755II backport stm32h7: allow Ethernet MAC without PHY imxrt: imxrt11xx set core clock to 1p15v regardless of ocotp imxrt: Correctly update PLL, bit has to toggled instead of being set	2024-07-10 22:00:47 -04:00
Peter van der Perk	e00101b771	[BACKPORT] imxrt: Change PLL settings for more accurate dshot timing	2024-07-10 22:00:47 -04:00
Peter van der Perk	c8fedda09a	[BACKPORT] fmu-v6xrt: MTD use full FRAM (32KB)	2024-07-10 22:00:47 -04:00
alexklimaj	de07e2bef0	boards ark pi6x add vl53l0x	2024-06-26 17:09:48 -04:00
fury1895	9a422dbfe8	gimbal - input_mavlink: return NoUpdate by default	2024-06-19 14:49:04 +02:00
Julian Oes	e2558046b8	mavlink: enable gimbal controls in QGC over USB	2024-06-11 15:08:38 +12:00
Julian Oes	00b6df1de5	gimbal: fix auto RC and MAVLink mode This fixes various edge cases when input is set to both: RC and MAVLink gimbal protocol v2. Specifically: - We no longer immediately reset primary control if there is no update, otherwise this will reset immediately after an commands. - Talking of commands: GIMBAL_MANAGER_CONFIGURE no longer switches control to MAVLink but only an actual incoming setpoint command does. - And incoming setpoint command only triggers UpdatedActiveOnce which means we will check RC again afterwards and if there is big movement switch back to RC. That's the intuitive thing to do until we have better reporting about who/what is in control. - Also, with RC we no longer always set us to be in control but only on major movement.	2024-06-11 15:08:38 +12:00
Jacob Dahl	061373f45b	cdcacm_autostart: handle USB power only	2024-06-07 08:05:15 -04:00
Silvan Fuhrer	f3787708d7	VTOL: remove _dt passing as it's no longer used (and was wrong) Signed-off-by: Silvan Fuhrer <silvan@auterion.com>	2024-06-06 21:52:40 -04:00
Silvan Fuhrer	4fe51d4911	VTOL Standard: fix transition pusher motor slew rate Signed-off-by: Silvan Fuhrer <silvan@auterion.com>	2024-06-06 21:52:40 -04:00
Julian Oes	71bf06af56	boards: update all bootloaders	2024-06-07 09:24:40 +12:00
Peize-Liu	5f2568231d	[Fix][hkust_nxt-dual]:board hkust_nxt-dual fix hw_config.h missing APP_RESERVATION_SIZE param (#23204 )	2024-06-07 09:24:40 +12:00
Julian Oes	ce9109cf5e	Makefile: add missing bootloader targets Quite a few were missing, and everything on one line was hard to diff.	2024-06-07 09:24:40 +12:00
David Sidrane	ec2c91fa90	nxp/imxrt_common/main:Fix Breakage from `a9962dc`	2024-06-07 09:24:40 +12:00
Julian Oes	9f07f2a076	px_uploader: catch serial exception correctly Signed-off-by: Julian Oes <julian@oes.ch>	2024-06-07 09:24:40 +12:00
Julian Oes	9dc3f6ea12	bootloader: remove unused/duplicate defines	2024-06-07 09:24:40 +12:00
Julian Oes	0d957e9e87	bootloader: track ArduPilot protocol Just so we don't conflict on these commands in the future.	2024-06-07 09:24:40 +12:00
Julian Oes	62e61a3d7e	px_uploader.py: clean up various tidbits Includes: - Remove some of the outdated Python2 checks and compatibility. - Try not catch all exceptions but only the expected ones. Otherwise, this makes it really hard to debug if anything unexpected actually goes wrong. - Make use of fstrings. - Make output slightly prettier. Signed-off-by: Julian Oes <julian@oes.ch>	2024-06-07 09:24:40 +12:00
Julian Oes	cc83186dcc	bootloader: add bootloader version This adds a new protocol extension which allows to get the bootloader version. The bootloader version is different from the bootloader protocol revision which has stabilized at 5 and is not easy to update unless a bootloader is actually breaking the protocol. The reason being that both the Python script as well as the uploader used in QGC will not attempt to load firmware if they don't know the bootloader version, so it could basically be considered a "breaking" protocol revision. Signed-off-by: Julian Oes <julian@oes.ch>	2024-06-07 09:24:40 +12:00
Julian Oes	eb9fd7ec76	tools/bootloader: add force-erase option If the STM32H7 fails to program or erase a full chunk of 256 bytes, the ECC check will trigger a busfault when trying to read from it. To speed up erasing and optimize wear, we read before erasing to check if it actually needs erasing. That's when a busfault happens and the erase time outs. The workaround is to add an option to do a full erase without check. Credit goes to: https://github.com/ArduPilot/ardupilot/pull/22090 And the protocol option added to the bootloader is the same as for ArduPilot, so compatible. Signed-off-by: Julian Oes <julian@oes.ch>	2024-06-07 09:24:40 +12:00
Peter van der Perk	d8655fdde9	[BACKPORT] fmu-v6xrt: Support RC telemetry	2024-06-05 11:15:45 -04:00
Peter van der Perk	d8b6b2a5ad	[BACKPORT] fmu-v6xrt: Fix flash configuration Fixes correct dummy cycle count of 20	2024-06-05 11:15:45 -04:00
David Sidrane	ef9b1b75c3	[BACKPORT] Update px4_fmu-v6xrt Bootloader	2024-06-05 11:15:45 -04:00
David Sidrane	f10650e114	[BACKPORT] px4_fmu-v6xrt & bootloader:Bootloader enusres that ITCM memory is writable before jump to APP	2024-06-05 11:15:45 -04:00
David Sidrane	82a259cebe	[BACKPORT] bootloader/common/bl.c:Fixed Wrong vec_base caculation - only effects imxrt	2024-06-05 11:15:45 -04:00
David Sidrane	5903a815b7	NuttX with imxrt:lpuart & 1170 MPU Backports [BACKPORT] imxrt: lpuart singlewire transfer support These correctly enables mpu_rest on MPU init if CONFIG_ARM_MPU_RESET is defined. [BACKPORT] imxrt: 1170 MPU config ensure no lockups can occur [BACKPORT] armv{7\|8}-{m\|r}:MPU fix CONFIG naming to include ARM	2024-06-05 11:15:45 -04:00
Peter van der Perk	b5e5b2a186	[BACKPORT] dronecan: SocketCAN driver check size before copying Avoids memory corruption if we get packets to big	2024-06-05 11:15:45 -04:00
Peter van der Perk	901ac16583	[BACKPORT] fmu-v6xrt: Add I2C driver launcher	2024-06-05 11:15:45 -04:00
Peter van der Perk	27ed745b95	[BACKPORT] fmu-v6xrt: Enable debug features for more verbose hardfault output	2024-06-05 11:15:45 -04:00
David Sidrane	0ca57a5547	NuttX with imxrt_sd-preflight backport	2024-06-05 11:15:45 -04:00
David Sidrane	d182b202c8	[BACKPORT] px4_fmu-v6xrt:Support_MMCSD_MULTIBLOCK with preflight	2024-06-05 11:15:45 -04:00
alexklimaj	192bbd177b	airframes: dexi remove EKF2_HGT_REF default	2024-05-29 20:39:10 -04:00
alexklimaj	bb1f104a1a	boards: ark-pi6x remove ekf delay param defaults	2024-05-29 11:23:16 -04:00
Jacob Dahl	e173520273	boards: ark: pi6x: CONFIG_DRIVERS_CDCACM_AUTOSTART=y (#23163 )	2024-05-29 11:23:16 -04:00
Jacob Dahl	b8e43e1649	[mavlink] Parameter to always start on USB (#22234 ) * usb: Added parameter to enable always starting mavlink on USB. Refactored cdcacm_init into a module and added a paramter to allow always starting mavlink on USB, also added a paramter to choose the mode. The current default behavior is to wait and listen for data on USB and auto-detect the protocol (mavlink, nsh, ublox). This results in the mavlink stream not starting until something else on the mavlink network sends a packet first. The new default behavior is to always start mavlink. Added parameters MAV_USB_ENABLE -- default 1 (always start mavlink on USB) MAV_USE_MODE -- default 3 (onboard) * added 3 retries for opening serial port in mavlink, removed sleep before sercon * added DRIVERS_CDCACM_AUTOSTART to ark-v6x default.px4board * added CONFIG_DRIVERS_CDCACM_AUTOSTART=y to default.px4board for boards with CONFIG_CDCACM in their nsh/defconfig * format * remove PGA460 from COMMON_DISTANCE_SENSOR to save flash * remove LIS2MDL from COMMON_MAGNETOMETER to save flash * disable CONFIG_DRIVERS_CDCACM_AUTOSTART for fmu-v5 protected.px4board * moved and renamed parameters, removed mode logic in mavlink * changed parameter names, added mode none * remove parameters from mavlink	2024-05-29 11:23:16 -04:00
alexklimaj	a59b6fe5e9	boards: add iis2mdc mag to ark pi6x	2024-05-29 11:23:16 -04:00
Jacob Dahl	3b0a712c70	drivers/magnetometer: new ST IIS2MDC Magnetometer driver	2024-05-29 11:23:16 -04:00
Alexis Guijarro	60138da56b	mRo Control Zero Classic: Definition for GPS2 by default added	2024-05-23 18:29:10 -07:00