[BACKPORT] imxrt: Change PLL settings for more accurate dshot timing

This commit is contained in:
Peter van der Perk
2024-07-05 15:51:17 +02:00
committed by Daniel Agar
parent c8fedda09a
commit e00101b771
3 changed files with 8 additions and 23 deletions
@@ -52,6 +52,7 @@
#define IMXRT_IPG_PODF_DIVIDER 5
#define BOARD_GPT_FREQUENCY 24000000
#define BOARD_XTAL_FREQUENCY 24000000
#define BOARD_FLEXIO_PREQ 108000000
/* SDIO *********************************************************************/
+6 -6
View File
@@ -114,11 +114,11 @@ const struct clock_configuration_s g_initial_clkconfig = {
.div = 1,
.mux = ACMP_CLK_ROOT_OSC_RC_48M_DIV2,
},
.flexio1_clk_root =
.flexio1_clk_root = /* 432 / 4 = 108Mhz */
{
.enable = 1,
.div = 2,
.mux = FLEXIO1_CLK_ROOT_SYS_PLL3_DIV2,
.div = 4,
.mux = FLEXIO1_CLK_ROOT_SYS_PLL2_PFD3,
},
.flexio2_clk_root =
{
@@ -492,9 +492,9 @@ const struct clock_configuration_s g_initial_clkconfig = {
.mfd = 268435455,
.ss_enable = 0,
.pfd0 = 27, /* (528 * 18) / 27 = 352 MHz */
.pfd1 = 16, /* (528 * 16) / 16 = 594 MHz */
.pfd2 = 24, /* (528 * 24) / 27 = 396 MHz */
.pfd3 = 32, /* (528 * 32) / 27 = 297 MHz */
.pfd1 = 16, /* (528 * 18) / 16 = 594 MHz */
.pfd2 = 24, /* (528 * 18) / 24 = 396 MHz */
.pfd3 = 22, /* (528 * 18) / 22 = 216 MHz */
},
.sys_pll3 =
{
@@ -81,24 +81,8 @@ static int flexio_irq_handler(int irq, void *context, void *arg)
int up_dshot_init(uint32_t channel_mask, unsigned dshot_pwm_freq)
{
uint32_t timer_compare;
uint32_t timer_compare = 0x2F00 | (((BOARD_FLEXIO_PREQ / (dshot_pwm_freq * 3) / 2) - 1) & 0xFF);
if (dshot_pwm_freq == 150000) {
timer_compare = 0x2F8A;
} else if (dshot_pwm_freq == 300000) {
timer_compare = 0x2F45;
} else if (dshot_pwm_freq == 600000) {
timer_compare = 0x2F22;
} else if (dshot_pwm_freq == 1200000) {
timer_compare = 0x2F11;
} else {
// Not supported Dshot frequency
return 0;
}
/* Init FlexIO peripheral */