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[BACKPORT] imxrt: Change PLL settings for more accurate dshot timing
This commit is contained in:
committed by
Daniel Agar
parent
c8fedda09a
commit
e00101b771
@@ -52,6 +52,7 @@
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#define IMXRT_IPG_PODF_DIVIDER 5
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#define BOARD_GPT_FREQUENCY 24000000
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#define BOARD_XTAL_FREQUENCY 24000000
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#define BOARD_FLEXIO_PREQ 108000000
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/* SDIO *********************************************************************/
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@@ -114,11 +114,11 @@ const struct clock_configuration_s g_initial_clkconfig = {
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.div = 1,
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.mux = ACMP_CLK_ROOT_OSC_RC_48M_DIV2,
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},
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.flexio1_clk_root =
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.flexio1_clk_root = /* 432 / 4 = 108Mhz */
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{
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.enable = 1,
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.div = 2,
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.mux = FLEXIO1_CLK_ROOT_SYS_PLL3_DIV2,
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.div = 4,
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.mux = FLEXIO1_CLK_ROOT_SYS_PLL2_PFD3,
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},
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.flexio2_clk_root =
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{
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@@ -492,9 +492,9 @@ const struct clock_configuration_s g_initial_clkconfig = {
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.mfd = 268435455,
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.ss_enable = 0,
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.pfd0 = 27, /* (528 * 18) / 27 = 352 MHz */
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.pfd1 = 16, /* (528 * 16) / 16 = 594 MHz */
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.pfd2 = 24, /* (528 * 24) / 27 = 396 MHz */
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.pfd3 = 32, /* (528 * 32) / 27 = 297 MHz */
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.pfd1 = 16, /* (528 * 18) / 16 = 594 MHz */
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.pfd2 = 24, /* (528 * 18) / 24 = 396 MHz */
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.pfd3 = 22, /* (528 * 18) / 22 = 216 MHz */
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},
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.sys_pll3 =
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{
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@@ -81,24 +81,8 @@ static int flexio_irq_handler(int irq, void *context, void *arg)
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int up_dshot_init(uint32_t channel_mask, unsigned dshot_pwm_freq)
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{
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uint32_t timer_compare;
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uint32_t timer_compare = 0x2F00 | (((BOARD_FLEXIO_PREQ / (dshot_pwm_freq * 3) / 2) - 1) & 0xFF);
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if (dshot_pwm_freq == 150000) {
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timer_compare = 0x2F8A;
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} else if (dshot_pwm_freq == 300000) {
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timer_compare = 0x2F45;
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} else if (dshot_pwm_freq == 600000) {
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timer_compare = 0x2F22;
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} else if (dshot_pwm_freq == 1200000) {
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timer_compare = 0x2F11;
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} else {
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// Not supported Dshot frequency
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return 0;
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}
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/* Init FlexIO peripheral */
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