Commit Graph
73 Commits
Author SHA1 Message Date
David Sidrane 0b70a8cc44 px4fmu-v5:Add FMUv5 HW revision and version 2017-09-29 10:13:51 -04:00
David Sidrane d95e985f59 px4fmu-v5:Set non default BOARD_ADC_OPEN_CIRCUIT_V
Due to higher bias, V open circuit on the ADC is high with a 1M
   termination. This override the default connected threshold on
   V5 HW. Revist once lowe termination is chosen.
2017-09-29 10:13:51 -04:00
Daniel Agar 01b3e6fd25 NuttX upgrade cmake wrapper (#7873)
* NuttX cmake

* px4_macros:Pass the stringified predicate as second arg to static assert

   CC_ASSERT mapes to the c++ static_assert or provides the same
   funtionality for c via the other macros. The c++ static assert
   takes 2 argumants the prdicate and a message. This fixes the
   lacking second argument.

* Updated nuttx and apps submodule to upstream nuttx 7.21+==master

   This is the latest uptake of upstream nuttx and apps.

* ROMFS generate with xxd instead of objcopy

* delete nuttx-patches

* NuttX update submodules to latest px4_nuttx-master

* fix nuttx apps and board dependency

* docker_run update to latest container 2017-08-29

* cmake ROMFS portable sed usage

* NuttX update submodules to latest px4_nuttx-master
2017-09-29 10:13:51 -04:00
David Sidrane 1e25a61b37 px4fmu-v5: Upstream NuttX up_cxxinitialize moved
was:<nuttx/arch.h> is:platform/cxxinitialize.h
   Removed PX4 version:src/modules/systemlib/up_cxxinitialize.c
   in favor of nuttx platform/gnu/gnu_cxxinitialize.c
2017-09-29 10:13:51 -04:00
David Sidrane 9dbaa001d3 px4fmu-v5:spi_dev_e is now uint32_t in NuttX
Using new type of uint32_t for spi device and macros
   that define a PX4 device on a given BUS and Chip Select
2017-09-29 10:13:51 -04:00
Daniel Agar dd6892443c px4fmu-v5 fix sign-compare 2017-09-07 10:27:36 +02:00
David Sidrane cde3545560 px4fmu-v5:Configure PWM LED polarity, and swapping
Test HW has R and G LED swapped and drives the UI LED's active
  high. The changes support all the configuratons of FMUv5 on
  RC00 and RC01 HW for PWM status and UI LEDs.
2017-08-26 03:44:59 -10:00
David Sidrane 3e46b5d02f px4fmu-v5:Extend PWM LED definitions to suport polarity, drive and swaps
Added palarity mask to support active low drive on per channel
   bassis.

   Added open drain drive type when the enables are active low to
   ensure the LED are off when supplied form 5 volts.
   For active Push Pull is used. Active low drive is recomended.

   Added support for test HW that had the R and G LED signals
   swapped.
2017-08-26 03:44:59 -10:00
David Sidrane 9c68783c54 px4fmu-v5:Reorder I2C busses int 1-4 order
This alows the -b option map 1-to-1 with the 12C bus numbers
2017-08-26 03:44:59 -10:00
David Sidrane 67e470b0e1 px4fmu-v5:Use arch/polarity agnostic Power control macros
Use the board supplied Power control macros, in the
   the board_peripheral_reset.

   This abstacts the polarity from the code. Therefore changes
   in signal sense can be made, just in the board config.
2017-08-12 08:02:41 +02:00
David Sidrane 5506588a31 px4fmu-v5:Add conditional support for Test RC00 HW
RC00 had an active high VDD_5V_PERIPH_EN
   PC01 has an active low  VDD_5V_PERIPH_EN

   RC00 Test hardware did not use an LTC4417

   While RC00 HW is still in circulation you can build with
   PX4_FMUV5_RC00 defined and BOARD_HAS_LTC4417 undefined.

   The default is PX4_FMUV5_RC01 and BOARD_HAS_LTC4417 defined.
2017-08-12 08:02:41 +02:00
David Sidrane b4f5e36fb1 px4fmu-v5:Add all I2C defines for all busses
Define BOARD_NUMBER_I2C_BUSES and BOARD_I2C_BUS_CLOCK_INIT
   for I2C1-4
2017-08-08 21:45:01 +02:00
David Sidrane fc38bc4144 px4fmu-v5:Added Muti Brick support definitions
BOARD_HAS_LTC44XX_VALIDS - 0 -> No LTC44xx IC, N is the number of
                              Power Bricks connected to the LTC44xx
                              For a LTC4417 this would be 2 as the
                              third prioriy is used for USB

   BOARD_HAS_USB_VALID     - If defied as 1 imples that infact
                             the USB has a priority connection
                             on the LTC44XX

   BOARD_HAS_NBAT_V       - the number of battery voltage sensing chennels
                            on the ADC

   BOARD_HAS_NBAT_I      - the number of battery current  sensing chennels
                            on the ADC

   A super simple (non FMUv5 compliant) board with no LTC44xx and just one battery
   that have no current sense:

    BOARD_HAS_LTC44XX_VALIDS = 0
    BOARD_HAS_USB_VALID      = 0
    BOARD_HAS_NBAT_V         = 1
    BOARD_HAS_NBAT_0         = 0

   A fully FMUv5 compliant design would use:

    BOARD_HAS_LTC44XX_VALIDS = 2
    BOARD_HAS_USB_VALID      = 1
    BOARD_HAS_NBAT_V         = 2
    BOARD_HAS_NBAT_0         = 2

   These setting properly condition the ADC channles and all the Power
   module valid sensing logic in the ADC module.
2017-07-17 21:02:50 -10:00
David Sidrane 53a04f3ba7 px4fmu-v5:board_config clean up
Removed unused headers and placed the __BEGIN_DECLS where it belonged
2017-07-17 21:02:50 -10:00
David Sidrane 579b55f2cb px4fmu-v5:There will be variants that will [not]have the PX4IO.
The PX4IO is an population option on some varients. To have
   1) FMU only control
   2) IO Only control
   3) FMU fall back control

   These pins need to come up as inputs, until the configuration
   is determined.
2017-07-17 21:02:50 -10:00
David Sidrane f7e3f34f48 px4fmu-v5:Insure the VBUS signal is low if USB is not connected.
Dispite what the ref manaul says. Some HW needs the added pull
   down to insure the pin reads low when not plugged in to USB.
2017-07-17 21:02:50 -10:00
David Sidrane 15f9f6c06f px4fmu-v5:formatting 2017-07-17 21:02:50 -10:00
David Sidrane ddddedf410 px4fmu-v5:Define Tone Alarm in terms of the FMUv5 Spec 2017-07-17 21:02:50 -10:00
David Sidrane 90fd7734bb px4fmu-v5:Define UI LEDs per the FMUv5 Spec 2017-07-17 21:02:50 -10:00
David Sidrane a254b0dca5 px4fmu-v5:Define the FMU_CAP[1:3] per FMUv5 Spec 2017-07-17 21:02:50 -10:00
David Sidrane 14ce28b1f3 px4fmu-v5:GPIO Clean up per FMUv5 Spec.
Added comments to ADC defines with Pin numbers.
  Added the GPIO_HW_{REV:VER}_DRIVE signals
  Define the GPIO_nPOWER_IN_{A:C] and assign them to
  BRICK1, BRICK2 and USB Valid.
  Regroupped power signals and defined true logic Power Control macros
  in the arch agnostic form.
  Defined the same IOCTL defines for FMU GPIO IOCTL
  Use the power Control macros on board_app_initialize
2017-07-17 21:02:50 -10:00
David Sidrane d33b945db6 px4fmu-v5:SPI chip selects per FMUv5 Spec 2017-07-17 21:02:50 -10:00
David Sidrane 8607b72805 px4fmu-v5:Removed unused LED alias defines. 2017-07-17 21:02:50 -10:00
David Sidrane 4188c4d0d5 px4fmu-v5:Turn On SD card 2017-07-17 21:02:50 -10:00
David Sidrane a09bc63747 px4fmu-v5:Use PX4_ERR in board init, spi init and sdio init 2017-07-17 21:02:50 -10:00
David Sidrane 229c5d482f px4fmu-v5:More GPIO_VDD_3V3V_SD_CARD_EN -> GPIO_VDD_3V3_SD_CARD_EN 2017-07-17 21:02:50 -10:00
David Sidrane 46daebfb6c px4fmu-v5:Removed a SPI 5 reeady signal from board_spi_reset
board_spi_reset is used to reset the internal SPI bus.
   therefore GPIO_SPI5_DRDY7_EXTERNAL1 should not have been
   minipulated, as it is on SPI5
2017-07-17 21:02:50 -10:00
David Sidrane 59d020fba3 px4fmu-v5:Added comment block to board_spi_reset 2017-07-17 21:02:50 -10:00
David Sidrane 85b6986079 px4fmu-v5:Fix board_peripheral_reset to use correct polarity
GPIO_nVDD_5V_PERIPH_EN is Active low. board_peripheral_reset
   need to tune it OFF then ON
2017-07-17 21:02:50 -10:00
David Sidrane ebc8b47fad px4fmu-v5:Added board_on_reset api to reset PWM 2017-07-17 21:02:50 -10:00
David Sidrane 54bd0a9f2a px4fmu-v5:Using arch agnostic gpio init
Define the GPIO pin list use the board_gpio_init
2017-07-17 21:02:50 -10:00
David Sidrane 044b845c40 px4fmu-v5:Match GPIO_VDD_3V3_SD_CARD_EN and polarity to FMUv5 Pin Spec RC01
Removed extra V GPIO_VDD_3V3[V]_SD_CARD_EN and it is active High
2017-07-17 21:02:50 -10:00
David Sidrane 82dc6de19f px4fmu-v5:Define the BOARD_NUMBER_BRICKS for future enumeration
When BOARD_NUMBER_BRICKS exists it will enable multiple
   power source testing and reporting.
2017-07-17 21:02:50 -10:00
David Sidrane b9f43068af px4fmu-v5:Define the existance of the UI PWM LED and it's polarity
Per https://docs.google.com/spreadsheets/d/1-n0__BYDedQrc_2NHqBenG1DNepAgnHpSGglke-QQwY/edit#gid=730959725
  Usage of the PWM UI led is optional and if used it's polaity may
  be set ot Active low or high.
2017-07-17 21:02:50 -10:00
David Sidrane 33cd8c7093 px4fmu-v5:Fixed comment 8 PWM 2017-07-17 21:02:50 -10:00
David Sidrane e20d685f40 px4fmu-v5:Add Timer and Channel to comment for HEATER 2017-07-17 21:02:50 -10:00
David Sidrane c1eac11823 px4fmu-v5:Match signals names to FMUv5 Pin Spec RC01 2017-07-17 21:02:50 -10:00
David Sidrane 5669434585 px4fmu-v5:Define ADC GPIO and Channels clearly
Moving forward we want all the board configs to drive the
   configuration. This is just cleanup to give a clear
   example of how ADC should be defined by a simple list,
   based on ADC pin number as related to the GPIO and
   channel number. Then the xxx_CHANNEL bit are
   used to form the ADC_CHANNELS (mask). The GPIO
   will are used to for a list for initalization.
2017-07-17 21:02:50 -10:00
David Sidrane 5ba02d740c px4fmu-v5:Group SPI signals by bus 2017-07-17 21:02:50 -10:00
David Sidrane 88c1521b5e px4fmu-v5:Status LED's are driven open drain
Allows Anaode of LEDs to be tied to V5 or V3.3
2017-07-17 21:02:50 -10:00
David Sidrane 68e5764dbc board common:Add arch agnostic gpio init 2017-07-17 21:02:50 -10:00
Simone Guscetti ada48571d7 fmu-v5: fix timer config 2017-07-17 21:02:50 -10:00
Simone Guscetti a00441ecf4 fmu-v5 timer_config: timer io channels for FMU_CH7/8 2017-07-17 21:02:50 -10:00
Simone Guscetti a4d8bf56cc fmu-v5 timer_config: set up the timers for v5 board
FMU_CH7/8 use timer 12 ch1/2
FMU_CAP use timer 2
Buzzer use timer 9
2017-07-17 21:02:50 -10:00
Simone Guscetti bc793d15cf fmu-v5 board_config: add FMU_CH7 and FMU_CH8 2017-07-17 21:02:50 -10:00
Simone Guscetti db9bef352a fmu-v5 board_config: config SPI5 sync and reset pins 2017-07-17 21:02:50 -10:00
Simone Guscetti 1e86f24cf9 fmu-v5 board_config: set up external spi 2017-07-17 21:02:50 -10:00
Simone Guscetti 74dfa8805f fmu-v5 board_config: power A is the brick voltage sensing 2017-07-17 21:02:50 -10:00
Simone Guscetti 518383ada8 fmu-v5: update board config to the newest pin assigment 2017-07-17 21:02:50 -10:00
Simone Guscetti 308295f648 fmu-v5: fix compiling errors 2017-07-17 21:02:50 -10:00