Update src/modules/mavlink/mavlink_receiver.cpp

Autotune mavlink - reject invalid param1 or 2 with fail
add cmake variant and px4board file to ark flow mr target (#25793 )
2026-05-23 22:27:34 +08:00 · 2025-10-23 16:11:44 +11:00 · 2025-10-22 10:12:42 +11:00 · 2025-10-21 13:20:55 -06:00 · 2025-10-21 11:48:03 +02:00 · 2025-10-21 11:21:27 +02:00
233 changed files with 5804 additions and 6276 deletions
@@ -2,37 +2,6 @@
 # - If you want to keep the tests running in GitHub Actions you need to uncomment the "runs-on: ubuntu-latest" lines
 #   and comment the "runs-on: [runs-on,runner=..." lines.
 # - If you would like to duplicate this setup try setting up "RunsOn" on your own AWS account try https://runs-on.com
-#
-# ===================================================================================
-# RELEASE UPLOAD LOGIC
-# ===================================================================================
-# This workflow handles building firmware and uploading to S3 + GitHub Releases.
-#
-# S3 Bucket Structure (s3://px4-travis/Firmware/):
-#   - master/          <- Latest main branch build (for QGC compatibility)
-#   - stable/          <- Latest stable release, controlled by 'stable' branch
-#   - beta/            <- Latest pre-release, controlled by 'beta' branch
-#   - vX.Y.Z/          <- Archived stable release
-#   - vX.Y.Z-beta1/    <- Archived pre-release
-#
-# Trigger Behavior:
-#   - Tag v1.16.1        -> Upload to: v1.16.1/ only (versioned archive)
-#   - Tag v1.17.0-beta1  -> Upload to: v1.17.0-beta1/ only (versioned archive)
-#   - Branch main        -> Upload to: master/ (for QGC compatibility)
-#   - Branch stable      -> Upload to: stable/ (QGC stable firmware)
-#   - Branch beta        -> Upload to: beta/ (QGC beta firmware)
-#   - Branch release/**  -> Build only, no S3 upload (CI validation)
-#   - Pull requests      -> Build only, no S3 upload (CI validation)
-#
-# GitHub Releases:
-#   - All version tags create a draft GitHub Release
-#   - Pre-releases (alpha/beta/rc suffixes) are automatically marked as such
-#
-# IMPORTANT: Version tags do NOT upload to stable/ or beta/. Only the
-# corresponding branch pushes control those directories. This prevents
-# pre-release tags from accidentally overwriting stable firmware (#26340)
-# and avoids race conditions between tag and branch builds.
-# ===================================================================================

 name: Build all targets

@@ -190,13 +159,6 @@ jobs:
          path: ~/.ccache
          key: ${{ steps.cc_restore.outputs.cache-primary-key }}

-  # ===========================================================================
-  # ARTIFACT UPLOAD JOB
-  # ===========================================================================
-  # Uploads build artifacts to S3 and creates GitHub Releases.
-  # Runs for version tags (v*), main, stable, and beta branch pushes.
-  # See header comments for full upload logic documentation.
-  # ===========================================================================
  artifacts:
    name: Upload Artifacts
    # runs-on: ubuntu-latest
@@ -215,31 +177,31 @@ jobs:
      - name: Choose Upload Location
        id: upload-location
        run: |
+          # Determine upload location based on branch or tag with the following considerations:
+          # Destination: AWS S3 bucket px4-travis in folder Firmware/
+          # - If branch is main -> upload to master/
+          #   - Older versions of QGC are hardocded to look for master/
+          # - If branch is stable or beta -> upload to stable/ or beta/
+          # - If a tag vX.Y.Z -> upload to vX.Y.Z/
+          #   - Also update stable/ to point to the same version
+          #.  - Older versions of QGC are hardocded to look for stable/
+          # - If a pull request -> do not upload
          set -euo pipefail

          ref="${GITHUB_REF}"
          branch=${{ needs.group_targets.outputs.branchname  }}
          location="$branch"
-          is_prerelease="false"

-          # Main branch uploads to "master" for QGC backward compatibility
          if [[ "$branch" == "main" ]]; then
            location="master"
          fi

-          # Version tags: upload to versioned directory (e.g., v1.16.1/)
          if [[ "$ref" == refs/tags/v[0-9]* ]]; then
            tag="${ref#refs/tags/}"
            location="$tag"
-
-            # Pre-release tags contain -alpha, -beta, or -rc suffix
-            if [[ "$tag" =~ -(alpha|beta|rc) ]]; then
-              is_prerelease="true"
-            fi
          fi

          echo "uploadlocation=$location" >> $GITHUB_OUTPUT
-          echo "is_prerelease=$is_prerelease" >> $GITHUB_OUTPUT

      - name: Uploading Artifacts to S3 [${{ steps.upload-location.outputs.uploadlocation }}]
        uses: jakejarvis/s3-sync-action@master
@@ -253,13 +215,28 @@ jobs:
          SOURCE_DIR: artifacts/
          DEST_DIR: Firmware/${{ steps.upload-location.outputs.uploadlocation }}/

-      # Create a draft GitHub Release for all version tags
-      # Pre-releases are automatically marked as such
+      # if we are uploading artifacts to a versioned folder
+      # we should also update the stable folder in the s3 bucket
+      - name: Uploading Artifacts to S3 [stable]
+        uses: jakejarvis/s3-sync-action@master
+        if: startsWith(github.ref, 'refs/tags/v')
+        with:
+          args: --acl public-read
+        env:
+          AWS_S3_BUCKET: 'px4-travis'
+          AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }}
+          AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
+          AWS_REGION: 'us-west-1'
+          SOURCE_DIR: artifacts/
+          DEST_DIR: Firmware/stable/
+
+      # if build is a release triggered by a versioned tag then create a github release
+      # and upload the build artifacts. A draft release is created so that the release
+      # can be reviewed before publishing
      - name: Upload Artifacts to GitHub Release
        uses: softprops/action-gh-release@v2
        if: startsWith(github.ref, 'refs/tags/v')
        with:
          draft: true
-          prerelease: ${{ steps.upload-location.outputs.is_prerelease == 'true' }}
          files: artifacts/*.px4
          name: ${{ steps.upload-location.outputs.uploadlocation }}
@@ -19,10 +19,6 @@ concurrency:
 jobs:
  build:
    runs-on: ubuntu-latest
-
-    container:
-      image: px4io/px4-dev:v1.16.0-rc1-258-g0369abd556
-
    strategy:
      fail-fast: false
      matrix:
@@ -39,17 +35,20 @@ jobs:
          "px4_sitl_allyes",
          "module_documentation",
        ]
-
    steps:
      - uses: actions/checkout@v4
        with:
          fetch-depth: 0

      - name: Building [${{ matrix.check }}]
-        run: |
-          cd "$GITHUB_WORKSPACE"
-          git config --global --add safe.directory "$GITHUB_WORKSPACE"
-          make ${{ matrix.check }}
+        uses: addnab/docker-run-action@v3
+        with:
+          image: px4io/px4-dev:v1.16.0-rc1-258-g0369abd556
+          options: -v ${{ github.workspace }}:/workspace
+          run: |
+            cd /workspace
+            git config --global --add safe.directory /workspace
+            make ${{ matrix.check }}

      - name: Uploading Coverage to Codecov.io
        if: contains(matrix.check, 'coverage')
@@ -15,21 +15,21 @@ concurrency:
 jobs:
  unit_tests:
    runs-on: ubuntu-latest
-
-    container:
-      image: px4io/px4-dev:v1.16.0-rc1-258-g0369abd556
-
    steps:
-      - uses: actions/checkout@v4
-        with:
-          fetch-depth: 0
+    - uses: actions/checkout@v4
+      with:
+        fetch-depth: 0

-      - name: main test
+    - name: main test
+      uses: addnab/docker-run-action@v3
+      with:
+        image: px4io/px4-dev:v1.16.0-rc1-258-g0369abd556
+        options: -v ${{ github.workspace }}:/workspace
        run: |
-          cd "$GITHUB_WORKSPACE"
-          git config --global --add safe.directory "$GITHUB_WORKSPACE"
+          cd /workspace
+          git config --global --add safe.directory /workspace
          make tests TESTFILTER=EKF

-      - name: Check if there is a functional change
-        run: git diff --exit-code
-        working-directory: src/modules/ekf2/test/change_indication
+    - name: Check if there is a functional change
+      run: git diff --exit-code
+      working-directory: src/modules/ekf2/test/change_indication
@@ -8,47 +8,40 @@ on:
 jobs:
  unit_tests:
    runs-on: ubuntu-latest
-
-    container:
-      image: px4io/px4-dev:v1.16.0-rc1-258-g0369abd556
-
    env:
      GIT_COMMITTER_EMAIL: bot@px4.io
      GIT_COMMITTER_NAME: PX4BuildBot
-
    steps:
-      - uses: actions/checkout@v4
-        with:
-          fetch-depth: 0
+    - uses: actions/checkout@v4
+      with:
+        fetch-depth: 0

-      - name: main test
+    - name: main test
+      uses: addnab/docker-run-action@v3
+      with:
+        image: px4io/px4-dev:v1.16.0-rc1-258-g0369abd556
+        options: -v ${{ github.workspace }}:/workspace
        run: |
-          cd "$GITHUB_WORKSPACE"
-          git config --global --add safe.directory "$GITHUB_WORKSPACE"
+          cd /workspace
+          git config --global --add safe.directory /workspace
          make tests TESTFILTER=EKF

-      - name: Check if there exists diff and save result in variable
-        id: diff-check
-        working-directory: src/modules/ekf2/test/change_indication
-        run: |
-          if git diff --quiet; then
-            echo "CHANGE_INDICATED=false" >> $GITHUB_OUTPUT
-          else
-            echo "CHANGE_INDICATED=true" >> $GITHUB_OUTPUT
-          fi
+    - name: Check if there exists diff and save result in variable
+      id: diff-check
+      run: echo "CHANGE_INDICATED=$(git diff --exit-code --output=/dev/null || echo $?)" >> $GITHUB_OUTPUT
+      working-directory: src/modules/ekf2/test/change_indication

-      - name: auto-commit any changes to change indication
-        if: steps.diff-check.outputs.CHANGE_INDICATED == 'true'
-        uses: stefanzweifel/git-auto-commit-action@v4
-        with:
-          file_pattern: 'src/modules/ekf2/test/change_indication/*.csv'
-          commit_user_name: ${{ env.GIT_COMMITTER_NAME }}
-          commit_user_email: ${{ env.GIT_COMMITTER_EMAIL }}
-          commit_message: |
-            [AUTO COMMIT] update change indication
+    - name: auto-commit any changes to change indication
+      uses: stefanzweifel/git-auto-commit-action@v4
+      with:
+        file_pattern: 'src/modules/ekf2/test/change_indication/*.csv'
+        commit_user_name: ${GIT_COMMITTER_NAME}
+        commit_user_email: ${GIT_COMMITTER_EMAIL}
+        commit_message: |
+          '[AUTO COMMIT] update change indication'

-            See .github/workflows/ekf_update_change_indicator.yml for more details
+          See .github/workflopws/ekf_update_change_indicator.yml for more details

-      - name: if there is a functional change, fail check
-        if: steps.diff-check.outputs.CHANGE_INDICATED == 'true'
-        run: exit 1
+    - name: if there is a functional change, fail check
+      if: ${{ steps.diff-check.outputs.CHANGE_INDICATED }}
+      run: exit 1
@@ -41,10 +41,6 @@ jobs:
            scripts: >
              boards/nxp/tropic-community/nuttx-config/scripts/itcm_functions_includes.ld
              boards/nxp/tropic-community/nuttx-config/scripts/itcm_static_functions.ld
-          - target: nxp_mr-tropic
-            scripts: >
-              boards/nxp/mr-tropic/nuttx-config/scripts/itcm_functions_includes.ld
-              boards/nxp/mr-tropic/nuttx-config/scripts/itcm_static_functions.ld
    steps:
      - uses: actions/checkout@v4
        with:
@@ -19,27 +19,25 @@ concurrency:
 jobs:
  build:
    runs-on: ubuntu-latest
-
    strategy:
      fail-fast: false
+      matrix:
+        config:
+          - {vehicle: "iris",          mission: "MC_mission_box"}

    steps:
-      - uses: actions/checkout@v4
-        with:
-          fetch-depth: 0
+    - uses: actions/checkout@v4
+      with:
+        fetch-depth: 0

-      - name: Build SITL and Run Tests (inside old ROS container)
+    - name: Build SITL and Run Tests
+      uses: addnab/docker-run-action@v3
+      with:
+        image: px4io/px4-dev-ros-melodic:2021-09-08
+        options: -v ${{ github.workspace }}:/workspace
        run: |
-          docker run --rm \
-            -v "${GITHUB_WORKSPACE}:/workspace" \
-            -w /workspace \
-            px4io/px4-dev-ros-melodic:2021-09-08 \
-            bash -c '
-              git config --global --add safe.directory /workspace
-              make px4_sitl_default
-              make px4_sitl_default sitl_gazebo-classic
-              ./test/rostest_px4_run.sh \
-                mavros_posix_test_mission.test \
-                mission:=MC_mission_box \
-                vehicle:=iris
-            '
+          cd /workspace
+          git config --global --add safe.directory /workspace
+          make px4_sitl_default
+          make px4_sitl_default sitl_gazebo-classic
+          ./test/rostest_px4_run.sh mavros_posix_test_mission.test mission:=${{matrix.config.mission}} vehicle:=${{matrix.config.vehicle}}
@@ -19,26 +19,27 @@ concurrency:
 jobs:
  build:
    runs-on: ubuntu-latest
-
+    env:
+      ACTIONS_ALLOW_USE_UNSECURE_NODE_VERSION: true
    strategy:
      fail-fast: false
+      matrix:
+        config:
+          - {test_file: "mavros_posix_tests_offboard_posctl.test",    vehicle: "iris"}

    steps:
-      - uses: actions/checkout@v4
-        with:
-          fetch-depth: 0
+    - uses: actions/checkout@v4
+      with:
+        fetch-depth: 0

-      - name: Build SITL and Run Tests (inside old ROS container)
+    - name: Build PX4 and Run Tests
+      uses: addnab/docker-run-action@v3
+      with:
+        image: px4io/px4-dev-ros-melodic:2021-09-08
+        options: -v ${{ github.workspace }}:/workspace
        run: |
-          docker run --rm \
-            -v "${GITHUB_WORKSPACE}:/workspace" \
-            -w /workspace \
-            px4io/px4-dev-ros-melodic:2021-09-08 \
-            bash -c '
-              git config --global --add safe.directory /workspace
-              make px4_sitl_default
-              make px4_sitl_default sitl_gazebo-classic
-              ./test/rostest_px4_run.sh \
-                mavros_posix_tests_offboard_posctl.test \
-                vehicle:=iris
-            '
+          cd /workspace
+          git config --global --add safe.directory /workspace
+          make px4_sitl_default
+          make px4_sitl_default sitl_gazebo-classic
+          ./test/rostest_px4_run.sh ${{matrix.config.test_file}} vehicle:=${{matrix.config.vehicle}}
@@ -19,28 +19,27 @@ concurrency:
 jobs:
  build:
    runs-on: ubuntu-latest
-
-    container:
-      image: px4io/px4-dev:v1.16.0-rc1-258-g0369abd556
-
    strategy:
      matrix:
-        config:
-          - px4_fmu-v5_default
+        config: [
+          px4_fmu-v5_default,
+          ]

    steps:
-      - uses: actions/checkout@v4
-        with:
-          fetch-depth: 0
+    - uses: actions/checkout@v4
+      with:
+        fetch-depth: 0

-      - name: Build PX4 and Run Test [${{ matrix.config }}]
+    - name: Build PX4 and Run Test [${{ matrix.config }}]
+      uses: addnab/docker-run-action@v3
+      with:
+        image: px4io/px4-dev:v1.16.0-rc1-258-g0369abd556
+        options: -v ${{ github.workspace }}:/workspace
        run: |
-          cd "$GITHUB_WORKSPACE"
-          git config --global --add safe.directory "$GITHUB_WORKSPACE"
-          export PX4_EXTRA_NUTTX_CONFIG='CONFIG_NSH_LOGIN_PASSWORD="test";CONFIG_NSH_CONSOLE_LOGIN=y'
+          cd /workspace
+          git config --global --add safe.directory /workspace
+          export PX4_EXTRA_NUTTX_CONFIG="CONFIG_NSH_LOGIN_PASSWORD=\"test\";CONFIG_NSH_CONSOLE_LOGIN=y"
          echo "PX4_EXTRA_NUTTX_CONFIG: $PX4_EXTRA_NUTTX_CONFIG"
-
          make ${{ matrix.config }} nuttx_context
-
          echo "Check that the config option is set"
          grep CONFIG_NSH_LOGIN_PASSWORD build/${{ matrix.config }}/NuttX/nuttx/.config
@@ -141,6 +141,11 @@ CONFIG:
      buildType: MinSizeRel
      settings:
        CONFIG: ark_can-flow_canbootloader
+    ark_can-flow-mr_default:
+      short: ark_can-flow-mr_default
+      buildType: MinSizeRel
+      settings:
+        CONFIG: ark_can-flow-mr_default
    ark_can-flow-mr_canbootloader:
      short: ark_can-flow-mr_canbootloader
      buildType: MinSizeRel
@@ -456,16 +461,6 @@ CONFIG:
      buildType: MinSizeRel
      settings:
        CONFIG: nxp_mr-canhubk3_fmu
-    nxp_mr-tropic_default:
-      short: nxp_mr-tropic_default
-      buildType: MinSizeRel
-      settings:
-        CONFIG: nxp_mr-tropic_default
-    nxp_mr-tropic_bootloader:
-      short: nxp_mr-tropic_bootloader
-      buildType: MinSizeRel
-      settings:
-        CONFIG: nxp_mr-tropic_bootloader
    nxp_tropic-community_default:
      short: nxp_tropic-community_default
      buildType: MinSizeRel
@@ -496,3 +491,13 @@ CONFIG:
      buildType: MinSizeRel
      settings:
        CONFIG: x-mav_ap-h743v2_default
+    svehicle_e2_bootloader:
+      short: svehicle_e2_bootloader
+      buildType: MinSizeRel
+      settings:
+        CONFIG: svehicle_e2_bootloader
+    svehicle_e2_default:
+      short: svehicle_e2
+      buildType: MinSizeRel
+      settings:
+        CONFIG: svehicle_e2_default
@@ -1,6 +1,6 @@
 BSD 3-Clause License

-Copyright (c) 2012 - 2023, PX4 Development Team
+Copyright (c) 2012 - 2025, PX4 Development Team
 All rights reserved.

 Redistribution and use in source and binary forms, with or without
@@ -26,6 +26,7 @@ param set-default EKF2_MAG_ACCLIM 0
 param set-default EKF2_REQ_EPH 10
 param set-default EKF2_REQ_EPV 10
 param set-default EKF2_REQ_HDRIFT 0.5
+param set-default EKF2_REQ_PDOP 4
 param set-default EKF2_REQ_SACC 1
 param set-default EKF2_REQ_VDRIFT 1
 param set-default EKF2_RNG_QLTY_T 3
@@ -238,7 +238,6 @@ def get_actuator_output(yaml_config, output_functions, timer_config_file, verbos
            ( 'disarmed', 'Disarmed', 'DIS', False ),
            ( 'min', 'Minimum', 'MIN', False ),
            ( 'max', 'Maximum', 'MAX', False ),
-            ( 'center', 'Center\n(for Servos)', 'CENT', False ),
            ( 'failsafe', 'Failsafe', 'FAIL', True ),
            ]
        for key, label, param_suffix, advanced in standard_params_array:
@@ -284,9 +284,6 @@ Note that non-motor outputs might already be active in prearm state if COM_PREAR
 '''
        minimum_description = \
 '''Minimum output value (when not disarmed).
-'''
-        center_description = \
-'''Servo Center output value (when not disarmed).
 '''
        maximum_description = \
 '''Maxmimum output value (when not disarmed).
@@ -299,7 +296,6 @@ When set to -1 (default), the value depends on the function (see {:}).
        standard_params_array = [
            ( 'disarmed', 'Disarmed', 'DIS', disarmed_description ),
            ( 'min', 'Minimum', 'MIN', minimum_description ),
-            ( 'center', 'Center', 'CENT', center_description ),
            ( 'max', 'Maximum', 'MAX', maximum_description ),
            ( 'failsafe', 'Failsafe', 'FAIL', failsafe_description ),
            ]
@@ -316,10 +312,6 @@ When set to -1 (default), the value depends on the function (see {:}).
                    standard_params[key]['default'] = -1
                    standard_params[key]['min'] = -1

-                if key == 'center':
-                    standard_params[key]['default'] = -1
-                    standard_params[key]['min'] = -1
-
                param = {
                    'description': {
                        'short': channel_label+' ${i} '+label+' Value',
@@ -0,0 +1,30 @@
+CONFIG_BOARD_TOOLCHAIN="arm-none-eabi"
+CONFIG_BOARD_ARCHITECTURE="cortex-m4"
+CONFIG_BOARD_ROMFSROOT="cannode"
+CONFIG_BOARD_CONSTRAINED_FLASH=y
+CONFIG_BOARD_NO_HELP=y
+CONFIG_BOARD_CONSTRAINED_MEMORY=y
+CONFIG_DRIVERS_BOOTLOADERS=y
+CONFIG_DRIVERS_DISTANCE_SENSOR_BROADCOM_AFBRS50=y
+CONFIG_DRIVERS_IMU_INVENSENSE_IIM42653=y
+CONFIG_DRIVERS_OPTICAL_FLOW_PAA3905=y
+CONFIG_BOARD_UAVCAN_INTERFACES=1
+CONFIG_DRIVERS_UAVCANNODE=y
+CONFIG_UAVCANNODE_FLOW_MEASUREMENT=y
+CONFIG_UAVCANNODE_RANGE_SENSOR_MEASUREMENT=y
+CONFIG_UAVCANNODE_RAW_IMU=y
+CONFIG_MODULES_GYRO_CALIBRATION=y
+CONFIG_MODULES_SENSORS=y
+# CONFIG_SENSORS_VEHICLE_AIRSPEED is not set
+# CONFIG_SENSORS_VEHICLE_AIR_DATA is not set
+# CONFIG_SENSORS_VEHICLE_ACCELERATION is not set
+# CONFIG_SENSORS_VEHICLE_GPS_POSITION is not set
+# CONFIG_SENSORS_VEHICLE_MAGNETOMETER is not set
+CONFIG_SYSTEMCMDS_PARAM=y
+CONFIG_SYSTEMCMDS_PERF=y
+CONFIG_SYSTEMCMDS_REBOOT=y
+CONFIG_SYSTEMCMDS_TOP=y
+CONFIG_SYSTEMCMDS_TOPIC_LISTENER=y
+CONFIG_SYSTEMCMDS_UORB=y
+CONFIG_SYSTEMCMDS_VER=y
+CONFIG_SYSTEMCMDS_WORK_QUEUE=y
@@ -8,9 +8,8 @@ param set-default SENS_FLOW_RATE 150
 param set-default SENS_IMU_CLPNOTI 0

 param set-default SENS_AFBR_S_RATE 25
-param set-default SENS_AFBR_L_RATE 10
-param set-default SENS_AFBR_THRESH 8
-param set-default SENS_AFBR_HYSTER 2
+param set-default SENS_AFBR_L_RATE 5
+param set-default SENS_AFBR_MODE 1

 # Internal SPI
 paa3905 -s start -Y 180
@@ -1,4 +0,0 @@
-#!/bin/sh
-#
-# Tropic Community specific board MAVLink startup script.
-#------------------------------------------------------------------------------
@@ -1,68 +0,0 @@
-#!/bin/sh
-#
-# PX4 board sensors init
-#------------------------------------------------------------------------------
-#
-# UART mapping on Tropic Community:
-#
-# LPUART5       /dev/ttyS0      CONSOLE
-# LPUART3       /dev/ttyS1      GPS
-# LPUART2       /dev/ttyS2      TELEM1
-# LPUART4       /dev/ttyS3      TELEM2
-# LPUART8       /dev/ttyS4      RC
-#
-#------------------------------------------------------------------------------
-
-set INA_CONFIGURED no
-
-board_adc start
-
-if param compare SENS_EN_INA226 1
-then
-	# Start Digital power monitors
-	ina226 -X -b 3 -t 1 -k start
-	set INA_CONFIGURED yes
-fi
-
-if param compare SENS_EN_INA228 1
-then
-	# Start Digital power monitors
-	ina228 -X -b 3 -t 1 -k start
-	set INA_CONFIGURED yes
-fi
-
-if param compare SENS_EN_INA238 1
-then
-	# Start Digital power monitors
-	ina238 -X -b 3 -t 1 -k start
-	set INA_CONFIGURED yes
-fi
-
-if [ $INA_CONFIGURED = no ]
-then
-	# INA226, INA228, INA238 auto-start
-	i2c_launcher start -b 3 -t 1
-fi
-
-# Internal SPI bus icm45686
-icm45686 -R 2 -b 3 -s start
-
-# Internal on IMU SPI BMI088
-bmi088 -A -R 2 -b 4 -s start
-bmi088 -G -R 2 -b 4 -s start
-
-# Internal magnetometer on I2c
-bmm350 -I -b 4 -R 6 start
-
-# External compass on GPS1/I2C1 (the 3rd external bus): standard Holybro Pixhawk 4 or CUAV V5 GPS/compass puck (with lights, safety button, and buzzer)
-ist8310 -X -b 1 -R 10 start
-
-# Possible internal Baro
-
-# Disable startup of internal baros if param is set to false
-if param compare SENS_INT_BARO_EN 1
-then
-	bmp388 -I -b 4 start
-fi
-
-unset INA_CONFIGURED
@@ -1,4 +0,0 @@
-#
-# For a description of the syntax of this configuration file,
-# see the file kconfig-language.txt in the NuttX tools repository.
-#
@@ -1,416 +0,0 @@
-/************************************************************************************
- * nuttx-configs/nxp/nxp_mr-tropic/include/board.h
- *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
- *   Authors: Gregory Nutt <gnutt@nuttx.org>
- *            David Sidrane <david_s5@nscdg.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __NUTTX_CONFIG_NXP_TROPIC_INCLUDE_BOARD_H
-#define __NUTTX_CONFIG_NXP_TROPIC_INCLUDE_BOARD_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Clocking *************************************************************************/
-
-/* Set VDD_SOC to 1.25V */
-
-#define IMXRT_VDD_SOC (0x12)
-
-/* Set Arm PLL (PLL1) to  fOut    = (24Mhz * ARM_PLL_DIV_SELECT/2) / ARM_PODF_DIVISOR
- *                        576Mhz  = (24Mhz * ARM_PLL_DIV_SELECT/2) / ARM_PODF_DIVISOR
- *                        ARM_PLL_DIV_SELECT = 96
- *                        ARM_PODF_DIVISOR   = 2
- *                        576Mhz  = (24Mhz * 96/2) / 2
- *
- *     AHB_CLOCK_ROOT             = PLL1fOut / IMXRT_AHB_PODF_DIVIDER
- *     1Hz to 600 Mhz             = 576Mhz / IMXRT_ARM_CLOCK_DIVIDER
- *                        IMXRT_ARM_CLOCK_DIVIDER = 1
- *                        576Mhz  = 576Mhz / 1
- *
- *     PRE_PERIPH_CLK_SEL         = PRE_PERIPH_CLK_SEL_PLL1
- *     PERIPH_CLK_SEL             = 1 (0 select PERIPH_CLK2_PODF, 1 select PRE_PERIPH_CLK_SEL_PLL1)
- *     PERIPH_CLK                 = 576Mhz
- *
- *     IPG_CLOCK_ROOT             = AHB_CLOCK_ROOT / IMXRT_IPG_PODF_DIVIDER
- *                       IMXRT_IPG_PODF_DIVIDER = 4
- *                       144Mhz = 576Mhz / 4
- *
- *     PRECLK_CLOCK_ROOT          = IPG_CLOCK_ROOT / IMXRT_PERCLK_PODF_DIVIDER
- *                       IMXRT_PERCLK_PODF_DIVIDER = 1
- *                       16Mhz = 144Mhz / 9
- *
- *     SEMC_CLK_ROOT              = 576Mhz / IMXRT_SEMC_PODF_DIVIDER (labeled AIX_PODF in 18.2)
- *                       IMXRT_SEMC_PODF_DIVIDER = 8
- *                       72Mhz    = 576Mhz / 8
- *
- * Set Sys PLL (PLL2) to  fOut    = (24Mhz * (20+(2*(DIV_SELECT)))
- *                        528Mhz  = (24Mhz * (20+(2*(1)))
- *
- * Set USB1 PLL (PLL3) to fOut    = (24Mhz * 20)
- *                         480Mhz = (24Mhz * 20)
- *
- * Set LPSPI PLL3 PFD0 to fOut    = (480Mhz / 12 * 18)
- *                        720Mhz  = (480Mhz / 12 * 18)
- *                         90Mhz  = (720Mhz / LSPI_PODF_DIVIDER)
- *
- * Set LPI2C PLL3 / 8 to   fOut   = (480Mhz / 8)
- *                         60Mhz  = (480Mhz / 8)
- *                         12Mhz  = (60Mhz / LSPI_PODF_DIVIDER)
- *
- * Set USDHC1 PLL2 PFD2 to fOut   = (528Mhz / 24 * 18)
- *                        396Mhz  = (528Mhz / 24 * 18)
- *                        198Mhz  = (396Mhz / IMXRT_USDHC1_PODF_DIVIDER)
- */
-
-#define BOARD_XTAL_FREQUENCY      24000000
-#define IMXRT_PRE_PERIPH_CLK_SEL  CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1
-#define IMXRT_PERIPH_CLK_SEL      CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH
-#define IMXRT_ARM_PLL_DIV_SELECT  96
-#define IMXRT_ARM_PODF_DIVIDER    2
-#define IMXRT_AHB_PODF_DIVIDER    1
-#define IMXRT_IPG_PODF_DIVIDER    4
-#define IMXRT_PERCLK_CLK_SEL      CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT
-#define IMXRT_PERCLK_PODF_DIVIDER 9
-#define IMXRT_SEMC_PODF_DIVIDER   8
-#define IMXRT_CAN_CLK_SELECT       CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80
-#define IMXRT_CAN_PODF_DIVIDER    1
-
-#define IMXRT_LPSPI_CLK_SELECT    CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0
-#define IMXRT_LSPI_PODF_DIVIDER   8
-
-#define IMXRT_LPI2C_CLK_SELECT    CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M
-#define IMXRT_LSI2C_PODF_DIVIDER  5
-
-#define IMXRT_USDHC1_CLK_SELECT    CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0
-#define IMXRT_USDHC1_PODF_DIVIDER 2
-
-#define IMXRT_USB1_PLL_DIV_SELECT  CCM_ANALOG_PLL_USB1_DIV_SELECT_20
-
-#define IMXRT_SYS_PLL_SELECT      CCM_ANALOG_PLL_SYS_DIV_SELECT_22
-
-#define IMXRT_USB1_PLL_DIV_SELECT  CCM_ANALOG_PLL_USB1_DIV_SELECT_20
-
-#define BOARD_CPU_FREQUENCY \
-	(BOARD_XTAL_FREQUENCY * (IMXRT_ARM_PLL_DIV_SELECT / 2)) / IMXRT_ARM_PODF_DIVIDER
-
-#define BOARD_GPT_FREQUENCY \
-	(BOARD_CPU_FREQUENCY / IMXRT_IPG_PODF_DIVIDER) / IMXRT_PERCLK_PODF_DIVIDER
-
-
-/* 108Mhz clock for FlexIO using PLL3 PFD2 @ 520 */
-#define CONFIG_FLEXIO1_CLK          1
-#define CONFIG_FLEXIO1_PRED_DIVIDER 5
-#define CONFIG_FLEXIO1_PODF_DIVIDER 1
-#define CONFIG_PLL3_PFD2_FRAC       16
-#define BOARD_FLEXIO_PREQ           108000000
-
-/* Define this to enable tracing */
-#if CONFIG_USE_TRACE
-#  define IMXRT_TRACE_PODF_DIVIDER 1
-#  define IMXRT_TRACE_CLK_SELECT   CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0
-#endif
-
-/* SDIO *****************************************************************************/
-
-/* Pin drive characteristics */
-
-#define USDHC1_DATAX_IOMUX  (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
-#define USDHC1_CMD_IOMUX    (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
-#define USDHC1_CLK_IOMUX    (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_SPEED_MAX)
-#define USDHC1_CD_IOMUX     (IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
-
-#define PIN_USDHC1_D0       (GPIO_USDHC1_DATA0_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_02 */
-#define PIN_USDHC1_D1       (GPIO_USDHC1_DATA1_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_03 */
-#define PIN_USDHC1_D2       (GPIO_USDHC1_DATA2_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_04 */
-#define PIN_USDHC1_D3       (GPIO_USDHC1_DATA3_1 | USDHC1_DATAX_IOMUX) /* GPIO_SD_B0_05 */
-#define PIN_USDHC1_DCLK     (GPIO_USDHC1_CLK_1   | USDHC1_CLK_IOMUX)   /* GPIO_SD_B0_01 */
-#define PIN_USDHC1_CMD      (GPIO_USDHC1_CMD_1   | USDHC1_CMD_IOMUX)   /* GPIO_SD_B0_00 */
-#define PIN_USDHC1_CD       (PIN_USDHC1_D3)
-
-/* #define PIN_USDHC1_CD       (GPIO_USDHC1_CD_3    | USDHC1_CD_IOMUX)
- *  CD_B Pin works fine but somehow the driver has a timing issue with
- *  Thus use D3 instead
- */
-
-/* Ideal 400Khz for initial inquiry.
- *  Given input clock 198 Mhz.
- *   386.71875 KHz =  198 Mhz / (256 * 2)
- */
-
-#define BOARD_USDHC_IDMODE_PRESCALER    USDHC_SYSCTL_SDCLKFS_DIV256
-#define BOARD_USDHC_IDMODE_DIVISOR      USDHC_SYSCTL_DVS_DIV(2)
-
-/* Ideal 25 Mhz for other modes
- *  Given input clock 198 Mhz.
- *    24.75 MHz =  198 Mhz / (8 * 1)
- */
-
-#define BOARD_USDHC_MMCMODE_PRESCALER   USDHC_SYSCTL_SDCLKFS_DIV8
-#define BOARD_USDHC_MMCMODE_DIVISOR     USDHC_SYSCTL_DVS_DIV(1)
-
-#define BOARD_USDHC_SD1MODE_PRESCALER   USDHC_SYSCTL_SDCLKFS_DIV8
-#define BOARD_USDHC_SD1MODE_DIVISOR     USDHC_SYSCTL_DVS_DIV(1)
-
-#define BOARD_USDHC_SD4MODE_PRESCALER   USDHC_SYSCTL_SDCLKFS_DIV8
-#define BOARD_USDHC_SD4MODE_DIVISOR     USDHC_SYSCTL_DVS_DIV(1)
-
-/* ETH Disambiguation *******************************************************/
-
-/* Ethernet Interrupt: GPIO_B0_15
- *
- * This pin has a week pull-up within the PHY, is open-drain, and requires
- * an external 1k ohm pull-up resistor (present on the EVK).  A falling
- * edge then indicates a change in state of the PHY.
- */
-
-#define GPIO_ENET_INT   (IOMUX_ENET_INT_DEFAULT | \
-			 GPIO_PORT2 | GPIO_PIN15)    /* B0_15 */
-#define GPIO_ENET_IRQ   IMXRT_IRQ_GPIO2_15
-
-/* Ethernet Reset:  GPIO_B0_14
- *
- * The #RST uses inverted logic.  The initial value of zero will put the
- * PHY into the reset state.
- */
-
-#define GPIO_ENET_RST   (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
-			 GPIO_PORT2 | GPIO_PIN14 | IOMUX_ENET_RST_DEFAULT) /* B0_14 */
-
-#define GPIO_ENET_TX_DATA00  (GPIO_ENET_TX_DATA00_1| \
-			      IOMUX_ENET_DATA_DEFAULT)                    /* GPIO_B1_07 */
-#define GPIO_ENET_TX_DATA01  (GPIO_ENET_TX_DATA01_1| \
-			      IOMUX_ENET_DATA_DEFAULT)                    /* GPIO_B1_08 */
-#define GPIO_ENET_RX_DATA00  (GPIO_ENET_RX_DATA00_1| \
-			      IOMUX_ENET_DATA_DEFAULT)                    /* GPIO_B1_04 */
-#define GPIO_ENET_RX_DATA01  (GPIO_ENET_RX_DATA01_1| \
-			      IOMUX_ENET_DATA_DEFAULT)                    /* GPIO_B1_05 */
-#define GPIO_ENET_MDIO       (GPIO_ENET_MDIO_1|IOMUX_ENET_MDIO_DEFAULT)   /* GPIO_B1_15 */
-#define GPIO_ENET_MDC        (GPIO_ENET_MDC_1|IOMUX_ENET_MDC_DEFAULT)     /* GPIO_B1_14 */
-#define GPIO_ENET_RX_EN      (GPIO_ENET_RX_EN_1|IOMUX_ENET_EN_DEFAULT)    /* GPIO_B1_06 */
-#define GPIO_ENET_RX_ER      (GPIO_ENET_RX_ER_1|IOMUX_ENET_RXERR_DEFAULT) /* GPIO_B1_11 */
-#define GPIO_ENET_TX_CLK     (GPIO_ENET_REF_CLK_2|\
-			      IOMUX_ENET_TX_CLK_DEFAULT)                  /* GPIO_B1_10 */
-#define GPIO_ENET_TX_EN      (GPIO_ENET_TX_EN_1|IOMUX_ENET_EN_DEFAULT)    /* GPIO_B1_09 */
-
-/* LED definitions ******************************************************************/
-/* The nxp fmutr1062 board has numerous LEDs but only three, LED_GREEN a Green LED,
- * LED_BLUE a Blue LED and LED_RED a Red LED, that can be controlled by software.
- *
- * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
- * The following definitions are used to access individual LEDs.
- */
-
-/* LED index values for use with board_userled() */
-
-#define BOARD_LED1        0
-#define BOARD_LED2        1
-#define BOARD_LED3        2
-#define BOARD_NLEDS       3
-
-#define BOARD_LED_RED     BOARD_LED1
-#define BOARD_LED_GREEN   BOARD_LED2
-#define BOARD_LED_BLUE    BOARD_LED3
-
-/* LED bits for use with board_userled_all() */
-
-#define BOARD_LED1_BIT    (1 << BOARD_LED1)
-#define BOARD_LED2_BIT    (1 << BOARD_LED2)
-#define BOARD_LED3_BIT    (1 << BOARD_LED3)
-
-/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
- * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
- * events as follows:
- *
- *
- *   SYMBOL                     Meaning                      LED state
- *                                                        Red   Green Blue
- *   ----------------------  --------------------------  ------ ------ ----*/
-
-#define LED_STARTED        0 /* NuttX has been started   OFF    OFF   OFF  */
-#define LED_HEAPALLOCATE   1 /* Heap has been allocated  OFF    OFF   ON   */
-#define LED_IRQSENABLED    2 /* Interrupts enabled       OFF    ON    OFF  */
-#define LED_STACKCREATED   3 /* Idle stack created       OFF    ON    ON   */
-#define LED_INIRQ          4 /* In an interrupt          N/C    N/C   GLOW */
-#define LED_SIGNAL         5 /* In a signal handler      N/C    GLOW  N/C  */
-#define LED_ASSERTION      6 /* An assertion failed      GLOW   N/C   GLOW */
-#define LED_PANIC          7 /* The system has crashed   Blink  OFF   N/C  */
-#define LED_IDLE           8 /* MCU is is sleep mode     ON     OFF   OFF  */
-
-/* Thus if the Green LED is statically on, NuttX has successfully booted and
- * is, apparently, running normally.  If the Red LED is flashing at
- * approximately 2Hz, then a fatal error has been detected and the system
- * has halted.
- */
-
-/* PIO Disambiguation ***************************************************************/
-/* LPUARTs
- */
-#define LPUART_IOMUX      (IOMUX_PULL_UP_22K | IOMUX_DRIVE_40OHM | IOMUX_SLEW_SLOW | IOMUX_SPEED_LOW | IOMUX_SCHMITT_TRIGGER)
-#define IOMUX_UART_CTS_DEFAULT (IOMUX_PULL_DOWN_100K | IOMUX_DRIVE_40OHM | IOMUX_SLEW_SLOW)
-
-/* Debug */
-
-#define GPIO_LPUART6_RX   (GPIO_LPUART6_RX_2 | LPUART_IOMUX) /* GPIO_EMC_26 */
-#define GPIO_LPUART6_TX   (GPIO_LPUART6_TX_2 | LPUART_IOMUX) /* GPIO_EMC_25 */
-
-
-/* Telem 2 */
-
-#define GPIO_LPUART5_RX   (GPIO_LPUART5_RX_1 | LPUART_IOMUX) /* GPIO_B1_13 */
-#define GPIO_LPUART5_TX   (GPIO_LPUART5_TX_1 | LPUART_IOMUX) /* GPIO_B1_12 */
-#define GPIO_LPUART5_CTS  (GPIO_LPUART5_CTS_1 | IOMUX_UART_CTS_DEFAULT | PADMUX_SION)  /* GPIO_EMC_28 GPIO4_IO27 */
-#define GPIO_LPUART5_RTS  (GPIO_PORT4 | GPIO_PIN27 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) /* GPIO_EMC_27 GPIO4_IO27 (GPIO only, no HW Flow control) */
-
-/* AUX */
-
-#define GPIO_LPUART4_RX   (GPIO_LPUART4_RX_1 | LPUART_IOMUX) /* GPIO_B1_01 */
-#define GPIO_LPUART4_TX   (GPIO_LPUART4_TX_1 | LPUART_IOMUX) /* GPIO_B1_00 */
-#define GPIO_LPUART4_CTS  (GPIO_PORT1 | GPIO_PIN15 | GPIO_INPUT | PADMUX_SION | IOMUX_UART_CTS_DEFAULT)  /* GPIO_AD_B0_15 GPIO1_IO14 (Fixme Add GPIO Flow support in LPUART) */
-#define GPIO_LPUART4_RTS  (GPIO_PORT1 | GPIO_PIN14 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) /* GPIO_AD_B0_14 GPIO1_IO14 (GPIO only, no HW Flow control) */
-
-/* GPS 1 */
-
-#define GPIO_LPUART2_RX   (GPIO_LPUART2_RX_1 | LPUART_IOMUX) /* GPIO_AD_B1_03 */
-#define GPIO_LPUART2_TX   (GPIO_LPUART2_TX_1 | LPUART_IOMUX) /* GPIO_AD_B1_02 */
-
-/* Telem 1 */
-
-#define GPIO_LPUART3_RX   (GPIO_LPUART3_RX_1 | LPUART_IOMUX) /* GPIO_AD_B1_07 */
-#define GPIO_LPUART3_TX   (GPIO_LPUART3_TX_1 | LPUART_IOMUX) /* GPIO_AD_B1_06 */
-#define GPIO_LPUART3_CTS  (GPIO_LPUART3_CTS_1 | IOMUX_UART_CTS_DEFAULT | PADMUX_SION)  /* GPIO_AD_B1_04 GPIO1_IO20 */
-#define GPIO_LPUART3_RTS  (GPIO_PORT1 | GPIO_PIN21 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_UART_DEFAULT) /* GPIO_AD_B1_05 GPIO1_IO21 (GPIO only, no HW Flow control) */
-//TODO check RT7 partial HW handshake
-
-/* ESC ONEWIRE */
-#define GPIO_LPUART7_RX   (GPIO_LPUART7_TX_1 | LPUART_IOMUX) /* GPIO_EMC_31 */
-#define GPIO_LPUART7_TX   (GPIO_LPUART7_TX_1 | LPUART_IOMUX) /* GPIO_EMC_31 */
-
-
-/* RC INPUT single wire mode on Input on TX, for CRSF use TX and RX */
-
-#define GPIO_LPUART8_RX   (GPIO_LPUART8_RX_1 | LPUART_IOMUX) /* GPIO_AD_B1_11 */
-#define GPIO_LPUART8_TX   (GPIO_LPUART8_TX_1 | LPUART_IOMUX) /* GPIO_AD_B1_10 */
-
-/* CAN
- *
- * CAN1 is routed to transceiver.
- * CAN2 is routed to transceiver.
- * CAN3 is routed to transceiver.
- */
-#define FLEXCAN_IOMUX     (IOMUX_PULL_UP_100K | IOMUX_DRIVE_40OHM | IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM)
-
-#define GPIO_FLEXCAN3_RX  (GPIO_FLEXCAN3_RX_3 | FLEXCAN_IOMUX) /* GPIO_EMC_37 */
-#define GPIO_FLEXCAN3_TX  (GPIO_FLEXCAN3_TX_3 | FLEXCAN_IOMUX) /* GPIO_EMC_36 */
-
-/* LPSPI */
-#define LPSPI_IOMUX       (IOMUX_PULL_UP_100K | IOMUX_DRIVE_33OHM | IOMUX_SLEW_FAST | IOMUX_SPEED_MAX)
-
-
-#define GPIO_LPSPI3_SCK   (GPIO_LPSPI3_SCK_1 | LPSPI_IOMUX) /* GPIO_AD_B1_15 */
-#define GPIO_LPSPI3_MISO  (GPIO_LPSPI3_SDI_1 | LPSPI_IOMUX) /* GPIO_AD_B1_13 */
-#define GPIO_LPSPI3_MOSI  (GPIO_LPSPI3_SDO_1 | LPSPI_IOMUX) /* GPIO_AD_B1_14 */
-
-#define GPIO_LPSPI4_SCK   (GPIO_LPSPI4_SCK_2 | LPSPI_IOMUX) /* GPIO_B0_03 */
-#define GPIO_LPSPI4_MISO  (GPIO_LPSPI4_SDI_2 | LPSPI_IOMUX) /* GPIO_B0_01 */
-#define GPIO_LPSPI4_MOSI  (GPIO_LPSPI4_SDO_2 | LPSPI_IOMUX) /* GPIO_B0_02 */
-
-#define BOARD_SPI_BUS_MAX_BUS_ITEMS 2
-
-/* LPI2Cs */
-
-#define LPI2C_IOMUX    (IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM  | IOMUX_OPENDRAIN | GPIO_SION_ENABLE)
-#define LPI2C_IO_IOMUX (IOMUX_SPEED_MAX | IOMUX_SLEW_FAST | IOMUX_DRIVE_33OHM  | IOMUX_OPENDRAIN | IOMUX_PULL_NONE)
-
-#define GPIO_LPI2C1_SDA   (GPIO_LPI2C1_SDA_2 | LPI2C_IOMUX) /* EVK J24-9 R276  */ /* GPIO_AD_B1_01 */
-#define GPIO_LPI2C1_SCL   (GPIO_LPI2C1_SCL_2 | LPI2C_IOMUX) /* EVK J24-10 R277 */ /* GPIO_AD_B1_00 */
-
-#define GPIO_LPI2C1_SDA_RESET (GPIO_PORT1 | GPIO_PIN17 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_AD_B1_01 GPIO1_IO17 */
-#define GPIO_LPI2C1_SCL_RESET (GPIO_PORT1 | GPIO_PIN16 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_AD_B1_00 GPIO1_IO16 */
-
-#define GPIO_LPI2C3_SDA   (GPIO_LPI2C3_SDA_2 | LPI2C_IOMUX) /* GPIO_EMC_21 */
-#define GPIO_LPI2C3_SCL   (GPIO_LPI2C3_SCL_2 | LPI2C_IOMUX) /* GPIO_EMC_22 */
-
-#define GPIO_LPI2C3_SDA_RESET (GPIO_PORT4 | GPIO_PIN21 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_EMC_21 */
-#define GPIO_LPI2C3_SCL_RESET (GPIO_PORT4 | GPIO_PIN22 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_EMC_22 */
-
-#define GPIO_LPI2C4_SDA   (GPIO_LPI2C4_SDA_1 | LPI2C_IOMUX) /* GPIO_AD_B0_13 */
-#define GPIO_LPI2C4_SCL   (GPIO_LPI2C4_SCL_1 | LPI2C_IOMUX) /* GPIO_AD_B0_12 */
-
-#define GPIO_LPI2C4_SDA_RESET (GPIO_PORT1 | GPIO_PIN13 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_AD_B0_13 */
-#define GPIO_LPI2C4_SCL_RESET (GPIO_PORT1 | GPIO_PIN12 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LPI2C_IO_IOMUX) /* GPIO_AD_B0_12 */
-
-#define BOARD_PHY_ADDR (18)
-
-/* Board doesn't provide GPIO or other Hardware for signaling to timing analyzer */
-
-#define PROBE_INIT(mask)
-#define PROBE(n,s)
-#define PROBE_MARK(n)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __NUTTX_CONFIG_NXP_TROPIC_INCLUDE_BOARD_H */
@@ -1,270 +0,0 @@
-#
-# This file is autogenerated: PLEASE DO NOT EDIT IT.
-#
-# You can use "make menuconfig" to make any modifications to the installed .config file.
-# You can then do "make savedefconfig" to generate a new defconfig file that includes your
-# modifications.
-#
-# CONFIG_NSH_DISABLE_MB is not set
-# CONFIG_NSH_DISABLE_MH is not set
-# CONFIG_NSH_DISABLE_MW is not set
-# CONFIG_SPI_CALLBACK is not set
-CONFIG_ARCH="arm"
-CONFIG_ARCH_BOARD_CUSTOM=y
-CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/nxp/mr-tropic/nuttx-config"
-CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
-CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
-CONFIG_ARCH_CHIP="imxrt"
-CONFIG_ARCH_CHIP_IMXRT=y
-CONFIG_ARCH_CHIP_MIMXRT1064DVL6A=y
-CONFIG_ARCH_INTERRUPTSTACK=2048
-CONFIG_ARCH_RAMVECTORS=y
-CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARMV7M_DCACHE=y
-CONFIG_ARMV7M_DTCM=y
-CONFIG_ARMV7M_ICACHE=y
-CONFIG_ARMV7M_ITCM=y
-CONFIG_ARMV7M_MEMCPY=y
-CONFIG_ARMV7M_USEBASEPRI=y
-CONFIG_ARM_MPU=y
-CONFIG_ARM_MPU_RESET=y
-CONFIG_BOARDCTL_RESET=y
-CONFIG_BOARD_ASSERT_RESET_VALUE=0
-CONFIG_BOARD_LOOPSPERMSEC=115000
-CONFIG_BOARD_RESET_ON_ASSERT=2
-CONFIG_BUILTIN=y
-CONFIG_CDCACM=y
-CONFIG_CDCACM_BULKIN_REQLEN=96
-CONFIG_CDCACM_PRODUCTID=0x0025
-CONFIG_CDCACM_PRODUCTSTR="PX4 MR-TROPIC"
-CONFIG_CDCACM_RXBUFSIZE=600
-CONFIG_CDCACM_TXBUFSIZE=12000
-CONFIG_CDCACM_VENDORID=0x1FC9
-CONFIG_CDCACM_VENDORSTR="NXP SEMICONDUCTORS"
-CONFIG_DEBUG_ERROR=y
-CONFIG_DEBUG_FEATURES=y
-CONFIG_DEBUG_HARDFAULT_ALERT=y
-CONFIG_DEBUG_MEMFAULT=y
-CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DEBUG_TCBINFO=y
-CONFIG_DEV_FIFO_SIZE=0
-CONFIG_DEV_PIPE_SIZE=70
-CONFIG_DEV_URANDOM=y
-CONFIG_ETH0_PHY_TJA1103=y
-CONFIG_FAT_DMAMEMORY=y
-CONFIG_FAT_LCNAMES=y
-CONFIG_FAT_LFN=y
-CONFIG_FAT_LFN_ALIAS_HASH=y
-CONFIG_FDCLONE_STDIO=y
-CONFIG_FSUTILS_IPCFG=y
-CONFIG_FS_BINFS=y
-CONFIG_FS_CROMFS=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FATTIME=y
-CONFIG_FS_LITTLEFS=y
-CONFIG_FS_LITTLEFS_CACHE_SIZE_FACTOR=2
-CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE=64
-CONFIG_FS_LITTLEFS_PROGRAM_SIZE_FACTOR=1
-CONFIG_FS_PROCFS=y
-CONFIG_FS_PROCFS_MAX_TASKS=64
-CONFIG_FS_PROCFS_REGISTER=y
-CONFIG_FS_ROMFS=y
-CONFIG_GRAN=y
-CONFIG_GRAN_INTR=y
-CONFIG_HAVE_CXX=y
-CONFIG_HAVE_CXXINITIALIZE=y
-CONFIG_I2C=y
-CONFIG_I2C_RESET=y
-CONFIG_IDLETHREAD_STACKSIZE=2048
-CONFIG_IMXRT_DTCM_HEAP=y
-CONFIG_IMXRT_DTCM_HEAP_SIZE=127
-CONFIG_IMXRT_EDMA=y
-CONFIG_IMXRT_EDMA_EDBG=y
-CONFIG_IMXRT_EDMA_ELINK=y
-CONFIG_IMXRT_EDMA_NTCD=64
-CONFIG_IMXRT_ENET=y
-CONFIG_IMXRT_ENET_NTXBUFFERS=8
-CONFIG_IMXRT_ENET_PHYINIT=y
-CONFIG_IMXRT_FLEXCAN3=y
-CONFIG_IMXRT_FLEXCAN_TXMB=1
-CONFIG_IMXRT_GPIO1_0_15_IRQ=y
-CONFIG_IMXRT_GPIO1_16_31_IRQ=y
-CONFIG_IMXRT_GPIO2_0_15_IRQ=y
-CONFIG_IMXRT_GPIO2_16_31_IRQ=y
-CONFIG_IMXRT_GPIO_IRQ=y
-CONFIG_IMXRT_INIT_FLEXRAM=y
-CONFIG_IMXRT_ITCM=384
-CONFIG_IMXRT_LPI2C1=y
-CONFIG_IMXRT_LPI2C3=y
-CONFIG_IMXRT_LPI2C4=y
-CONFIG_IMXRT_LPI2C_DMA=y
-CONFIG_IMXRT_LPI2C_DMA_MAXMSG=16
-CONFIG_IMXRT_LPI2C_DYNTIMEO=y
-CONFIG_IMXRT_LPI2C_DYNTIMEO_STARTSTOP=10
-CONFIG_IMXRT_LPSPI3=y
-CONFIG_IMXRT_LPSPI3_DMA=y
-CONFIG_IMXRT_LPSPI4=y
-CONFIG_IMXRT_LPSPI4_DMA=y
-CONFIG_IMXRT_LPSPI_DMA=y
-CONFIG_IMXRT_LPUART2=y
-CONFIG_IMXRT_LPUART3=y
-CONFIG_IMXRT_LPUART4=y
-CONFIG_IMXRT_LPUART5=y
-CONFIG_IMXRT_LPUART6=y
-CONFIG_IMXRT_LPUART7=y
-CONFIG_IMXRT_LPUART8=y
-CONFIG_IMXRT_LPUART_INVERT=y
-CONFIG_IMXRT_LPUART_SINGLEWIRE=y
-CONFIG_IMXRT_PHY_POLLING=y
-CONFIG_IMXRT_SNVS_LPSRTC=y
-CONFIG_IMXRT_USBDEV=y
-CONFIG_IMXRT_USDHC1=y
-CONFIG_IMXRT_USDHC1_INVERT_CD=y
-CONFIG_IMXRT_USDHC1_WIDTH_D1_D4=y
-CONFIG_INIT_ENTRYPOINT="nsh_main"
-CONFIG_INIT_STACKSIZE=2944
-CONFIG_IOB_NBUFFERS=24
-CONFIG_IOB_THROTTLE=0
-CONFIG_IPCFG_BINARY=y
-CONFIG_IPCFG_PATH="/fs/nor"
-CONFIG_LIBC_MAX_EXITFUNS=1
-CONFIG_LIBC_STRERROR=y
-CONFIG_LPI2C1_DMA=y
-CONFIG_LPI2C3_DMA=y
-CONFIG_LPI2C4_DMA=y
-CONFIG_LPUART2_RXDMA=y
-CONFIG_LPUART2_TXDMA=y
-CONFIG_LPUART3_BAUD=57600
-CONFIG_LPUART3_IFLOWCONTROL=y
-CONFIG_LPUART3_OFLOWCONTROL=y
-CONFIG_LPUART3_RXBUFSIZE=600
-CONFIG_LPUART3_RXDMA=y
-CONFIG_LPUART3_TXBUFSIZE=3000
-CONFIG_LPUART3_TXDMA=y
-CONFIG_LPUART4_BAUD=57600
-CONFIG_LPUART4_IFLOWCONTROL=y
-CONFIG_LPUART4_RXBUFSIZE=600
-CONFIG_LPUART4_RXDMA=y
-CONFIG_LPUART4_TXBUFSIZE=3000
-CONFIG_LPUART4_TXDMA=y
-CONFIG_LPUART5_BAUD=57600
-CONFIG_LPUART5_IFLOWCONTROL=y
-CONFIG_LPUART5_OFLOWCONTROL=y
-CONFIG_LPUART5_RXBUFSIZE=600
-CONFIG_LPUART5_RXDMA=y
-CONFIG_LPUART5_TXBUFSIZE=3000
-CONFIG_LPUART5_TXDMA=y
-CONFIG_LPUART6_BAUD=57600
-CONFIG_LPUART6_SERIAL_CONSOLE=y
-CONFIG_LPUART7_RXDMA=y
-CONFIG_LPUART7_TXBUFSIZE=128
-CONFIG_LPUART8_BAUD=420000
-CONFIG_LPUART8_RXBUFSIZE=600
-CONFIG_LPUART8_RXDMA=y
-CONFIG_LPUART8_TXDMA=y
-CONFIG_MEMSET_64BIT=y
-CONFIG_MEMSET_OPTSPEED=y
-CONFIG_MMCSD=y
-CONFIG_MMCSD_SDIO=y
-CONFIG_MM_REGIONS=2
-CONFIG_MTD=y
-CONFIG_MTD_BYTE_WRITE=y
-CONFIG_MTD_PARTITION=y
-CONFIG_NAME_MAX=40
-CONFIG_NET=y
-CONFIG_NETDB_DNSCLIENT=y
-CONFIG_NETDB_DNSSERVER_NOADDR=y
-CONFIG_NETDEV_CAN_BITRATE_IOCTL=y
-CONFIG_NETDEV_CAN_FILTER_IOCTL=y
-CONFIG_NETDEV_LATEINIT=y
-CONFIG_NETDEV_PHY_IOCTL=y
-CONFIG_NETINIT_DHCPC=y
-CONFIG_NETINIT_DNS=y
-CONFIG_NETINIT_DNSIPADDR=0XC0A800FE
-CONFIG_NETINIT_DRIPADDR=0XC0A800FE
-CONFIG_NETINIT_MONITOR=y
-CONFIG_NETINIT_RETRY_MOUNTPATH=10
-CONFIG_NETINIT_THREAD=y
-CONFIG_NETINIT_THREAD_PRIORITY=49
-CONFIG_NETUTILS_TELNETD=y
-CONFIG_NET_ARP_IPIN=y
-CONFIG_NET_ARP_SEND=y
-CONFIG_NET_BROADCAST=y
-CONFIG_NET_CAN=y
-CONFIG_NET_CAN_EXTID=y
-CONFIG_NET_CAN_NOTIFIER=y
-CONFIG_NET_CAN_RAW_TX_DEADLINE=y
-CONFIG_NET_CAN_SOCK_OPTS=y
-CONFIG_NET_ETH_PKTSIZE=1518
-CONFIG_NET_ICMP=y
-CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_IGMP=y
-CONFIG_NET_SOLINGER=y
-CONFIG_NET_TCP=y
-CONFIG_NET_TCPBACKLOG=y
-CONFIG_NET_TCP_DELAYED_ACK=y
-CONFIG_NET_TCP_KEEPALIVE=y
-CONFIG_NET_TCP_WRITE_BUFFERS=y
-CONFIG_NET_TIMESTAMP=y
-CONFIG_NET_UDP=y
-CONFIG_NET_UDP_CHECKSUMS=y
-CONFIG_NET_UDP_WRITE_BUFFERS=y
-CONFIG_NSH_ARCHINIT=y
-CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_CROMFSETC=y
-CONFIG_NSH_LINELEN=128
-CONFIG_NSH_MAXARGUMENTS=15
-CONFIG_NSH_NESTDEPTH=8
-CONFIG_NSH_READLINE=y
-CONFIG_NSH_ROMFSETC=y
-CONFIG_NSH_ROMFSSECTSIZE=128
-CONFIG_NSH_STRERROR=y
-CONFIG_NSH_TELNET_LOGIN=y
-CONFIG_NSH_VARS=y
-CONFIG_PIPES=y
-CONFIG_PREALLOC_TIMERS=50
-CONFIG_PRIORITY_INHERITANCE=y
-CONFIG_PTHREAD_MUTEX_TYPES=y
-CONFIG_PTHREAD_STACK_MIN=512
-CONFIG_RAM_SIZE=1048576
-CONFIG_RAM_START=0x20200000
-CONFIG_RAW_BINARY=y
-CONFIG_READLINE_CMD_HISTORY=y
-CONFIG_READLINE_TABCOMPLETION=y
-CONFIG_RTC=y
-CONFIG_SCHED_HPWORK=y
-CONFIG_SCHED_HPWORKPRIORITY=249
-CONFIG_SCHED_HPWORKSTACKSIZE=1800
-CONFIG_SCHED_INSTRUMENTATION=y
-CONFIG_SCHED_INSTRUMENTATION_EXTERNAL=y
-CONFIG_SCHED_INSTRUMENTATION_SWITCH=y
-CONFIG_SCHED_LPWORK=y
-CONFIG_SCHED_LPWORKPRIORITY=50
-CONFIG_SCHED_LPWORKSTACKSIZE=2032
-CONFIG_SDIO_BLOCKSETUP=y
-CONFIG_SEM_PREALLOCHOLDERS=32
-CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
-CONFIG_SERIAL_TERMIOS=y
-CONFIG_SIG_DEFAULT=y
-CONFIG_SIG_SIGALRM_ACTION=y
-CONFIG_SIG_SIGUSR1_ACTION=y
-CONFIG_SIG_SIGUSR2_ACTION=y
-CONFIG_SIG_SIGWORK=4
-CONFIG_SPI=y
-CONFIG_STACK_COLORATION=y
-CONFIG_START_DAY=30
-CONFIG_START_MONTH=11
-CONFIG_STDIO_BUFFER_SIZE=256
-CONFIG_SYSTEM_CDCACM=y
-CONFIG_SYSTEM_CLE=y
-CONFIG_SYSTEM_DHCPC_RENEW=y
-CONFIG_SYSTEM_NSH=y
-CONFIG_SYSTEM_PING=y
-CONFIG_SYSTEM_SYSTEM=y
-CONFIG_TASK_NAME_SIZE=24
-CONFIG_USBDEV=y
-CONFIG_USBDEV_BUSPOWERED=y
-CONFIG_USBDEV_DUALSPEED=y
-CONFIG_USBDEV_MAXPOWER=500
-CONFIG_USEC_PER_TICK=1000
-CONFIG_WATCHDOG=y
@@ -1,177 +0,0 @@
-/****************************************************************************
- * boards/nxp/mr-tropic/nuttx-config/scripts/bootloader_script.ld
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/* Specify the memory areas */
-
-MEMORY
-{
-  flash (rx)  : ORIGIN = 0x70000000, LENGTH = 128K
-  sram  (rwx) : ORIGIN = 0x20200000, LENGTH = 512K
-  itcm  (rwx) : ORIGIN = 0x00000000, LENGTH = 384K
-  dtcm  (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
-}
-
-OUTPUT_ARCH(arm)
-EXTERN(_vectors)
-EXTERN(g_flash_config)
-EXTERN(g_image_vector_table)
-EXTERN(g_boot_data)
-EXTERN(board_get_manifest)
-EXTERN(_bootdelay_signature)
-
-ENTRY(_stext)
-
-SECTIONS
-{
-    /* Image Vector Table and Boot Data for booting from external flash */
-
-    .boot_hdr : ALIGN(4)
-    {
-        FILL(0xff)
-        __boot_hdr_start__ = ABSOLUTE(.) ;
-        KEEP(*(.boot_hdr.conf))
-        . = 0x1000 ;
-        KEEP(*(.boot_hdr.ivt))
-        . = 0x1020 ;
-        KEEP(*(.boot_hdr.boot_data))
-        . = 0x1030 ;
-        KEEP(*(.boot_hdr.dcd_data))
-        __boot_hdr_end__ = ABSOLUTE(.) ;
-        . = 0x2000 ;
-    } >flash
-
-    .vectors :
-    {
-        KEEP(*(.vectors))
-        *(.text .text.__start)
-    } >flash
-
-    .itcmfunc :
-    {
-        . = ALIGN(8);
-        _sitcmfuncs = ABSOLUTE(.);
-        FILL(0xFF)
-        . = 0x40 ;
-        *(.ram_vectors)
-        . = ALIGN(8);
-        _eitcmfuncs = ABSOLUTE(.);
-    } > itcm AT > flash
-
-    _fitcmfuncs = LOADADDR(.itcmfunc);
-
-    .text : ALIGN(4)
-    {
-        _stext = ABSOLUTE(.);
-        *(.vectors)
-		. = ALIGN(32);
-		/*
-		This signature provides the bootloader with a way to delay booting
-		*/
-		_bootdelay_signature = ABSOLUTE(.);
-		FILL(0xffecc2925d7d05c5)
-		. += 8;
-        *(.text .text.*)
-        *(.fixup)
-        *(.gnu.warning)
-        *(.gnu.linkonce.t.*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.got)
-        *(.gcc_except_table)
-        *(.gnu.linkonce.r.*)
-        . = ALIGN(4096);
-        _etext = ABSOLUTE(.);
-        _srodata = ABSOLUTE(.);
-        *(.rodata .rodata.*)
-        . = ALIGN(4096);
-        _erodata = ABSOLUTE(.);
-    } > flash
-
-    .init_section :
-    {
-        _sinit = ABSOLUTE(.);
-        KEEP(*(.init_array .init_array.*))
-        _einit = ABSOLUTE(.);
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab*)
-    } > flash
-
-    .ARM.exidx :
-    {
-        __exidx_start = ABSOLUTE(.);
-        *(.ARM.exidx*)
-        __exidx_end = ABSOLUTE(.);
-    } > flash
-
-    _eronly = ABSOLUTE(.);
-
-    .data :
-    {
-        _sdata = ABSOLUTE(.);
-        *(.data .data.*)
-        *(.gnu.linkonce.d.*)
-        CONSTRUCTORS
-        . = ALIGN(4);
-        _edata = ABSOLUTE(.);
-    } > sram AT > flash
-
-    .ramfunc ALIGN(4):
-    {
-        _sramfuncs = ABSOLUTE(.);
-        *(.ramfunc  .ramfunc.*)
-        _eramfuncs = ABSOLUTE(.);
-    } > sram AT > flash
-
-    _framfuncs = LOADADDR(.ramfunc);
-
-    .bss :
-    {
-        _sbss = ABSOLUTE(.);
-        *(.bss .bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = ABSOLUTE(.);
-    } > sram
-
-    /* Stabs debugging sections. */
-
-    .stab 0 : { *(.stab) }
-    .stabstr 0 : { *(.stabstr) }
-    .stab.excl 0 : { *(.stab.excl) }
-    .stab.exclstr 0 : { *(.stab.exclstr) }
-    .stab.index 0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment 0 : { *(.comment) }
-    .debug_abbrev 0 : { *(.debug_abbrev) }
-    .debug_info 0 : { *(.debug_info) }
-    .debug_line 0 : { *(.debug_line) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    .debug_aranges 0 : { *(.debug_aranges) }
-
-    _boot_loadaddr = ORIGIN(flash);
-    _boot_size = LENGTH(flash);
-    _ram_size = LENGTH(sram);
-    _sdtcm = ORIGIN(dtcm);
-    _edtcm = ORIGIN(dtcm) + LENGTH(dtcm);
-}
@@ -1,719 +0,0 @@
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-*(.text._ZN13MavlinkStream6updateERKy)
-*(.text._ZN7Mavlink16update_rate_multEv)
-*(.text._ZN3sym17PredictCovarianceIfEEN6matrix6MatrixIT_Lj23ELj23EEERKNS2_IS3_Lj24ELj1EEERKS4_RKNS2_IS3_Lj3ELj1EEES3_SC_SC_S3_S3_) /* itcm-check-ignore */
-*(.text._ZN13MavlinkStream12get_size_avgEv)
-*(.text._ZN16ControlAllocator3RunEv)
-*(.text._ZN22MulticopterRateControl3RunEv.part.0)
-*(.text._ZN7Mavlink9task_mainEiPPc)
-*(.text._ZN7sensors22VehicleAngularVelocity3RunEv)
-*(.text._ZN4uORB12Subscription9subscribeEv.part.0)
-*(.text._ZN4uORB7Manager13orb_data_copyEPvS1_Rjb)
-*(.text._ZN4uORB10DeviceNode5writeEP4filePKcj)
-*(.text._ZN4uORB10DeviceNode7publishEPK12orb_metadataPvPKv)
-*(.text._ZN4uORB12DeviceMaster19getDeviceNodeLockedEPK12orb_metadatah)
-*(.text._Z12get_orb_meta6ORB_ID)
-*(.text._ZN9ICM42688P12ProcessAccelERKyPKN20InvenSense_ICM42688P4FIFO4DATAEh)
-*(.text._ZN3px49WorkQueue3RunEv)
-*(.text._ZN9ICM42688P11ProcessGyroERKyPKN20InvenSense_ICM42688P4FIFO4DATAEh)
-*(.text._ZN4EKF23RunEv)
-*(.text._ZN7sensors10VehicleIMU7PublishEv)
-*(.text._ZN4math17WelfordMeanVectorIfLj3EE6updateERKN6matrix6VectorIfLj3EEE)
-*(.text._ZN7sensors10VehicleIMU10UpdateGyroEv)
-*(.text._ZN9ICM42688P8FIFOReadERKyh)
-*(.text._ZN3Ekf20controlGravityFusionERKN9estimator9imuSampleE)
-*(.text._ZN16PX4Accelerometer10updateFIFOER19sensor_accel_fifo_s)
-*(.text._ZN7sensors22VehicleAngularVelocity19CalibrateAndPublishERKyRKN6matrix7Vector3IfEES7_)
-*(.text._ZN4uORB12Subscription10advertisedEv)
-*(.text._ZNK15AttitudeControl6updateERKN6matrix10QuaternionIfEE)
-*(.text._ZN7sensors10VehicleIMU11UpdateAccelEv)
-*(.text.perf_set_elapsed.part.0)
-*(.text._ZN4uORB12Subscription6updateEPv)
-*(.text._ZN12PX4Gyroscope10updateFIFOER18sensor_gyro_fifo_s)
-*(.text._ZN7sensors10VehicleIMU3RunEv)
-*(.text.__aeabi_l2f)
-*(.text._ZN39ControlAllocationSequentialDesaturation23computeDesaturationGainERKN6matrix6VectorIfLj16EEES4_)
-*(.text.pthread_mutex_timedlock)
-*(.text._ZN7sensors22VehicleAngularVelocity21FilterAngularVelocityEiPfi)
-*(.text._ZN26MulticopterAttitudeControl3RunEv.part.0)
-*(.text._ZN6device3SPI9_transferEPhS1_j)
-*(.text._ZN15OutputPredictor21calculateOutputStatesEyRKN6matrix7Vector3IfEEfS4_f)
-*(.text._ZN7sensors18VotedSensorsUpdate7imuPollER17sensor_combined_s)
-*(.text._Z9rotate_3i8RotationRsS0_S0_)
-*(.text.fs_getfilep)
-*(.text.MEM_DataCopy0_1)
-*(.text._ZN7sensors19VehicleAcceleration3RunEv)
-*(.text.uart_ioctl)
-*(.text._ZN26MulticopterPositionControl3RunEv.part.0)
-*(.text.pthread_mutex_take)
-*(.text._ZN14ImuDownSampler6updateERKN9estimator9imuSampleE)
-*(.text._ZN39ControlAllocationSequentialDesaturation6mixYawEv)
-*(.text._ZN16ControlAllocator25publish_actuator_controlsEv.part.0)
-*(.text._ZN9ICM42688P7RunImplEv)
-*(.text._ZN4uORB12Subscription9subscribeEv)
-*(.text.param_get)
-*(.text._ZN7sensors22VehicleAngularVelocity21SensorSelectionUpdateERKyb)
-*(.text._ZN3px49WorkQueue3AddEPNS_8WorkItemE)
-*(.text._ZN4EKF220PublishLocalPositionERKy)
-*(.text._mav_finalize_message_chan_send)
-*(.text._ZN7sensors22VehicleAngularVelocity16ParametersUpdateEb)
-*(.text._ZN6events12SendProtocol6updateERKy)
-*(.text._ZN6device3SPI8transferEPhS1_j)
-*(.text._ZN27MavlinkStreamDistanceSensor4sendEv)
-*(.text.hrt_call_internal)
-*(.text._ZN39ControlAllocationSequentialDesaturation18mixAirmodeDisabledEv)
-*(.text._ZN7Mavlink15get_free_tx_bufEv)
-*(.text.nx_poll)
-*(.text._ZN15MavlinkReceiver3runEv)
-*(.text._ZN9ICM42688P18ProcessTemperatureEPKN20InvenSense_ICM42688P4FIFO4DATAEh)
-*(.text._ZN15OutputPredictor19correctOutputStatesEyRKN6matrix10QuaternionIfEERKNS0_7Vector3IfEERK9LatLonAltS8_S8_)
-*(.text._ZN3Ekf12predictStateERKN9estimator9imuSampleE)
-*(.text._ZN3px46logger6Logger3runEv)
-*(.text._ZN4uORB20SubscriptionInterval7updatedEv)
-*(.text._ZN24MavlinkStreamCommandLong4sendEv)
-*(.text._ZN9Commander3runEv)
-*(.text._ZN3Ekf17predictCovarianceERKN9estimator9imuSampleE)
-*(.text.wd_cancel)
-*(.text._ZN7Sensors3RunEv)
-*(.text.perf_end)
-*(.text._ZN4uORB12Subscription7updatedEv)
-*(.text._ZN13land_detector12LandDetector3RunEv)
-*(.text.sched_idletask)
-*(.text.atanf)
-*(.text.uart_write)
-*(.text.pthread_mutex_unlock)
-*(.text.__ieee754_asinf)
-*(.text.MEM_DataCopy0_2)
-*(.text._ZN20MavlinkCommandSender13check_timeoutE17mavlink_channel_t)
-*(.text._ZN16ControlAllocator32publish_control_allocator_statusEi)
-*(.text.__ieee754_atan2f)
-*(.text._ZNK18DynamicSparseLayer3getEt)
-*(.text.__udivmoddi4)
-*(.text._ZN8Failsafe17checkStateAndModeERKyRKN12FailsafeBase5StateERK16failsafe_flags_s)
-*(.text._ZN29MavlinkStreamHygrometerSensor4sendEv)
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-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope8FIFOReadERKyh)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope9DataReadyEv)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD0Ev)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD1Ev)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD2Ev)
-*(.text._ZN12I2CSPIDriverI6BMI088E3RunEv)
-
-/* BMM350 */
-*(.text._ZN12I2CSPIDriverI6BMM350E3RunEv)
-*(.text._ZN6BMM3507RunImplEv)
-*(.text._ZN6BMM35013RegisterWriteEN12Bosch_BMM3508RegisterEh)
-*(.text._ZN6BMM35012RegisterReadEN12Bosch_BMM3508RegisterEPh)
-*(.text._ZN6BMM35014ReadOutRawDataEPf)
@@ -1,187 +0,0 @@
-/****************************************************************************
- * boards/nxp/mr-tropic/nuttx-config/scripts/script.ld
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/* Specify the memory areas */
-
-MEMORY
-{
-  flash (rx)  : ORIGIN = 0x70020000, LENGTH = 4194304 - 256K
-  sram  (rwx) : ORIGIN = 0x20200000, LENGTH = 512K
-  itcm  (rwx) : ORIGIN = 0x00000000, LENGTH = 384K
-  dtcm  (rwx) : ORIGIN = 0x20000000, LENGTH = 127K
-  dtcm_nocache  (rwx) : ORIGIN = 0x2001FC00, LENGTH = 1K
-}
-
-OUTPUT_ARCH(arm)
-EXTERN(_vectors)
-EXTERN(g_flash_config)
-EXTERN(g_image_vector_table)
-EXTERN(g_boot_data)
-EXTERN(board_get_manifest)
-EXTERN(_bootdelay_signature)
-
-ENTRY(_stext)
-
-SECTIONS
-{
-    /* Image Vector Table and Boot Data for booting from external flash */
-
-    .boot_hdr : ALIGN(4)
-    {
-        FILL(0xff)
-        __boot_hdr_start__ = ABSOLUTE(.) ;
-        KEEP(*(.boot_hdr.conf))
-        . = 0x1000 ;
-        KEEP(*(.boot_hdr.ivt))
-        . = 0x1020 ;
-        KEEP(*(.boot_hdr.boot_data))
-        . = 0x1030 ;
-        KEEP(*(.boot_hdr.dcd_data))
-        __boot_hdr_end__ = ABSOLUTE(.) ;
-        . = 0x2000 ;
-    } >flash
-
-    /* Workaround for ethernet issue, by placing g_desc_pool into DTCM,
-       which effectively puts it into a no-cache region */
-    .dtcm_nocache : {
-        *(.bss.g_desc_pool)
-    } > dtcm_nocache
-
-    .vectors :
-    {
-        KEEP(*(.vectors))
-        *(.text .text.__start)
-    } >flash
-
-    .itcmfunc :
-    {
-        . = ALIGN(8);
-        _sitcmfuncs = ABSOLUTE(.);
-        FILL(0xFF)
-        . = 0x40 ;
-        *(.ram_vectors)
-        INCLUDE "itcm_static_functions.ld"
-        INCLUDE "itcm_functions_includes.ld"
-        . = ALIGN(8);
-        _eitcmfuncs = ABSOLUTE(.);
-    } > itcm AT > flash
-
-    _fitcmfuncs = LOADADDR(.itcmfunc);
-
-    .text :
-    {
-        _stext = ABSOLUTE(.);
-        *(.vectors)
-	. = ALIGN(32);
-	/*
-	This signature provides the bootloader with a way to delay booting
-	*/
-	_bootdelay_signature = ABSOLUTE(.);
-	FILL(0xffecc2925d7d05c5)
-	. += 8;
-        *(.text .text.*)
-        *(.fixup)
-        *(.gnu.warning)
-        *(.gnu.linkonce.t.*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.got)
-        *(.gcc_except_table)
-        *(.gnu.linkonce.r.*)
-        . = ALIGN(4096);
-        _etext = ABSOLUTE(.);
-        _srodata = ABSOLUTE(.);
-        *(.rodata .rodata.*)
-        . = ALIGN(4096);
-        _erodata = ABSOLUTE(.);
-    } > flash
-
-    .init_section :
-    {
-        _sinit = ABSOLUTE(.);
-        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
-        KEEP(*(.init_array .ctors))
-        _einit = ABSOLUTE(.);
-    } > flash
-
-    .ARM.extab :
-    {
-        *(.ARM.extab*)
-    } > flash
-
-    .ARM.exidx :
-    {
-        __exidx_start = ABSOLUTE(.);
-        *(.ARM.exidx*)
-        __exidx_end = ABSOLUTE(.);
-    } > flash
-
-    _eronly = ABSOLUTE(.);
-
-    .data :
-    {
-        _sdata = ABSOLUTE(.);
-        *(.data .data.*)
-        *(.gnu.linkonce.d.*)
-        CONSTRUCTORS
-        . = ALIGN(4);
-        _edata = ABSOLUTE(.);
-    } > sram AT > flash
-
-    .ramfunc ALIGN(4):
-    {
-        _sramfuncs = ABSOLUTE(.);
-        *(.ramfunc  .ramfunc.*)
-        _eramfuncs = ABSOLUTE(.);
-    } > sram AT > flash
-
-    _framfuncs = LOADADDR(.ramfunc);
-
-    .bss :
-    {
-        _sbss = ABSOLUTE(.);
-        *(.bss .bss.*)
-        *(.gnu.linkonce.b.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = ABSOLUTE(.);
-    } > sram
-
-    /* Stabs debugging sections. */
-
-    .stab 0 : { *(.stab) }
-    .stabstr 0 : { *(.stabstr) }
-    .stab.excl 0 : { *(.stab.excl) }
-    .stab.exclstr 0 : { *(.stab.exclstr) }
-    .stab.index 0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment 0 : { *(.comment) }
-    .debug_abbrev 0 : { *(.debug_abbrev) }
-    .debug_info 0 : { *(.debug_info) }
-    .debug_line 0 : { *(.debug_line) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    .debug_aranges 0 : { *(.debug_aranges) }
-
-    _boot_loadaddr = ORIGIN(flash);
-    _boot_size = LENGTH(flash);
-    _ram_size = LENGTH(sram);
-    _sdtcm = ORIGIN(dtcm);
-    _edtcm = ORIGIN(dtcm) + LENGTH(dtcm);
-}
@@ -1,355 +0,0 @@
-/****************************************************************************
- *
- *   Copyright (c) 2024 PX4 Development Team. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name PX4 nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/**
- * @file board_config.h
- *
- * Tropic Community internal definitions
- */
-
-#pragma once
-
-/****************************************************************************************************
- * Included Files
- ****************************************************************************************************/
-
-#include <px4_platform_common/px4_config.h>
-#include <px4_arch/io_timer.h>
-#include <nuttx/compiler.h>
-#include <stdint.h>
-
-#include "imxrt_gpio.h"
-#include "imxrt_iomuxc.h"
-#include "hardware/imxrt_pinmux.h"
-#include "hardware/imxrt_usb_analog.h"
-
-#include <arch/board/board.h>
-#include <arm_internal.h>
-
-/****************************************************************************************************
- * Definitions
- ****************************************************************************************************/
-
-/* Configuration ************************************************************************************/
-
-/* FMURT1062 GPIOs ***********************************************************************************/
-/* LEDs */
-/* An RGB LED is connected through GPIO as shown below:
- */
-#define LED_IOMUX (IOMUX_OPENDRAIN | IOMUX_PULL_NONE | IOMUX_DRIVE_33OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_SLOW)
-#define GPIO_nLED_RED   /* GPIO_EMC_33 GPIO3_IO19 */ (GPIO_PORT3 | GPIO_PIN19 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LED_IOMUX)
-#define GPIO_nLED_BLUE  /* GPIO_EMC_34 GPIO3_IO20 */ (GPIO_PORT3 | GPIO_PIN20 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LED_IOMUX)
-#define GPIO_nLED_GREEN /* GPIO_EMC_38 GPIO3_IO24 */ (GPIO_PORT3 | GPIO_PIN24 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | LED_IOMUX)
-
-#define BOARD_HAS_CONTROL_STATUS_LEDS   1
-#define BOARD_OVERLOAD_LED              LED_RED
-#define BOARD_ARMED_STATE_LED           LED_BLUE
-
-/*
- *  Define the ability to shut off off the sensor signals
- *  by changing the signals to inputs
- */
-
-#define _PIN_OFF(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT | IOMUX_PULL_DOWN_100K | IOMUX_CMOS_INPUT))
-
-/*  Define the Chip Selects, Data Ready and Control signals per SPI bus */
-
-#define CS_IOMUX  (IOMUX_CMOS_OUTPUT | IOMUX_PULL_UP_100K | IOMUX_DRIVE_33OHM | IOMUX_SPEED_LOW | IOMUX_SLEW_FAST)
-#define OUT_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_UP_100K | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_FAST)
-
-
-/* SPI1 off */
-
-#define _GPIO_LPSPI1_SCK   /* GPIO_EMC_27  GPIO4_IO27 */  (GPIO_PORT4 | GPIO_PIN27 | CS_IOMUX)
-#define _GPIO_LPSPI1_MISO  /* GPIO_EMC_29  GPIO4_IO29 */  (GPIO_PORT4 | GPIO_PIN29 | CS_IOMUX)
-#define _GPIO_LPSPI1_MOSI  /* GPIO_EMC_28  GPIO4_IO28 */  (GPIO_PORT4 | GPIO_PIN28 | CS_IOMUX)
-
-#define GPIO_SPI1_SCK_OFF   _PIN_OFF(_GPIO_LPSPI1_SCK)
-#define GPIO_SPI1_MISO_OFF  _PIN_OFF(_GPIO_LPSPI1_MISO)
-#define GPIO_SPI1_MOSI_OFF  _PIN_OFF(_GPIO_LPSPI1_MOSI)
-
-#define _GPIO_LPSPI3_SCK   /* GPIO_AD_B1_15 GPIO1_IO27 */  (GPIO_PORT1 | GPIO_PIN31 | CS_IOMUX)
-#define _GPIO_LPSPI3_MISO  /* GPIO_AD_B1_13 GPIO1_IO27 */  (GPIO_PORT1 | GPIO_PIN29 | CS_IOMUX)
-#define _GPIO_LPSPI3_MOSI  /* GPIO_AD_B1_14 GPIO1_IO27 */  (GPIO_PORT1 | GPIO_PIN30 | CS_IOMUX)
-
-#define GPIO_SPI3_SCK_OFF   _PIN_OFF(_GPIO_LPSPI3_SCK)
-#define GPIO_SPI3_MISO_OFF  _PIN_OFF(_GPIO_LPSPI3_MISO)
-#define GPIO_SPI3_MOSI_OFF  _PIN_OFF(_GPIO_LPSPI3_MOSI)
-
-/*  Define the SPI4 Data Ready and Control signals */
-
-#define GPIO_SPI4_DRDY7_EXTERNAL1   /* GPIO_EMC_35 GPIO3_IO21*/ (GPIO_PORT3 | GPIO_PIN21 | GPIO_INPUT  | DRDY_IOMUX)
-
-#define GPIO_DRDY_OFF_SPI4_DRDY7_EXTERNAL1   _PIN_OFF(GPIO_SPI4_DRDY7_EXTERNAL1)
-
-#define ADC_IOMUX (IOMUX_CMOS_INPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_HIZ)
-
-#define ADC1_CH(n)                  (n)
-#define ADC1_GPIO(n, p)             (GPIO_PORT1 | GPIO_PIN##p | ADC_IOMUX) //
-
-/* Define GPIO pins used as ADC N.B. Channel numbers are for reference, */
-
-#define PX4_ADC_GPIO  \
-	/* ADC_5V_RAIL_SENSE       GPIO_AD_B1_08 GPIO1 Pin 24 */  ADC1_GPIO(0,  24)
-
-/* Define Channel numbers must match above GPIO pin IN(n)*/
-
-#define ADC_5V_RAIL_SENSE        /* GPIO_AD_B1_08 GPIO1 Pin 24 */  ADC1_CH(13)
-
-#define ADC_CHANNELS 	         (1 << ADC_5V_RAIL_SENSE)
-
-/* Power supply control and monitoring GPIOs */
-
-#define GENERAL_INPUT_IOMUX  (IOMUX_CMOS_INPUT |  IOMUX_PULL_UP_47K | IOMUX_DRIVE_HIZ)
-#define GENERAL_OUTPUT_IOMUX (IOMUX_CMOS_OUTPUT | IOMUX_PULL_KEEP | IOMUX_DRIVE_33OHM  | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_FAST)
-
-
-/* PWM
- */
-
-#define DIRECT_PWM_OUTPUT_CHANNELS  8
-#define BOARD_NUM_IO_TIMERS         4
-
-// Input Capture not supported on MVP
-
-#define BOARD_HAS_NO_CAPTURE
-
-//#define BOARD_HAS_UI_LED_PWM           1  Not ported yet (Still Kinetis driver)
-#define BOARD_HAS_LED_PWM              1
-#define BOARD_LED_PWM_DRIVE_ACTIVE_LOW 1
-#define BOARD_HAS_CUSTOM_LED_PWM       1
-
-#define PWM_LED_RED    /* GPIO_EMC_33 */ (GPIO_FLEXPWM3_PWMA02_1 | GENERAL_OUTPUT_IOMUX)
-#define PWM_LED_BLUE   /* GPIO_EMC_34 */ (GPIO_FLEXPWM3_PWMB02_1 | GENERAL_OUTPUT_IOMUX)
-#define PWM_LED_GREEN  /* GPIO_EMC_38 */ (GPIO_FLEXPWM1_PWMA03_2 | GENERAL_OUTPUT_IOMUX)
-
-
-/* ETHERNET GPIO */
-
-#define GPIO_ENET_RX_ER_CONFIG1       /* GPIO_B1_11 GPIO2_IO27 PHYAD18        Open */  (GPIO_PORT2 | GPIO_PIN27 | GPIO_INPUT | IOMUX_PULL_NONE)
-#define GPIO_ENET_RX_DATA01_CONFIG4   /* GPIO_B1_05 GPIO2_IO21 (RMII-clkmode) High */  (GPIO_PORT2 | GPIO_PIN21 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | GENERAL_OUTPUT_IOMUX)
-#define GPIO_ENET_RX_DATA00_CONFIG5   /* GPIO_B1_04 GPIO2_IO20 SLAVE:Auto     Open */  (GPIO_PORT2 | GPIO_PIN20 | GPIO_INPUT  | IOMUX_PULL_NONE)
-#define GPIO_ENET_CRS_DV_CONFIG6      /* GPIO_B1_06 GPIO4_IO22 SLAVE:POl Corr Low  */  (GPIO_PORT2 | GPIO_PIN22 | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GENERAL_OUTPUT_IOMUX)
-
-/* Tone alarm output */
-
-//FIXME FlexPWM TONE DRIVER
-#define TONE_ALARM_FLEXPWM      PWMA_VAL
-#define TONE_ALARM_TIMER        1  /* FlexPWM 3 */
-#define TONE_ALARM_CHANNEL      0  /* GPIO_EMC_23 PWM1_PWMA00 */
-
-#define GPIO_BUZZER_1           /* GPIO_EMC_23  GPIO4_IO23  */ (GPIO_PORT4 | GPIO_PIN23  | GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GENERAL_OUTPUT_IOMUX)
-
-#define GPIO_TONE_ALARM_IDLE    GPIO_BUZZER_1
-#define GPIO_TONE_ALARM         (GPIO_FLEXPWM1_PWMA00_1 | GENERAL_OUTPUT_IOMUX)
-
-/* USB OTG FS
- *
- * VBUS_VALID is detected in USB_ANALOG_USB1_VBUS_DETECT_STAT
- */
-
-/* High-resolution timer */
-#define HRT_TIMER               1  /* use GPT1 for the HRT */
-#define HRT_TIMER_CHANNEL       1  /* use capture/compare channel 1 */
-
-#define RC_SERIAL_PORT                  "/dev/ttyS6"
-//#define RC_SERIAL_SINGLEWIRE            1 // Suport Single wire wiring
-//#define RC_SERIAL_SWAP_RXTX             1 // Set Swap (but not supported in HW) to use Single wire
-//#define RC_SERIAL_SWAP_USING_SINGLEWIRE 1 // Set to use Single wire swap as HW does not support swap
-#define BOARD_SUPPORTS_RC_SERIAL_PORT_OUTPUT
-
-/* Safety Switch is HW version dependent on having an PX4IO
- * So we init to a benign state with the _INIT definition
- * and provide the the non _INIT one for the driver to make a run time
- * decision to use it.
- */
-#define SAFETY_INIT_IOMUX (IOMUX_CMOS_INPUT  | IOMUX_PULL_NONE | IOMUX_DRIVE_HIZ)
-#define SAFETY_IOMUX      (IOMUX_CMOS_OUTPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_33OHM  | IOMUX_SPEED_MEDIUM | IOMUX_SLEW_SLOW)
-#define SAFETY_SW_IOMUX   (IOMUX_CMOS_INPUT  | IOMUX_PULL_UP_22K | IOMUX_DRIVE_HIZ)
-
-/* Safety Switch is HW version dependent on having an PX4IO
- * So we init to a benign state with the _INIT definition
- * and provide the the non _INIT one for the driver to make a run time
- * decision to use it.
- */
-#define GPIO_nSAFETY_SWITCH_LED_OUT_INIT   /* EMC_39 */ (GPIO_PORT3 | GPIO_PIN25 | GPIO_INPUT  | SAFETY_INIT_IOMUX)
-#define GPIO_nSAFETY_SWITCH_LED_OUT        /* EMC_39 */ (GPIO_PORT3 | GPIO_PIN25 | GPIO_OUTPUT | GPIO_OUTPUT_ONE | SAFETY_IOMUX)
-
-/* Enable the FMU to control it if there is no px4io fixme:This should be BOARD_SAFETY_LED(__ontrue) */
-#define GPIO_LED_SAFETY GPIO_nSAFETY_SWITCH_LED_OUT
-
-#define GPIO_SAFETY_SWITCH_IN              /* GPIO_B0_12 GPIO2_IO12 */ (GPIO_PORT2 | GPIO_PIN12 | GPIO_INPUT | SAFETY_SW_IOMUX)
-/* Enable the FMU to use the switch it if there is no px4io fixme:This should be BOARD_SAFTY_BUTTON() */
-#define GPIO_BTN_SAFETY GPIO_SAFETY_SWITCH_IN /* Enable the FMU to control it if there is no px4io */
-
-#define SDIO_SLOTNO                    0  /* Only one slot */
-#define SDIO_MINOR                     0
-
-/* SD card bringup does not work if performed on the IDLE thread because it
- * will cause waiting.  Use either:
- *
- *  CONFIG_BOARDCTL=y, OR
- *  CONFIG_BOARD_INITIALIZE=y && CONFIG_BOARD_INITTHREAD=y
- */
-
-#if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_BOARDCTL) && \
-   !defined(CONFIG_BOARD_INITTHREAD)
-#  warning SDIO initialization cannot be perfomed on the IDLE thread
-#endif
-
-/* By Providing BOARD_ADC_USB_CONNECTED (using the px4_arch abstraction)
- * this board support the ADC system_power interface, and therefore
- * provides the true logic GPIO BOARD_ADC_xxxx macros.
- */
-
-#define BOARD_NUMBER_BRICKS 1
-#define BOARD_NUMBER_DIGITAL_BRICKS     1
-
-#define BOARD_ADC_BRICK_VALID   1
-
-#define BOARD_ADC_USB_CONNECTED (board_read_VBUS_state() == 0)
-
-/* FMUv5 never powers odd the Servo rail */
-
-#define BOARD_ADC_SERVO_VALID     (1)
-
-
-/* This board provides a DMA pool and APIs */
-#define BOARD_DMA_ALLOC_POOL_SIZE 5120
-
-/* This board provides the board_on_reset interface */
-
-#define BOARD_HAS_ON_RESET 1
-#define BOARD_HAS_ISP_BOOTLOADER 1
-
-#define PX4_GPIO_INIT_LIST { \
-		GPIO_FLEXCAN3_TX,                 \
-		GPIO_FLEXCAN3_RX,                 \
-		GPIO_TONE_ALARM_IDLE,             \
-		GPIO_SAFETY_SWITCH_IN,            \
-		GPIO_ENET_RX_ER_CONFIG1,          \
-		GPIO_ENET_RX_DATA01_CONFIG4,      \
-		GPIO_ENET_RX_DATA00_CONFIG5,      \
-		GPIO_ENET_CRS_DV_CONFIG6,         \
-		GPIO_ENET_RST                     \
-	}
-
-#define BOARD_ENABLE_CONSOLE_BUFFER
-
-/* To detect IMU */
-#define BOARD_HAS_HW_VERSIONING  1
-#define BOARD_HAS_HW_SPLIT_VERSIONING 1
-#define HW_INFO_INIT_PREFIX    "TROPIC"
-
-#define BOARD_NUM_SPI_CFG_HW_VERSIONS 3
-//                 Base/FMUM
-#define TROPIC_0   HW_FMUM_ID(0x0) // ICM45686
-#define TROPIC_1   HW_FMUM_ID(0x1) // ICM42688
-#define TROPIC_2   HW_FMUM_ID(0x2) // ICM42686
-
-/* Flash instance for storage */
-#define NOR_INSTANCE      1
-
-__BEGIN_DECLS
-
-/****************************************************************************************************
- * Public Types
- ****************************************************************************************************/
-
-/****************************************************************************************************
- * Public data
- ****************************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************************************
- * Public Functions
- ****************************************************************************************************/
-
-/****************************************************************************
- * Name: fmurt1062_usdhc_initialize
- *
- * Description:
- *   Initialize SDIO-based MMC/SD card support
- *
- ****************************************************************************/
-
-int fmurt1062_usdhc_initialize(void);
-
-/****************************************************************************************************
- * Name: imxrt_spidev_initialize
- *
- * Description:
- *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
- *
- ****************************************************************************************************/
-
-extern void imxrt_spidev_initialize(void);
-
-/************************************************************************************
- * Name: imxrt_spi_bus_initialize
- *
- * Description:
- *   Called to configure SPI Buses.
- *
- ************************************************************************************/
-
-extern int imxrt1062_spi_bus_initialize(void);
-
-/************************************************************************************
- * Name: imxrt_usb_initialize
- *
- * Description:
- *   Called to configure USB.
- *
- ************************************************************************************/
-
-extern void imxrt_spiinitialize(void);
-
-extern int imxrt_usb_initialize(void);
-
-extern void imxrt_usbinitialize(void);
-
-extern void board_peripheral_reset(int ms);
-
-extern void fmurt1062_timer_initialize(void);
-
-#include <px4_platform_common/board_common.h>
-
-void imxrt_flash_romapi_initialize(void);
-
-int imxrt_flexspi_storage_initialize(void);
-
-#endif /* __ASSEMBLY__ */
-
-__END_DECLS
@@ -1,165 +0,0 @@
-/****************************************************************************
- *
- *   Copyright (C) 2023 PX4 Development Team. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name PX4 nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/**
- * @file hw_rev_ver_canhubk3.c
- * CANHUBK3 Hardware Revision and Version ID API
- */
-#include <drivers/drv_adc.h>
-#include <px4_arch/adc.h>
-#include <px4_platform_common/micro_hal.h>
-#include <px4_platform_common/px4_config.h>
-#include <px4_platform/board_determine_hw_info.h>
-#include <stdio.h>
-#include <board_config.h>
-#include <drivers/drv_sensor.h>
-
-#include <systemlib/px4_macros.h>
-
-#include <nuttx/spi/spi.h>
-
-#if defined(BOARD_HAS_HW_VERSIONING)
-
-#define HW_INFO_SIZE HW_INFO_VER_DIGITS + HW_INFO_REV_DIGITS
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-static int hw_revision = 0;
-static char hw_info[HW_INFO_SIZE] = {0};
-#if defined(BOARD_HAS_HW_SPLIT_VERSIONING)
-static char hw_base_info[HW_INFO_SIZE] = {0};
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-/************************************************************************************
- * Name: board_get_hw_type
- *
- * Description:
- *   Optional returns a 0 terminated string defining the HW type.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   a 0 terminated string defining the HW type. This my be a 0 length string ""
- *
- ************************************************************************************/
-
-__EXPORT const char *board_get_hw_type_name()
-{
-	return (const char *) hw_info;
-}
-
-#if defined(BOARD_HAS_HW_SPLIT_VERSIONING)
-/************************************************************************************
- * Name: board_get_hw_base_type_name
- *
- * Description:
- *   Optional returns a 0 terminated string defining the base type.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   a 0 terminated string defining the HW type. This my be a 0 length string ""
- *
- ************************************************************************************/
-
-__EXPORT const char *board_get_hw_base_type_name()
-{
-	return (const char *) hw_base_info;
-}
-#endif
-
-/************************************************************************************
- * Name: board_get_hw_version
- *
- * Description:
- *   Optional returns a integer HW version
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   An integer value of this boards hardware version.
- *   A value of -1 is the default for boards not supporting the BOARD_HAS_VERSIONING API.
- *   A value of 0 is the default for boards supporting the API but not having version.
- *
- ************************************************************************************/
-
-__EXPORT int board_get_hw_version()
-{
-	return 0;
-}
-
-/************************************************************************************
- * Name: board_get_hw_revision
- *
- * Description:
- *   Optional returns a integer HW revision
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   An integer value of this boards hardware revision.
- *   A value of -1 is the default for boards not supporting the BOARD_HAS_VERSIONING API.
- *   A value of 0 is the default for boards supporting the API but not having revision.
- *
- ************************************************************************************/
-
-__EXPORT int board_get_hw_revision()
-{
-	return hw_revision;
-}
-
-/************************************************************************************
-  * Name: board_determine_hw_info
- *
- * Description:
- *	Uses GPIO to detect MR-CANHUBK3-ADAP
- *
- ************************************************************************************/
-
-int board_determine_hw_info()
-{
-	hw_revision = 0; //TODO Read fuses
-
-	sprintf(hw_info, "%03d", hw_revision);
-
-	return 0;
-}
-#endif
@@ -1,55 +0,0 @@
-/****************************************************************************
- * boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_boot.c
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "imxrt_flexspi_nor_boot.h"
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-locate_data(".boot_hdr.ivt")
-const struct ivt_s g_image_vector_table = {
-	IVT_HEADER,                         /* IVT Header */
-	IMAGE_ENTRY_ADDRESS,                /* Image  Entry Function */
-	IVT_RSVD,                           /* Reserved = 0 */
-	(uint32_t)DCD_ADDRESS,              /* Address where DCD information is stored */
-	(uint32_t)BOOT_DATA_ADDRESS,        /* Address where BOOT Data Structure is stored */
-	(uint32_t)IMAG_VECTOR_TABLE,        /* Pointer to IVT Self (absolute address */
-	(uint32_t)CSF_ADDRESS,              /* Address where CSF file is stored */
-	IVT_RSVD                            /* Reserved = 0 */
-};
-
-locate_data(".boot_hdr.boot_data")
-const struct boot_data_s g_boot_data = {
-	IMAGE_DEST,                         /* boot start location */
-	(IMAGE_DEST_END - IMAGE_DEST),      /* size */
-	PLUGIN_FLAG,                        /* Plugin flag */
-	0xffffffff                          /* empty - extra data word */
-};
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/* None */
@@ -1,166 +0,0 @@
-/****************************************************************************
- * boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_boot.h
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __BOARDS_ARM_IMXRT_IMXRT1060_EVK_SRC_IMXRT_FLEXSPI_NOR_BOOT_H
-#define __BOARDS_ARM_IMXRT_IMXRT1060_EVK_SRC_IMXRT_FLEXSPI_NOR_BOOT_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <stdint.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* IVT Data */
-
-#define IVT_MAJOR_VERSION           0x4
-#define IVT_MAJOR_VERSION_SHIFT     0x4
-#define IVT_MAJOR_VERSION_MASK      0xf
-#define IVT_MINOR_VERSION           0x1
-#define IVT_MINOR_VERSION_SHIFT     0x0
-#define IVT_MINOR_VERSION_MASK      0xf
-
-#define IVT_VERSION(major, minor)   \
-	((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) |  \
-	 (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
-
-#define IVT_TAG_HEADER              (0xd1)       /* Image Vector Table */
-#define IVT_SIZE                    0x2000
-#define IVT_PAR                     IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
-
-#define IVT_HEADER                  (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
-#define IVT_RSVD                    (uint32_t)(0x00000000)
-
-/* DCD Data */
-
-#define DCD_TAG_HEADER              (0xd2)
-#define DCD_TAG_HEADER_SHIFT        (24)
-#define DCD_VERSION                 (0x40)
-#define DCD_ARRAY_SIZE              1
-
-#define FLASH_BASE                  0x70000000
-#define FLASH_END                   0x70400000
-
-/* This needs to take into account  the memory configuration at boot
- * bootloader
- */
-
-#define ROM_BOOTLOADER_OCRAM_RES    0x8000
-#define OCRAM_BASE                  (0x20200000 + ROM_BOOTLOADER_OCRAM_RES)
-#define OCRAM_END                   (OCRAM_BASE + (512 * 1024) + (256 * 1024) \
-				     - ROM_BOOTLOADER_OCRAM_RES)
-
-#define SCLK 1
-#if defined(CONFIG_BOOT_RUNFROMFLASH)
-#  define IMAGE_DEST                FLASH_BASE
-#  define IMAGE_DEST_END            FLASH_END
-#  define IMAGE_DEST_OFFSET         0
-#else
-#  define IMAGE_DEST                OCRAM_BASE
-#  define IMAGE_DEST_END            OCRAM_END
-#  define IMAGE_DEST_OFFSET         IVT_SIZE
-#endif
-
-#define LOCATE_IN_DEST(x)           (((uint32_t)(x)) - FLASH_BASE + IMAGE_DEST)
-#define LOCATE_IN_SRC(x)            (((uint32_t)(x)) - IMAGE_DEST + FLASH_BASE)
-
-#ifdef CONFIG_IMXRT1064_EVK_SDRAM
-#  define DCD_ADDRESS               &g_dcd_data
-#else
-#  define DCD_ADDRESS               0
-#endif
-#define BOOT_DATA_ADDRESS           LOCATE_IN_DEST(&g_boot_data)
-#define CSF_ADDRESS                 0
-#define PLUGIN_FLAG                 (uint32_t)0
-
-/* Located in Destination Memory */
-
-#define IMAGE_ENTRY_ADDRESS        ((uint32_t)&_vectors)
-#define IMAG_VECTOR_TABLE           LOCATE_IN_DEST(&g_image_vector_table)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/* IVT Data */
-
-struct ivt_s {
-	/* Header with tag #HAB_TAG_IVT, length and HAB version fields
-	 * (see data)
-	 */
-
-	uint32_t hdr;
-
-	/* Absolute address of the first instruction to execute from the
-	 * image
-	 */
-
-	uint32_t entry;
-
-	/* Reserved in this version of HAB: should be NULL. */
-
-	uint32_t reserved1;
-
-	/* Absolute address of the image DCD: may be NULL. */
-
-	uint32_t dcd;
-
-	/* Absolute address of the Boot Data: may be NULL, but not interpreted
-	 * any further by HAB
-	 */
-
-	uint32_t boot_data;
-
-	/* Absolute address of the IVT. */
-
-	uint32_t self;
-
-	/* Absolute address of the image CSF. */
-
-	uint32_t csf;
-
-	/* Reserved in this version of HAB: should be zero. */
-
-	uint32_t reserved2;
-};
-
-/* Boot Data */
-
-struct boot_data_s {
-	uint32_t start;           /* boot start location */
-	uint32_t size;            /* size */
-	uint32_t plugin;          /* plugin flag - 1 if downloaded application is plugin */
-	uint32_t placeholder;     /* placeholder to make even 0x10 size */
-};
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-extern const struct boot_data_s g_boot_data;
-#ifdef CONFIG_IMXRT1064_EVK_SDRAM
-extern const uint8_t g_dcd_data[];
-#endif
-extern  const uint32_t  _vectors[];
-
-#endif /* __BOARDS_ARM_IMXRT_IMXRT1060_EVK_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */
@@ -1,107 +0,0 @@
-/****************************************************************************
- * boards/arm/imxrt/teensy-4.x/src/imxrt_flexspi_nor_flash.c
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "imxrt_flexspi_nor_flash.h"
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-enum {
-	/* SPI instructions */
-
-	READ_FAST = 0,
-	READ_STATUS_REG = 1,
-	WRITE_ENABLE = 3,
-	SECTOR_ERASE_4K = 5,
-	READ_FAST_QUAD_OUTPUT = 6,
-	PAGE_PROGRAM_QUAD_INPUT = 7,
-	ERASE_BLOCK = 8,
-	PAGE_PROGRAM = 9,
-	CHIP_ERASE = 11,
-};
-
-locate_data(".boot_hdr.conf")
-const struct flexspi_nor_config_s g_flash_config = {
-	.mem_config =
-	{
-		.tag                    = FLEXSPI_CFG_BLK_TAG,
-		.version                = FLEXSPI_CFG_BLK_VERSION,
-		.read_sample_clksrc     = FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD,
-		.cs_hold_time           = 3u,
-		.cs_setup_time          = 3u,
-		.column_address_width   = 0u,
-		.device_type            = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
-		.sflash_pad_type        = SERIAL_FLASH_4PADS,
-		.serial_clk_freq        = FLEXSPI_SERIAL_CLKFREQ_133MHz,
-		.sflash_a1size          = 4u * 1024u * 1024u,
-		.lookup_table           =
-		{
-			[4 * READ_FAST] =       FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xeb,
-								RADDR_SDR, FLEXSPI_4PAD, 0x18),
-			[4 * READ_FAST + 1] =   FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06,
-								READ_SDR,  FLEXSPI_4PAD, 0x04),
-
-			[4 * READ_STATUS_REG] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05,
-								READ_SDR,  FLEXSPI_1PAD, 0x04),
-
-			[4 * WRITE_ENABLE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06,
-							     STOP, FLEXSPI_1PAD, 0),
-
-			[4 * SECTOR_ERASE_4K] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20,
-								RADDR_SDR, FLEXSPI_1PAD, 0x18),
-
-			[4 * CHIP_ERASE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60,
-							   STOP, FLEXSPI_1PAD, 0),
-
-			[4 * ERASE_BLOCK] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xd8,
-							    RADDR_SDR, FLEXSPI_1PAD, 0x18),
-
-			[4 * PAGE_PROGRAM] =     FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x02,
-					RADDR_SDR, FLEXSPI_1PAD, 0x18),
-			[4 * PAGE_PROGRAM + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04,
-					STOP,      FLEXSPI_1PAD, 0x0),
-
-			[4 * READ_FAST_QUAD_OUTPUT] =     FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6b,
-					RADDR_SDR, FLEXSPI_1PAD, 0x18),
-			[4 * READ_FAST_QUAD_OUTPUT + 1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08,
-					READ_SDR,  FLEXSPI_4PAD, 0x04),
-
-			[4 * PAGE_PROGRAM_QUAD_INPUT] =     FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32,
-					RADDR_SDR, FLEXSPI_1PAD, 0x18),
-			[4 * PAGE_PROGRAM_QUAD_INPUT + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04,
-					STOP,      FLEXSPI_1PAD, 0),
-
-		},
-	},
-
-	.page_size = 256u,
-	.sector_size = 4u * 1024u,
-	.blocksize = 64u * 1024u,
-	.is_uniform_blocksize = false,
-};
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
@@ -1,349 +0,0 @@
-/****************************************************************************
- * boards/arm/imxrt/imxrt1064-evk/src/imxrt_flexspi_nor_flash.h
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __BOARDS_ARM_IMXRT_IMXRT1064_EVK_SRC_IMXRT_FLEXSPI_NOR_FLASH_H
-#define __BOARDS_ARM_IMXRT_IMXRT1064_EVK_SRC_IMXRT_FLEXSPI_NOR_FLASH_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <stdint.h>
-#include <stdbool.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* FLEXSPI memory config block related definitions */
-
-#define FLEXSPI_CFG_BLK_TAG         (0x42464346ul)
-#define FLEXSPI_CFG_BLK_VERSION     (0x56010400ul)
-#define FLEXSPI_CFG_BLK_SIZE        (512)
-
-/* FLEXSPI Feature related definitions */
-
-#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
-
-/* Lookup table related definitions */
-
-#define CMD_INDEX_READ              0
-#define CMD_INDEX_READSTATUS        1
-#define CMD_INDEX_WRITEENABLE       2
-#define CMD_INDEX_WRITE             4
-
-#define CMD_LUT_SEQ_IDX_READ        0
-#define CMD_LUT_SEQ_IDX_READSTATUS  1
-#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
-#define CMD_LUT_SEQ_IDX_WRITE       9
-
-#define CMD_SDR                     0x01
-#define CMD_DDR                     0x21
-#define RADDR_SDR                   0x02
-#define RADDR_DDR                   0x22
-#define CADDR_SDR                   0x03
-#define CADDR_DDR                   0x23
-#define MODE1_SDR                   0x04
-#define MODE1_DDR                   0x24
-#define MODE2_SDR                   0x05
-#define MODE2_DDR                   0x25
-#define MODE4_SDR                   0x06
-#define MODE4_DDR                   0x26
-#define MODE8_SDR                   0x07
-#define MODE8_DDR                   0x27
-#define WRITE_SDR                   0x08
-#define WRITE_DDR                   0x28
-#define READ_SDR                    0x09
-#define READ_DDR                    0x29
-#define LEARN_SDR                   0x0a
-#define LEARN_DDR                   0x2a
-#define DATSZ_SDR                   0x0b
-#define DATSZ_DDR                   0x2b
-#define DUMMY_SDR                   0x0c
-#define DUMMY_DDR                   0x2c
-#define DUMMY_RWDS_SDR              0x0d
-#define DUMMY_RWDS_DDR              0x2d
-#define JMP_ON_CS                   0x1f
-#define STOP                        0
-
-#define FLEXSPI_1PAD                0
-#define FLEXSPI_2PAD                1
-#define FLEXSPI_4PAD                2
-#define FLEXSPI_8PAD                3
-
-#define FLEXSPI_LUT_OPERAND0_MASK   (0xffu)
-#define FLEXSPI_LUT_OPERAND0_SHIFT  (0U)
-#define FLEXSPI_LUT_OPERAND0(x)     (((uint32_t) \
-				      (((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & \
-				     FLEXSPI_LUT_OPERAND0_MASK)
-#define FLEXSPI_LUT_NUM_PADS0_MASK  (0x300u)
-#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8u)
-#define FLEXSPI_LUT_NUM_PADS0(x)    (((uint32_t) \
-				      (((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & \
-				     FLEXSPI_LUT_NUM_PADS0_MASK)
-#define FLEXSPI_LUT_OPCODE0_MASK    (0xfc00u)
-#define FLEXSPI_LUT_OPCODE0_SHIFT   (10u)
-#define FLEXSPI_LUT_OPCODE0(x)      (((uint32_t) \
-				      (((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & \
-				     FLEXSPI_LUT_OPCODE0_MASK)
-#define FLEXSPI_LUT_OPERAND1_MASK   (0xff0000u)
-#define FLEXSPI_LUT_OPERAND1_SHIFT  (16U)
-#define FLEXSPI_LUT_OPERAND1(x)     (((uint32_t) \
-				      (((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & \
-				     FLEXSPI_LUT_OPERAND1_MASK)
-#define FLEXSPI_LUT_NUM_PADS1_MASK  (0x3000000u)
-#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24u)
-#define FLEXSPI_LUT_NUM_PADS1(x)    (((uint32_t) \
-				      (((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & \
-				     FLEXSPI_LUT_NUM_PADS1_MASK)
-#define FLEXSPI_LUT_OPCODE1_MASK    (0xfc000000u)
-#define FLEXSPI_LUT_OPCODE1_SHIFT   (26u)
-#define FLEXSPI_LUT_OPCODE1(x)      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & \
-				     FLEXSPI_LUT_OPCODE1_MASK)
-
-#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)  \
-	(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \
-	 FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
-	 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
-
-/*  */
-
-#define NOR_CMD_INDEX_READ          CMD_INDEX_READ
-#define NOR_CMD_INDEX_READSTATUS    CMD_INDEX_READSTATUS
-#define NOR_CMD_INDEX_WRITEENABLE   CMD_INDEX_WRITEENABLE
-#define NOR_CMD_INDEX_ERASESECTOR   3
-#define NOR_CMD_INDEX_PAGEPROGRAM   CMD_INDEX_WRITE
-#define NOR_CMD_INDEX_CHIPERASE     5
-#define NOR_CMD_INDEX_DUMMY         6
-#define NOR_CMD_INDEX_ERASEBLOCK    7
-
-/*  READ LUT sequence id in lookupTable stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_READ    CMD_LUT_SEQ_IDX_READ
-
-/* Read Status LUT sequence id in lookupTable stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
-
-/* 2  Read status DPI/QPI/OPI sequence id in LUT stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2
-
-/* 3  Write Enable sequence id in lookupTable stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
-
-/* 4  Write Enable DPI/QPI/OPI sequence id in LUT stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
-
-/* 5  Erase Sector sequence id in lookupTable stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
-
-/* 8 Erase Block sequence id in lookupTable stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
-
-/* 9  Program sequence id in lookupTable stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
-
-/* 11 Chip Erase sequence in lookupTable id stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
-
-/* 13 Read SFDP sequence in lookupTable id stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
-
-/* 14 Restore 0-4-4/0-8-8 mode sequence id in LUT stored in config block */
-
-#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
-
-/* 15 Exit 0-4-4/0-8-8 mode sequence id in LUT stored in config blobk */
-
-#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/* Definitions for FlexSPI Serial Clock Frequency */
-
-enum flexspi_serial_clkfreq_e {
-	FLEXSPI_SERIAL_CLKFREQ_30MHz  = 1,
-	FLEXSPI_SERIAL_CLKFREQ_50MHz  = 2,
-	FLEXSPI_SERIAL_CLKFREQ_60MHz  = 3,
-	FLEXSPI_SERIAL_CLKFREQ_75MHz  = 4,
-	FLEXSPI_SERIAL_CLKFREQ_80MHz  = 5,
-	FLEXSPI_SERIAL_CLKFREQ_100MHz = 6,
-	FLEXSPI_SERIAL_CLKFREQ_120MHz = 7,
-	FLEXSPI_SERIAL_CLKFREQ_133MHz = 8,
-	FLEXSPI_SERIAL_CLKFREQ_166MHz = 9,
-};
-
-/* FlexSPI clock configuration type */
-
-enum flexspi_serial_clockmode_e {
-	FLEXSPI_CLKMODE_SDR,
-	FLEXSPI_CLKMODE_DDR,
-};
-
-/* FlexSPI Read Sample Clock Source definition */
-
-enum flash_read_sample_clk_e {
-	FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY = 0,
-	FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD = 1,
-	FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD = 2,
-	FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD = 3,
-};
-
-/*  Misc feature bit definitions */
-
-enum flash_misc_feature_e {
-	FLEXSPIMISC_OFFSET_DIFFCLKEN = 0,                /* Bit for Differential clock enable */
-	FLEXSPIMISC_OFFSET_CK2EN = 1,                    /* Bit for CK2 enable */
-	FLEXSPIMISC_OFFSET_PARALLELEN = 2,               /* Bit for Parallel mode enable */
-	FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3,      /* Bit for Word Addressable enable */
-	FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4,       /* Bit for Safe Configuration Frequency enable */
-	FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5,  /* Bit for Pad setting override enable */
-	FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6,              /* Bit for DDR clock confiuration indication. */
-};
-
-/* Flash Type Definition */
-
-enum flash_flash_type_e {
-	FLEXSPI_DEVICE_TYPE_SERIAL_NOR = 1,              /* Flash devices are Serial NOR */
-	FLEXSPI_DEVICE_TYPE_SERIAL_NAND = 2,             /* Flash devices are Serial NAND */
-	FLEXSPI_DEVICE_TYPE_SERIAL_RAM = 3,              /* Flash devices are Serial RAM/HyperFLASH */
-	FLEXSPI_DEVICE_TYPE_MCP_NOR_NAND = 0x12,         /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */
-	FLEXSPI_DEVICE_TYPE_MCP_NOR_RAM = 0x13,          /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */
-};
-
-/* Flash Pad Definitions */
-
-enum flash_flash_pad_e {
-	SERIAL_FLASH_1PAD  = 1,
-	SERIAL_FLASH_2PADS = 2,
-	SERIAL_FLASH_4PADS = 4,
-	SERIAL_FLASH_8PADS = 8,
-};
-
-/* Flash Configuration Command Type */
-
-enum flash_config_cmd_e {
-	DEVICE_CONFIG_CMD_TYPE_GENERIC,     /* Generic command, for example: configure dummy cycles, drive strength, etc */
-	DEVICE_CONFIG_CMD_TYPE_QUADENABLE,  /* Quad Enable command */
-	DEVICE_CONFIG_CMD_TYPE_SPI2XPI,     /* Switch from SPI to DPI/QPI/OPI mode */
-	DEVICE_CONFIG_CMD_TYPE_XPI2SPI,     /* Switch from DPI/QPI/OPI to SPI mode */
-	DEVICE_CONFIG_CMD_TYPE_SPI2NO_CMD,  /* Switch to 0-4-4/0-8-8 mode */
-	DEVICE_CONFIG_CMD_TYPE_RESET,       /* Reset device command */
-};
-
-/* FlexSPI LUT Sequence structure */
-
-struct flexspi_lut_seq_s {
-	uint8_t seq_num;                    /* Sequence Number, valid number: 1-16 */
-	uint8_t seq_id;                     /* Sequence Index, valid number: 0-15 */
-	uint16_t reserved;
-};
-
-/* FlexSPI Memory Configuration Block */
-
-struct flexspi_mem_config_s {
-	uint32_t tag;
-	uint32_t version;
-	uint32_t reserved0;
-	uint8_t read_sample_clksrc;
-	uint8_t cs_hold_time;
-	uint8_t cs_setup_time;
-	uint8_t column_address_width;     /* [0x00f-0x00f] Column Address with, for
-                                     * HyperBus protocol, it is fixed to 3,
-                                     * For Serial NAND, need to refer to
-                                     * datasheet
-                                     */
-	uint8_t device_mode_cfg_enable;
-	uint8_t device_mode_type;
-	uint16_t wait_time_cfg_commands;
-	struct flexspi_lut_seq_s device_mode_seq;
-	uint32_t device_mode_arg;
-	uint8_t config_cmd_enable;
-	uint8_t config_mode_type[3];
-	struct flexspi_lut_seq_s config_cmd_seqs[3];
-	uint32_t reserved1;
-	uint32_t config_cmd_args[3];
-	uint32_t reserved2;
-	uint32_t controller_misc_option;
-	uint8_t device_type;
-	uint8_t sflash_pad_type;
-	uint8_t serial_clk_freq;
-	uint8_t lut_custom_seq_enable;
-	uint32_t reserved3[2];
-	uint32_t sflash_a1size;
-	uint32_t sflash_a2size;
-	uint32_t sflash_b1size;
-	uint32_t sflash_b2size;
-	uint32_t cspad_setting_override;
-	uint32_t sclkpad_setting_override;
-	uint32_t datapad_setting_override;
-	uint32_t dqspad_setting_override;
-	uint32_t timeout_in_ms;
-	uint32_t command_interval;
-	uint16_t data_valid_time[2];
-	uint16_t busy_offset;
-	uint16_t busybit_polarity;
-	uint32_t lookup_table[64];
-	struct flexspi_lut_seq_s lut_customseq[12];
-	uint32_t reserved4[4];
-};
-
-/* Serial NOR configuration block */
-
-struct flexspi_nor_config_s {
-	struct flexspi_mem_config_s mem_config; /* Common memory configuration info
-                                           * via FlexSPI
-                                           */
-
-	uint32_t page_size;                  /* Page size of Serial NOR */
-	uint32_t sector_size;                /* Sector size of Serial NOR */
-	uint8_t ipcmd_serial_clkfreq;        /* Clock frequency for IP command */
-	uint8_t is_uniform_blocksize;        /* Sector/Block size is the same */
-	uint8_t reserved0[2];                /* Reserved for future use */
-	uint8_t serial_nor_type;             /* Serial NOR Flash type: 0/1/2/3 */
-	uint8_t need_exit_nocmdmode;         /* Need to exit NoCmd mode before
-                                        * other IP command
-                                        */
-
-	uint8_t halfclk_for_nonreadcmd;      /* Half the Serial Clock for non-read
-                                        * command: true/false
-                                        */
-
-	uint8_t need_restore_nocmdmode;      /* Need to Restore NoCmd mode after IP
-                                        * command execution
-                                        */
-
-	uint32_t blocksize;                  /* Block size */
-	uint32_t reserve2[11];               /* Reserved for future use */
-};
-
-extern const struct flexspi_nor_config_s g_flash_config;
-
-#endif /* __BOARDS_ARM_IMXRT_IMXRT1064_EVK_SRC_IMXRT_FLEXSPI_NOR_FLASH_H */
@@ -1,411 +0,0 @@
-/****************************************************************************
- * boards/nxp/mr-tropic/src/imxrt_flexspi_storage.c
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdbool.h>
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/kmalloc.h>
-#include <nuttx/signal.h>
-#include <nuttx/fs/fs.h>
-#include <nuttx/mtd/mtd.h>
-
-#include <px4_platform_common/px4_mtd.h>
-#include "px4_log.h"
-
-#include <px4_arch/imxrt_flexspi_nor_flash.h>
-#include <px4_arch/imxrt_romapi.h>
-#include "board_config.h"
-#include "hardware/imxrt_pinmux.h"
-#include "barriers.h"
-
-/* Used sectors must be multiple of the flash block size
- * i.e. W25Q32JV has a block size of 64KB
-*/
-
-#define NOR_USED_SECTORS  (0x40U)   /* 64 * 4KB = 256KB */
-#define NOR_TOTAL_SECTORS (0x0400U)
-#define NOR_PAGE_SIZE     (0x0100U) /* 256 bytes */
-#define NOR_SECTOR_SIZE   (0x1000U) /* 4KB */
-#define NOR_START_SECTOR  (NOR_TOTAL_SECTORS - NOR_USED_SECTORS)
-#define NOR_START_PAGE    ((NOR_START_SECTOR * NOR_SECTOR_SIZE) / NOR_PAGE_SIZE)
-#define NOR_STORAGE_ADDR  (IMXRT_FLEX2CIPHER_BASE + NOR_START_SECTOR * NOR_SECTOR_SIZE)
-#define NOR_STORAGE_END   (IMXRT_FLEX2CIPHER_BASE + (NOR_START_SECTOR + NOR_TOTAL_SECTORS) * NOR_SECTOR_SIZE)
-
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-
-extern struct flexspi_nor_config_s g_bootConfig;
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/* FlexSPI NOR device private data */
-
-struct imxrt_flexspi_storage_dev_s {
-	struct mtd_dev_s mtd;
-	uint8_t *ahb_base;
-};
-
-/****************************************************************************
- * Private Functions Prototypes
- ****************************************************************************/
-
-/* MTD driver methods */
-
-static int imxrt_flexspi_storage_erase(struct mtd_dev_s *dev,
-				       off_t startblock,
-				       size_t nblocks);
-static ssize_t imxrt_flexspi_storage_read(struct mtd_dev_s *dev,
-		off_t offset,
-		size_t nbytes,
-		uint8_t *buffer);
-static ssize_t imxrt_flexspi_storage_bread(struct mtd_dev_s *dev,
-		off_t startblock,
-		size_t nblocks,
-		uint8_t *buffer);
-static ssize_t imxrt_flexspi_storage_bwrite(struct mtd_dev_s *dev,
-		off_t startblock,
-		size_t nblocks,
-		const uint8_t *buffer);
-static int imxrt_flexspi_storage_ioctl(struct mtd_dev_s *dev,
-				       int cmd,
-				       unsigned long arg);
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-static struct imxrt_flexspi_storage_dev_s g_flexspi_nor = {
-	.mtd =
-	{
-		.erase  = imxrt_flexspi_storage_erase,
-		.bread  = imxrt_flexspi_storage_bread,
-		.bwrite = imxrt_flexspi_storage_bwrite,
-		.read   = imxrt_flexspi_storage_read,
-		.ioctl  = imxrt_flexspi_storage_ioctl,
-#ifdef CONFIG_MTD_BYTE_WRITE
-		.write  = NULL,
-#endif
-		.name   = "imxrt_flexspi_storage"
-	},
-	.ahb_base = (uint8_t *) NOR_STORAGE_ADDR,
-};
-
-/* Ensure exclusive access to the driver */
-
-static sem_t g_exclsem = SEM_INITIALIZER(1);
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-static int imxrt_flexspi_storage_erase_chip(
-	const struct imxrt_flexspi_storage_dev_s *dev)
-{
-	/* We can't erase the chip we're executing from */
-	return -EINVAL;
-}
-
-static ssize_t imxrt_flexspi_storage_read(struct mtd_dev_s *dev,
-		off_t offset,
-		size_t nbytes,
-		uint8_t *buffer)
-{
-	ssize_t ret;
-	struct imxrt_flexspi_storage_dev_s *priv =
-		(struct imxrt_flexspi_storage_dev_s *)dev;
-	uint8_t *src;
-
-	finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
-
-	if (offset < 0) {
-		return -EIO;
-	}
-
-	src = priv->ahb_base + offset;
-
-	if (src + nbytes > (uint8_t *)NOR_STORAGE_END) {
-		return -EIO;
-	}
-
-	ret = nxsem_wait(&g_exclsem);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	memcpy(buffer, src, nbytes);
-
-	nxsem_post(&g_exclsem);
-
-	finfo("return nbytes: %d\n", (int)nbytes);
-	return (ssize_t)nbytes;
-}
-
-static ssize_t imxrt_flexspi_storage_bread(struct mtd_dev_s *dev,
-		off_t startblock,
-		size_t nblocks,
-		uint8_t *buffer)
-{
-	ssize_t nbytes;
-
-	finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
-
-	/* On this device, we can handle the block read just like the byte-oriented
-	 * read
-	 */
-
-	nbytes = imxrt_flexspi_storage_read(dev, startblock * NOR_PAGE_SIZE,
-					    nblocks * NOR_PAGE_SIZE, buffer);
-
-	if (nbytes > 0) {
-		nbytes /= NOR_PAGE_SIZE;
-	}
-
-	return nbytes;
-}
-
-locate_code(".ramfunc")
-static ssize_t imxrt_flexspi_storage_bwrite(struct mtd_dev_s *dev,
-		off_t startblock,
-		size_t nblocks,
-		const uint8_t *buffer)
-{
-	ssize_t ret;
-	struct flexspi_nor_config_s *pConfig = &g_bootConfig;
-	size_t len = nblocks * NOR_PAGE_SIZE;
-	off_t offset = (startblock + NOR_START_PAGE) * NOR_PAGE_SIZE;
-	uint8_t *src = (uint8_t *) buffer;
-#ifdef CONFIG_ARMV7M_DCACHE
-	struct imxrt_flexspi_storage_dev_s *priv =
-		(struct imxrt_flexspi_storage_dev_s *)dev;
-	uint8_t *dst = priv->ahb_base + startblock * NOR_PAGE_SIZE;
-#endif
-	int i;
-
-	if (((uintptr_t)buffer % 4) != 0) {
-		return -EINVAL; // Byte aligned write not supported
-	}
-
-	finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
-
-	ret = nxsem_wait(&g_exclsem);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	while (len) {
-		i = MIN(NOR_PAGE_SIZE, len);
-		cpsid(); // Disable interrupts
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wcast-align"
-		volatile uint32_t status = ROM_FLEXSPI_NorFlash_ProgramPage(NOR_INSTANCE, pConfig, offset, (const uint32_t *)src);
-#pragma GCC diagnostic pop
-		cpsie(); // Enable interrupts
-		usleep(0); // Yield to scheduler
-		UNUSED(status);
-
-		offset += i;
-		src += i;
-		len -= i;
-	}
-
-#ifdef CONFIG_ARMV7M_DCACHE
-	up_invalidate_dcache((uintptr_t)dst,
-			     (uintptr_t)dst + nblocks * NOR_PAGE_SIZE);
-#endif
-
-	nxsem_post(&g_exclsem);
-
-	return nblocks;
-}
-
-locate_code(".ramfunc")
-static int imxrt_flexspi_storage_erase(struct mtd_dev_s *dev,
-				       off_t startblock,
-				       size_t nblocks)
-{
-	struct flexspi_nor_config_s *pConfig = &g_bootConfig;
-	size_t blocksleft = nblocks;
-#ifdef CONFIG_ARMV7M_DCACHE
-	struct imxrt_flexspi_storage_dev_s *priv =
-		(struct imxrt_flexspi_storage_dev_s *)dev;
-	uint8_t *dst = priv->ahb_base + startblock * NOR_SECTOR_SIZE;
-#endif
-	ssize_t ret;
-
-	startblock += NOR_START_SECTOR;
-
-	finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
-
-	ret = nxsem_wait(&g_exclsem);
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	while (blocksleft-- > 0) {
-		/* Erase each sector */
-		cpsid(); // Disable interrupts
-		volatile uint32_t status = ROM_FLEXSPI_NorFlash_Erase(NOR_INSTANCE, pConfig,
-					   (startblock * NOR_SECTOR_SIZE), NOR_SECTOR_SIZE);
-		cpsie(); // Enable interrupts
-		usleep(0); // Yield to scheduler
-		UNUSED(status);
-		startblock++;
-	}
-
-#ifdef CONFIG_ARMV7M_DCACHE
-	up_invalidate_dcache((uintptr_t)dst,
-			     (uintptr_t)dst + nblocks * NOR_SECTOR_SIZE);
-#endif
-	nxsem_post(&g_exclsem);
-
-	return (int)nblocks;
-}
-
-static int imxrt_flexspi_storage_ioctl(struct mtd_dev_s *dev,
-				       int cmd,
-				       unsigned long arg)
-{
-	struct imxrt_flexspi_storage_dev_s *priv =
-		(struct imxrt_flexspi_storage_dev_s *)dev;
-	int ret = -EINVAL; /* Assume good command with bad parameters */
-
-	finfo("cmd: %d\n", cmd);
-
-	switch (cmd) {
-	case MTDIOC_GEOMETRY: {
-			struct mtd_geometry_s *geo =
-				(struct mtd_geometry_s *)((uintptr_t)arg);
-
-			if (geo) {
-				/* Populate the geometry structure with information need to
-				 * know the capacity and how to access the device.
-				 *
-				 * NOTE:
-				 * that the device is treated as though it where just an array
-				 * of fixed size blocks.  That is most likely not true, but the
-				 * client will expect the device logic to do whatever is
-				 * necessary to make it appear so.
-				 */
-
-				geo->blocksize    = (NOR_PAGE_SIZE);
-				geo->erasesize    = (NOR_SECTOR_SIZE);
-				geo->neraseblocks = (NOR_USED_SECTORS);
-
-				ret               = OK;
-
-				finfo("blocksize: %lu erasesize: %lu neraseblocks: %lu\n",
-				      geo->blocksize, geo->erasesize, geo->neraseblocks);
-			}
-		}
-		break;
-
-	case BIOC_PARTINFO: {
-			struct partition_info_s *info =
-				(struct partition_info_s *)arg;
-
-			if (info != NULL) {
-				info->numsectors  = (NOR_USED_SECTORS * NOR_SECTOR_SIZE) / NOR_PAGE_SIZE;
-				info->sectorsize  = NOR_PAGE_SIZE;
-				info->startsector = 0;
-				info->parent[0]   = '\0';
-				ret               = OK;
-			}
-		}
-		break;
-
-	case MTDIOC_BULKERASE: {
-			/* Erase the entire device */
-
-			imxrt_flexspi_storage_erase_chip(priv);
-			ret               = OK;
-		}
-		break;
-
-	default:
-		ret = -ENOTTY; /* Bad/unsupported command */
-		break;
-	}
-
-	finfo("return %d\n", ret);
-	return ret;
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-
-/****************************************************************************
- * Name: imxrt_flexspi_storage_initialize
- *
- * Description:
- *  This function is called by board-bringup logic to configure the
- *  flash device.
- *
- * Returned Value:
- *   Zero is returned on success.  Otherwise, a negated errno value is
- *   returned to indicate the nature of the failure.
- *
- ****************************************************************************/
-
-int imxrt_flexspi_storage_initialize(void)
-{
-	struct mtd_dev_s *mtd_dev = &g_flexspi_nor.mtd;
-	int ret = -ENODEV;
-
-	/* Register the MTD driver so that it can be accessed from the
-	 * VFS.
-	 */
-
-	ret = register_mtddriver("/dev/nor", mtd_dev, 0755, NULL);
-
-	if (ret < 0) {
-		syslog(LOG_ERR, "ERROR: Failed to register MTD driver: %d\n",
-		       ret);
-	}
-
-#ifdef CONFIG_FS_LITTLEFS
-
-	/* Mount the LittleFS file system */
-
-	ret = nx_mount("/dev/nor", "/fs/nor", "littlefs", 0,
-		       "autoformat");
-
-	if (ret < 0) {
-		syslog(LOG_ERR,
-		       "ERROR: Failed to mount LittleFS at /mnt/lfs: %d\n",
-		       ret);
-	}
-
-#endif
-
-	return ret;
-}
@@ -1,95 +0,0 @@
-/************************************************************************************
- *
- *   Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
- *   Authors: Gregory Nutt <gnutt@nuttx.org>
- *            David Sidrane <david_s5@nscdg.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name PX4 nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <px4_arch/spi_hw_description.h>
-#include <drivers/drv_sensor.h>
-#include <nuttx/spi/spi.h>
-
-#include <px4_platform_common/px4_config.h>
-#include <px4_log.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <debug.h>
-
-#include <nuttx/spi/spi.h>
-#include <arch/board/board.h>
-#include <systemlib/px4_macros.h>
-#include <px4_platform/gpio.h>
-
-#include <arm_internal.h>
-#include <chip.h>
-#include "imxrt_lpspi.h"
-#include "imxrt_gpio.h"
-#include "board_config.h"
-#include <systemlib/err.h>
-
-constexpr px4_spi_bus_all_hw_t px4_spi_buses_all_hw[BOARD_NUM_SPI_CFG_HW_VERSIONS] = {
-	initSPIFmumID(TROPIC_0, {
-		initSPIBus(SPI::Bus::LPSPI3, {
-			initSPIDevice(DRV_IMU_DEVTYPE_ICM45686, SPI::CS{GPIO::Port1, GPIO::Pin28}, SPI::DRDY{GPIO::Port3, GPIO::Pin18}), /* GPIO_AD_B1_12 GPIO1_IO28 */
-		}),
-		initSPIBus(SPI::Bus::LPSPI4, {
-			initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::Port2, GPIO::Pin18}, SPI::DRDY{GPIO::Port2, GPIO::Pin10}),  /* GPIO_B1_02 GPIO2_IO18 */
-			initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::Port2, GPIO::Pin0}, SPI::DRDY{GPIO::Port1, GPIO::Pin25}), /* GPIO_B0_00 GPIO2_IO00 */
-		}),
-	}),
-
-	initSPIFmumID(TROPIC_1, {
-		initSPIBus(SPI::Bus::LPSPI3, {
-			initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::Port1, GPIO::Pin28}), /* GPIO_AD_B1_12 GPIO1_IO28 */
-		}),
-		initSPIBus(SPI::Bus::LPSPI4, {
-			initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::Port2, GPIO::Pin18}),  /* GPIO_B1_02 GPIO2_IO18 */
-			initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::Port2, GPIO::Pin0}), /* GPIO_B0_00 GPIO2_IO00 */
-		}),
-	}),
-
-	initSPIFmumID(TROPIC_2, {
-		initSPIBus(SPI::Bus::LPSPI3, {
-			initSPIDevice(DRV_IMU_DEVTYPE_ICM42686P, SPI::CS{GPIO::Port1, GPIO::Pin28}), /* GPIO_AD_B1_12 GPIO1_IO28 */
-		}),
-		initSPIBus(SPI::Bus::LPSPI4, {
-			initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::Port2, GPIO::Pin18}),  /* GPIO_B1_02 GPIO2_IO18 */
-			initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::Port2, GPIO::Pin0}), /* GPIO_B0_00 GPIO2_IO00 */
-		}),
-	}),
-};
-
-static constexpr bool unused = validateSPIConfig(px4_spi_buses_all_hw);
@@ -1,152 +0,0 @@
-/****************************************************************************
- *
- *   Copyright (C) 2024 PX4 Development Team. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name PX4 nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-#include <stdint.h>
-
-#include <chip.h>
-#include "hardware/imxrt_tmr.h"
-#include "hardware/imxrt_flexpwm.h"
-#include "imxrt_gpio.h"
-#include "imxrt_iomuxc.h"
-#include "hardware/imxrt_pinmux.h"
-#include "imxrt_xbar.h"
-#include "imxrt_periphclks.h"
-
-#include <drivers/drv_pwm_output.h>
-#include <px4_arch/io_timer_hw_description.h>
-
-#include "board_config.h"
-
-/****************************************************************************************************
- * Definitions
- ****************************************************************************************************/
-
-/* Register accessors */
-
-#define _REG(_addr) (*(volatile uint16_t *)(_addr))
-
-/* QTimer3 register accessors */
-
-#define REG(_reg) _REG(IMXRT_QTIMER3_BASE + IMXRT_TMR_OFFSET(IMXRT_TMR_CH0,(_reg)))
-
-#define rCOMP1        REG(IMXRT_TMR_COMP1_OFFSET)
-#define rCOMP2        REG(IMXRT_TMR_COMP2_OFFSET)
-#define rCAPT         REG(IMXRT_TMR_CAPT_OFFSET)
-#define rLOAD         REG(IMXRT_TMR_LOAD_OFFSET)
-#define rHOLD         REG(IMXRT_TMR_HOLD_OFFSET)
-#define rCNTR         REG(IMXRT_TMR_CNTR_OFFSET)
-#define rCTRL         REG(IMXRT_TMR_CTRL_OFFSET)
-#define rSCTRL        REG(IMXRT_TMR_SCTRL_OFFSET)
-#define rCMPLD1       REG(IMXRT_TMR_CMPLD1_OFFSET)
-#define rCMPLD2       REG(IMXRT_TMR_CMPLD2_OFFSET)
-#define rCSCTRL       REG(IMXRT_TMR_CSCTRL_OFFSET)
-#define rFILT         REG(IMXRT_TMR_FILT_OFFSET)
-#define rDMA          REG(IMXRT_TMR_DMA_OFFSET)
-#define rENBL         REG(IMXRT_TMR_ENBL_OFFSET)
-
-
-constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
-	initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule0), // PWM_1, PMW_2
-	initIOPWMDshot(PWM::FlexPWM2, PWM::Submodule1), // PWM_3, PWM_4
-	initIOPWMDshot(PWM::FlexPWM4, PWM::Submodule1), // PWM_5, PWM_6
-	initIOPWMDshot(PWM::FlexPWM4, PWM::Submodule2), // PWM_7, PWM_8
-};
-
-#define FXIO_IOMUX  (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
-
-constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
-	initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_06, GPIO_FLEXIO1_FLEXIO06_1 | FXIO_IOMUX, 6),
-	initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_B, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_07, GPIO_FLEXIO1_FLEXIO07_1 | FXIO_IOMUX, 7),
-	initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_08, GPIO_FLEXIO1_FLEXIO08_1 | FXIO_IOMUX, 8),
-	initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_B, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_09, GPIO_FLEXIO1_FLEXIO09_1 | FXIO_IOMUX, 9),
-	initIOTimerChannelDshot(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_02, GPIO_FLEXIO1_FLEXIO02_1 | FXIO_IOMUX, 2),
-	initIOTimerChannelDshot(io_timers, {PWM::PWM4_PWM_B, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_03, GPIO_FLEXIO1_FLEXIO03_1 | FXIO_IOMUX, 3),
-	initIOTimerChannelDshot(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_04, GPIO_FLEXIO1_FLEXIO04_1 | FXIO_IOMUX, 4),
-	initIOTimerChannelDshot(io_timers, {PWM::PWM4_PWM_B, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_05, GPIO_FLEXIO1_FLEXIO05_1 | FXIO_IOMUX, 5),
-};
-
-constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
-	initIOTimerChannelMapping(io_timers, timer_io_channels);
-
-constexpr io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
-};
-
-constexpr timer_io_channels_t led_pwm_channels[MAX_TIMER_LED_CHANNELS] = {
-};
-
-#include <stdio.h>
-void fmurt1062_timer_initialize(void)
-{
-	/* We must configure Qtimer 3 as the IPG divide by to yield 16 Mhz
-	 * and deliver that clock to the eFlexPWM234 via XBAR
-	 *
-	 * IPG    = 144 Mhz
-	 * 16Mhz  = 144 / 9
-	 * COMP 1 = 5, COMP2 = 4
-	 *
-	 * */
-
-	/* Enable Block Clocks for Qtimer and XBAR1 */
-
-	imxrt_clockall_timer3();
-	imxrt_clockall_xbar1();
-
-	/* Disable Timer */
-
-	rCTRL = 0;
-	rCOMP1 = 5 - 1; // N - 1
-	rCOMP2 = 4 - 1;
-
-	rCAPT = 0;
-	rLOAD = 0;
-	rCNTR = 0;
-
-	rSCTRL = TMR_SCTRL_OEN;
-
-	rCMPLD1 = 0;
-	rCMPLD2 = 0;
-	rCSCTRL = 0;
-	rFILT   = 0;
-	rDMA    = 0;
-
-	/* Count rising edges of primary source,
-	 * Prescaler is /1
-	 * Count UP until compare, then re-initialize. a successful compare occurs when the counter reaches a COMP1 value.
-	 * Toggle OFLAG output using alternating compare registers
-	 */
-	rCTRL   = (TMR_CTRL_CM_MODE1 | TMR_CTRL_PCS_DIV1 | TMR_CTRL_LENGTH | TMR_CTRL_OUTMODE_TOG_ALT);
-
-	/* QTIMER3_TIMER0  -> Flexpwm234ExtClk  */
-
-	imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
-	imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
-}
@@ -1,182 +0,0 @@
-/****************************************************************************
- *
- *   Copyright (c) 2024 PX4 Development Team. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name Airmind nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/**
-* @file tropic_led_pwm.cpp
-*/
-
-#include <px4_platform_common/px4_config.h>
-#include <systemlib/px4_macros.h>
-#include <nuttx/arch.h>
-#include <nuttx/irq.h>
-
-#include <sys/types.h>
-#include <stdbool.h>
-
-#include <assert.h>
-#include <debug.h>
-#include <time.h>
-#include <queue.h>
-#include <errno.h>
-#include <string.h>
-#include <stdio.h>
-
-#include <arch/board/board.h>
-#include <drivers/drv_pwm_output.h>
-
-#include <px4_arch/io_timer.h>
-
-#include <chip.h>
-#include "imxrt_xbar.h"
-#include "imxrt_periphclks.h"
-#include "hardware/imxrt_tmr.h"
-#include "hardware/imxrt_flexpwm.h"
-
-#define LED_PWM_FREQ    1000
-#define FLEXPWM_FREQ    1000000
-#define QTMR_FREQ       (144000000/128)
-
-#define SM_SPACING (IMXRT_FLEXPWM_SM1CNT_OFFSET-IMXRT_FLEXPWM_SM0CNT_OFFSET)
-
-#define FLEXPWM_TIMER_BASE  IMXRT_FLEXPWM2_BASE
-
-/* Register accessors */
-#define _REG(_addr)	(*(volatile uint16_t *)(_addr))
-#define _REG16(_base, _reg)	(*(volatile uint16_t *)(_base + _reg))
-#define FLEXPWMREG(_tmr, _sm, _reg)		_REG16(_tmr + ((_sm) * SM_SPACING), (_reg))
-
-/* FlexPWM Registers for LED_G */
-#define rINIT(_tim, _sm)       FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0INIT_OFFSET)       /* Initial Count Register */
-#define rCTRL(_tim, _sm)       FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0CTRL_OFFSET)       /* Control Register */
-#define rCTRL2(_tim, _sm)      FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0CTRL2_OFFSET)      /* Control 2 Register */
-#define rFSTS0(_tim)           FLEXPWMREG(_tim,  0, IMXRT_FLEXPWM_FSTS0_OFFSET)         /* Fault Status Register */
-#define rVAL0(_tim, _sm)       FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0VAL0_OFFSET)       /* Value Register 0 */
-#define rVAL1(_tim, _sm)       FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0VAL1_OFFSET)       /* Value Register 1 */
-#define rVAL2(_tim, _sm)       FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0VAL2_OFFSET)       /* Value Register 2 */
-#define rVAL3(_tim, _sm)       FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0VAL3_OFFSET)       /* Value Register 3 */
-#define rVAL4(_tim, _sm)       FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0VAL4_OFFSET)       /* Value Register 4 */
-#define rVAL5(_tim, _sm)       FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0VAL5_OFFSET)       /* Value Register 5 */
-#define rFFILT0(_tim)          FLEXPWMREG(_tim,  0, IMXRT_FLEXPWM_FFILT0_OFFSET)        /* Fault Filter Register */
-#define rDISMAP0(_tim, _sm)    FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0DISMAP0_OFFSET)    /* Fault Disable Mapping Register 0 */
-#define rDISMAP1(_tim, _sm)    FLEXPWMREG(_tim, _sm,IMXRT_FLEXPWM_SM0DISMAP1_OFFSET)    /* Fault Disable Mapping Register 1 */
-#define rOUTEN(_tim)           FLEXPWMREG(_tim,  0, IMXRT_FLEXPWM_OUTEN_OFFSET)         /* Output Enable Register */
-#define rDTSRCSEL(_tim)        FLEXPWMREG(_tim,  0, IMXRT_FLEXPWM_DTSRCSEL_OFFSET)      /* PWM Source Select Register */
-#define rMCTRL(_tim)           FLEXPWMREG(_tim,  0, IMXRT_FLEXPWM_MCTRL_OFFSET)         /* Master Control Register */
-
-#define OUTEN_A_MASK 0x1
-#define OUTEN_B_MASK 0x2
-
-#define FREQ
-
-static void flexpwm_led(uint32_t timer, uint32_t sm, uint16_t cvalue, uint32_t gpio_mux, uint32_t pwm_mux,
-			uint32_t out_mask)
-{
-	if (cvalue == 0) {
-		//rMCTRL(timer) &= ~MCTRL_RUN(1 << sm);
-		px4_arch_configgpio(gpio_mux);
-
-	} else {
-		rMCTRL(timer) |= (1 << (sm + MCTRL_CLDOK_SHIFT));
-		rVAL1(timer, sm) = (FLEXPWM_FREQ / LED_PWM_FREQ) - 1;
-
-		if (out_mask & OUTEN_A_MASK) {
-			rVAL3(timer, sm) = (FLEXPWM_FREQ / LED_PWM_FREQ) - (cvalue);
-
-		} else if (out_mask & OUTEN_B_MASK) {
-			rVAL5(timer, sm) = (FLEXPWM_FREQ / LED_PWM_FREQ) - (cvalue);
-		}
-
-		rMCTRL(timer) |= MCTRL_LDOK(1 << sm) | MCTRL_RUN(1 << sm);
-		px4_arch_configgpio(pwm_mux);
-	}
-}
-
-int
-led_pwm_servo_set(unsigned channel, uint8_t cvalue)
-{
-	if (channel == 0) {
-		flexpwm_led(IMXRT_FLEXPWM3_BASE, 2, cvalue, GPIO_nLED_RED, PWM_LED_RED, OUTEN_A_MASK);
-
-	} else if (channel == 1) {
-		flexpwm_led(IMXRT_FLEXPWM1_BASE, 3, cvalue, GPIO_nLED_GREEN, PWM_LED_GREEN, OUTEN_A_MASK);
-
-	} else if (channel == 2) {
-		flexpwm_led(IMXRT_FLEXPWM3_BASE, 2, cvalue * 3, GPIO_nLED_BLUE, PWM_LED_BLUE, OUTEN_B_MASK);
-	}
-
-	return 0;
-}
-
-void flexpwm_init(uint32_t timer, uint32_t sm, uint32_t out_mask)
-{
-	/* Clear all Faults */
-	rFSTS0(timer) = FSTS_FFLAG_MASK;
-	rMCTRL(timer) |= (1 << (sm + MCTRL_CLDOK_SHIFT));
-
-	rCTRL2(timer, sm) = SMCTRL2_CLK_SEL_EXT_CLK | SMCTRL2_DBGEN | SMCTRL2_INDEP;
-	rCTRL(timer, sm)  = SMCTRL_PRSC_DIV16 | SMCTRL_FULL;
-	/* Edge aligned at 0 */
-	rINIT(timer, sm) = 0;
-	rVAL0(timer, sm) = 0;
-	rVAL2(timer, sm) = 0;
-	rVAL4(timer, sm) = 0;
-	rFFILT0(timer) &= ~FFILT_FILT_PER_MASK;
-	rDISMAP0(timer, sm) = 0xf000;
-	rDISMAP1(timer, sm) = 0xf000;
-
-
-	if (out_mask & OUTEN_A_MASK) {
-		rOUTEN(timer) |= OUTEN_PWMA_EN(1 << sm);
-	}
-
-	if (out_mask & OUTEN_B_MASK) {
-		rOUTEN(timer) |= OUTEN_PWMB_EN(1 << sm);
-	}
-
-	rDTSRCSEL(timer) = 0;
-	rMCTRL(timer) |= MCTRL_LDOK(1 << sm);
-}
-
-int led_pwm_servo_init()
-{
-	/* PWM_LED_GREEN - FLEXPWM2_PWMB03 */
-	imxrt_clockall_pwm1();
-	imxrt_clockall_pwm3();
-
-	flexpwm_init(IMXRT_FLEXPWM3_BASE, 2, OUTEN_A_MASK | OUTEN_B_MASK); // GPIO_FLEXPWM3_PWMA02_1
-	flexpwm_init(IMXRT_FLEXPWM1_BASE, 3, OUTEN_A_MASK); // GPIO_FLEXPWM1_PWMA03_2
-
-
-
-	return OK;
-}
@@ -14,7 +14,6 @@ CONFIG_DRIVERS_CAMERA_TRIGGER=y
 CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
 CONFIG_COMMON_DISTANCE_SENSOR=y
-CONFIG_DRIVERS_DISTANCE_SENSOR_LIGHTWARE_SF45_SERIAL=y
 CONFIG_DRIVERS_DSHOT=y
 CONFIG_DRIVERS_GNSS_SEPTENTRIO=y
 CONFIG_DRIVERS_GPS=y
@@ -27,12 +26,12 @@ CONFIG_COMMON_LIGHT=y
 CONFIG_DRIVERS_LIGHTS_RGBLED_PWM=y
 CONFIG_COMMON_MAGNETOMETER=y
 CONFIG_COMMON_OPTICAL_FLOW=y
-CONFIG_DRIVERS_OSD_MSP_OSD=y
+CONFIG_COMMON_OSD=y
 CONFIG_DRIVERS_POWER_MONITOR_INA226=y
 CONFIG_DRIVERS_POWER_MONITOR_INA228=y
 CONFIG_DRIVERS_POWER_MONITOR_INA238=y
 CONFIG_DRIVERS_PWM_OUT=y
-CONFIG_COMMON_RC=y
+CONFIG_DRIVERS_RC_INPUT=y
 CONFIG_DRIVERS_SAFETY_BUTTON=y
 CONFIG_COMMON_TELEMETRY=y
 CONFIG_DRIVERS_TONE_ALARM=y
@@ -45,15 +44,13 @@ CONFIG_MODULES_CAMERA_FEEDBACK=y
 CONFIG_MODULES_COMMANDER=y
 CONFIG_MODULES_CONTROL_ALLOCATOR=y
 CONFIG_MODULES_DATAMAN=y
-CONFIG_NUM_MISSION_ITMES_SUPPORTED=1000
 CONFIG_MODULES_EKF2=y
 CONFIG_MODULES_ESC_BATTERY=y
 CONFIG_MODULES_EVENTS=y
 CONFIG_MODULES_FLIGHT_MODE_MANAGER=y
 CONFIG_MODULES_FW_ATT_CONTROL=y
 CONFIG_MODULES_FW_AUTOTUNE_ATTITUDE_CONTROL=y
-CONFIG_MODULES_FW_LATERAL_LONGITUDINAL_CONTROL=y
-CONFIG_MODULES_FW_MODE_MANAGER=y
+CONFIG_MODULES_FW_POS_CONTROL=y
 CONFIG_MODULES_FW_RATE_CONTROL=y
 CONFIG_MODULES_GIMBAL=y
 CONFIG_MODULES_GYRO_CALIBRATION=y
@@ -103,4 +100,3 @@ CONFIG_SYSTEMCMDS_UORB=y
 CONFIG_SYSTEMCMDS_USB_CONNECTED=y
 CONFIG_SYSTEMCMDS_VER=y
 CONFIG_SYSTEMCMDS_WORK_QUEUE=y
-CONFIG_ARCH_CHIP_IMXRT=y
@@ -62,9 +62,7 @@ CONFIG_FS_CROMFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FATTIME=y
 CONFIG_FS_LITTLEFS=y
-CONFIG_FS_LITTLEFS_CACHE_SIZE_FACTOR=2
-CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE=64
-CONFIG_FS_LITTLEFS_PROGRAM_SIZE_FACTOR=1
+CONFIG_FS_LITTLEFS_PROGRAM_SIZE_FACTOR=2
 CONFIG_FS_PROCFS=y
 CONFIG_FS_PROCFS_MAX_TASKS=64
 CONFIG_FS_PROCFS_REGISTER=y
@@ -77,7 +75,6 @@ CONFIG_I2C=y
 CONFIG_I2C_RESET=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_IMXRT_DTCM_HEAP=y
-CONFIG_IMXRT_DTCM_HEAP_SIZE=127
 CONFIG_IMXRT_EDMA=y
 CONFIG_IMXRT_EDMA_EDBG=y
 CONFIG_IMXRT_EDMA_ELINK=y
@@ -87,6 +84,8 @@ CONFIG_IMXRT_ENET_NTXBUFFERS=8
 CONFIG_IMXRT_ENET_PHYINIT=y
 CONFIG_IMXRT_FLEXCAN3=y
 CONFIG_IMXRT_FLEXCAN_TXMB=1
+CONFIG_IMXRT_FLEXSPI1=y
+CONFIG_IMXRT_FLEXSPI1_XIP=y
 CONFIG_IMXRT_GPIO1_0_15_IRQ=y
 CONFIG_IMXRT_GPIO1_16_31_IRQ=y
 CONFIG_IMXRT_GPIO2_0_15_IRQ=y
@@ -115,29 +115,18 @@
 *(.text.work_thread)
 *(.text.work_queue)

-/* BMI088 */
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer12RegisterReadENS1_8RegisterE)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer13FIFOReadCountEv)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer8FIFOReadERKyh)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer13RegisterCheckERKNS2_17register_config_tE)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer13RegisterWriteENS1_8RegisterEh)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer17UpdateTemperatureEv)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer23RegisterSetAndClearBitsENS1_8RegisterEhh)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer26DataReadyInterruptCallbackEiPvS3_)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer7RunImplEv)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer9DataReadyEv)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_AccelerometerD0Ev)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_AccelerometerD1Ev)
-*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_AccelerometerD2Ev)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope12RegisterReadENS1_8RegisterE)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope13RegisterCheckERKNS2_17register_config_tE)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope13RegisterWriteENS1_8RegisterEh)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope23RegisterSetAndClearBitsENS1_8RegisterEhh)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope26DataReadyInterruptCallbackEiPvS3_)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope7RunImplEv)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope8FIFOReadERKyh)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope9DataReadyEv)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD0Ev)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD1Ev)
-*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD2Ev)
-*(.text._ZN12I2CSPIDriverI6BMI088E3RunEv)
+/* Flash Storage */
+*(.text.imxrt_flexspi_transfer_blocking)
+*(.text.imxrt_flexspi_transfer_blocking_private)
+*(.text.imxrt_flexspi_write_blocking)
+*(.text.imxrt_flexspi_read_blocking)
+*(.text.imxrt_flexspi_check_and_clear_error)
+*(.text.imxrt_flexspi_get_bus_idle_status)
+*(.text.imxrt_flexspi_configure_prefetch)
+*(.text.imxrt_flexspi_configure_prefetch_private)
+*(.text.imxrt_flexspi_storage_write_enable)
+*(.text.imxrt_flexspi_storage_wait_bus_busy)
+*(.text.imxrt_flexspi_storage_read_status)
+*(.text.imxrt_flexspi_storage_erase)
+*(.text.imxrt_flexspi_storage_bwrite)
+*(.text.imxrt_flexspi_storage_page_program)
@@ -22,11 +22,10 @@

 MEMORY
 {
-  flash (rx)  : ORIGIN = 0x60000000, LENGTH = 7936K - 256K
+  flash (rx)  : ORIGIN = 0x60000000, LENGTH = 7936K - 128K
  sram  (rwx) : ORIGIN = 0x20200000, LENGTH = 512K
  itcm  (rwx) : ORIGIN = 0x00000000, LENGTH = 384K
-  dtcm  (rwx) : ORIGIN = 0x20000000, LENGTH = 127K
-  dtcm_nocache  (rwx) : ORIGIN = 0x2001FC00, LENGTH = 1K
+  dtcm  (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
 }

 OUTPUT_ARCH(arm)
@@ -56,12 +55,6 @@ SECTIONS
        . = 0x2000 ;
    } >flash

-    /* Workaround for ethernet issue, by placing g_desc_pool into DTCM,
-       which effectively puts it into a no-cache region */
-    .dtcm_nocache : {
-        *(.bss.g_desc_pool)
-    } > dtcm_nocache
-
    .vectors :
    {
        KEEP(*(.vectors))
@@ -169,10 +162,6 @@ SECTIONS
    .debug_line 0 : { *(.debug_line) }
    .debug_pubnames 0 : { *(.debug_pubnames) }
    .debug_aranges 0 : { *(.debug_aranges) }
-
-    _boot_loadaddr = ORIGIN(flash);
-    _boot_size = LENGTH(flash);
-    _ram_size = LENGTH(sram);
    _sdtcm = ORIGIN(dtcm);
    _edtcm = ORIGIN(dtcm) + LENGTH(dtcm);
 }
@@ -51,8 +51,6 @@ set_source_files_properties(imxrt_ocram_initialize.c PROPERTIES COMPILE_FLAGS -f

 target_link_libraries(drivers_board
 	PRIVATE
-		arch_board_romapi
-		arch_spi
 		nuttx_arch # sdio
 		nuttx_drivers # sdio
 		px4_layer
@@ -112,6 +112,7 @@

 #define GPIO_DRDY_OFF_SPI4_DRDY7_EXTERNAL1   _PIN_OFF(GPIO_SPI4_DRDY7_EXTERNAL1)

+
 #define ADC_IOMUX (IOMUX_CMOS_INPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_HIZ)

 #define ADC1_CH(n)                  (n)
@@ -261,10 +262,6 @@ static inline int board_read_usb2_vbus_state(void)
 	}

 #define BOARD_ENABLE_CONSOLE_BUFFER
-
-/* Flash instance for storage */
-#define NOR_INSTANCE      0
-
 __BEGIN_DECLS

 /****************************************************************************************************
@@ -319,8 +316,6 @@ extern int imxrt1062_spi_bus_initialize(void);
 *
 ************************************************************************************/

-extern void imxrt_spiinitialize(void);
-
 extern int imxrt_usb_initialize(void);

 extern void imxrt_usbinitialize(void);
@@ -331,8 +326,6 @@ extern void fmurt1062_timer_initialize(void);

 #include <px4_platform_common/board_common.h>

-void imxrt_flash_romapi_initialize(void);
-
 int imxrt_flexspi_storage_initialize(void);

 #endif /* __ASSEMBLY__ */
@@ -28,71 +28,55 @@
 * Public Data
 ****************************************************************************/

-enum {
-	/* SPI instructions */
-
-	READ_FAST = 0,
-	READ_STATUS_REG = 1,
-	WRITE_ENABLE = 3,
-	SECTOR_ERASE_4K = 5,
-	READ_FAST_QUAD_OUTPUT = 6,
-	PAGE_PROGRAM_QUAD_INPUT = 7,
-	ERASE_BLOCK = 8,
-	PAGE_PROGRAM = 9,
-	CHIP_ERASE = 11,
-};
-
 locate_data(".boot_hdr.conf")
 const struct flexspi_nor_config_s g_flash_config = {
 	.mem_config =
 	{
-		.tag                    = FLEXSPI_CFG_BLK_TAG,
-		.version                = FLEXSPI_CFG_BLK_VERSION,
-		.read_sample_clksrc     =  FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD,
-		.cs_hold_time           = 1u,
-		.cs_setup_time          = 1u,
-		.column_address_width   = 0u,
-		.device_type            = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
-		.sflash_pad_type        = SERIAL_FLASH_4PADS,
-		.serial_clk_freq        = FLEXSPI_SERIAL_CLKFREQ_133MHz,
-		.sflash_a1size          = 8u * 1024u * 1024u,
-		.lookup_table           =
+		.tag = FLEXSPI_CFG_BLK_TAG,
+		.version = FLEXSPI_CFG_BLK_VERSION,
+		.read_sample_clksrc =  FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD,
+		.cs_hold_time = 1u,
+		.cs_setup_time = 1u,
+		.column_address_width = 0u,
+		.device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
+		.sflash_pad_type = SERIAL_FLASH_4PADS,
+		.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz,
+		.sflash_a1size = 8u * 1024u * 1024u,
+		.data_valid_time =
 		{
-			[4 * READ_FAST] =       FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xeb,
-								RADDR_SDR, FLEXSPI_4PAD, 0x18),
-			[4 * READ_FAST + 1] =   FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06,
-								READ_SDR,  FLEXSPI_4PAD, 0x04),
+			0u, 0u
+		},
+		.lookup_table =
+		{
+			/* Fast Read Quad I/O */
+			[0 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xeb,
+						  RADDR_SDR, FLEXSPI_4PAD, 0x18),
+			[0 + 1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06,
+						  READ_SDR, FLEXSPI_4PAD, 0x04),

-			[4 * READ_STATUS_REG] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05,
-								READ_SDR,  FLEXSPI_1PAD, 0x04),
+			/* Read Status Register-1 */
+			[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05,
+						      READ_SDR, FLEXSPI_1PAD, 0x04),

-			[4 * WRITE_ENABLE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06,
-							     STOP, FLEXSPI_1PAD, 0),
+			/* Write Status Register-1 */
+			[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, STOP, FLEXSPI_1PAD, 0x0),

-			[4 * SECTOR_ERASE_4K] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20,
-								RADDR_SDR, FLEXSPI_1PAD, 0x18),
+			/* Sector Erase (4KB) */
+			[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20,
+						      RADDR_SDR, FLEXSPI_1PAD, 0x18),

-			[4 * CHIP_ERASE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60,
-							   STOP, FLEXSPI_1PAD, 0),
+			/* Block Erase (64KB) */
+			[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xd8,
+						      RADDR_SDR, FLEXSPI_1PAD, 0x18),

-			[4 * ERASE_BLOCK] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xd8,
-							    RADDR_SDR, FLEXSPI_1PAD, 0x18),
-
-			[4 * PAGE_PROGRAM] =     FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0x02,
-					RADDR_SDR, FLEXSPI_1PAD, 0x18),
-			[4 * PAGE_PROGRAM + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04,
-					STOP,      FLEXSPI_1PAD, 0x0),
-
-			[4 * READ_FAST_QUAD_OUTPUT] =     FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6b,
-					RADDR_SDR, FLEXSPI_1PAD, 0x18),
-			[4 * READ_FAST_QUAD_OUTPUT + 1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08,
-					READ_SDR,  FLEXSPI_4PAD, 0x04),
-
-			[4 * PAGE_PROGRAM_QUAD_INPUT] =     FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32,
-					RADDR_SDR, FLEXSPI_1PAD, 0x18),
-			[4 * PAGE_PROGRAM_QUAD_INPUT + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04,
-					STOP,      FLEXSPI_1PAD, 0),
+			/* Page Program */
+			[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02,
+						      RADDR_SDR, FLEXSPI_1PAD, 0x18),
+			[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04,
+						      STOP, FLEXSPI_1PAD, 0x0),

+			/* Chip Erase */
+			[4 * 11 + 0] =  FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
 		},
 	},

@@ -1,5 +1,5 @@
 /****************************************************************************
- * boards/nxp/tropic-community/src/imxrt_flexspi_storage.c
+ * boards/px4/fmu-v6xrt/src/imxrt_flexspi_storage.c
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
@@ -36,28 +36,104 @@
 #include <px4_platform_common/px4_mtd.h>
 #include "px4_log.h"

-#include <px4_arch/imxrt_flexspi_nor_flash.h>
-#include <px4_arch/imxrt_romapi.h>
+#include "imxrt_flexspi.h"
 #include "board_config.h"
 #include "hardware/imxrt_pinmux.h"
-#include "barriers.h"
+
+#ifdef CONFIG_IMXRT_FLEXSPI

 /* Used sectors must be multiple of the flash block size
 * i.e. W25Q32JV has a block size of 64KB
 */

-#define NOR_USED_SECTORS  (0x40U)   /* 64 * 4KB = 256KB */
+#define NOR_USED_SECTORS  (0x20U)   /* 32 * 4KB = 128KB */
 #define NOR_TOTAL_SECTORS (0x0800U)
 #define NOR_PAGE_SIZE     (0x0100U) /* 256 bytes */
 #define NOR_SECTOR_SIZE   (0x1000U) /* 4KB */
 #define NOR_START_SECTOR  (NOR_TOTAL_SECTORS - NOR_USED_SECTORS)
 #define NOR_START_PAGE    ((NOR_START_SECTOR * NOR_SECTOR_SIZE) / NOR_PAGE_SIZE)
 #define NOR_STORAGE_ADDR  (IMXRT_FLEXCIPHER_BASE + NOR_START_SECTOR * NOR_SECTOR_SIZE)
-#define NOR_STORAGE_END   (IMXRT_FLEXCIPHER_BASE + (NOR_START_SECTOR + NOR_TOTAL_SECTORS) * NOR_SECTOR_SIZE)

 #define MIN(a, b) (((a) < (b)) ? (a) : (b))

-extern struct flexspi_nor_config_s g_bootConfig;
+enum {
+	/* SPI instructions */
+
+	READ_FAST = 0,
+	READ_STATUS_REG = 1,
+	WRITE_STATUS_REG = 3,
+	WRITE_ENABLE = 4,
+	SECTOR_ERASE_4K = 5,
+	READ_FAST_QUAD_OUTPUT = 6,
+	PAGE_PROGRAM_QUAD_INPUT = 7,
+	PAGE_PROGRAM = 9,
+	CHIP_ERASE = 11,
+};
+
+static const uint32_t g_flexspi_nor_lut[][4] = {
+	[READ_FAST] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0xeb,
+				FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_4PAD, 0x18),
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_DUMMY_SDR, FLEXSPI_4PAD, 0x06,
+				FLEXSPI_COMMAND_READ_SDR,  FLEXSPI_4PAD, 0x04),
+	},
+
+	[READ_STATUS_REG] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0x05,
+				FLEXSPI_COMMAND_READ_SDR,  FLEXSPI_1PAD, 0x04),
+	},
+
+	[WRITE_STATUS_REG] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0x01,
+				FLEXSPI_COMMAND_WRITE_SDR, FLEXSPI_1PAD, 0x04),
+	},
+
+	[WRITE_ENABLE] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0x06,
+				FLEXSPI_COMMAND_STOP,      FLEXSPI_1PAD, 0),
+	},
+
+	[SECTOR_ERASE_4K] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0x20,
+				FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_1PAD, 0x18),
+	},
+
+	[CHIP_ERASE] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0xc7,
+				FLEXSPI_COMMAND_STOP,      FLEXSPI_1PAD, 0),
+	},
+
+	[PAGE_PROGRAM] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0x02,
+				FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_1PAD, 0x18),
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_WRITE_SDR, FLEXSPI_1PAD, 0x04,
+				FLEXSPI_COMMAND_STOP,  FLEXSPI_1PAD, 0x0),
+	},
+
+	[READ_FAST_QUAD_OUTPUT] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0x6b,
+				FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_1PAD, 0x18),
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_DUMMY_SDR, FLEXSPI_4PAD, 0x08,
+				FLEXSPI_COMMAND_READ_SDR,  FLEXSPI_4PAD, 0x04),
+	},
+
+	[PAGE_PROGRAM_QUAD_INPUT] =
+	{
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR,       FLEXSPI_1PAD, 0x32,
+				FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_1PAD, 0x18),
+		FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_WRITE_SDR, FLEXSPI_4PAD, 0x04,
+				FLEXSPI_COMMAND_STOP,      FLEXSPI_1PAD, 0),
+	},
+
+};

 /****************************************************************************
 * Private Types
@@ -67,7 +143,10 @@ extern struct flexspi_nor_config_s g_bootConfig;

 struct imxrt_flexspi_storage_dev_s {
 	struct mtd_dev_s mtd;
+	struct flexspi_dev_s *flexspi;   /* Saved FlexSPI interface instance */
 	uint8_t *ahb_base;
+	enum flexspi_port_e port;
+	struct flexspi_device_config_s *config;
 };

 /****************************************************************************
@@ -99,6 +178,26 @@ static int imxrt_flexspi_storage_ioctl(struct mtd_dev_s *dev,
 * Private Data
 ****************************************************************************/

+static struct flexspi_device_config_s g_flexspi_device_config = {
+	.flexspi_root_clk = 4000000,
+	.is_sck2_enabled = 0,
+	.flash_size = NOR_USED_SECTORS * NOR_SECTOR_SIZE / 4,
+	.cs_interval_unit = FLEXSPI_CS_INTERVAL_UNIT1_SCK_CYCLE,
+	.cs_interval = 0,
+	.cs_hold_time = 3,
+	.cs_setup_time = 3,
+	.data_valid_time = 0,
+	.columnspace = 0,
+	.enable_word_address = 0,
+	.awr_seq_index = 0,
+	.awr_seq_number = 0,
+	.ard_seq_index = READ_FAST,
+	.ard_seq_number = 1,
+	.ahb_write_wait_unit = FLEXSPI_AHB_WRITE_WAIT_UNIT2_AHB_CYCLE,
+	.ahb_write_wait_interval = 0,
+	.rx_sample_clock = FLEXSPI_READ_SAMPLE_CLK_LOOPBACK_FROM_DQS_PAD,
+};
+
 static struct imxrt_flexspi_storage_dev_s g_flexspi_nor = {
 	.mtd =
 	{
@@ -112,17 +211,90 @@ static struct imxrt_flexspi_storage_dev_s g_flexspi_nor = {
 #endif
 		.name   = "imxrt_flexspi_storage"
 	},
+	.flexspi = (void *)0,
 	.ahb_base = (uint8_t *) NOR_STORAGE_ADDR,
+	.port = FLEXSPI_PORT_A1,
+	.config = &g_flexspi_device_config
 };

-/* Ensure exclusive access to the driver */
-
-static sem_t g_exclsem = SEM_INITIALIZER(1);
-
 /****************************************************************************
 * Private Functions
 ****************************************************************************/

+static int imxrt_flexspi_storage_read_status(
+	const struct imxrt_flexspi_storage_dev_s *dev,
+	uint32_t *status)
+{
+	int stat;
+
+	struct flexspi_transfer_s transfer = {
+		.device_address = 0,
+		.port = dev->port,
+		.cmd_type = FLEXSPI_READ,
+		.seq_number = 1,
+		.seq_index = READ_STATUS_REG,
+		.data = status,
+		.data_size = 1,
+	};
+
+	stat = FLEXSPI_TRANSFER(dev->flexspi, &transfer);
+
+	if (stat != 0) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int imxrt_flexspi_storage_write_enable(
+	const struct imxrt_flexspi_storage_dev_s *dev)
+{
+	int stat;
+
+	struct flexspi_transfer_s transfer = {
+		.device_address = 0,
+		.port = dev->port,
+		.cmd_type = FLEXSPI_COMMAND,
+		.seq_number = 1,
+		.seq_index = WRITE_ENABLE,
+		.data = NULL,
+		.data_size = 0,
+	};
+
+	stat = FLEXSPI_TRANSFER(dev->flexspi, &transfer);
+
+	if (stat != 0) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int imxrt_flexspi_storage_erase_sector(
+	const struct imxrt_flexspi_storage_dev_s *dev,
+	off_t offset)
+{
+	int stat;
+	struct flexspi_transfer_s transfer = {
+		.device_address = offset,
+		.port = dev->port,
+		.cmd_type = FLEXSPI_COMMAND,
+		.seq_number = 1,
+		.seq_index = SECTOR_ERASE_4K,
+		.data = NULL,
+		.data_size = 0,
+	};
+
+	stat = FLEXSPI_TRANSFER(dev->flexspi, &transfer);
+
+	if (stat != 0) {
+		return -EIO;
+	}
+
+
+	return 0;
+}
+
 static int imxrt_flexspi_storage_erase_chip(
 	const struct imxrt_flexspi_storage_dev_s *dev)
 {
@@ -130,38 +302,69 @@ static int imxrt_flexspi_storage_erase_chip(
 	return -EINVAL;
 }

+static int imxrt_flexspi_storage_page_program(
+	const struct imxrt_flexspi_storage_dev_s *dev,
+	off_t offset,
+	const void *buffer,
+	size_t len)
+{
+	int stat;
+
+	struct flexspi_transfer_s transfer = {
+		.device_address = offset,
+		.port = dev->port,
+		.cmd_type = FLEXSPI_WRITE,
+		.seq_number = 1,
+		.seq_index = PAGE_PROGRAM_QUAD_INPUT,
+		.data = (uint32_t *) buffer,
+		.data_size = len,
+	};
+
+	stat = FLEXSPI_TRANSFER(dev->flexspi, &transfer);
+
+	if (stat != 0) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int imxrt_flexspi_storage_wait_bus_busy(
+	const struct imxrt_flexspi_storage_dev_s *dev)
+{
+	uint32_t status = 0;
+	int ret;
+
+	do {
+		ret = imxrt_flexspi_storage_read_status(dev, &status);
+
+		if (ret) {
+			return ret;
+		}
+	} while (status & 1);
+
+	return 0;
+}
+
 static ssize_t imxrt_flexspi_storage_read(struct mtd_dev_s *dev,
 		off_t offset,
 		size_t nbytes,
 		uint8_t *buffer)
 {
-	ssize_t ret;
 	struct imxrt_flexspi_storage_dev_s *priv =
 		(struct imxrt_flexspi_storage_dev_s *)dev;
 	uint8_t *src;

 	finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);

-	if (offset < 0) {
+	if (priv->port >= FLEXSPI_PORT_COUNT) {
 		return -EIO;
 	}

 	src = priv->ahb_base + offset;

-	if (src + nbytes > (uint8_t *)NOR_STORAGE_END) {
-		return -EIO;
-	}
-
-	ret = nxsem_wait(&g_exclsem);
-
-	if (ret < 0) {
-		return ret;
-	}
-
 	memcpy(buffer, src, nbytes);

-	nxsem_post(&g_exclsem);
-
 	finfo("return nbytes: %d\n", (int)nbytes);
 	return (ssize_t)nbytes;
 }
@@ -189,102 +392,85 @@ static ssize_t imxrt_flexspi_storage_bread(struct mtd_dev_s *dev,
 	return nbytes;
 }

-locate_code(".ramfunc")
 static ssize_t imxrt_flexspi_storage_bwrite(struct mtd_dev_s *dev,
 		off_t startblock,
 		size_t nblocks,
 		const uint8_t *buffer)
 {
-	ssize_t ret;
-	struct flexspi_nor_config_s *pConfig = &g_bootConfig;
+	struct imxrt_flexspi_storage_dev_s *priv =
+		(struct imxrt_flexspi_storage_dev_s *)dev;
 	size_t len = nblocks * NOR_PAGE_SIZE;
 	off_t offset = (startblock + NOR_START_PAGE) * NOR_PAGE_SIZE;
 	uint8_t *src = (uint8_t *) buffer;
 #ifdef CONFIG_ARMV7M_DCACHE
-	struct imxrt_flexspi_storage_dev_s *priv =
-		(struct imxrt_flexspi_storage_dev_s *)dev;
 	uint8_t *dst = priv->ahb_base + startblock * NOR_PAGE_SIZE;
 #endif
 	int i;

-	if (((uintptr_t)buffer % 4) != 0) {
-		return -EINVAL; // Byte aligned write not supported
-	}
-
 	finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);

-	ret = nxsem_wait(&g_exclsem);
+	FLEXSPI_CONFIGURE_PREFETCH(priv->flexspi, false);

-	if (ret < 0) {
-		return ret;
-	}
+	irqstate_t flags = enter_critical_section();

 	while (len) {
 		i = MIN(NOR_PAGE_SIZE, len);
-		cpsid(); // Disable interrupts
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wcast-align"
-		volatile uint32_t status = ROM_FLEXSPI_NorFlash_ProgramPage(NOR_INSTANCE, pConfig, offset, (const uint32_t *)src);
-#pragma GCC diagnostic pop
-		cpsie(); // Enable interrupts
-		usleep(0); // Yield to scheduler
-		UNUSED(status);
-
+		imxrt_flexspi_storage_write_enable(priv);
+		imxrt_flexspi_storage_page_program(priv, offset, src, i);
+		imxrt_flexspi_storage_wait_bus_busy(priv);
 		offset += i;
 		src += i;
 		len -= i;
 	}

+	FLEXSPI_CONFIGURE_PREFETCH(priv->flexspi, true);
+
+	leave_critical_section(flags);
+
 #ifdef CONFIG_ARMV7M_DCACHE
 	up_invalidate_dcache((uintptr_t)dst,
 			     (uintptr_t)dst + nblocks * NOR_PAGE_SIZE);
 #endif

-	nxsem_post(&g_exclsem);
-
 	return nblocks;
 }

-locate_code(".ramfunc")
 static int imxrt_flexspi_storage_erase(struct mtd_dev_s *dev,
 				       off_t startblock,
 				       size_t nblocks)
 {
-	struct flexspi_nor_config_s *pConfig = &g_bootConfig;
-	size_t blocksleft = nblocks;
-#ifdef CONFIG_ARMV7M_DCACHE
 	struct imxrt_flexspi_storage_dev_s *priv =
 		(struct imxrt_flexspi_storage_dev_s *)dev;
+	size_t blocksleft = nblocks;
+#ifdef CONFIG_ARMV7M_DCACHE
 	uint8_t *dst = priv->ahb_base + startblock * NOR_SECTOR_SIZE;
 #endif
-	ssize_t ret;

 	startblock += NOR_START_SECTOR;

 	finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);

-	ret = nxsem_wait(&g_exclsem);
+	FLEXSPI_CONFIGURE_PREFETCH(priv->flexspi, false);

-	if (ret < 0) {
-		return ret;
-	}
+	irqstate_t flags = enter_critical_section();

 	while (blocksleft-- > 0) {
 		/* Erase each sector */
-		cpsid(); // Disable interrupts
-		volatile uint32_t status = ROM_FLEXSPI_NorFlash_Erase(NOR_INSTANCE, pConfig,
-					   (startblock * NOR_SECTOR_SIZE), NOR_SECTOR_SIZE);
-		cpsie(); // Enable interrupts
-		usleep(0); // Yield to scheduler
-		UNUSED(status);
+
+		imxrt_flexspi_storage_write_enable(priv);
+		imxrt_flexspi_storage_erase_sector(priv, startblock * NOR_SECTOR_SIZE);
+		imxrt_flexspi_storage_wait_bus_busy(priv);
 		startblock++;
 	}

+	FLEXSPI_CONFIGURE_PREFETCH(priv->flexspi, true);
+
+	leave_critical_section(flags);
+
 #ifdef CONFIG_ARMV7M_DCACHE
 	up_invalidate_dcache((uintptr_t)dst,
 			     (uintptr_t)dst + nblocks * NOR_SECTOR_SIZE);
 #endif
-	nxsem_post(&g_exclsem);

 	return (int)nblocks;
 }
@@ -344,7 +530,9 @@ static int imxrt_flexspi_storage_ioctl(struct mtd_dev_s *dev,
 	case MTDIOC_BULKERASE: {
 			/* Erase the entire device */

+			imxrt_flexspi_storage_write_enable(priv);
 			imxrt_flexspi_storage_erase_chip(priv);
+			imxrt_flexspi_storage_wait_bus_busy(priv);
 			ret               = OK;
 		}
 		break;
@@ -381,6 +569,20 @@ int imxrt_flexspi_storage_initialize(void)
 	struct mtd_dev_s *mtd_dev = &g_flexspi_nor.mtd;
 	int ret = -ENODEV;

+	/* Select FlexSPI1 */
+
+	g_flexspi_nor.flexspi = imxrt_flexspi_initialize(0);
+
+	if (g_flexspi_nor.flexspi) {
+		ret = OK;
+
+
+		FLEXSPI_UPDATE_LUT(g_flexspi_nor.flexspi,
+				   0,
+				   (const uint32_t *)g_flexspi_nor_lut,
+				   sizeof(g_flexspi_nor_lut) / 4);
+	}
+
 	/* Register the MTD driver so that it can be accessed from the
 	 * VFS.
 	 */
@@ -409,3 +611,4 @@ int imxrt_flexspi_storage_initialize(void)

 	return ret;
 }
+#endif /* CONFIG_IMXRT_FLEXSPI */
@@ -64,9 +64,9 @@
 #include <nuttx/analog/adc.h>
 #include <nuttx/mm/gran.h>

+#include "arm_internal.h"
 #include "arm_internal.h"
 #include "imxrt_flexspi_nor_boot.h"
-#include <px4_arch/imxrt_flexspi_nor_flash.h>
 #include "imxrt_iomuxc.h"
 #include "imxrt_flexcan.h"
 #include "imxrt_enet.h"
@@ -84,7 +84,6 @@
 #include <drivers/drv_board_led.h>
 #include <systemlib/px4_macros.h>
 #include <px4_arch/io_timer.h>
-#include <px4_arch/imxrt_romapi.h>
 #include <px4_platform_common/init.h>
 #include <px4_platform/gpio.h>
 #include <px4_platform/board_dma_alloc.h>
@@ -145,30 +144,6 @@ __EXPORT void board_on_reset(int status)
 	}
 }

-/****************************************************************************
- * Name: imxrt_flash_romapi_initialize
- *
- * Description:
- *
- ****************************************************************************/
-struct flexspi_nor_config_s g_bootConfig;
-
-locate_code(".ramfunc")
-void imxrt_flash_romapi_initialize(void)
-{
-	memcpy((struct flexspi_nor_config_s *)&g_bootConfig, &g_flash_config,
-	       sizeof(struct flexspi_nor_config_s));
-	g_bootConfig.memConfig.tag = FLEXSPI_CFG_BLK_TAG;
-
-	ROM_API_Init();
-
-	ROM_FLEXSPI_NorFlash_Init(NOR_INSTANCE, (struct flexspi_nor_config_s *)&g_bootConfig);
-	ROM_FLEXSPI_NorFlash_ClearCache(NOR_INSTANCE);
-
-	ARM_DSB();
-	ARM_ISB();
-	ARM_DMB();
-}

 locate_code(".ramfunc")
 void imxrt_flash_setup_prefetch_partition(void)
@@ -232,8 +207,6 @@ __EXPORT void imxrt_boardinitialize(void)
 {
 	imxrt_flash_setup_prefetch_partition();

-	imxrt_flash_romapi_initialize();
-
 	board_on_reset(-1); /* Reset PWM first thing */

 	/* configure LEDs */
@@ -245,6 +218,10 @@ __EXPORT void imxrt_boardinitialize(void)
 	const uint32_t gpio[] = PX4_GPIO_INIT_LIST;
 	px4_gpio_init(gpio, arraySize(gpio));

+	/* configure SPI interfaces */
+
+	imxrt_spidev_initialize();
+
 	imxrt_usb_initialize();

 	fmurt1062_timer_initialize();
@@ -353,17 +330,13 @@ void imxrt_flexio_clocking(void)
 ****************************************************************************/
 __EXPORT int board_app_initialize(uintptr_t arg)
 {
-	int ret = OK;
-
-#if !defined(BOOTLOADER)
-
 	imxrt_flexio_clocking();

 	/* Power on Interfaces */

-	px4_platform_init();
+	board_spi_reset(10, 0xffff);

-	imxrt_spiinitialize();
+	px4_platform_init();

 	/* configure the DMA allocator */

@@ -377,13 +350,14 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 	hrt_call_every(&serial_dma_call, 1000, 1000, (hrt_callout)imxrt_serial_dma_poll, NULL);
 #endif

+	int ret = OK;
 #if defined(CONFIG_IMXRT_USDHC)
 	ret = fmurt1062_usdhc_initialize();
 #endif

-	imxrt_spiinitialize();
+	/* Configure SPI-based devices */

-	board_spi_reset(10, 0xffff);
+	ret = imxrt1062_spi_bus_initialize();

 #ifdef CONFIG_IMXRT_ENET
 	imxrt_netinitialize(0);
@@ -393,6 +367,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 	imxrt_caninitialize(3);
 #endif

+#ifdef CONFIG_IMXRT_FLEXSPI
 	ret = imxrt_flexspi_storage_initialize();

 	if (ret < 0) {
@@ -400,7 +375,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 		       "ERROR: imxrt_flexspi_nor_initialize failed: %d\n", ret);
 	}

-#endif /* !defined(BOOTLOADER) */
+#endif

 	return ret;
 }
@@ -62,6 +62,7 @@

 #if defined(CONFIG_IMXRT_LPSPI3) || defined(CONFIG_IMXRT_LPSPI4)

+
 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
 	initSPIBus(SPI::Bus::LPSPI3, {
 		initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::Port1, GPIO::Pin28}), /* GPIO_AD_B1_12 GPIO1_IO28 */
@@ -74,4 +75,241 @@ constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {

 static constexpr bool unused = validateSPIConfig(px4_spi_buses);

+#define _PIN_OFF(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT | IOMUX_PULL_DOWN_100K | IOMUX_CMOS_INPUT))
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+/************************************************************************************
+ * Name: fmurt1062_spidev_initialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the NXP FMUKRT1062-V1 board.
+ *
+ ************************************************************************************/
+
+void imxrt_spidev_initialize(void)
+{
+	for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
+		for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
+			if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
+				px4_arch_configgpio(px4_spi_buses[bus].devices[i].cs_gpio);
+			}
+		}
+	}
+}
+
+/************************************************************************************
+ * Name: imxrt_spi_bus_initialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the NXP FMUKRT1062-V1 board.
+ *
+ ************************************************************************************/
+
+static const px4_spi_bus_t *_spi_bus3;
+static const px4_spi_bus_t *_spi_bus4;
+
+__EXPORT int imxrt1062_spi_bus_initialize(void)
+{
+	for (int i = 0; i < SPI_BUS_MAX_BUS_ITEMS; ++i) {
+		switch (px4_spi_buses[i].bus) {
+		case 3: _spi_bus3 = &px4_spi_buses[i]; break;
+
+		case 4: _spi_bus4 = &px4_spi_buses[i]; break;
+		}
+	}
+
+	/* Configure SPI-based devices */
+
+	struct spi_dev_s *spi_icm = px4_spibus_initialize(3);
+
+	if (!spi_icm) {
+		PX4_ERR("[boot] FAILED to initialize SPI port %d\n", 1);
+		return -ENODEV;
+	}
+
+	/* Default bus 1 to 8MHz and de-assert the known chip selects.
+	 */
+
+	SPI_SETFREQUENCY(spi_icm, 8 * 1000 * 1000);
+	SPI_SETBITS(spi_icm, 8);
+	SPI_SETMODE(spi_icm, SPIDEV_MODE3);
+
+	/* Get the SPI port for the BMI088 */
+
+	struct spi_dev_s *spi_bmi = px4_spibus_initialize(4);
+
+	if (!spi_bmi) {
+		PX4_ERR("[boot] FAILED to initialize SPI port %d\n", 4);
+		return -ENODEV;
+	}
+
+	/* Default ext bus to 8MHz and de-assert the known chip selects.
+	 */
+
+	SPI_SETFREQUENCY(spi_bmi, 8 * 1000 * 1000);
+	SPI_SETBITS(spi_bmi, 8);
+	SPI_SETMODE(spi_bmi, SPIDEV_MODE3);
+
+	/* deselect all */
+	for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
+		for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
+			if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
+				SPI_SELECT(spi_bmi, px4_spi_buses[bus].devices[i].devid, false);
+			}
+		}
+	}
+
+	return OK;
+
+}
+
+/****************************************************************************
+ * Name:  imxrt_lpspi1/2/3select and imxrt_lpspi1/2/3status
+ *
+ * Description:
+ *   The external functions, imxrt_lpspi1/2/3select and imxrt_lpspi1/2/3status must be
+ *   provided by board-specific logic.  They are implementations of the select
+ *   and status methods of the SPI interface defined by struct spi_ops_s (see
+ *   include/nuttx/spi/spi.h). All other methods (including imxrt_lpspibus_initialize())
+ *   are provided by common STM32 logic.  To use this common SPI logic on your
+ *   board:
+ *
+ *   1. Provide logic in imxrt_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide imxrt_lpspi1/2/3select() and imxrt_lpspi1/2/3status() functions in your
+ *      board-specific logic.  These functions will perform chip selection and
+ *      status operations using GPIOs in the way your board is configured.
+ *   3. Add a calls to imxrt_lpspibus_initialize() in your low level application
+ *      initialization logic
+ *   4. The handle returned by imxrt_lpspibus_initialize() may then be used to bind the
+ *      SPI driver to higher level logic (e.g., calling
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+static inline void imxrt_spixselect(const px4_spi_bus_t *bus, struct spi_dev_s *dev, uint32_t devid, bool selected)
+{
+	for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
+		if (bus->devices[i].cs_gpio == 0) {
+			break;
+		}
+
+		if (devid == bus->devices[i].devid) {
+			// SPI select is active low, so write !selected to select the device
+			imxrt_gpio_write(bus->devices[i].cs_gpio, !selected);
+		}
+	}
+}
+
+#if defined(CONFIG_IMXRT_LPSPI3)
+__EXPORT void imxrt_lpspi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
+{
+	imxrt_spixselect(_spi_bus3, dev, devid, selected);
+}
+
+__EXPORT uint8_t imxrt_lpspi3status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+#endif
+
+#if defined(CONFIG_IMXRT_LPSPI4)
+__EXPORT void imxrt_lpspi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
+{
+	imxrt_spixselect(_spi_bus4, dev, devid, selected);
+}
+
+__EXPORT uint8_t imxrt_lpspi4status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+#endif
+
+/************************************************************************************
+ * Name: board_spi_reset
+ *
+ * Description:
+ *
+ *
+ ************************************************************************************/
+
+__EXPORT void board_spi_reset(int ms, int bus_mask)
+{
+#ifdef CONFIG_IMXRT_LPSPI1
+
+	/* Goal not to back feed the chips on the bus via IO lines */
+	for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
+		if (px4_spi_buses[bus].bus == 1 || px4_spi_buses[bus].bus == 3) {
+			for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
+				if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
+					imxrt_config_gpio(_PIN_OFF(px4_spi_buses[bus].devices[i].cs_gpio));
+				}
+
+				if (px4_spi_buses[bus].devices[i].drdy_gpio != 0) {
+					imxrt_config_gpio(_PIN_OFF(px4_spi_buses[bus].devices[i].drdy_gpio));
+				}
+			}
+		}
+	}
+
+	imxrt_config_gpio(GPIO_SPI1_SCK_OFF);
+	imxrt_config_gpio(GPIO_SPI1_MISO_OFF);
+	imxrt_config_gpio(GPIO_SPI1_MOSI_OFF);
+
+	imxrt_config_gpio(GPIO_SPI3_SCK_OFF);
+	imxrt_config_gpio(GPIO_SPI3_MISO_OFF);
+	imxrt_config_gpio(GPIO_SPI3_MOSI_OFF);
+
+
+	imxrt_config_gpio(_PIN_OFF(GPIO_LPI2C3_SDA_RESET));
+	imxrt_config_gpio(_PIN_OFF(GPIO_LPI2C3_SCL_RESET));
+
+	/* set the sensor rail off */
+	imxrt_gpio_write(GPIO_VDD_3V3_SENSORS_EN, 0);
+
+	/* wait for the sensor rail to reach GND */
+	usleep(ms * 1000);
+	warnx("reset done, %d ms", ms);
+
+	/* re-enable power */
+
+	/* switch the sensor rail back on */
+	imxrt_gpio_write(GPIO_VDD_3V3_SENSORS_EN, 1);
+
+	/* wait a bit before starting SPI, different times didn't influence results */
+	usleep(100);
+
+	/* reconfigure the SPI pins */
+	for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
+		if (px4_spi_buses[bus].bus == 1 || px4_spi_buses[bus].bus == 3) {
+			for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
+				if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
+					imxrt_config_gpio(px4_spi_buses[bus].devices[i].cs_gpio);
+				}
+
+				if (px4_spi_buses[bus].devices[i].drdy_gpio != 0) {
+					imxrt_config_gpio(px4_spi_buses[bus].devices[i].drdy_gpio);
+				}
+			}
+		}
+	}
+
+	imxrt_config_gpio(GPIO_LPSPI1_SCK);
+	imxrt_config_gpio(GPIO_LPSPI1_MISO);
+	imxrt_config_gpio(GPIO_LPSPI1_MOSI);
+
+	imxrt_config_gpio(GPIO_LPSPI3_SCK);
+	imxrt_config_gpio(GPIO_LPSPI3_MISO);
+	imxrt_config_gpio(GPIO_LPSPI3_MOSI);
+
+	imxrt_config_gpio(GPIO_LPI2C3_SDA);
+	imxrt_config_gpio(GPIO_LPI2C3_SCL);
+
+#endif /* CONFIG_IMXRT_LPSPI1 */
+
+}
+
 #endif /* CONFIG_IMXRT_LPSPI3 || CONFIG_IMXRT_LPSPI4  */
@@ -1,5 +1,4 @@
 # CONFIG_BOARD_UAVCAN_TIMER_OVERRIDE is not set
 CONFIG_DRIVERS_UAVCAN=n
 CONFIG_MODULES_UXRCE_DDS_CLIENT=n
-CONFIG_BOARD_CONSTRAINED_FLASH=y
 CONFIG_MODULES_ZENOH=y
@@ -1,6 +1,6 @@
 ############################################################################
 #
-#   Copyright (c) 2023 PX4 Development Team. All rights reserved.
+#   Copyright (c) 2025 PX4 Development Team. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
@@ -31,4 +31,4 @@
 #
 ############################################################################

-add_subdirectory(../imxrt_common arch_bootloader)
+add_subdirectory(pwm_voltage)
@@ -1,47 +1,43 @@
 CONFIG_BOARD_TOOLCHAIN="arm-none-eabi"
 CONFIG_BOARD_ARCHITECTURE="cortex-m7"
 CONFIG_BOARD_ETHERNET=y
-CONFIG_BOARD_SERIAL_GPS1="/dev/ttyS1"
-CONFIG_BOARD_SERIAL_TEL1="/dev/ttyS2"
+CONFIG_BOARD_SERIAL_GPS1="/dev/ttyS0"
+CONFIG_BOARD_SERIAL_GPS2="/dev/ttyS7"
+CONFIG_BOARD_SERIAL_TEL1="/dev/ttyS6"
 CONFIG_BOARD_SERIAL_TEL2="/dev/ttyS4"
-CONFIG_BOARD_SERIAL_TEL3="/dev/ttyS3"
-CONFIG_BOARD_SERIAL_RC="/dev/ttyS6"
-CONFIG_BOARD_PARAM_FILE="/fs/nor/mtd_params"
+CONFIG_BOARD_SERIAL_TEL3="/dev/ttyS1"
+CONFIG_BOARD_SERIAL_EXT2="/dev/ttyS3"
+CONFIG_DRIVERS_ADC_ADS1115=y
 CONFIG_DRIVERS_ADC_BOARD_ADC=y
 CONFIG_DRIVERS_BAROMETER_BMP388=y
-CONFIG_DRIVERS_BAROMETER_INVENSENSE_ICP201XX=y
 CONFIG_DRIVERS_BAROMETER_MS5611=y
-CONFIG_DRIVERS_CAMERA_CAPTURE=y
-CONFIG_DRIVERS_CAMERA_TRIGGER=y
+CONFIG_DRIVERS_IMU_INVENSENSE_ICM42688P=y
+CONFIG_DRIVERS_BAROMETER_INVENSENSE_ICP201XX=y
+CONFIG_DRIVERS_IMU_INVENSENSE_ICM20649=y
 CONFIG_DRIVERS_CDCACM_AUTOSTART=y
 CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
 CONFIG_COMMON_DISTANCE_SENSOR=y
-CONFIG_DRIVERS_DISTANCE_SENSOR_LIGHTWARE_SF45_SERIAL=y
 CONFIG_DRIVERS_DSHOT=y
-CONFIG_DRIVERS_GNSS_SEPTENTRIO=y
 CONFIG_DRIVERS_GPS=y
+CONFIG_DRIVERS_HEATER=y
 CONFIG_DRIVERS_IMU_BOSCH_BMI088=y
-CONFIG_DRIVERS_IMU_INVENSENSE_ICM20948=y
-CONFIG_DRIVERS_IMU_INVENSENSE_ICM42688P=y
 CONFIG_DRIVERS_IMU_INVENSENSE_ICM45686=y
-CONFIG_COMMON_INS=y
+CONFIG_DRIVERS_MAGNETOMETER_QMC5883L=y
+CONFIG_DRIVERS_MAGNETOMETER_BOSCH_BMM150=y
+CONFIG_DRIVERS_GNSS_SEPTENTRIO=y
 CONFIG_COMMON_LIGHT=y
-CONFIG_DRIVERS_LIGHTS_RGBLED_PWM=y
 CONFIG_COMMON_MAGNETOMETER=y
-CONFIG_DRIVERS_MAGNETOMETER_BOSCH_BMM350=y
-CONFIG_COMMON_OPTICAL_FLOW=y
-CONFIG_DRIVERS_OSD_MSP_OSD=y
 CONFIG_DRIVERS_POWER_MONITOR_INA226=y
 CONFIG_DRIVERS_POWER_MONITOR_INA228=y
 CONFIG_DRIVERS_POWER_MONITOR_INA238=y
+CONFIG_DRIVERS_POWER_MONITOR_PM_SELECTOR_AUTERION=y
 CONFIG_DRIVERS_PWM_OUT=y
+CONFIG_DRIVERS_PX4IO=y
 CONFIG_COMMON_RC=y
 CONFIG_DRIVERS_SAFETY_BUTTON=y
-CONFIG_COMMON_TELEMETRY=y
 CONFIG_DRIVERS_TONE_ALARM=y
 CONFIG_DRIVERS_UAVCAN=y
-CONFIG_BOARD_UAVCAN_INTERFACES=1
-CONFIG_COMMON_UWB=y
+CONFIG_BOARD_UAVCAN_TIMER_OVERRIDE=2
 CONFIG_MODULES_AIRSPEED_SELECTOR=y
 CONFIG_MODULES_BATTERY_STATUS=y
 CONFIG_MODULES_CAMERA_FEEDBACK=y
@@ -59,15 +55,14 @@ CONFIG_MODULES_FW_LATERAL_LONGITUDINAL_CONTROL=y
 CONFIG_MODULES_FW_RATE_CONTROL=y
 CONFIG_MODULES_GIMBAL=y
 CONFIG_MODULES_GYRO_CALIBRATION=y
-CONFIG_MODULES_GYRO_FFT=y
 CONFIG_MODULES_LAND_DETECTOR=y
 CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
 CONFIG_MODULES_LOAD_MON=y
-CONFIG_MODULES_LOCAL_POSITION_ESTIMATOR=y
 CONFIG_MODULES_LOGGER=y
 CONFIG_MODULES_MAG_BIAS_ESTIMATOR=y
 CONFIG_MODULES_MANUAL_CONTROL=y
 CONFIG_MODULES_MAVLINK=y
+CONFIG_MAVLINK_DIALECT="development"
 CONFIG_MODULES_MC_ATT_CONTROL=y
 CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=y
 CONFIG_MODULES_MC_HOVER_THRUST_ESTIMATOR=y
@@ -75,35 +70,30 @@ CONFIG_MODULES_MC_POS_CONTROL=y
 CONFIG_MODULES_MC_RATE_CONTROL=y
 CONFIG_MODULES_NAVIGATOR=y
 CONFIG_MODE_NAVIGATOR_VTOL_TAKEOFF=y
-CONFIG_NUM_MISSION_ITMES_SUPPORTED=1000
 CONFIG_MODULES_RC_UPDATE=y
-CONFIG_MODULES_ROVER_POS_CONTROL=y
 CONFIG_MODULES_SENSORS=y
 CONFIG_MODULES_TEMPERATURE_COMPENSATION=y
 CONFIG_MODULES_UXRCE_DDS_CLIENT=y
-CONFIG_MODULES_VTOL_ATT_CONTROL=y
-CONFIG_MODULES_ZENOH=y
+#CONFIG_MODULES_VTOL_ATT_CONTROL=y
 CONFIG_SYSTEMCMDS_ACTUATOR_TEST=y
 CONFIG_SYSTEMCMDS_BSONDUMP=y
 CONFIG_SYSTEMCMDS_DMESG=y
-CONFIG_SYSTEMCMDS_DUMPFILE=y
+CONFIG_SYSTEMCMDS_GPIO=y
+CONFIG_SYSTEMCMDS_HARDFAULT_LOG=y
 CONFIG_SYSTEMCMDS_I2C_LAUNCHER=y
 CONFIG_SYSTEMCMDS_I2CDETECT=y
 CONFIG_SYSTEMCMDS_LED_CONTROL=y
 CONFIG_SYSTEMCMDS_MFT=y
+CONFIG_SYSTEMCMDS_MTD=y
 CONFIG_SYSTEMCMDS_NETMAN=y
 CONFIG_SYSTEMCMDS_NSHTERM=y
 CONFIG_SYSTEMCMDS_PARAM=y
 CONFIG_SYSTEMCMDS_PERF=y
 CONFIG_SYSTEMCMDS_REBOOT=y
-CONFIG_SYSTEMCMDS_SD_BENCH=y
-CONFIG_SYSTEMCMDS_SD_STRESS=y
-CONFIG_SYSTEMCMDS_SERIAL_TEST=y
 CONFIG_SYSTEMCMDS_SYSTEM_TIME=y
 CONFIG_SYSTEMCMDS_TOP=y
 CONFIG_SYSTEMCMDS_TOPIC_LISTENER=y
 CONFIG_SYSTEMCMDS_TUNE_CONTROL=y
 CONFIG_SYSTEMCMDS_UORB=y
-CONFIG_SYSTEMCMDS_USB_CONNECTED=y
 CONFIG_SYSTEMCMDS_VER=y
 CONFIG_SYSTEMCMDS_WORK_QUEUE=y
@@ -1,13 +1,13 @@
 {
-    "board_id": 37,
+    "board_id": 6110,
    "magic": "PX4FWv1",
-    "description": "Firmware for the MR-TROPIC board",
+    "description": "Firmware for the SVehicleE2 board",
    "image": "",
    "build_time": 0,
-    "summary": "MR-TROPIC",
+    "summary": "SVehicleE2",
    "version": "0.1",
    "image_size": 0,
-    "image_maxsize": 3932160,
+    "image_maxsize": 1966080,
    "git_identity": "",
    "board_revision": 0
 }
@@ -3,6 +3,12 @@
 # board specific defaults
 #------------------------------------------------------------------------------

+# By disabling all 3 INA modules, we use the
+# i2c_launcher instead.
+param set-default SENS_EN_INA238 0
+param set-default SENS_EN_INA228 0
+param set-default SENS_EN_INA226 0
+
 # Mavlink ethernet (CFG 1000)
 param set-default MAV_2_CONFIG 1000
 param set-default MAV_2_BROADCAST 1
@@ -12,27 +18,12 @@ param set-default MAV_2_RATE 100000
 param set-default MAV_2_REMOTE_PRT 14550
 param set-default MAV_2_UDP_PRT 14550

-param set-default SENS_EN_INA238 0
-param set-default SENS_EN_INA228 0
-param set-default SENS_EN_INA226 0
+param set-default BAT1_V_DIV 21.5
+param set-default BAT1_A_PER_V 33.33

-param set-default RC_CRSF_PRT_CFG 300
-param set-default RC_CRSF_TEL_EN 1
-param set-default RC_SBUS_PRT_CFG 0
+param set-default SENS_EXT_I2C_PRB 0

-if [ -f "/fs/microsd/ipcfg-eth0" ]
-then
-else
-	netman update -i eth0
-fi
-
-rgbled_pwm start
 safety_button start

-if param greater -s UAVCAN_ENABLE 0
-then
-	ifup can0
-fi
-
-# Start the ESC telemetry
-dshot telemetry -d /dev/ttyS5 -x
+# pwm voltage 3.3V/5V switch
+pwm_voltage_apply start
@@ -0,0 +1,34 @@
+#!/bin/sh
+#
+# SVehicle E2 specific board sensors init
+#------------------------------------------------------------------------------
+
+if param compare -s ADC_ADS1115_EN 1
+then
+	ads1115 start -X
+	board_adc start -n
+else
+	board_adc start
+fi
+
+if param compare SENS_EN_INA228 1
+then
+	# Start Digital power monitors
+	ina228 -X  start
+fi
+
+bmi088 -A -R 4 -s -b 3 start
+bmi088 -G -R 4 -s -b 3 start
+
+icm42688p -R 6 -s start
+
+# Internal SPI bus ICM-20649 (hard-mounted)
+icm20649 -R 14 -s start
+
+# Internal magnetometer on I2c
+rm3100 -I -R 12 start
+
+bmm150 -I -R 4 start
+
+icp201xx -X start
+icp201xx -I -a 0x64 start
@@ -0,0 +1,17 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+config BOARD_HAS_PROBES
+	bool "Board provides GPIO or other Hardware for signaling to timing analyze."
+	default y
+	---help---
+		This board provides GPIO FMU-CH1-5, CAP1-6 as PROBE_1-11 to provide timing signals from selected drivers.
+
+config BOARD_USE_PROBES
+	bool "Enable the use the board provided FMU-CH1-5, CAP1-6 as PROBE_1-11"
+	default n
+	depends on BOARD_HAS_PROBES
+
+	---help---
+		Select to use GPIO FMU-CH1-5, CAP1-6  to provide timing signals from selected drivers.
@@ -9,82 +9,57 @@
 # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
 # CONFIG_DISABLE_PTHREAD is not set
 # CONFIG_SPI_EXCHANGE is not set
+# CONFIG_STM32H7_SYSCFG is not set
 CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD_CUSTOM=y
-CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/nxp/mr-tropic/nuttx-config"
+CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/svehicle/e2/nuttx-config"
 CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
-CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
-CONFIG_ARCH_CHIP="imxrt"
-CONFIG_ARCH_CHIP_IMXRT=y
-CONFIG_ARCH_CHIP_MIMXRT1064DVL6A=y
-CONFIG_ARCH_INTERRUPTSTACK=4096
-CONFIG_ARCH_RAMVECTORS=y
-CONFIG_ARCH_STACKDUMP=y
-CONFIG_ARMV7M_DCACHE=y
-CONFIG_ARMV7M_DTCM=y
+CONFIG_ARCH_BOARD_CUSTOM_NAME="svehicle"
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32H753II=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_INTERRUPTSTACK=768
+CONFIG_ARMV7M_BASEPRI_WAR=y
 CONFIG_ARMV7M_ICACHE=y
-CONFIG_ARMV7M_ITCM=y
 CONFIG_ARMV7M_MEMCPY=y
 CONFIG_ARMV7M_USEBASEPRI=y
-CONFIG_ARM_MPU=y
-CONFIG_ARM_MPU_RESET=y
 CONFIG_BOARDCTL=y
 CONFIG_BOARDCTL_RESET=y
 CONFIG_BOARD_ASSERT_RESET_VALUE=0
 CONFIG_BOARD_INITTHREAD_PRIORITY=254
 CONFIG_BOARD_LATE_INITIALIZE=y
-CONFIG_BOARD_LOOPSPERMSEC=115000
+CONFIG_BOARD_LOOPSPERMSEC=95150
 CONFIG_BOARD_RESET_ON_ASSERT=2
 CONFIG_CDCACM=y
-CONFIG_CDCACM_BULKIN_REQLEN=96
 CONFIG_CDCACM_IFLOWCONTROL=y
-CONFIG_CDCACM_PRODUCTID=0x0025
-CONFIG_CDCACM_PRODUCTSTR="PX4 BL MR-TROPIC"
+CONFIG_CDCACM_PRODUCTID=0x41F8
+CONFIG_CDCACM_PRODUCTSTR="SVehicle BL E2.x"
 CONFIG_CDCACM_RXBUFSIZE=600
 CONFIG_CDCACM_TXBUFSIZE=12000
-CONFIG_CDCACM_VENDORID=0x1FC9
-CONFIG_CDCACM_VENDORSTR="NXP SEMICONDUCTORS"
-CONFIG_DEBUG_ASSERTIONS=y
-CONFIG_DEBUG_ERROR=y
-CONFIG_DEBUG_FEATURES=y
-CONFIG_DEBUG_HARDFAULT_ALERT=y
+CONFIG_CDCACM_VENDORID=0x20A3
+CONFIG_CDCACM_VENDORSTR="SVehicle"
+CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEBUG_TCBINFO=y
-CONFIG_DEBUG_USAGEFAULT=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FDCLONE_DISABLE=y
 CONFIG_FDCLONE_STDIO=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
-CONFIG_IDLETHREAD_STACKSIZE=2048
-CONFIG_IMXRT_EDMA=y
-CONFIG_IMXRT_EDMA_EDBG=y
-CONFIG_IMXRT_EDMA_ELINK=y
-CONFIG_IMXRT_EDMA_NTCD=64
-CONFIG_IMXRT_ITCM=384
-CONFIG_IMXRT_LPUART3=y
-CONFIG_IMXRT_SNVS_LPSRTC=y
-CONFIG_IMXRT_USBDEV=y
+CONFIG_IDLETHREAD_STACKSIZE=750
 CONFIG_INIT_ENTRYPOINT="bootloader_main"
 CONFIG_INIT_STACKSIZE=3194
 CONFIG_LIBC_FLOATINGPOINT=y
 CONFIG_LIBC_LONG_LONG=y
 CONFIG_LIBC_STRERROR=y
-CONFIG_LPUART3_BAUD=57600
-CONFIG_LPUART3_IFLOWCONTROL=y
-CONFIG_LPUART3_OFLOWCONTROL=y
-CONFIG_LPUART3_RXBUFSIZE=600
-CONFIG_LPUART3_RXDMA=y
-CONFIG_LPUART3_TXBUFSIZE=1500
-CONFIG_LPUART3_TXDMA=y
 CONFIG_MEMSET_64BIT=y
 CONFIG_MEMSET_OPTSPEED=y
 CONFIG_PREALLOC_TIMERS=50
 CONFIG_PTHREAD_MUTEX_ROBUST=y
 CONFIG_PTHREAD_STACK_MIN=512
-CONFIG_RAM_SIZE=1048576
-CONFIG_RAM_START=0x20200000
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
 CONFIG_RAW_BINARY=y
 CONFIG_SERIAL_TERMIOS=y
 CONFIG_SIG_DEFAULT=y
@@ -96,12 +71,25 @@ CONFIG_STACK_COLORATION=y
 CONFIG_START_DAY=30
 CONFIG_START_MONTH=11
 CONFIG_STDIO_BUFFER_SIZE=32
+CONFIG_STM32H7_BKPSRAM=y
+CONFIG_STM32H7_DMA1=y
+CONFIG_STM32H7_DMA2=y
+CONFIG_STM32H7_OTGFS=y
+CONFIG_STM32H7_PROGMEM=y
+CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
+CONFIG_STM32H7_TIM1=y
+CONFIG_STM32H7_UART5=y
 CONFIG_SYSTEMTICK_HOOK=y
 CONFIG_SYSTEM_CDCACM=y
 CONFIG_TASK_NAME_SIZE=24
+CONFIG_TTY_SIGINT=y
+CONFIG_TTY_SIGINT_CHAR=0x03
+CONFIG_TTY_SIGTSTP=y
+CONFIG_UART5_RXBUFSIZE=512
+CONFIG_UART5_RXDMA=y
+CONFIG_UART5_TXBUFSIZE=512
+CONFIG_UART5_TXDMA=y
 CONFIG_USBDEV=y
 CONFIG_USBDEV_BUSPOWERED=y
-CONFIG_USBDEV_DMA=y
-CONFIG_USBDEV_DUALSPEED=y
 CONFIG_USBDEV_MAXPOWER=500
 CONFIG_USEC_PER_TICK=1000
@@ -0,0 +1,562 @@
+/************************************************************************************
+ * nuttx-configs/px4_fmu-v6x/include/board.h
+ *
+ *   Copyright (C) 2016-2019 Gregory Nutt. All rights reserved.
+ *   Authors: David Sidrane <david.sidrane@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+#ifndef __NUTTX_CONFIG_PX4_FMU_V6X_INCLUDE_BOARD_H
+#define __NUTTX_CONFIG_PX4_FMU_V6X_INCLUDE_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include "board_dma_map.h"
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+#include "stm32_rcc.h"
+#include "stm32_sdmmc.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+/* The px4_fmu-v6X  board provides the following clock sources:
+ *
+ *   X1: 16 MHz crystal for HSE
+ *
+ * So we have these clock source available within the STM32
+ *
+ *   HSI: 16 MHz RC factory-trimmed
+ *   HSE: 16 MHz crystal for HSE
+ */
+
+#define STM32_BOARD_XTAL        16000000ul
+
+#define STM32_HSI_FREQUENCY     16000000ul
+#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 16,000,000
+ *
+ * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ *     1 <= PLLM <= 63
+ *     4 <= PLLN <= 512
+ *   150 MHz <= PLL_VCOL <= 420MHz
+ *   192 MHz <= PLL_VCOH <= 836MHz
+ *
+ * SYSCLK  = PLL_VCO / PLLP
+ * CPUCLK  = SYSCLK / D1CPRE
+ * Subject to
+ *
+ *   PLLP1   = {2, 4, 6, 8, ..., 128}
+ *   PLLP2,3 = {2, 3, 4, ..., 128}
+ *   CPUCLK <= 480 MHz
+ */
+
+#define STM32_BOARD_USEHSE
+
+#define STM32_PLLCFG_PLLSRC      RCC_PLLCKSELR_PLLSRC_HSE
+
+/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
+ *
+ *   PLL1_VCO = (16,000,000 / 1) * 60 = 960 MHz
+ *
+ *   PLL1P = PLL1_VCO/2  = 960 MHz / 2   = 480 MHz
+ *   PLL1Q = PLL1_VCO/4  = 960 MHz / 4   = 240 MHz
+ *   PLL1R = PLL1_VCO/8  = 960 MHz / 8   = 120 MHz
+ */
+
+#define STM32_PLLCFG_PLL1CFG    (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
+				 RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \
+				 RCC_PLLCFGR_DIVP1EN | \
+				 RCC_PLLCFGR_DIVQ1EN | \
+				 RCC_PLLCFGR_DIVR1EN)
+#define STM32_PLLCFG_PLL1M       RCC_PLLCKSELR_DIVM1(1)
+#define STM32_PLLCFG_PLL1N       RCC_PLL1DIVR_N1(60)
+#define STM32_PLLCFG_PLL1P       RCC_PLL1DIVR_P1(2)
+#define STM32_PLLCFG_PLL1Q       RCC_PLL1DIVR_Q1(4)
+#define STM32_PLLCFG_PLL1R       RCC_PLL1DIVR_R1(8)
+
+#define STM32_VCO1_FREQUENCY     ((STM32_HSE_FREQUENCY / 1) * 60)
+#define STM32_PLL1P_FREQUENCY    (STM32_VCO1_FREQUENCY / 2)
+#define STM32_PLL1Q_FREQUENCY    (STM32_VCO1_FREQUENCY / 4)
+#define STM32_PLL1R_FREQUENCY    (STM32_VCO1_FREQUENCY / 8)
+
+/* PLL2 */
+
+#define STM32_PLLCFG_PLL2CFG     (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \
+				  RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \
+				  RCC_PLLCFGR_DIVP2EN | \
+				  RCC_PLLCFGR_DIVQ2EN | \
+				  RCC_PLLCFGR_DIVR2EN)
+#define STM32_PLLCFG_PLL2M       RCC_PLLCKSELR_DIVM2(4)
+#define STM32_PLLCFG_PLL2N       RCC_PLL2DIVR_N2(48)
+#define STM32_PLLCFG_PLL2P       RCC_PLL2DIVR_P2(2)
+#define STM32_PLLCFG_PLL2Q       RCC_PLL2DIVR_Q2(2)
+#define STM32_PLLCFG_PLL2R       RCC_PLL2DIVR_R2(2)
+
+#define STM32_VCO2_FREQUENCY     ((STM32_HSE_FREQUENCY / 4) * 48)
+#define STM32_PLL2P_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
+#define STM32_PLL2Q_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
+#define STM32_PLL2R_FREQUENCY    (STM32_VCO2_FREQUENCY / 2)
+
+/* PLL3 */
+
+#define STM32_PLLCFG_PLL3CFG    (RCC_PLLCFGR_PLL3VCOSEL_WIDE | \
+				 RCC_PLLCFGR_PLL3RGE_4_8_MHZ | \
+				 RCC_PLLCFGR_DIVQ3EN)
+#define STM32_PLLCFG_PLL3M      RCC_PLLCKSELR_DIVM3(4)
+#define STM32_PLLCFG_PLL3N      RCC_PLL3DIVR_N3(48)
+#define STM32_PLLCFG_PLL3P      RCC_PLL3DIVR_P3(2)
+#define STM32_PLLCFG_PLL3Q      RCC_PLL3DIVR_Q3(4)
+#define STM32_PLLCFG_PLL3R      RCC_PLL3DIVR_R3(2)
+
+#define STM32_VCO3_FREQUENCY    ((STM32_HSE_FREQUENCY / 4) * 48)
+#define STM32_PLL3P_FREQUENCY   (STM32_VCO3_FREQUENCY / 2)
+#define STM32_PLL3Q_FREQUENCY   (STM32_VCO3_FREQUENCY / 4)
+#define STM32_PLL3R_FREQUENCY   (STM32_VCO3_FREQUENCY / 2)
+
+/* SYSCLK = PLL1P = 480MHz
+ * CPUCLK = SYSCLK / 1 = 480 MHz
+ */
+
+#define STM32_RCC_D1CFGR_D1CPRE  (RCC_D1CFGR_D1CPRE_SYSCLK)
+#define STM32_SYSCLK_FREQUENCY   (STM32_PLL1P_FREQUENCY)
+#define STM32_CPUCLK_FREQUENCY   (STM32_SYSCLK_FREQUENCY / 1)
+
+/* Configure Clock Assignments */
+
+/* AHB clock (HCLK) is SYSCLK/2 (240 MHz max)
+ * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 240
+ */
+
+#define STM32_RCC_D1CFGR_HPRE   RCC_D1CFGR_HPRE_SYSCLKd2        /* HCLK  = SYSCLK / 2 */
+#define STM32_ACLK_FREQUENCY    (STM32_CPUCLK_FREQUENCY / 2)    /* ACLK in D1, HCLK3 in D1 */
+#define STM32_HCLK_FREQUENCY    (STM32_CPUCLK_FREQUENCY / 2)    /* HCLK in D2, HCLK4 in D3 */
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY            /* same as above, to satisfy compiler */
+
+/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */
+
+#define STM32_RCC_D2CFGR_D2PPRE1  RCC_D2CFGR_D2PPRE1_HCLKd2       /* PCLK1 = HCLK / 2 */
+#define STM32_PCLK1_FREQUENCY     (STM32_HCLK_FREQUENCY/2)
+
+/* APB2 clock (PCLK2) is HCLK/2 (120 MHz) */
+
+#define STM32_RCC_D2CFGR_D2PPRE2  RCC_D2CFGR_D2PPRE2_HCLKd2       /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY     (STM32_HCLK_FREQUENCY/2)
+
+/* APB3 clock (PCLK3) is HCLK/2 (120 MHz) */
+
+#define STM32_RCC_D1CFGR_D1PPRE   RCC_D1CFGR_D1PPRE_HCLKd2        /* PCLK3 = HCLK / 2 */
+#define STM32_PCLK3_FREQUENCY     (STM32_HCLK_FREQUENCY/2)
+
+/* APB4 clock (PCLK4) is HCLK/4 (120 MHz) */
+
+#define STM32_RCC_D3CFGR_D3PPRE   RCC_D3CFGR_D3PPRE_HCLKd2       /* PCLK4 = HCLK / 2 */
+#define STM32_PCLK4_FREQUENCY     (STM32_HCLK_FREQUENCY/2)
+
+/* Timer clock frequencies */
+
+/* Timers driven from APB1 will be twice PCLK1 */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
+/* Timers driven from APB2 will be twice PCLK2 */
+
+#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM15_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM16_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM17_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+
+/* Kernel Clock Configuration
+ *
+ * Note: look at Table 54 in ST Manual
+ */
+
+/* I2C123 clock source */
+
+#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI
+
+/* I2C4 clock source */
+
+#define STM32_RCC_D3CCIPR_I2C4SRC    RCC_D3CCIPR_I2C4SEL_HSI
+
+/* SPI123 clock source */
+
+#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL2
+
+/* SPI45 clock source */
+
+#define STM32_RCC_D2CCIP1R_SPI45SRC  RCC_D2CCIP1R_SPI45SEL_PLL2
+
+/* SPI6 clock source */
+
+#define STM32_RCC_D3CCIPR_SPI6SRC    RCC_D3CCIPR_SPI6SEL_PLL2
+
+/* USB 1 and 2 clock source */
+
+#define STM32_RCC_D2CCIP2R_USBSRC    RCC_D2CCIP2R_USBSEL_PLL3
+
+/* ADC 1 2 3 clock source */
+
+#define STM32_RCC_D3CCIPR_ADCSRC     RCC_D3CCIPR_ADCSEL_PLL2
+
+/* UART clock selection */
+/* reset to default to overwrite any changes done by any bootloader */
+
+#define STM32_RCC_D2CCIP2R_USART234578_SEL RCC_D2CCIP2R_USART234578SEL_RCC
+#define STM32_RCC_D2CCIP2R_USART16_SEL     RCC_D2CCIP2R_USART16SEL_RCC
+
+/* FDCAN 1 2 clock source */
+
+#define STM32_RCC_D2CCIP1R_FDCANSEL  RCC_D2CCIP1R_FDCANSEL_HSE   /* FDCAN 1 2 clock source */
+
+#define STM32_FDCANCLK               STM32_HSE_FREQUENCY
+
+/* FLASH wait states
+ *
+ *  ------------ ---------- -----------
+ *  Vcore        MAX ACLK   WAIT STATES
+ *  ------------ ---------- -----------
+ *  1.15-1.26 V     70 MHz    0
+ *  (VOS1 level)   140 MHz    1
+ *                 210 MHz    2
+ *  1.05-1.15 V     55 MHz    0
+ *  (VOS2 level)   110 MHz    1
+ *                 165 MHz    2
+ *                 220 MHz    3
+ *  0.95-1.05 V     45 MHz    0
+ *  (VOS3 level)    90 MHz    1
+ *                 135 MHz    2
+ *                 180 MHz    3
+ *                 225 MHz    4
+ *  ------------ ---------- -----------
+ */
+
+#define BOARD_FLASH_WAITSTATES 2
+
+/* SDMMC definitions ********************************************************/
+
+/* Init 400kHz, freq = PLL1Q/(2*div)  div =  PLL1Q/(2*freq) */
+
+#define STM32_SDMMC_INIT_CLKDIV     (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+
+/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div =  PLL1Q/(2*freq)
+ * div = 4.8 = 240 / 50, So round up to 5 for default speed 24 MB/s
+ */
+
+#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA)
+#  define STM32_SDMMC_MMCXFR_CLKDIV   (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#else
+#  define STM32_SDMMC_MMCXFR_CLKDIV   (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#endif
+#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA)
+#  define STM32_SDMMC_SDXFR_CLKDIV    (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#else
+#  define STM32_SDMMC_SDXFR_CLKDIV    (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#endif
+
+#define STM32_SDMMC_CLKCR_EDGE      STM32_SDMMC_CLKCR_NEGEDGE
+
+/* LED definitions ******************************************************************/
+/* The PX4 FMUV6X board has three, LED_GREEN a Green LED, LED_BLUE a Blue LED and
+ * LED_RED a Red LED, that can be controlled by software.
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
+ * The following definitions are used to access individual LEDs.
+ */
+
+/* LED index values for use with board_userled() */
+
+/* LED definitions ******************************************************************/
+/* The px4_fmu-v6x board has three, LED_GREEN a Green LED, LED_BLUE a Blue LED and
+ * LED_RED a Red LED, that can be controlled by software.
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
+ * The following definitions are used to access individual LEDs.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED1        0
+#define BOARD_LED2        1
+#define BOARD_LED3        2
+#define BOARD_NLEDS       3
+
+#define BOARD_LED_RED     BOARD_LED1
+#define BOARD_LED_GREEN   BOARD_LED2
+#define BOARD_LED_BLUE    BOARD_LED3
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED1_BIT    (1 << BOARD_LED1)
+#define BOARD_LED2_BIT    (1 << BOARD_LED2)
+#define BOARD_LED3_BIT    (1 << BOARD_LED3)
+
+/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
+ * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
+ * events as follows:
+ *
+ *
+ *   SYMBOL                     Meaning                      LED state
+ *                                                        Red   Green Blue
+ *   ----------------------  --------------------------  ------ ------ ----*/
+
+#define LED_STARTED        0 /* NuttX has been started   OFF    OFF   OFF  */
+#define LED_HEAPALLOCATE   1 /* Heap has been allocated  OFF    OFF   ON   */
+#define LED_IRQSENABLED    2 /* Interrupts enabled       OFF    ON    OFF  */
+#define LED_STACKCREATED   3 /* Idle stack created       OFF    ON    ON   */
+#define LED_INIRQ          4 /* In an interrupt          N/C    N/C   GLOW */
+#define LED_SIGNAL         5 /* In a signal handler      N/C    GLOW  N/C  */
+#define LED_ASSERTION      6 /* An assertion failed      GLOW   N/C   GLOW */
+#define LED_PANIC          7 /* The system has crashed   Blink  OFF   N/C  */
+#define LED_IDLE           8 /* MCU is is sleep mode     ON     OFF   OFF  */
+
+/* Thus if the Green LED is statically on, NuttX has successfully booted and
+ * is, apparently, running normally.  If the Red LED is flashing at
+ * approximately 2Hz, then a fatal error has been detected and the system
+ * has halted.
+ */
+
+/* Alternate function pin selections ************************************************/
+
+#define GPIO_USART1_RX   GPIO_USART1_RX_3      /* PB7 */
+#define GPIO_USART1_TX   GPIO_USART1_TX_3      /* PB6 */
+
+#define GPIO_USART2_RX   GPIO_USART2_RX_1       /* PA3   */
+#define GPIO_USART2_TX   GPIO_USART2_TX_2       /* PD5   */
+#define GPIO_USART2_RTS  GPIO_USART2_RTS_2      /* PD4   */
+#define GPIO_USART2_CTS  GPIO_USART2_CTS_NSS_2  /* PD3   */
+
+#define GPIO_USART3_RX   GPIO_USART3_RX_3   /* PD9   */
+#define GPIO_USART3_TX   GPIO_USART3_TX_3   /* PD8   */
+
+#define GPIO_UART4_RX    GPIO_UART4_RX_6    /* PH14 */
+#define GPIO_UART4_TX    GPIO_UART4_TX_6    /* PH13 */
+
+#define GPIO_UART5_RX    GPIO_UART5_RX_3    /* PD2  */
+#define GPIO_UART5_TX    GPIO_UART5_TX_3    /* PC12 */
+#undef GPIO_UART5_CTS
+#define GPIO_UART5_CTS   ((GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN9) | GPIO_PULLDOWN) /* PC9  */
+
+#define GPIO_USART6_RX   GPIO_USART6_RX_1   /* PC7 */
+#define GPIO_USART6_TX   GPIO_USART6_TX_1   /* PC6  */
+
+#define GPIO_UART7_RX    GPIO_UART7_RX_4    /* PF6  */
+#define GPIO_UART7_TX    GPIO_UART7_TX_3    /* PE8  */
+#define GPIO_UART7_RTS   (GPIO_UART7_RTS_2 | GPIO_PULLDOWN)   /* PF8  */
+#define GPIO_UART7_CTS   (GPIO_UART7_CTS_1 | GPIO_PULLDOWN)   /* PE10 */
+
+#define GPIO_UART8_RX    GPIO_UART8_RX_1    /* PE0 */
+#define GPIO_UART8_TX    GPIO_UART8_TX_1    /* PE1 */
+
+
+/* CAN
+ *
+ * CAN1 is routed to transceiver.
+ * CAN2 is routed to transceiver.
+ */
+#define GPIO_CAN1_RX     GPIO_CAN1_RX_3     /* PD0  */
+#define GPIO_CAN1_TX     GPIO_CAN1_TX_3     /* PD1  */
+#define GPIO_CAN2_RX     GPIO_CAN2_RX_1     /* PB12 */
+#define GPIO_CAN2_TX     GPIO_CAN2_TX_1     /* PB13  */
+
+/* SPI
+ * SPI1 is sensors1
+ * SPI2 is sensors2
+ * SPI3 is sensors3
+ * SPI4 is Not Used
+ * SPI5 is FRAM
+ * SPI6 is EXTERNAL1
+ *
+ */
+
+#define ADJ_SLEW_RATE(p) (((p) & ~GPIO_SPEED_MASK) | (GPIO_SPEED_2MHz))
+
+#define GPIO_SPI1_MISO   GPIO_SPI1_MISO_3               /* PG9  */
+#define GPIO_SPI1_MOSI   GPIO_SPI1_MOSI_2               /* PB5  */
+#define GPIO_SPI1_SCK    ADJ_SLEW_RATE(GPIO_SPI1_SCK_1) /* PA5  */
+
+#define GPIO_SPI2_MISO   GPIO_SPI2_MISO_3               /* PI2  */
+#define GPIO_SPI2_MOSI   GPIO_SPI2_MOSI_4               /* PI3  */
+#define GPIO_SPI2_SCK    ADJ_SLEW_RATE(GPIO_SPI2_SCK_6) /* PI1  */
+
+#define GPIO_SPI3_MISO   GPIO_SPI3_MISO_2               /* PC11 */
+#define GPIO_SPI3_MOSI   GPIO_SPI3_MOSI_3               /* PB2  */
+#define GPIO_SPI3_SCK    ADJ_SLEW_RATE(GPIO_SPI3_SCK_2) /* PC10 */
+
+#define GPIO_SPI5_MISO   GPIO_SPI5_MISO_2               /* PH7  */
+#define GPIO_SPI5_MOSI   GPIO_SPI5_MOSI_1               /* PF11 */
+#define GPIO_SPI5_SCK    ADJ_SLEW_RATE(GPIO_SPI5_SCK_1) /* PF7  */
+
+#define GPIO_SPI6_MISO   GPIO_SPI6_MISO_2               /* PA6  */
+#define GPIO_SPI6_MOSI   GPIO_SPI6_MOSI_1               /* PG14 */
+#define GPIO_SPI6_SCK    ADJ_SLEW_RATE(GPIO_SPI6_SCK_3) /* PB3  */
+
+/* I2C
+ *
+ *   The optional _GPIO configurations allow the I2C driver to manually
+ *   reset the bus to clear stuck slaves.  They match the pin configuration,
+ *   but are normally-high GPIOs.
+ *
+ */
+
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2       /* PB8  */
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2       /* PB9  */
+
+#define GPIO_I2C1_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_I2C1_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
+
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2       /* PF1 */
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2       /* PF0 */
+
+#define GPIO_I2C2_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN1)
+#define GPIO_I2C2_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN0)
+
+#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1       /* PA8 */
+#define GPIO_I2C3_SDA GPIO_I2C3_SDA_2       /* PH8 */
+
+#define GPIO_I2C3_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_I2C3_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN8)
+
+#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2       /* PF14 */
+#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2       /* PF15 */
+
+#define GPIO_I2C4_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN14)
+#define GPIO_I2C4_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN15)
+
+/* SDMMC2
+ *
+ *      VDD 3.3
+ *      GND
+ *      SDMMC2_CK                           PD6
+ *      SDMMC2_CMD                          PD7
+ *      SDMMC2_D0                           PB14
+ *      SDMMC2_D1                           PB15
+ *      SDMMC2_D2                           PG11
+ *      SDMMC2_D3                           PB4
+ */
+
+#define GPIO_SDMMC2_CK   GPIO_SDMMC2_CK_1  /* PD6 */
+#define GPIO_SDMMC2_CMD  GPIO_SDMMC2_CMD_1 /* PD7 */
+//      GPIO_SDMMC2_D0   No Remap          /* PB14 */
+//      GPIO_SDMMC2_D1   No Remap          /* PB15 */
+#define GPIO_SDMMC2_D2   GPIO_SDMMC2_D2_1  /* PG11 */
+//      GPIO_SDMMC2_D3    No Remap         /* PB4 */
+
+/* The STM32 H7 connects to a TI DP83848TSQ/NOPB
+ * using RMII
+ *
+ *   STM32 H7 BOARD        DP83848TSQ/NOPB
+ *   GPIO     SIGNAL       PIN NAME
+ *   -------- ------------ -------------
+ *   PA7     ETH_CRS_DV    CRS_DV
+ *   PC1     ETH_MDC       MDC
+ *   PA2     ETH_MDIO      MDIO
+ *   PA1     ETH_REF_CL    X1
+ *   PC4     ETH_RXD0      RX_D0
+ *   PC5     ETH_RXD1      RX_D1
+ *   PB11    ETH_TX_EN     TX_EN
+ *   PG13    ETH_TXD0      TX_D0
+ *   PG12    ETH_TXD1      TX_D1
+ *
+ * The PHY address is 1, since COL/PHYAD0 features a pull up.
+ */
+
+#define GPIO_ETH_RMII_TX_EN	GPIO_ETH_RMII_TX_EN_1 /* PB11 */
+#define GPIO_ETH_RMII_TXD0	GPIO_ETH_RMII_TXD0_2  /* PG13 */
+#define GPIO_ETH_RMII_TXD1	GPIO_ETH_RMII_TXD1_2  /* PG12 */
+
+
+/* USB
+ *
+ *      OTG_FS_DM                           PA11
+ *      OTG_FS_DP                           PA12
+ *      VBUS                                PA9
+ */
+
+
+/* Board provides GPIO or other Hardware for signaling to timing analyzer */
+
+#if defined(CONFIG_BOARD_USE_PROBES)
+# include "stm32_gpio.h"
+# define PROBE_N(n) (1<<((n)-1))
+# define PROBE_1    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTI|GPIO_PIN0)   /* PI0 AUX1 */
+# define PROBE_2    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN12)  /* PH12 AUX2 */
+# define PROBE_3    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN11)  /* PH11 AUX3 */
+# define PROBE_4    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN10)  /* PH10 AUX4 */
+# define PROBE_5    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN13)  /* PD13 AUX5 */
+# define PROBE_6    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN14)  /* PD14 AUX6 */
+# define PROBE_7    (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11)  /* PE11  CAP1 */
+
+# define PROBE_INIT(mask) \
+	do { \
+		if ((mask)& PROBE_N(1)) { stm32_configgpio(PROBE_1); } \
+		if ((mask)& PROBE_N(2)) { stm32_configgpio(PROBE_2); } \
+		if ((mask)& PROBE_N(3)) { stm32_configgpio(PROBE_3); } \
+		if ((mask)& PROBE_N(4)) { stm32_configgpio(PROBE_4); } \
+		if ((mask)& PROBE_N(5)) { stm32_configgpio(PROBE_5); } \
+		if ((mask)& PROBE_N(6)) { stm32_configgpio(PROBE_6); } \
+		if ((mask)& PROBE_N(7)) { stm32_configgpio(PROBE_7); } \
+		if ((mask)& PROBE_N(8)) { stm32_configgpio(PROBE_8); } \
+		if ((mask)& PROBE_N(9)) { stm32_configgpio(PROBE_9); } \
+	} while(0)
+
+# define PROBE(n,s)  do {stm32_gpiowrite(PROBE_##n,(s));}while(0)
+# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true)
+#else
+# define PROBE_INIT(mask)
+# define PROBE(n,s)
+# define PROBE_MARK(n)
+#endif
+
+#endif  /*__NUTTX_CONFIG_PX4_FMU_V6X_INCLUDE_BOARD_H  */
@@ -0,0 +1,87 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2020 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#pragma once
+
+// DMAMUX1 Using at most 8 Channels on DMA1 --------   Assigned
+//                                                     V
+
+#define DMAMAP_SPI1_RX    DMAMAP_DMA12_SPI1RX_0     /* 1 DMA1:37 ICM-20649 */
+#define DMAMAP_SPI1_TX    DMAMAP_DMA12_SPI1TX_0     /* 2 DMA1:38 ICM-20649 */
+
+#define DMAMAP_SPI2_RX    DMAMAP_DMA12_SPI2RX_0     /* 3 DMA1:39 ICM-42688-P */
+#define DMAMAP_SPI2_TX    DMAMAP_DMA12_SPI2TX_0     /* 4 DMA1:40 ICM-42688-P */
+
+//#define DMAMAP_USART1_RX  DMAMAP_DMA12_USART1RX_0 /*  DMA1:41  GPS1 */
+//#define DMAMAP_USART1_TX  DMAMAP_DMA12_USART1TX_0 /*  DMA1:42  GPS1 */
+
+//#define DMAMAP_USART2_RX  DMAMAP_DMA12_USART2RX_0 /*  DMA1:43 Telem3 */
+//#define DMAMAP_USART2_TX  DMAMAP_DMA12_USART2TX_0 /*  DMA1:44 Telem3 */
+
+//#define DMAMAP_USART3_RX  DMAMAP_DMA12_USART3RX_0 /*  DMA1:45 DEBUG */
+//#define DMAMAP_USART3_TX  DMAMAP_DMA12_USART3TX_0 /*  DMA1:46 DEBUG */
+
+//#define DMAMAP_UART4_RX   DMAMAP_DMA12_UART4RX_0  /*  DMA1:63 EXT2 */
+//#define DMAMAP_UART4_TX   DMAMAP_DMA12_UART4TX_0  /*  DMA1:64 EXT2 */
+
+#define DMAMAP_USART6_RX  DMAMAP_DMA12_USART6RX_0   /* 5 DMA1:71 PX4IO */
+#define DMAMAP_USART6_TX  DMAMAP_DMA12_USART6TX_0   /* 6 DMA1:72 PX4IO */
+
+// Assigned in timer_config.cpp
+
+// Timer 4                                          /* 7 DMA1:32 TIM4UP */
+// Timer 5                                          /* 8 DMA1:50 TIM5UP */
+
+// DMAMUX2 Using at most 8 Channels on DMA2 --------   Assigned
+//                                                     V
+
+#define DMAMAP_SPI3_RX    DMAMAP_DMA12_SPI3RX_1     /* 1 DMA2:61 BMI088 */
+#define DMAMAP_SPI3_TX    DMAMAP_DMA12_SPI3TX_1     /* 2 DMA2:62 BMI088 */
+
+#define DMAMAP_USART3_RX  DMAMAP_DMA12_USART3RX_1   /* 3 DMA2:45 DEBUG */
+#define DMAMAP_USART3_TX  DMAMAP_DMA12_USART3TX_1   /* 4 DMA2:46 DEBUG */
+
+#define DMAMAP_UART5_RX   DMAMAP_DMA12_UART5RX_1    /* 5 DMA2:65 TELEM2 */
+#define DMAMAP_UART5_TX   DMAMAP_DMA12_UART5TX_1    /* 6 DMA2:66  TELEM2 */
+
+#define DMAMAP_UART7_RX   DMAMAP_DMA12_UART7RX_1    /* 7 DMA1:79  TELEM1 */
+#define DMAMAP_UART7_TX   DMAMAP_DMA12_UART7TX_1    /* 8 DMA1:80  TELEM1 */
+
+//#define DMAMAP_UART8_RX   DMAMAP_DMA12_UART8RX_1  /*  DMA1:81  GPS2 */
+//#define DMAMAP_UART8_TX   DMAMAP_DMA12_UART8TX_1  /*  DMA1:82  GPS2 */
+
+// DMAMUX2 Using at most 8 Channels on BDMA --------   Assigned
+//                                                     V
+
+#define DMAMAP_SPI6_RX    DMAMAP_BDMA_SPI6_RX       /* 1 BDMA:11 SPI J11 */
+#define DMAMAP_SPI6_TX    DMAMAP_BDMA_SPI6_TX       /* 2 BDMA:12 SPI J11 */
@@ -0,0 +1,330 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_DISABLE_ENVIRON is not set
+# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
+# CONFIG_DISABLE_PTHREAD is not set
+# CONFIG_MMCSD_HAVE_CARDDETECT is not set
+# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set
+# CONFIG_MMCSD_MMCSUPPORT is not set
+# CONFIG_MMCSD_SPI is not set
+# CONFIG_NSH_DISABLEBG is not set
+# CONFIG_NSH_DISABLESCRIPT is not set
+# CONFIG_NSH_DISABLE_ARP is not set
+# CONFIG_NSH_DISABLE_CAT is not set
+# CONFIG_NSH_DISABLE_CD is not set
+# CONFIG_NSH_DISABLE_CP is not set
+# CONFIG_NSH_DISABLE_DATE is not set
+# CONFIG_NSH_DISABLE_DF is not set
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_ENV is not set
+# CONFIG_NSH_DISABLE_EXEC is not set
+# CONFIG_NSH_DISABLE_EXPORT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+# CONFIG_NSH_DISABLE_GET is not set
+# CONFIG_NSH_DISABLE_HELP is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_IFUPDOWN is not set
+# CONFIG_NSH_DISABLE_ITEF is not set
+# CONFIG_NSH_DISABLE_KILL is not set
+# CONFIG_NSH_DISABLE_LOOPS is not set
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFATFS is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MV is not set
+# CONFIG_NSH_DISABLE_NSLOOKUP is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set
+# CONFIG_NSH_DISABLE_PWD is not set
+# CONFIG_NSH_DISABLE_RM is not set
+# CONFIG_NSH_DISABLE_RMDIR is not set
+# CONFIG_NSH_DISABLE_SEMICOLON is not set
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+# CONFIG_NSH_DISABLE_SOURCE is not set
+# CONFIG_NSH_DISABLE_TELNETD is not set
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_TIME is not set
+# CONFIG_NSH_DISABLE_UMOUNT is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD_CUSTOM=y
+CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/svehicle/e2/nuttx-config"
+CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
+CONFIG_ARCH_BOARD_CUSTOM_NAME="svehicle"
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32H753II=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_INTERRUPTSTACK=768
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_BASEPRI_WAR=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_MEMCPY=y
+CONFIG_ARMV7M_USEBASEPRI=y
+CONFIG_ARM_MPU_EARLY_RESET=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_ASSERT_RESET_VALUE=0
+CONFIG_BOARD_CRASHDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=95751
+CONFIG_BOARD_RESET_ON_ASSERT=2
+CONFIG_BUILTIN=y
+CONFIG_CDCACM=y
+CONFIG_CDCACM_IFLOWCONTROL=y
+CONFIG_CDCACM_PRODUCTID=0x41F8
+CONFIG_CDCACM_PRODUCTSTR="SVehicle E2.x"
+CONFIG_CDCACM_RXBUFSIZE=600
+CONFIG_CDCACM_TXBUFSIZE=12000
+CONFIG_CDCACM_VENDORID=0x20A3
+CONFIG_CDCACM_VENDORSTR="SVehicle"
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_HARDFAULT_ALERT=y
+CONFIG_DEBUG_MEMFAULT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_TCBINFO=y
+CONFIG_DEFAULT_SMALL=y
+CONFIG_DEV_FIFO_SIZE=0
+CONFIG_DEV_PIPE_MAXSIZE=1024
+CONFIG_DEV_PIPE_SIZE=70
+CONFIG_ETH0_PHY_LAN8742A=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_FAT_DMAMEMORY=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FAT_LFN=y
+CONFIG_FAT_LFN_ALIAS_HASH=y
+CONFIG_FDCLONE_STDIO=y
+CONFIG_FSUTILS_IPCFG=y
+CONFIG_FS_BINFS=y
+CONFIG_FS_CROMFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FATTIME=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_INCLUDE_PROGMEM=y
+CONFIG_FS_PROCFS_MAX_TASKS=64
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_FS_ROMFS=y
+CONFIG_GRAN=y
+CONFIG_GRAN_INTR=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2C_RESET=y
+CONFIG_IDLETHREAD_STACKSIZE=750
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=3194
+CONFIG_IOB_NBUFFERS=24
+CONFIG_IOB_THROTTLE=0
+CONFIG_IPCFG_BINARY=y
+CONFIG_IPCFG_CHARDEV=y
+CONFIG_IPCFG_PATH="/fs/mtd_net"
+CONFIG_LIBC_FLOATINGPOINT=y
+CONFIG_LIBC_LONG_LONG=y
+CONFIG_LIBC_MAX_EXITFUNS=1
+CONFIG_LIBC_STRERROR=y
+CONFIG_MEMSET_64BIT=y
+CONFIG_MEMSET_OPTSPEED=y
+CONFIG_MMCSD=y
+CONFIG_MMCSD_SDIO=y
+CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y
+CONFIG_MM_REGIONS=4
+CONFIG_MTD=y
+CONFIG_MTD_BYTE_WRITE=y
+CONFIG_MTD_PARTITION=y
+CONFIG_MTD_PROGMEM=y
+CONFIG_MTD_RAMTRON=y
+CONFIG_NAME_MAX=40
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETDB_DNSCLIENT_ENTRIES=8
+CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETDEV_PHY_IOCTL=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DNS=y
+CONFIG_NETINIT_DNSIPADDR=0xA290AFE
+CONFIG_NETINIT_DRIPADDR=0xA290AFE
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
+CONFIG_NETINIT_THREAD_PRIORITY=49
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NET_ARP_IPIN=y
+CONFIG_NET_ARP_SEND=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ETH_PKTSIZE=1518
+CONFIG_NET_ICMP=y
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_NACTIVESOCKETS=16
+CONFIG_NET_SOLINGER=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TCPBACKLOG=y
+CONFIG_NET_TCP_DELAYED_ACK=y
+CONFIG_NET_TCP_WRITE_BUFFERS=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_CHECKSUMS=y
+CONFIG_NET_UDP_WRITE_BUFFERS=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_ARGCAT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_CMDPARMS=y
+CONFIG_NSH_CROMFSETC=y
+CONFIG_NSH_LINELEN=128
+CONFIG_NSH_MAXARGUMENTS=15
+CONFIG_NSH_NESTDEPTH=8
+CONFIG_NSH_QUOTE=y
+CONFIG_NSH_ROMFSETC=y
+CONFIG_NSH_ROMFSSECTSIZE=128
+CONFIG_NSH_STRERROR=y
+CONFIG_NSH_TELNET=y
+CONFIG_NSH_TELNET_LOGIN=y
+CONFIG_NSH_VARS=y
+CONFIG_OTG_ID_GPIO_DISABLE=y
+CONFIG_PIPES=y
+CONFIG_PREALLOC_TIMERS=50
+CONFIG_PRIORITY_INHERITANCE=y
+CONFIG_PTHREAD_MUTEX_ROBUST=y
+CONFIG_PTHREAD_STACK_MIN=512
+CONFIG_RAMTRON_EMULATE_PAGE_SHIFT=5
+CONFIG_RAMTRON_EMULATE_SECTOR_SHIFT=5
+CONFIG_RAMTRON_SETSPEED=y
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_RTC_DATETIME=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_HPWORKPRIORITY=249
+CONFIG_SCHED_HPWORKSTACKSIZE=1280
+CONFIG_SCHED_INSTRUMENTATION=y
+CONFIG_SCHED_INSTRUMENTATION_EXTERNAL=y
+CONFIG_SCHED_INSTRUMENTATION_SWITCH=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_LPWORKPRIORITY=50
+CONFIG_SCHED_LPWORKSTACKSIZE=1632
+CONFIG_SDMMC2_SDIO_PULLUP=y
+CONFIG_SEM_PREALLOCHOLDERS=32
+CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y
+CONFIG_SERIAL_TERMIOS=y
+CONFIG_SIG_DEFAULT=y
+CONFIG_SIG_SIGALRM_ACTION=y
+CONFIG_SIG_SIGUSR1_ACTION=y
+CONFIG_SIG_SIGUSR2_ACTION=y
+CONFIG_SIG_SIGWORK=4
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=30
+CONFIG_START_MONTH=11
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_STM32H7_ADC1=y
+CONFIG_STM32H7_ADC3=y
+CONFIG_STM32H7_BBSRAM=y
+CONFIG_STM32H7_BBSRAM_FILES=5
+CONFIG_STM32H7_BDMA=y
+CONFIG_STM32H7_BKPSRAM=y
+CONFIG_STM32H7_DMA1=y
+CONFIG_STM32H7_DMA2=y
+CONFIG_STM32H7_DMACAPABLE=y
+CONFIG_STM32H7_ETHMAC=y
+CONFIG_STM32H7_FLASH_OVERRIDE_I=y
+CONFIG_STM32H7_FLOWCONTROL_BROKEN=y
+CONFIG_STM32H7_I2C1=y
+CONFIG_STM32H7_I2C2=y
+CONFIG_STM32H7_I2C3=y
+CONFIG_STM32H7_I2C4=y
+CONFIG_STM32H7_I2C_DYNTIMEO=y
+CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP=10
+CONFIG_STM32H7_OTGFS=y
+CONFIG_STM32H7_PHYSR=31
+CONFIG_STM32H7_PHYSR_100MBPS=0x8
+CONFIG_STM32H7_PHYSR_FULLDUPLEX=0x10
+CONFIG_STM32H7_PHYSR_MODE=0x10
+CONFIG_STM32H7_PHYSR_SPEED=0x8
+CONFIG_STM32H7_PHY_POLLING=y
+CONFIG_STM32H7_PROGMEM=y
+CONFIG_STM32H7_RTC=y
+CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y
+CONFIG_STM32H7_RTC_MAGIC_REG=1
+CONFIG_STM32H7_SAVE_CRASHDUMP=y
+CONFIG_STM32H7_SDMMC2=y
+CONFIG_STM32H7_SERIALBRK_BSDCOMPAT=y
+CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
+CONFIG_STM32H7_SPI1=y
+CONFIG_STM32H7_SPI1_DMA=y
+CONFIG_STM32H7_SPI1_DMA_BUFFER=1024
+CONFIG_STM32H7_SPI2=y
+CONFIG_STM32H7_SPI2_DMA=y
+CONFIG_STM32H7_SPI2_DMA_BUFFER=4096
+CONFIG_STM32H7_SPI3=y
+CONFIG_STM32H7_SPI3_DMA=y
+CONFIG_STM32H7_SPI3_DMA_BUFFER=1024
+CONFIG_STM32H7_SPI5=y
+CONFIG_STM32H7_SPI6=y
+CONFIG_STM32H7_SPI6_DMA=y
+CONFIG_STM32H7_SPI6_DMA_BUFFER=1024
+CONFIG_STM32H7_TIM12=y
+CONFIG_STM32H7_TIM1=y
+CONFIG_STM32H7_TIM4=y
+CONFIG_STM32H7_TIM5=y
+CONFIG_STM32H7_UART4=y
+CONFIG_STM32H7_UART5=y
+CONFIG_STM32H7_UART7=y
+CONFIG_STM32H7_UART8=y
+CONFIG_STM32H7_USART1=y
+CONFIG_STM32H7_USART2=y
+CONFIG_STM32H7_USART3=y
+CONFIG_STM32H7_USART6=y
+CONFIG_STM32H7_USART_BREAKS=y
+CONFIG_STM32H7_USART_INVERT=y
+CONFIG_STM32H7_USART_SINGLEWIRE=y
+CONFIG_STM32H7_USART_SWAP=y
+CONFIG_SYSTEM_CDCACM=y
+CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_PING=y
+CONFIG_SYSTEM_SYSTEM=y
+CONFIG_TASK_NAME_SIZE=24
+CONFIG_UART4_BAUD=57600
+CONFIG_UART4_RXBUFSIZE=600
+CONFIG_UART4_TXBUFSIZE=1500
+CONFIG_UART5_IFLOWCONTROL=y
+CONFIG_UART5_OFLOWCONTROL=y
+CONFIG_UART5_RXDMA=y
+CONFIG_UART5_TXBUFSIZE=10000
+CONFIG_UART5_TXDMA=y
+CONFIG_UART7_BAUD=57600
+CONFIG_UART7_IFLOWCONTROL=y
+CONFIG_UART7_OFLOWCONTROL=y
+CONFIG_UART7_RXBUFSIZE=600
+CONFIG_UART7_RXDMA=y
+CONFIG_UART7_TXBUFSIZE=3000
+CONFIG_UART7_TXDMA=y
+CONFIG_UART8_BAUD=57600
+CONFIG_UART8_RXBUFSIZE=600
+CONFIG_UART8_TXBUFSIZE=1500
+CONFIG_USART1_BAUD=57600
+CONFIG_USART1_RXBUFSIZE=600
+CONFIG_USART1_TXBUFSIZE=1500
+CONFIG_USART2_BAUD=57600
+CONFIG_USART2_IFLOWCONTROL=y
+CONFIG_USART2_OFLOWCONTROL=y
+CONFIG_USART2_RXBUFSIZE=600
+CONFIG_USART2_TXBUFSIZE=3000
+CONFIG_USART3_BAUD=57600
+CONFIG_USART3_RXBUFSIZE=180
+CONFIG_USART3_RXDMA=y
+CONFIG_USART3_SERIAL_CONSOLE=y
+CONFIG_USART3_TXBUFSIZE=1500
+CONFIG_USART3_TXDMA=y
+CONFIG_USART6_BAUD=57600
+CONFIG_USART6_RXBUFSIZE=600
+CONFIG_USART6_TXBUFSIZE=1500
+CONFIG_USBDEV=y
+CONFIG_USBDEV_BUSPOWERED=y
+CONFIG_USBDEV_MAXPOWER=500
+CONFIG_USEC_PER_TICK=1000
+CONFIG_WATCHDOG=y
@@ -0,0 +1,215 @@
+/****************************************************************************
+ * scripts/script.ld
+ *
+ *   Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The PX4 FMUV6X uses an STM32H753II has 2048Kb of main FLASH memory.
+ * The flash memory is partitioned into a User Flash memory and a System
+ * Flash memory. Each of these memories has two banks:
+ *
+ *   1) User Flash memory:
+ *
+ *      Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each
+ *      Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each
+ *
+ *   2) System Flash memory:
+ *
+ *      Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector
+ *      Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector
+ *
+ *   3) User option bytes for user configuration, only in Bank 1.
+ *
+ * In the STM32H743II, two different boot spaces can be selected through
+ * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
+ * BOOT_ADD1 option bytes:
+ *
+ *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
+ *      ST programmed value: Flash memory at 0x0800:0000
+ *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
+ *      ST programmed value: System bootloader at 0x1FF0:0000
+ *
+ * The PX4 FMUV6X has a test point on board, the BOOT0 pin is at ground so by
+ * default, the STM32 will boot to address 0x0800:0000 in FLASH unless the test
+ * point is pulled to 3.3V.then the boot will be from 0x1FF0:0000
+ *
+ * The STM32H743II also has 1024Kb of data SRAM.
+ * SRAM is split up into several blocks and into three power domains:
+ *
+ *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with
+ *      0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus
+ *
+ *      1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000
+ *
+ *           The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit
+ *           DTCM ports. The DTCM-RAM could be used for critical real-time
+ *           data, such as interrupt service routines or stack / heap memory.
+ *           Both DTCM-RAMs can be used in parallel (for load/store operations)
+ *           thanks to the Cortex-M7 dual issue capability.
+ *
+ *      1.2)  64Kb of ITCM-RAM beginning at address 0x0000:0000
+ *
+ *           This RAM is connected to ITCM 64-bit interface designed for
+ *           execution of critical real-times routines by the CPU.
+ *
+ *   2) AXI SRAM (D1 domain) accessible by all system masters except BDMA
+ *      through D1 domain AXI bus matrix
+ *
+ *      2.1) 512Kb of SRAM beginning at address 0x2400:0000
+ *
+ *   3) AHB SRAM (D2 domain) accessible by all system masters except BDMA
+ *      through D2 domain AHB bus matrix
+ *
+ *      3.1) 128Kb of SRAM1 beginning at address 0x3000:0000
+ *      3.2) 128Kb of SRAM2 beginning at address 0x3002:0000
+ *      3.3)  32Kb of SRAM3 beginning at address 0x3004:0000
+ *
+ *      SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000
+ *
+ *   4) AHB SRAM (D3 domain) accessible by most of system masters
+ *      through D3 domain AHB bus matrix
+ *
+ *      4.1)  64Kb of SRAM4 beginning at address 0x3800:0000
+ *      4.1)   4Kb of backup RAM beginning at address 0x3880:0000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ *
+ * The bootloader uses the first sector of the flash, which is 128K in length.
+ */
+
+MEMORY
+{
+	itcm  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+	flash (rx)  : ORIGIN = 0x08000000, LENGTH =  128K
+	dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+	dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+	sram  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K
+	sram1 (rwx) : ORIGIN = 0x30000000, LENGTH =  128K
+	sram2 (rwx) : ORIGIN = 0x30020000, LENGTH =  128K
+	sram3 (rwx) : ORIGIN = 0x30040000, LENGTH =   32K
+	sram4 (rwx) : ORIGIN = 0x38000000, LENGTH =   64K
+	bbram (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+
+/*
+ * Ensure that abort() is present in the final object.  The exception handling
+ * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).
+ */
+EXTERN(abort)
+EXTERN(_bootdelay_signature)
+
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		. = ALIGN(32);
+		/*
+		This signature provides the bootloader with a way to delay booting
+		*/
+		_bootdelay_signature = ABSOLUTE(.);
+		FILL(0xffecc2925d7d05c5)
+		. += 8;
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+
+	} > flash
+
+	/*
+	 * Init functions (static constructors and the like)
+	 */
+	.init_section : {
+		_sinit = ABSOLUTE(.);
+		KEEP(*(.init_array .init_array.*))
+		_einit = ABSOLUTE(.);
+	} > flash
+
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > flash
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > flash
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
@@ -0,0 +1,229 @@
+/****************************************************************************
+ * scripts/script.ld
+ *
+ *   Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The PX4 FMUV6X uses an STM32H753II has 2048Kb of main FLASH memory.
+ * The flash memory is partitioned into a User Flash memory and a System
+ * Flash memory. Each of these memories has two banks:
+ *
+ *   1) User Flash memory:
+ *
+ *      Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each
+ *      Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each
+ *
+ *   2) System Flash memory:
+ *
+ *      Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector
+ *      Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector
+ *
+ *   3) User option bytes for user configuration, only in Bank 1.
+ *
+ * In the STM32H743II, two different boot spaces can be selected through
+ * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
+ * BOOT_ADD1 option bytes:
+ *
+ *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
+ *      ST programmed value: Flash memory at 0x0800:0000
+ *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
+ *      ST programmed value: System bootloader at 0x1FF0:0000
+ *
+ * The PX4 FMUV6X has a test point on board, the BOOT0 pin is at ground so by
+ * default, the STM32 will boot to address 0x0800:0000 in FLASH unless the test
+ * point is pulled to 3.3V.then the boot will be from 0x1FF0:0000
+ *
+ * The STM32H743II also has 1024Kb of data SRAM.
+ * SRAM is split up into several blocks and into three power domains:
+ *
+ *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with
+ *      0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus
+ *
+ *      1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000
+ *
+ *           The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit
+ *           DTCM ports. The DTCM-RAM could be used for critical real-time
+ *           data, such as interrupt service routines or stack / heap memory.
+ *           Both DTCM-RAMs can be used in parallel (for load/store operations)
+ *           thanks to the Cortex-M7 dual issue capability.
+ *
+ *      1.2)  64Kb of ITCM-RAM beginning at address 0x0000:0000
+ *
+ *           This RAM is connected to ITCM 64-bit interface designed for
+ *           execution of critical real-times routines by the CPU.
+ *
+ *   2) AXI SRAM (D1 domain) accessible by all system masters except BDMA
+ *      through D1 domain AXI bus matrix
+ *
+ *      2.1) 512Kb of SRAM beginning at address 0x2400:0000
+ *
+ *   3) AHB SRAM (D2 domain) accessible by all system masters except BDMA
+ *      through D2 domain AHB bus matrix
+ *
+ *      3.1) 128Kb of SRAM1 beginning at address 0x3000:0000
+ *      3.2) 128Kb of SRAM2 beginning at address 0x3002:0000
+ *      3.3)  32Kb of SRAM3 beginning at address 0x3004:0000
+ *
+ *      SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000
+ *
+ *   4) AHB SRAM (D3 domain) accessible by most of system masters
+ *      through D3 domain AHB bus matrix
+ *
+ *      4.1)  64Kb of SRAM4 beginning at address 0x3800:0000
+ *      4.1)   4Kb of backup RAM beginning at address 0x3880:0000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ */
+
+MEMORY
+{
+	ITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K
+	FLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K
+
+	DTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K
+	DTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K
+	AXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K /* D1 domain AXI bus */
+	SRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K /* D2 domain AHB bus */
+	SRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K /* D2 domain AHB bus */
+	SRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K /* D3 domain */
+	BKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+
+/*
+ * Ensure that abort() is present in the final object.  The exception handling
+ * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).
+ */
+EXTERN(abort)
+EXTERN(_bootdelay_signature)
+EXTERN(board_get_manifest)
+
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		. = ALIGN(32);
+		/*
+		This signature provides the bootloader with a way to delay booting
+		*/
+		_bootdelay_signature = ABSOLUTE(.);
+		FILL(0xffecc2925d7d05c5)
+		. += 8;
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+
+	} > FLASH
+
+	/*
+	 * Init functions (static constructors and the like)
+	 */
+	.init_section : {
+		_sinit = ABSOLUTE(.);
+		KEEP(*(.init_array .init_array.*))
+		_einit = ABSOLUTE(.);
+	} > FLASH
+
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > FLASH
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > FLASH
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+
+		/* Pad out last section as the STM32H7 Flash write size is 256 bits. 32 bytes */
+		. = ALIGN(16);
+		FILL(0xffff)
+		. += 16;
+	} > AXI_SRAM AT > FLASH  = 0xffff
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = ABSOLUTE(.);
+	} > AXI_SRAM
+
+	/* Emit the the D3 power domain section for locating BDMA data */
+
+	.sram4_reserve (NOLOAD) :
+	{
+		*(.sram4)
+		. = ALIGN(4);
+		_sram4_heap_start = ABSOLUTE(.);
+	} > SRAM4
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
@@ -1,6 +1,6 @@
 ############################################################################
 #
-#   Copyright (c) 2024 PX4 Development Team. All rights reserved.
+#   Copyright (c) 2025 PX4 Development Team. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
@@ -31,14 +31,12 @@
 #
 ############################################################################

+px4_add_module(
+	MODULE modules__pwm_voltage_apply
+	MAIN pwm_voltage_apply

-set(PX4_FW_NAME ${PX4_BINARY_DIR}/${PX4_BOARD_VENDOR}_${PX4_BOARD_MODEL}_${PX4_BOARD_LABEL}.hex)
-
-add_custom_target(upload_teensy
-	COMMAND ${PYTHON_EXECUTABLE} ${PX4_SOURCE_DIR}/Tools/teensy_uploader.py --port ${serial_ports} ${PX4_FW_NAME} --vendor-id 0x1FC9 --product-id 0x0024
-	DEPENDS ${PX4_FW_NAME}
-	COMMENT "uploading px4"
-	VERBATIM
-	USES_TERMINAL
-	WORKING_DIRECTORY ${PX4_BINARY_DIR}
-)
+	SRCS
+		pwm_voltage.cpp
+	DEPENDS
+		px4_work_queue
+	)
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2024 PX4 Development Team. All rights reserved.
+ *   Copyright (c) 2025 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -30,7 +30,14 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
-#pragma once

-
-#include "../../../imxrt/include/px4_arch/imxrt_flexspi_nor_flash.h"
+/**
+ * Control PWM output voltage
+ *
+ * @value 0 3.3V
+ * @value 1 5.0V
+ *
+ * @reboot_required true
+ * @group PWM Outputs
+ */
+PARAM_DEFINE_INT32(PWM_VOLT_SEL, 0);
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2024 PX4 Development Team. All rights reserved.
+ *   Copyright (c) 2025 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -30,7 +30,27 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
-#pragma once

+#include <inttypes.h>
+#include <stdint.h>

-#include "../../../imxrt/include/px4_arch/imxrt_romapi.h"
+#include <px4_platform_common/getopt.h>
+#include <px4_platform_common/module_params.h>
+
+#include "board_config.h"
+
+extern "C" int pwm_voltage_apply_main(int argc, char *argv[])
+{
+	int32_t pwm_volt_sel = 0;
+
+	param_get(param_find("PWM_VOLT_SEL"), &pwm_volt_sel);
+
+	if (pwm_volt_sel != 0) {
+		PWM_5V_VOLT_SEL(true);
+
+	} else {
+		PWM_5V_VOLT_SEL(false);
+	}
+
+	return 0;
+}
@@ -1,6 +1,6 @@
 ############################################################################
 #
-#   Copyright (c) 2024 PX4 Development Team. All rights reserved.
+#   Copyright (c) 2016 PX4 Development Team. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
@@ -36,8 +36,6 @@ if("${PX4_BOARD_LABEL}" STREQUAL  "bootloader")
 		bootloader_main.c
 		init.c
 		usb.c
-		imxrt_flexspi_nor_boot.c
-		imxrt_flexspi_nor_flash.c
 		timer_config.cpp
 	)
 	target_link_libraries(drivers_board
@@ -46,41 +44,32 @@ if("${PX4_BOARD_LABEL}" STREQUAL  "bootloader")
 			nuttx_drivers # sdio
 			px4_layer #gpio
 			arch_io_pins # iotimer
-			arch_board_romapi
 			bootloader
 	)
 	target_include_directories(drivers_board PRIVATE ${PX4_SOURCE_DIR}/platforms/nuttx/src/bootloader/common)

 else()
-
-	px4_add_library(drivers_board
+	add_library(drivers_board
+		can.c
 		i2c.cpp
 		init.c
-		sdhc.c
+		led.c
+		mtd.cpp
+		sdio.c
 		spi.cpp
 		timer_config.cpp
-		tropic_led_pwm.cpp
 		usb.c
-		imxrt_flexspi_nor_boot.c
-		imxrt_flexspi_nor_flash.c
-		imxrt_flexspi_storage.c
-		imxrt_ocram_initialize.c
-		hw_rev_ver_tropic.c
-		manifest.c
 	)
-
-
-	# Force compiler not to use builtin functions (like memcpy)
-	# to optimize for loops in init.c (imxrt_ocram_initialize)
-	set_source_files_properties(imxrt_ocram_initialize.c PROPERTIES COMPILE_FLAGS -fno-builtin)
+	add_dependencies(drivers_board arch_board_hw_info)

 	target_link_libraries(drivers_board
 		PRIVATE
-			arch_board_romapi
+			arch_io_pins
 			arch_spi
+			arch_board_hw_info
+			drivers__led # drv_led_start
 			nuttx_arch # sdio
 			nuttx_drivers # sdio
 			px4_layer
 	)
-
 endif()
@@ -0,0 +1,484 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2016-2022 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file board_config.h
+ *
+ * PX4FMU-v6x internal definitions
+ */
+
+#pragma once
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <px4_platform_common/px4_config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+
+#include <stm32_gpio.h>
+
+/****************************************************************************************************
+ * Definitions
+ ****************************************************************************************************/
+
+#undef TRACE_PINS
+
+/* PX4IO connection configuration */
+
+#define BOARD_USES_PX4IO_VERSION       2
+#define PX4IO_SERIAL_DEVICE            "/dev/ttyS5"
+#define PX4IO_SERIAL_TX_GPIO           GPIO_USART6_TX
+#define PX4IO_SERIAL_RX_GPIO           GPIO_USART6_RX
+#define PX4IO_SERIAL_BASE              STM32_USART6_BASE
+#define PX4IO_SERIAL_VECTOR            STM32_IRQ_USART6
+#define PX4IO_SERIAL_TX_DMAMAP         DMAMAP_USART6_TX
+#define PX4IO_SERIAL_RX_DMAMAP         DMAMAP_USART6_RX
+#define PX4IO_SERIAL_RCC_REG           STM32_RCC_APB2ENR
+#define PX4IO_SERIAL_RCC_EN            RCC_APB2ENR_USART6EN
+#define PX4IO_SERIAL_CLOCK             STM32_PCLK2_FREQUENCY
+#define PX4IO_SERIAL_BITRATE           1500000               /* 1.5Mbps -> max rate for IO */
+
+/* Configuration ************************************************************************************/
+
+#define BOARD_HAS_LTC44XX_VALIDS      2 //  N Bricks
+#define BOARD_HAS_USB_VALID           1 // LTC Has USB valid
+#define BOARD_HAS_NBAT_V              2 // one is adc,another is Digital Voltage(iic or can)
+#define BOARD_HAS_NBAT_I              2 // one is adc,another is Digital Current(iic or can)
+
+/* PX4FMU GPIOs ***********************************************************************************/
+
+/* Trace Clock and D0-D3 are available on the trace connector
+ *
+ * TRACECLK PE2  - Dedicated       - Trace Connector Pin 1
+ * TRACED0  PE3  - nLED_RED        - Trace Connector Pin 3
+ * TRACED1  PE4  - nLED_GREEN      - Trace Connector Pin 5
+ * TRACED2  PE5  - nLED_BLUE       - Trace Connector Pin 7
+ * TRACED3  PE6  - nARMED          - Trace Connector Pin 8
+
+ */
+
+/* LEDs are driven with push open drain to support Anode to 5V or 3.3V or used as TRACE0-2 */
+
+#if !defined(TRACE_PINS)
+#  define GPIO_nLED_RED        /* PE3 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
+#  define GPIO_nLED_GREEN      /* PE4 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4)
+#  define GPIO_nLED_BLUE       /* PE5 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN5)
+
+#  define BOARD_HAS_CONTROL_STATUS_LEDS      1
+#  define BOARD_OVERLOAD_LED     LED_RED
+#  define BOARD_ARMED_STATE_LED  LED_BLUE
+
+#else
+
+#  define GPIO_TRACECLK1 (GPIO_TRACECLK |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2)
+#  define GPIO_TRACED0   (GPIO_TRACED0_2|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3)
+#  define GPIO_TRACED1   (GPIO_TRACED1_2|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4)
+#  define GPIO_TRACED2   (GPIO_TRACED2_2|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5)
+#  define GPIO_TRACED3   (GPIO_TRACED3_2|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL)  //(GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6)
+//#define GPIO_TRACESWO                        //(GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
+
+#  undef  BOARD_HAS_CONTROL_STATUS_LEDS
+#  undef  BOARD_OVERLOAD_LED
+#  undef  BOARD_ARMED_STATE_LED
+
+#  define GPIO_nLED_RED    GPIO_TRACED0
+#  define GPIO_nLED_GREEN  GPIO_TRACED1
+#  define GPIO_nLED_BLUE   GPIO_TRACED2
+#  define GPIO_nARMED      GPIO_TRACED3
+#  define GPIO_nARMED_INIT GPIO_TRACED3
+#endif
+
+/* I2C busses */
+
+/* Devices on the onboard buses.
+ *
+ * Note that these are unshifted addresses.
+ */
+#define BOARD_MTD_NUM_EEPROM        2 /* MTD: base_eeprom, imu_eeprom*/
+
+#define PX4_I2C_OBDEV_SE050         0x48
+
+#define GPIO_I2C2_DRDY1_BMP388      /* PG5  */  (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTG|GPIO_PIN5)
+
+/*
+ * ADC channels
+ *
+ * These are the channel numbers of the ADCs of the microcontroller that
+ * can be used by the Px4 Firmware in the adc driver
+ */
+
+/* ADC defines to be used in sensors.cpp to read from a particular channel */
+
+#define ADC1_CH(n)                  (n)
+
+/* N.B. there is no offset mapping needed for ADC3 because */
+#define ADC3_CH(n)                  (n)
+
+/* We are only use ADC3 for REV/VER.
+ * ADC3_6V6 and ADC3_3V3 are mapped back to ADC1
+ * To do this We are relying on PC2_C, PC3_C being connected to PC2, PC3
+ * respectively by the SYSCFG_PMCR default of setting for PC3SO PC2SO PA1SO
+ * PA0SO of 0.
+ *
+ *  0 Analog switch closed (pads are connected through the analog switch)
+ *
+ * So ADC3_INP0 is GPIO_ADC123_INP12
+ *    ADC3_INP1 is GPIO_ADC12_INP13
+ */
+
+/* Define GPIO pins used as ADC N.B. Channel numbers must match below  */
+
+#define PX4_ADC_GPIO  \
+	/* PA0  */  GPIO_ADC1_INP16,   \
+	/* PA4  */  GPIO_ADC12_INP18,  \
+	/* PB0  */  GPIO_ADC12_INP9,   \
+	/* PB1  */  GPIO_ADC12_INP5,   \
+	/* PC2  */  GPIO_ADC123_INP12, \
+	/* PC3  */  GPIO_ADC12_INP13,  \
+	/* PF12 */  GPIO_ADC1_INP6,    \
+	/* PH3  */  GPIO_ADC3_INP14,   \
+	/* PH4  */  GPIO_ADC3_INP15
+
+/* Define Channel numbers must match above GPIO pin IN(n)*/
+
+#define ADC_BATTERY_VOLTAGE_CHANNEL        	/* PF12 */ ADC1_CH(6)
+#define ADC_BATTERY_CURRENT_CHANNEL        	/* PB0 */  ADC1_CH(9)
+#define ADC_SCALED_VDD_3V3_SENSORS1_CHANNEL     /* PA0  */  ADC1_CH(16)
+#define ADC_SCALED_VDD_3V3_SENSORS2_CHANNEL     /* PA4  */  ADC1_CH(18)
+#define ADC_SCALED_V5_CHANNEL                   /* PB1  */  ADC1_CH(5)
+#define ADC_ADC3_6V6_CHANNEL                    /* PC2  */  ADC3_CH(12)
+#define ADC_ADC3_3V3_CHANNEL                    /* PC3  */  ADC3_CH(13)
+#define ADC_HW_VER_SENSE_CHANNEL                /* PH3  */  ADC3_CH(14)
+#define ADC_HW_REV_SENSE_CHANNEL                /* PH4  */  ADC3_CH(15)
+
+#define ADC_CHANNELS \
+	((1 << ADC_BATTERY_VOLTAGE_CHANNEL) | \
+	 (1 << ADC_BATTERY_CURRENT_CHANNEL) | \
+	 (1 << ADC_SCALED_VDD_3V3_SENSORS1_CHANNEL) | \
+	 (1 << ADC_SCALED_V5_CHANNEL)               | \
+	 (1 << ADC_ADC3_6V6_CHANNEL)                | \
+	 (1 << ADC_ADC3_3V3_CHANNEL))               | \
+	(1 << ADC_SCALED_VDD_3V3_SENSORS2_CHANNEL)
+
+
+/* HW has to large of R termination on ADC todo:change when HW value is chosen */
+
+#define HW_REV_VER_ADC_BASE STM32_ADC3_BASE
+
+#define SYSTEM_ADC_BASE STM32_ADC1_BASE
+
+/* HW has to large of R termination on ADC todo:change when HW value is chosen */
+#define BOARD_ADC_OPEN_CIRCUIT_V     (5.6f)
+
+// // /* HW Version and Revision drive signals Default to 1 to detect */
+// #define BOARD_HAS_HW_SPLIT_VERSIONING
+
+#define BOARD_HAS_STATIC_MANIFEST 1
+
+#define PX4_MFT_HW_SUPPORTED_PX4_MFT_CAN2 1
+
+#define GPIO_HW_VER_REV_DRIVE  /* PG0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN0)
+#define GPIO_HW_REV_SENSE      /* PH4 */  GPIO_ADC3_INP15
+#define GPIO_HW_VER_SENSE      /* PH3 */  GPIO_ADC3_INP14
+
+#define UAVCAN_NUM_IFACES_RUNTIME  1
+
+/* HEATER
+ * PWM in future
+ */
+#define GPIO_HEATER_OUTPUT   /* PB10  T2CH3 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
+#define HEATER_OUTPUT_EN(on_true)	       px4_arch_gpiowrite(GPIO_HEATER_OUTPUT, (on_true))
+
+/* PE6 is nARMED
+ *  The GPIO will be set as input while not armed HW will have external HW Pull UP.
+ *  While armed it shall be configured at a GPIO OUT set LOW
+ */
+#if !defined(TRACE_PINS)
+#define GPIO_nARMED_INIT     /* PE6 */  (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN6)
+#define GPIO_nARMED          /* PE6 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN6)
+#define BOARD_INDICATE_EXTERNAL_LOCKOUT_STATE(enabled)  px4_arch_configgpio((enabled) ? GPIO_nARMED : GPIO_nARMED_INIT)
+#define BOARD_GET_EXTERNAL_LOCKOUT_STATE() px4_arch_gpioread(GPIO_nARMED)
+#endif
+
+
+/* PWM
+ */
+#define DIRECT_PWM_OUTPUT_CHANNELS   9
+
+/* PWM Power */
+#define GPIO_PWM_VOLT_SEL		/* PG6  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN6)
+#define PWM_5V_VOLT_SEL(on_true)	px4_arch_gpiowrite(GPIO_PWM_VOLT_SEL, (on_true))
+
+/* Power supply control and monitoring GPIOs */
+
+#define GPIO_nPOWER_IN_A                /* PG1  */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTG|GPIO_PIN1)
+#define GPIO_nPOWER_IN_B                /* PG2  */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTG|GPIO_PIN2)
+#define GPIO_nPOWER_IN_C                /* PG3  */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTG|GPIO_PIN3)
+
+#define GPIO_nVDD_BRICK1_VALID          GPIO_nPOWER_IN_A /* Brick 1 Is Chosen */
+#define GPIO_nVDD_BRICK2_VALID          GPIO_nPOWER_IN_B /* Brick 2 Is Chosen  */
+#define BOARD_NUMBER_BRICKS             1
+#define GPIO_nVDD_USB_VALID             GPIO_nPOWER_IN_C /* USB     Is Chosen */
+
+#define GPIO_VDD_5V_PERIPH_nEN          /* PG4  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN4)
+#define GPIO_VDD_5V_PERIPH_nOC          /* PE15 */ (GPIO_INPUT |GPIO_FLOAT|GPIO_PORTE|GPIO_PIN15)
+#define GPIO_VDD_5V_HIPOWER_nEN         /* PG10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN10)
+#define GPIO_VDD_5V_HIPOWER_nOC         /* PF13 */ (GPIO_INPUT |GPIO_FLOAT|GPIO_PORTF|GPIO_PIN13)
+#define GPIO_VDD_3V3_SENSORS4_EN        /* PG8  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN8)
+#define GPIO_VDD_3V3_SPEKTRUM_POWER_EN  /* PH2  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN2)
+#define GPIO_VDD_3V3_SD_CARD_EN         /* PC13 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN13)
+
+/* ETHERNET GPIO */
+
+#define GPIO_ETH_POWER_EN              /* PG15 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN15)
+
+/* NFC GPIO */
+
+#define GPIO_NFC_GPIO                   /* PC0 */ (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN0)
+
+
+/* Define True logic Power Control in arch agnostic form */
+
+#define VDD_5V_PERIPH_EN(on_true)          px4_arch_gpiowrite(GPIO_VDD_5V_PERIPH_nEN, !(on_true))
+#define VDD_5V_HIPOWER_EN(on_true)         px4_arch_gpiowrite(GPIO_VDD_5V_HIPOWER_nEN, !(on_true))
+#define VDD_3V3_SENSORS4_EN(on_true)       px4_arch_gpiowrite(GPIO_VDD_3V3_SENSORS4_EN, (on_true))
+#define VDD_3V3_SPEKTRUM_POWER_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SPEKTRUM_POWER_EN, (on_true))
+#define READ_VDD_3V3_SPEKTRUM_POWER_EN()   px4_arch_gpioread(GPIO_VDD_3V3_SPEKTRUM_POWER_EN)
+#define VDD_3V3_SD_CARD_EN(on_true)        px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
+#define VDD_3V3_ETH_POWER_EN(on_true)      px4_arch_gpiowrite(GPIO_ETH_POWER_EN, (on_true))
+
+
+/* Tone alarm output */
+
+#define TONE_ALARM_TIMER        14  /* Timer 14 */
+#define TONE_ALARM_CHANNEL      1  /* PF9 GPIO_TIM14_CH1OUT_2 */
+
+#define GPIO_BUZZER_1           /* PF9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTF|GPIO_PIN9)
+
+#define GPIO_TONE_ALARM_IDLE    GPIO_BUZZER_1
+#define GPIO_TONE_ALARM         GPIO_TIM14_CH1OUT_2
+
+/* USB OTG FS
+ *
+ * PA9  OTG_FS_VBUS VBUS sensing
+ */
+#define GPIO_OTGFS_VBUS         /* PA9 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN9)
+
+/* High-resolution timer */
+#define HRT_TIMER               8  /* use timer8 for the HRT */
+#define HRT_TIMER_CHANNEL       3  /* use capture/compare channel 3 */
+
+#define HRT_PPM_CHANNEL         /* T8C1 */  1  /* use capture/compare channel 1 */
+#define GPIO_PPM_IN             /* PI5 T8C1 */ GPIO_TIM8_CH1IN_2
+
+/* RC Serial port */
+
+#define RC_SERIAL_PORT                     "/dev/ttyS5"
+#define RC_SERIAL_SINGLEWIRE
+
+/* Input Capture Channels. */
+#define INPUT_CAP1_TIMER                  1
+#define INPUT_CAP1_CHANNEL     /* T1C2 */ 2
+#define GPIO_INPUT_CAP1        /*  PE11 */ GPIO_TIM1_CH2IN
+
+/* PWM input driver. Use FMU AUX5 pins attached to timer4 channel 2 */
+#define PWMIN_TIMER                       4
+#define PWMIN_TIMER_CHANNEL    /* T4C2 */ 2
+#define GPIO_PWM_IN            /* PD13 */ GPIO_TIM4_CH2IN_2
+
+/* Safety Switch is HW version dependent on having an PX4IO
+ * So we init to a benign state with the _INIT definition
+ * and provide the the non _INIT one for the driver to make a run time
+ * decision to use it.
+ */
+#define GPIO_nSAFETY_SWITCH_LED_OUT_INIT   /* PD10 */ (GPIO_INPUT|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN10)
+#define GPIO_nSAFETY_SWITCH_LED_OUT        /* PD10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN10)
+
+/* Enable the FMU to control it if there is no px4io fixme:This should be BOARD_SAFETY_LED(__ontrue) */
+#define GPIO_LED_SAFETY GPIO_nSAFETY_SWITCH_LED_OUT
+
+#define GPIO_SAFETY_SWITCH_IN              /* PF5 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTF|GPIO_PIN5)
+/* Enable the FMU to use the switch it if there is no px4io fixme:This should be BOARD_SAFTY_BUTTON() */
+#define GPIO_BTN_SAFETY GPIO_SAFETY_SWITCH_IN /* Enable the FMU to control it if there is no px4io */
+
+/* Power switch controls ******************************************************/
+
+#define SPEKTRUM_POWER(_on_true)           VDD_3V3_SPEKTRUM_POWER_EN(_on_true)
+
+/*
+ * FMUv6X has a separate RC_IN
+ *
+ * GPIO PPM_IN on PI5 T8CH1
+ * SPEKTRUM_RX (it's TX or RX in Bind) on UART6 PC7
+ *   Inversion is possible in the UART and can drive  GPIO PPM_IN as an output
+ */
+
+#define GPIO_PPM_IN_AS_OUT             (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN5)
+#define SPEKTRUM_RX_AS_GPIO_OUTPUT()   px4_arch_configgpio(GPIO_PPM_IN_AS_OUT)
+#define SPEKTRUM_RX_AS_UART()          /* Can be left as uart */
+#define SPEKTRUM_OUT(_one_true)        px4_arch_gpiowrite(GPIO_PPM_IN_AS_OUT, (_one_true))
+
+#define SDIO_SLOTNO                    0  /* Only one slot */
+#define SDIO_MINOR                     0
+
+/* SD card bringup does not work if performed on the IDLE thread because it
+ * will cause waiting.  Use either:
+ *
+ *  CONFIG_BOARDCTL=y, OR
+ *  CONFIG_BOARD_INITIALIZE=y && CONFIG_BOARD_INITTHREAD=y
+ */
+
+#if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_BOARDCTL) && \
+   !defined(CONFIG_BOARD_INITTHREAD)
+#  warning SDIO initialization cannot be perfomed on the IDLE thread
+#endif
+
+/* By Providing BOARD_ADC_USB_CONNECTED (using the px4_arch abstraction)
+ * this board support the ADC system_power interface, and therefore
+ * provides the true logic GPIO BOARD_ADC_xxxx macros.
+ */
+#define BOARD_ADC_USB_CONNECTED (px4_arch_gpioread(GPIO_OTGFS_VBUS))
+#define BOARD_ADC_USB_VALID     (!px4_arch_gpioread(GPIO_nVDD_USB_VALID))
+
+/* FMUv6X never powers off the Servo rail */
+
+#define BOARD_ADC_SERVO_VALID     (1)
+
+
+#define BOARD_ADC_BRICK_VALID 	(!px4_arch_gpioread(GPIO_nVDD_BRICK1_VALID))
+
+#define BOARD_ADC_PERIPH_5V_OC  (!px4_arch_gpioread(GPIO_VDD_5V_PERIPH_nOC))
+#define BOARD_ADC_HIPOWER_5V_OC (!px4_arch_gpioread(GPIO_VDD_5V_HIPOWER_nOC))
+
+
+/* This board provides a DMA pool and APIs */
+#define BOARD_DMA_ALLOC_POOL_SIZE 5120
+
+/* This board provides the board_on_reset interface */
+
+#define BOARD_HAS_ON_RESET 1
+
+#if defined(TRACE_PINS)
+#define GPIO_TRACE                          \
+	GPIO_TRACECLK1,                           \
+	GPIO_TRACED0,                             \
+	GPIO_TRACED1,                             \
+	GPIO_TRACED2,                             \
+	GPIO_TRACED3
+#else
+#define GPIO_TRACE (GPIO_OUTPUT|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN2)
+#endif
+
+#define PX4_GPIO_INIT_LIST { \
+		GPIO_TRACE,                       \
+		PX4_ADC_GPIO,                     \
+		GPIO_HW_VER_REV_DRIVE,            \
+		GPIO_CAN1_TX,                     \
+		GPIO_CAN1_RX,                     \
+		GPIO_CAN2_TX,                     \
+		GPIO_CAN2_RX,                     \
+		GPIO_HEATER_OUTPUT,               \
+		GPIO_nPOWER_IN_A,                 \
+		GPIO_nPOWER_IN_B,                 \
+		GPIO_nPOWER_IN_C,                 \
+		GPIO_VDD_5V_PERIPH_nEN,           \
+		GPIO_VDD_5V_PERIPH_nOC,           \
+		GPIO_VDD_5V_HIPOWER_nEN,          \
+		GPIO_VDD_5V_HIPOWER_nOC,          \
+		GPIO_VDD_3V3_SENSORS4_EN,         \
+		GPIO_VDD_3V3_SPEKTRUM_POWER_EN,   \
+		GPIO_VDD_3V3_SD_CARD_EN,          \
+		GPIO_ETH_POWER_EN,                \
+		GPIO_NFC_GPIO,                    \
+		GPIO_TONE_ALARM_IDLE,             \
+		GPIO_nSAFETY_SWITCH_LED_OUT_INIT, \
+		GPIO_SAFETY_SWITCH_IN,            \
+		GPIO_nARMED_INIT,                 \
+		GPIO_PWM_VOLT_SEL                \
+	}
+
+#define BOARD_ENABLE_CONSOLE_BUFFER
+
+#define PX4_I2C_BUS_MTD      4,5
+
+
+#define BOARD_NUM_IO_TIMERS 5
+
+__BEGIN_DECLS
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public data
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO-based MMC/SD card support
+ *
+ ****************************************************************************/
+
+int stm32_sdio_initialize(void);
+
+/****************************************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
+ *
+ ****************************************************************************************************/
+
+extern void stm32_spiinitialize(void);
+
+extern void stm32_usbinitialize(void);
+
+extern void board_peripheral_reset(int ms);
+
+#include <px4_platform_common/board_common.h>
+
+#endif /* __ASSEMBLY__ */
+
+__END_DECLS
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2023 PX4 Development Team. All rights reserved.
+ *   Copyright (c) 2019-2021 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -43,6 +43,7 @@
 #include <nuttx/config.h>
 #include <nuttx/board.h>
 #include <chip.h>
+#include <stm32_uart.h>
 #include <arch/board/board.h>
 #include "arm_internal.h"
 #include <px4_platform_common/init.h>
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2018-2019, 2023 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -32,71 +32,111 @@
 ****************************************************************************/

 /**
- * @file imxrt_ocram_initialize.c
+ * @file px4fmu_can.c
 *
- * PX4 fmu-v6xrt RAM startup early startup code.
+ * Board-specific CAN functions.
 */

-/****************************************************************************
- * Included Files
- ****************************************************************************/
+#if !defined(CONFIG_CAN)

+#include <stdint.h>
+
+#include "board_config.h"
+
+
+__EXPORT
+uint16_t board_get_can_interfaces(void)
+{
+	uint16_t enabled_interfaces = 0x3;
+
+	if (!PX4_MFT_HW_SUPPORTED(PX4_MFT_CAN2)) {
+		enabled_interfaces &= ~(1 << 1);
+	}
+
+	return enabled_interfaces;
+}
+
+#else
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
 #include "arm_internal.h"
-#include "imxrt_iomuxc.h"

-/****************************************************************************
- * Pre-Processor Definitions
- ****************************************************************************/
+#include "chip.h"
+#include "stm32_can.h"
+#include "board_config.h"

-__BEGIN_DECLS
-extern const uint64_t _fitcmfuncs;   /* Copy source address in FLASH */
-extern uint64_t _sitcmfuncs;         /* Copy destination start address in ITCM */
-extern uint64_t _eitcmfuncs;         /* Copy destination end address in ITCM */
-extern uint64_t _sdtcm;              /* Copy destination start address in DTCM */
-extern uint64_t _edtcm;              /* Copy destination end address in DTCM */
-__END_DECLS
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/

-/****************************************************************************
- * Name: imxrt_ocram_initialize
+#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
+#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#  undef CONFIG_STM32_CAN2
+#endif
+
+#ifdef CONFIG_STM32_CAN1
+#  define CAN_PORT 1
+#else
+#  define CAN_PORT 2
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+int can_devinit(void);
+
+/************************************************************************************
+ * Name: can_devinit
 *
 * Description:
- *   Called off reset vector to reconfigure the flexRAM
- *   and finish the FLASH to RAM Copy.
- *   CMakeLists.txt Forces compiler not to use builtin functions using -fno-builtin
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/can.
 *
- ****************************************************************************/
+ ************************************************************************************/

-__EXPORT void imxrt_ocram_initialize(void)
+int can_devinit(void)
 {
-	uint32_t regval;
-	register uint64_t *src;
-	register uint64_t *dest;
+	static bool initialized = false;
+	struct can_dev_s *can;
+	int ret;

-	/* FlexRAM Configuration
-	 *    F = 64K ITCM
-	 *    A = 64K DTCM
-	 *    5 = 64K OCRAM
-	 *    So 0xFFFFFFAA is
-	 *    384K FlexRAM ITCM
-	 *    128K FlexRAM DTCM
-	 * */
+	/* Check if we have already initialized */

-	putreg32(0xFFFFFFAA, IMXRT_IOMUXC_GPR_GPR17);
-	regval = getreg32(IMXRT_IOMUXC_GPR_GPR16);
-	putreg32(regval | GPR_GPR16_FLEXRAM_BANK_CFG_SEL, IMXRT_IOMUXC_GPR_GPR16);
+	if (!initialized) {
+		/* Call stm32_caninitialize() to get an instance of the CAN interface */

-	/* Copy any necessary code sections from FLASH to ITCM. The process is the
-	* same as the code copying from FLASH to RAM above. */
-	for (src = (uint64_t *)&_fitcmfuncs, dest = (uint64_t *)&_sitcmfuncs;
-	     dest < (uint64_t *)&_eitcmfuncs;) {
-		*dest++ = *src++;
+		can = stm32_caninitialize(CAN_PORT);
+
+		if (can == NULL) {
+			canerr("ERROR:  Failed to get CAN interface\n");
+			return -ENODEV;
+		}
+
+		/* Register the CAN driver at "/dev/can0" */
+
+		ret = can_register("/dev/can0", can);
+
+		if (ret < 0) {
+			canerr("ERROR: can_register failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Now we are initialized */
+
+		initialized = true;
 	}

-	/* Clear .dtcm.  We'll do this inline (vs. calling memset) just to be
-	* certain that there are no issues with the state of global variables.
-	*/
-
-	for (dest = &_sdtcm; dest < &_edtcm;) {
-		*dest++ = 0;
-	}
+	return OK;
 }
+#endif /* CONFIG_CAN */
@@ -61,24 +61,22 @@
 #define SERIAL0_DEV    0x02
 #define SERIAL1_DEV    0x04

-#define APP_LOAD_ADDRESS               0x70020000
-#define APP_VECTOR_OFFSET              0x2000
+#define APP_LOAD_ADDRESS               0x08020000
 #define BOOTLOADER_DELAY               5000
 #define INTERFACE_USB                  1
 #define INTERFACE_USB_CONFIG           "/dev/ttyACM0"
+#define BOARD_VBUS                     MK_GPIO_INPUT(GPIO_OTGFS_VBUS)

 //#define USE_VBUS_PULL_DOWN
 #define INTERFACE_USART                1
 #define INTERFACE_USART_CONFIG         "/dev/ttyS0,1500000"
-#define BOOT_DELAY_ADDRESS             0x00039FA0
-#define BOARD_TYPE                     37
-// The board has a 64 Mb part with 16384, 4K secors, but we artificialy limit it to 4 Mb
-// as 1024, 4K sectors
-#define BOARD_FLASH_SECTORS            960 // 1024 * 4k sectors, 128k for bootloader, 128k for storage
-#define BOARD_FIRST_FLASH_SECTOR_TO_ERASE 32 // We resreve 128K for the bootloader
-#define BOARD_FLASH_SIZE               (BOARD_FLASH_SECTORS * 4096)
+#define BOOT_DELAY_ADDRESS             0x000001a0
+#define BOARD_TYPE                     6110
+#define _FLASH_KBYTES                  (*(uint32_t *)0x1FF1E880)
+#define BOARD_FLASH_SECTORS            (15)
+#define BOARD_FLASH_SIZE               (_FLASH_KBYTES * 1024)//1024

-#define OSC_FREQ                       24
+#define OSC_FREQ                       16

 #define BOARD_PIN_LED_ACTIVITY         GPIO_nLED_BLUE // BLUE
 #define BOARD_PIN_LED_BOOTLOADER       GPIO_nLED_GREEN // GREEN
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (C) 2024 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2020 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -35,6 +35,7 @@

 constexpr px4_i2c_bus_t px4_i2c_buses[I2C_BUS_MAX_BUS_ITEMS] = {
 	initI2CBusExternal(1),
+	initI2CBusExternal(2),
 	initI2CBusExternal(3),
 	initI2CBusInternal(4),
 };
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2024 PX4 Development Team. All rights reserved.
+ *   Copyright (c) 2012-2022 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -34,7 +34,7 @@
 /**
 * @file init.c
 *
- * NXP imxrt1062-v1 specific early startup code.  This file implements the
+ * PX4FMU-specific early startup code.  This file implements the
 * board_app_initialize() function that is called early by nsh during startup.
 *
 * Code here is run before the rcS script is invoked; it should start required
@@ -47,48 +47,37 @@

 #include "board_config.h"

-#include <barriers.h>
 #include <stdbool.h>
 #include <stdio.h>
 #include <string.h>
 #include <debug.h>
 #include <errno.h>
-#include <syslog.h>

 #include <nuttx/config.h>
 #include <nuttx/board.h>
 #include <nuttx/spi/spi.h>
-#include <nuttx/i2c/i2c_master.h>
 #include <nuttx/sdio.h>
 #include <nuttx/mmcsd.h>
 #include <nuttx/analog/adc.h>
 #include <nuttx/mm/gran.h>
-
-#include "arm_internal.h"
-#include "imxrt_flexspi_nor_boot.h"
-#include <px4_arch/imxrt_flexspi_nor_flash.h>
-#include "imxrt_iomuxc.h"
-#include "imxrt_flexcan.h"
-#include "imxrt_enet.h"
 #include <chip.h>
-#include "board_config.h"
-
-#include <hardware/imxrt_lpuart.h>
-#undef FLEXSPI_LUT_COUNT
-#include <hardware/imxrt_flexspi.h>
-#include <hardware/imxrt_ccm.h>
-
+#include <stm32_uart.h>
 #include <arch/board/board.h>
+#include "arm_internal.h"

 #include <drivers/drv_hrt.h>
 #include <drivers/drv_board_led.h>
 #include <systemlib/px4_macros.h>
 #include <px4_arch/io_timer.h>
-#include <px4_arch/imxrt_romapi.h>
 #include <px4_platform_common/init.h>
+#include <px4_platform_common/px4_manifest.h>
 #include <px4_platform/gpio.h>
-#include <px4_platform/board_dma_alloc.h>
 #include <px4_platform/board_determine_hw_info.h>
+#include <px4_platform/board_dma_alloc.h>
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/

 /* Configuration ************************************************************/

@@ -103,11 +92,9 @@ __BEGIN_DECLS
 extern void led_init(void);
 extern void led_on(int led);
 extern void led_off(int led);
-
-extern uint32_t _srodata;            /* Start of .rodata */
-extern uint32_t _erodata;            /* End of .rodata */
 __END_DECLS

+
 /************************************************************************************
 * Name: board_peripheral_reset
 *
@@ -116,8 +103,23 @@ __END_DECLS
 ************************************************************************************/
 __EXPORT void board_peripheral_reset(int ms)
 {
+	/* set the peripheral rails off */
+
+	VDD_5V_PERIPH_EN(false);
+	board_control_spi_sensors_power(false, 0xffff);
+
+	/* wait for the peripheral rail to reach GND */
+	usleep(ms * 1000);
+	syslog(LOG_DEBUG, "reset done, %d ms\n", ms);
+
+	/* re-enable power */
+
+	/* switch the peripheral rail back on */
+	board_control_spi_sensors_power(true, 0xffff);
+	VDD_5V_PERIPH_EN(true);

 }
+
 /************************************************************************************
 * Name: board_on_reset
 *
@@ -129,11 +131,10 @@ __EXPORT void board_peripheral_reset(int ms)
 *          0 if just resetting
 *
 ************************************************************************************/
-
 __EXPORT void board_on_reset(int status)
 {
 	for (int i = 0; i < DIRECT_PWM_OUTPUT_CHANNELS; ++i) {
-		px4_arch_configgpio(PX4_MAKE_GPIO_INPUT(io_timer_channel_get_gpio_output(i)));
+		px4_arch_configgpio(io_timer_channel_get_gpio_output(i));
 	}

 	/*
@@ -146,95 +147,19 @@ __EXPORT void board_on_reset(int status)
 	}
 }

-/****************************************************************************
- * Name: imxrt_flash_romapi_initialize
+/************************************************************************************
+ * Name: stm32_boardinitialize
 *
 * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the initialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
 *
- ****************************************************************************/
-struct flexspi_nor_config_s g_bootConfig;
+ ************************************************************************************/

-locate_code(".ramfunc")
-void imxrt_flash_romapi_initialize(void)
+__EXPORT void
+stm32_boardinitialize(void)
 {
-	memcpy((struct flexspi_nor_config_s *)&g_bootConfig, &g_flash_config,
-	       sizeof(struct flexspi_nor_config_s));
-	g_bootConfig.memConfig.tag = FLEXSPI_CFG_BLK_TAG;
-
-	ROM_API_Init();
-
-	ROM_FLEXSPI_NorFlash_Init(NOR_INSTANCE, (struct flexspi_nor_config_s *)&g_bootConfig);
-	ROM_FLEXSPI_NorFlash_ClearCache(NOR_INSTANCE);
-
-	ARM_DSB();
-	ARM_ISB();
-	ARM_DMB();
-}
-
-locate_code(".ramfunc")
-void imxrt_flash_setup_prefetch_partition(void)
-{
-//Prefetch tuning to be determined
-#if 0
-	putreg32((uint32_t)&_srodata, IMXRT_FLEXSPI1_AHBBUFREGIONSTART0);
-	putreg32((uint32_t)&_erodata, IMXRT_FLEXSPI1_AHBBUFREGIONEND0);
-	/*putreg32((uint32_t)&_stext, IMXRT_FLEXSPI1_AHBBUFREGIONSTART1);
-	putreg32((uint32_t)&_etext, IMXRT_FLEXSPI1_AHBBUFREGIONEND1);
-	putreg32((uint32_t)&_stext, IMXRT_FLEXSPI1_AHBBUFREGIONSTART2);
-	putreg32((uint32_t)&_etext, IMXRT_FLEXSPI1_AHBBUFREGIONEND2);
-	putreg32((uint32_t)&_stext, IMXRT_FLEXSPI1_AHBBUFREGIONSTART3);
-	putreg32((uint32_t)&_etext, IMXRT_FLEXSPI1_AHBBUFREGIONEND3);*/
-#endif
-#if 0
-	struct flexspi_type_s *g_flexspi = (struct flexspi_type_s *)IMXRT_FLEXSPIC_BASE;
-	/* RODATA */
-	g_flexspi->AHBRXBUFCR0[0] = FLEXSPI_AHBRXBUFCR0_BUFSZ(48) |
-				    FLEXSPI_AHBRXBUFCR0_MSTRID(0) |
-				    FLEXSPI_AHBRXBUFCR0_PREFETCHEN(1) |
-				    FLEXSPI_AHBRXBUFCR0_REGIONEN(1);
-
-
-	/* All Text */
-	g_flexspi->AHBRXBUFCR0[1] = FLEXSPI_AHBRXBUFCR0_BUFSZ(80) |
-				    FLEXSPI_AHBRXBUFCR0_MSTRID(0) |
-				    FLEXSPI_AHBRXBUFCR0_PREFETCHEN(1) |
-				    FLEXSPI_AHBRXBUFCR0_REGIONEN(1);
-
-	/* Disable 2 */
-	g_flexspi->AHBRXBUFCR0[2] = FLEXSPI_AHBRXBUFCR0_BUFSZ(0) |
-				    FLEXSPI_AHBRXBUFCR0_MSTRID(0) |
-				    FLEXSPI_AHBRXBUFCR0_PREFETCHEN(1) |
-				    FLEXSPI_AHBRXBUFCR0_REGIONEN(0);
-
-	/* Disable 3 */
-	g_flexspi->AHBRXBUFCR0[3] = FLEXSPI_AHBRXBUFCR0_BUFSZ(0) |
-				    FLEXSPI_AHBRXBUFCR0_MSTRID(0) |
-				    FLEXSPI_AHBRXBUFCR0_PREFETCHEN(1) |
-				    FLEXSPI_AHBRXBUFCR0_REGIONEN(0);
-#endif
-
-	ARM_DSB();
-	ARM_ISB();
-	ARM_DMB();
-}
-
-/****************************************************************************
- * Name: imxrt_boardinitialize
- *
- * Description:
- *   All i.MX RT architectures must provide the following entry point.  This
- *   entry point is called early in the initialization -- after clocking and
- *   memory have been configured but before caches have been enabled and
- *   before any devices have been initialized.
- *
- ****************************************************************************/
-
-__EXPORT void imxrt_boardinitialize(void)
-{
-	imxrt_flash_setup_prefetch_partition();
-
-	imxrt_flash_romapi_initialize();
-
 	board_on_reset(-1); /* Reset PWM first thing */

 	/* configure LEDs */
@@ -246,75 +171,14 @@ __EXPORT void imxrt_boardinitialize(void)
 	const uint32_t gpio[] = PX4_GPIO_INIT_LIST;
 	px4_gpio_init(gpio, arraySize(gpio));

-	imxrt_usb_initialize();
+	/* configure USB interfaces */
+
+	stm32_usbinitialize();
+
+	VDD_3V3_ETH_POWER_EN(true);

-	fmurt1062_timer_initialize();
 }

-/****************************************************************************
- * Function: imxrt_phy_boardinitialize
- *
- * Description:
- *   Some boards require specialized initialization of the PHY before it can
- *   be used.  This may include such things as configuring GPIOs, resetting
- *   the PHY, etc.
- *   If CONFIG_IMXRT_ENET_PHYINIT is defined in the configuration then the
- *   board specific logic must provide imxrt_phyinitialize();
- *   The i.MX RT Ethernet driver will call this function one time before it
- *   first uses the PHY.
- *
- * Input Parameters:
- *   intf - Always zero for now.
- *
- * Returned Value:
- *   OK on success; Negated errno on failure.
- *
- ****************************************************************************/
-
-int imxrt_phy_boardinitialize(int intf)
-{
-#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
-	/* Configure the PHY interrupt pin */
-
-	printf("Configuring interrupt: %08x\n", GPIO_ENET_INT);
-	imxrt_config_gpio(GPIO_ENET_INT);
-#endif
-	return OK;
-}
-
-void imxrt_flexio_clocking(void)
-{
-	uint32_t reg;
-
-	/* Init USB PLL3 PFD2 */
-
-	reg = getreg32(IMXRT_CCM_ANALOG_PFD_480);
-
-	while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) &
-		CCM_ANALOG_PLL_USB1_LOCK) == 0) {
-	}
-
-	reg &= ~CCM_ANALOG_PFD_480_PFD2_FRAC_MASK;
-
-	/* Set PLL3 PFD2 to 480 * 18 / CONFIG_PLL3_PFD2_FRAC */
-
-	reg |= ((uint32_t)(CONFIG_PLL3_PFD2_FRAC) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT);
-
-	putreg32(reg, IMXRT_CCM_ANALOG_PFD_480);
-
-	reg = getreg32(IMXRT_CCM_CDCDR);
-	reg &= ~(CCM_CDCDR_FLEXIO1_CLK_SEL_MASK |
-		 CCM_CDCDR_FLEXIO1_CLK_PODF_MASK |
-		 CCM_CDCDR_FLEXIO1_CLK_PRED_MASK);
-	reg |= CCM_CDCDR_FLEXIO1_CLK_SEL(CONFIG_FLEXIO1_CLK);
-	reg |= CCM_CDCDR_FLEXIO1_CLK_PODF
-	       (CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO1_PODF_DIVIDER));
-	reg |= CCM_CDCDR_FLEXIO1_CLK_PRED
-	       (CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO1_PRED_DIVIDER));
-	putreg32(reg, IMXRT_CCM_CDCDR);
-}
-
-
 /****************************************************************************
 * Name: board_app_initialize
 *
@@ -339,62 +203,74 @@ void imxrt_flexio_clocking(void)
 *   any failure to indicate the nature of the failure.
 *
 ****************************************************************************/
+
 __EXPORT int board_app_initialize(uintptr_t arg)
 {
-	int ret = OK;
-
 #if !defined(BOOTLOADER)

-	imxrt_flexio_clocking();
-
 	/* Power on Interfaces */
+	VDD_3V3_SD_CARD_EN(true);
+	VDD_5V_PERIPH_EN(true);
+	VDD_5V_HIPOWER_EN(true);
+	VDD_3V3_SENSORS4_EN(true);
+	VDD_3V3_SPEKTRUM_POWER_EN(true);
+
+	/* Need hrt running before using the ADC */

 	px4_platform_init();

-	imxrt_spiinitialize();
+	// Use the default HW_VER_REV(0x0,0x0) for Ramtron

-	board_determine_hw_info();
+	stm32_spiinitialize();

-	/* configure the DMA allocator */
+	/* Configure the HW based on the manifest */
+
+	px4_platform_configure();
+
+	/* Configure the Actual SPI interfaces (after we determined the HW version)  */
+
+	stm32_spiinitialize();
+
+	board_spi_reset(10, 0xffff);
+
+	/* Configure the DMA allocator */

 	if (board_dma_alloc_init() < 0) {
 		syslog(LOG_ERR, "[boot] DMA alloc FAILED\n");
 	}

-#if defined(SERIAL_HAVE_RXDMA)
+#  if defined(SERIAL_HAVE_RXDMA)
 	// set up the serial DMA polling at 1ms intervals for received bytes that have not triggered a DMA event.
 	static struct hrt_call serial_dma_call;
-	hrt_call_every(&serial_dma_call, 1000, 1000, (hrt_callout)imxrt_serial_dma_poll, NULL);
-#endif
+	hrt_call_every(&serial_dma_call, 1000, 1000, (hrt_callout)stm32_serial_dma_poll, NULL);
+#  endif

-#if defined(CONFIG_IMXRT_USDHC)
-	ret = fmurt1062_usdhc_initialize();
-#endif
+	/* initial LED state */
+	drv_led_start();
+	led_off(LED_RED);
+	led_on(LED_GREEN); // Indicate Power.
+	led_off(LED_BLUE);

-	imxrt_spiinitialize();
-
-	board_spi_reset(10, 0xffff);
-
-#ifdef CONFIG_IMXRT_ENET
-	imxrt_gpio_write(GPIO_ENET_RST, true);
-
-	usleep(2000);
-
-	imxrt_netinitialize(0);
-#endif
-
-#ifdef CONFIG_IMXRT_FLEXCAN3
-	imxrt_caninitialize(3);
-#endif
-
-	ret = imxrt_flexspi_storage_initialize();
-
-	if (ret < 0) {
-		syslog(LOG_ERR,
-		       "ERROR: imxrt_flexspi_nor_initialize failed: %d\n", ret);
+	if (board_hardfault_init(2, true) != 0) {
+		led_on(LED_RED);
 	}

+	// Ensure Power is off for > 10 mS
+	usleep(15 * 1000);
+	VDD_3V3_SD_CARD_EN(true);
+	usleep(500 * 1000);
+
+#  ifdef CONFIG_MMCSD
+	int ret = stm32_sdio_initialize();
+
+	if (ret != OK) {
+		led_on(LED_RED);
+		return ret;
+	}
+
+#  endif /* CONFIG_MMCSD */
+
 #endif /* !defined(BOOTLOADER) */

-	return ret;
+	return OK;
 }
@@ -0,0 +1,235 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2013 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file px4fmu2_led.c
+ *
+ * PX4FMU LED backend.
+ */
+
+#include <px4_platform_common/px4_config.h>
+
+#include <stdbool.h>
+
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "board_config.h"
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+/*
+ * Ideally we'd be able to get these from arm_internal.h,
+ * but since we want to be able to disable the NuttX use
+ * of leds for system indication at will and there is no
+ * separate switch, we need to build independent of the
+ * CONFIG_ARCH_LEDS configuration switch.
+ */
+__BEGIN_DECLS
+extern void led_init(void);
+extern void led_on(int led);
+extern void led_off(int led);
+extern void led_toggle(int led);
+__END_DECLS
+
+#ifdef CONFIG_ARCH_LEDS
+static bool nuttx_owns_leds = true;
+//                                B  R  S  G
+//                                0  1  2  3
+static const uint8_t xlatpx4[] = {1, 2, 4, 0};
+#  define xlat(p) xlatpx4[(p)]
+static uint32_t g_ledmap[] = {
+	GPIO_nLED_GREEN,   // Indexed by BOARD_LED_GREEN
+	GPIO_nLED_BLUE,    // Indexed by BOARD_LED_BLUE
+	GPIO_nLED_RED,     // Indexed by BOARD_LED_RED
+	GPIO_nSAFETY_SWITCH_LED_OUT,  // Indexed by LED_SAFETY by xlatpx4
+};
+
+#else
+
+#  define xlat(p) (p)
+static uint32_t g_ledmap[] = {
+	GPIO_nLED_BLUE,                     // Indexed by LED_BLUE
+	GPIO_nLED_RED,                      // Indexed by LED_RED, LED_AMBER
+	0,                                  // Indexed by LED_SAFETY (defaulted to an input)
+	GPIO_nLED_GREEN,                    // Indexed by LED_GREEN
+};
+
+#endif
+
+__EXPORT void led_init(void)
+{
+	for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
+		if (g_ledmap[l] != 0) {
+			stm32_configgpio(g_ledmap[l]);
+		}
+	}
+}
+
+static void phy_set_led(int led, bool state)
+{
+	/* Drive Low to switch on */
+
+	if (g_ledmap[led] != 0) {
+		stm32_gpiowrite(g_ledmap[led], !state);
+	}
+}
+
+static bool phy_get_led(int led)
+{
+	/* If Low it is on */
+	if (g_ledmap[led] != 0) {
+		return !stm32_gpioread(g_ledmap[led]);
+	}
+
+	return false;
+}
+
+__EXPORT void led_on(int led)
+{
+	phy_set_led(xlat(led), true);
+}
+
+__EXPORT void led_off(int led)
+{
+	phy_set_led(xlat(led), false);
+}
+
+__EXPORT void led_toggle(int led)
+{
+	phy_set_led(xlat(led), !phy_get_led(xlat(led)));
+}
+
+#ifdef CONFIG_ARCH_LEDS
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+	led_init();
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+	if (!nuttx_owns_leds) {
+		return;
+	}
+
+	switch (led) {
+	default:
+		break;
+
+	case LED_HEAPALLOCATE:
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_IRQSENABLED:
+		phy_set_led(BOARD_LED_BLUE, false);
+		phy_set_led(BOARD_LED_GREEN, true);
+		break;
+
+	case LED_STACKCREATED:
+		phy_set_led(BOARD_LED_GREEN, true);
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_INIRQ:
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_SIGNAL:
+		phy_set_led(BOARD_LED_GREEN, true);
+		break;
+
+	case LED_ASSERTION:
+		phy_set_led(BOARD_LED_RED, true);
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_PANIC:
+		phy_set_led(BOARD_LED_RED, true);
+		break;
+
+	case LED_IDLE : /* IDLE */
+		phy_set_led(BOARD_LED_RED, true);
+		break;
+	}
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+	if (!nuttx_owns_leds) {
+		return;
+	}
+
+	switch (led) {
+	default:
+		break;
+
+	case LED_SIGNAL:
+		phy_set_led(BOARD_LED_GREEN, false);
+		break;
+
+	case LED_INIRQ:
+		phy_set_led(BOARD_LED_BLUE, false);
+		break;
+
+	case LED_ASSERTION:
+		phy_set_led(BOARD_LED_RED, false);
+		phy_set_led(BOARD_LED_BLUE, false);
+		break;
+
+	case LED_PANIC:
+		phy_set_led(BOARD_LED_RED, false);
+		break;
+
+	case LED_IDLE : /* IDLE */
+		phy_set_led(BOARD_LED_RED, false);
+		break;
+	}
+}
+
+#endif /* CONFIG_ARCH_LEDS */
@@ -0,0 +1,130 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2020 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <board_config.h>
+
+#include <nuttx/spi/spi.h>
+#include <px4_platform_common/px4_manifest.h>
+//                                                              KiB BS    nB
+static const px4_mft_device_t spi5 = {             // FM25V02A on FMUM native: 32K X 8, emulated as (1024 Blocks of 32)
+	.bus_type = px4_mft_device_t::SPI,
+	.devid    = SPIDEV_FLASH(0)
+};
+static const px4_mft_device_t i2c3 = {             // 24LC64T on Base  8K 32 X 256
+	.bus_type = px4_mft_device_t::I2C,
+	.devid    = PX4_MK_I2C_DEVID(3, 0x51)
+};
+static const px4_mft_device_t i2c4 = {             // 24LC64T on IMU   8K 32 X 256
+	.bus_type =  px4_mft_device_t::I2C,
+	.devid    =  PX4_MK_I2C_DEVID(4, 0x50)
+};
+
+
+static const px4_mtd_entry_t fmum_fram = {
+	.device = &spi5,
+	.npart = 1,
+	.partd = {
+		{
+			.type = MTD_PARAMETERS,
+			.path = "/fs/mtd_params",
+			.nblocks = (32768 / (1 << CONFIG_RAMTRON_EMULATE_SECTOR_SHIFT))
+		}
+	},
+};
+
+static const px4_mtd_entry_t base_eeprom = {
+	.device = &i2c3,
+	.npart = 2,
+	.partd = {
+		{
+			.type = MTD_MFT_VER,
+			.path = "/fs/mtd_mft_ver",
+			.nblocks = 248
+		},
+		{
+			.type = MTD_NET,
+			.path = "/fs/mtd_net",
+			.nblocks = 8 // 256 = 32 * 8
+
+		}
+	},
+};
+
+static const px4_mtd_entry_t imu_eeprom = {
+	.device = &i2c4,
+	.npart = 3,
+	.partd = {
+		{
+			.type = MTD_CALDATA,
+			.path = "/fs/mtd_caldata",
+			.nblocks = 240
+		},
+		{
+			.type = MTD_MFT_REV,
+			.path = "/fs/mtd_mft_rev",
+			.nblocks = 8
+		},
+		{
+			.type = MTD_ID,
+			.path = "/fs/mtd_id",
+			.nblocks = 8 // 256 = 32 * 8
+		}
+	},
+};
+
+static const px4_mtd_manifest_t board_mtd_config = {
+	.nconfigs   = 3,
+	.entries = {
+		&fmum_fram,
+		&base_eeprom,
+		&imu_eeprom
+	}
+};
+
+static const px4_mft_entry_s mtd_mft = {
+	.type = MTD,
+	.pmft = (void *) &board_mtd_config,
+};
+
+static const px4_mft_s mft = {
+	.nmft = 1,
+	.mfts = {
+		&mtd_mft,
+	}
+};
+
+const px4_mft_s *board_get_manifest(void)
+{
+	return &mft;
+}
@@ -1,8 +1,7 @@
 /****************************************************************************
 *
- *   Copyright (C) 2016-2018 Gregory Nutt. All rights reserved.
- *   Authors: Gregory Nutt <gnutt@nuttx.org>
- *            David Sidrane <david_s5@nscdg.com>
+ *   Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -32,97 +31,147 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/
-/* A micro Secure Digital (SD) card slot is available on the board connected to
- * the SD Host Controller (USDHC1) signals of the MCU. This slot will accept
- * micro format SD memory cards.
- *
- *   ------------ ------------- --------
- *    SD Card Slot Board Signal  IMXRT Pin
- *    ------------ ------------- --------
- *    DAT0         USDHC1_DATA0  GPIO_SD_B0_02
- *    DAT1         USDHC1_DATA1  GPIO_SD_B0_03
- *    DAT2         USDHC1_DATA2  GPIO_SD_B0_04
- *    CD/DAT3      USDHC1_DATA3  GPIO_SD_B0_05
- *    CMD          USDHC1_CMD    GPIO_SD_B0_00
- *    CLK          USDHC1_CLK    GPIO_SD_B0_01
- *    CD           USDHC1_CD     GPIO_B1_12
- *    ------------ ------------- --------
- *
- * There are no Write Protect available to the IMXRT.
- */

 /****************************************************************************
 * Included Files
 ****************************************************************************/

-#include <px4_platform_common/px4_config.h>
-#include <px4_log.h>
+#include <nuttx/config.h>
+#include <board_config.h>

 #include <stdbool.h>
 #include <stdio.h>
 #include <debug.h>
 #include <errno.h>
-#include <debug.h>

 #include <nuttx/sdio.h>
 #include <nuttx/mmcsd.h>

 #include "chip.h"
-#include "imxrt_usdhc.h"
-
 #include "board_config.h"
+#include "stm32_gpio.h"
+#include "stm32_sdmmc.h"
+
+#ifdef CONFIG_MMCSD
+

-#ifdef CONFIG_IMXRT_USDHC
 /****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/

-/****************************************************************************
- * Private Types
- ****************************************************************************/
+/* Card detections requires card support and a card detection GPIO */
+
+#define HAVE_NCD   1
+#if !defined(GPIO_SDMMC1_NCD)
+#  undef HAVE_NCD
+#endif
+
 /****************************************************************************
 * Private Data
 ****************************************************************************/
+
+static FAR struct sdio_dev_s *sdio_dev;
+#ifdef HAVE_NCD
+static bool g_sd_inserted = 0xff; /* Impossible value */
+#endif
+
 /****************************************************************************
 * Private Functions
 ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_ncd_interrupt
+ *
+ * Description:
+ *   Card detect interrupt handler.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_NCD
+static int stm32_ncd_interrupt(int irq, FAR void *context)
+{
+	bool present;
+
+	present = !stm32_gpioread(GPIO_SDMMC1_NCD);
+
+	if (sdio_dev && present != g_sd_inserted) {
+		sdio_mediachange(sdio_dev, present);
+		g_sd_inserted = present;
+	}
+
+	return OK;
+}
+#endif
+
 /****************************************************************************
 * Public Functions
 ****************************************************************************/

 /****************************************************************************
- * Name: fmurt1062_usdhc_initialize
+ * Name: stm32_sdio_initialize
 *
 * Description:
- *   Inititialize the SDHC SD card slot
+ *   Initialize SDIO-based MMC/SD card support
 *
 ****************************************************************************/

-int fmurt1062_usdhc_initialize(void)
+int stm32_sdio_initialize(void)
 {
 	int ret;

-	/* Mount the SDHC-based MMC/SD block driver */
-	/* First, get an instance of the SDHC interface */
+#ifdef HAVE_NCD
+	/* Card detect */

-	struct sdio_dev_s *sdhc = imxrt_usdhc_initialize(CONFIG_NSH_MMCSDSLOTNO);
+	bool cd_status;

-	if (!sdhc) {
-		PX4_ERR("ERROR: Failed to initialize SDHC slot %d\n", CONFIG_NSH_MMCSDSLOTNO);
+	/* Configure the card detect GPIO */
+
+	stm32_configgpio(GPIO_SDMMC1_NCD);
+
+	/* Register an interrupt handler for the card detect pin */
+
+	stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, stm32_ncd_interrupt);
+#endif
+
+	/* Mount the SDIO-based MMC/SD block driver */
+	/* First, get an instance of the SDIO interface */
+
+	finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO);
+
+	sdio_dev = sdio_initialize(SDIO_SLOTNO);
+
+	if (!sdio_dev) {
+		syslog(LOG_ERR, "[boot] Failed to initialize SDIO slot %d\n", SDIO_SLOTNO);
 		return -ENODEV;
 	}

-	/* Now bind the SDHC interface to the MMC/SD driver */
+	/* Now bind the SDIO interface to the MMC/SD driver */

-	ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdhc);
+	finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR);
+
+	ret = mmcsd_slotinitialize(SDIO_MINOR, sdio_dev);

 	if (ret != OK) {
-		PX4_ERR("ERROR: Failed to bind SDHC to the MMC/SD driver: %d\n", ret);
+		syslog(LOG_ERR, "[boot] Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
 		return ret;
 	}

-	syslog(LOG_INFO, "Successfully bound SDHC to the MMC/SD driver\n");
+	finfo("Successfully bound SDIO to the MMC/SD driver\n");
+
+#ifdef HAVE_NCD
+	/* Use SD card detect pin to check if a card is g_sd_inserted */
+
+	cd_status = !stm32_gpioread(GPIO_SDMMC1_NCD);
+	finfo("Card detect : %d\n", cd_status);
+
+	sdio_mediachange(sdio_dev, cd_status);
+#else
+	/* Assume that the SD card is inserted.  What choice do we have? */
+
+	sdio_mediachange(sdio_dev, true);
+#endif

 	return OK;
 }
-#endif /* CONFIG_IMXRT_USDHC */
+
+#endif /* CONFIG_MMCSD */
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (c) 2023 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2020, 2022 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -31,49 +31,28 @@
 *
 ****************************************************************************/

-/**
- * @file manifest.c
- *
- * This module supplies the interface to the manifest of hardware that is
- * optional and dependent on the HW REV and HW VER IDs
- *
- * The manifest allows the system to know whether a hardware option
- * say for example the PX4IO is an no-pop option vs it is broken.
- *
- */
+#include <px4_arch/spi_hw_description.h>
+#include <drivers/drv_sensor.h>
+#include <nuttx/spi/spi.h>

-/****************************************************************************
- * Included Files
- ****************************************************************************/
+constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
+	initSPIBus(SPI::Bus::SPI1, {
+		initSPIDevice(DRV_IMU_DEVTYPE_ICM20649, SPI::CS{GPIO::PortI, GPIO::Pin9}, SPI::DRDY{GPIO::PortF, GPIO::Pin2}),
+	}, {GPIO::PortI, GPIO::Pin11}),
+	initSPIBus(SPI::Bus::SPI2, {
+		initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortH, GPIO::Pin5}, SPI::DRDY{GPIO::PortA, GPIO::Pin10}),
+	}, {GPIO::PortF, GPIO::Pin4}),
+	initSPIBus(SPI::Bus::SPI3, {
+		initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::PortI, GPIO::Pin8}, SPI::DRDY{GPIO::PortI, GPIO::Pin7}),
+		initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::PortI, GPIO::Pin4}, SPI::DRDY{GPIO::PortI, GPIO::Pin6}),
+	}, {GPIO::PortE, GPIO::Pin7}),
+	initSPIBus(SPI::Bus::SPI5, {
+		initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortG, GPIO::Pin7})
+	}),
+	initSPIBusExternal(SPI::Bus::SPI6, {
+		initSPIConfigExternal(SPI::CS{GPIO::PortI, GPIO::Pin10}, SPI::DRDY{GPIO::PortD, GPIO::Pin11}),
+		initSPIConfigExternal(SPI::CS{GPIO::PortA, GPIO::Pin15}, SPI::DRDY{GPIO::PortD, GPIO::Pin12}),
+	}),
+};

-#include <px4_platform_common/px4_config.h>
-#include <stdbool.h>
-#include <syslog.h>
-
-#include "systemlib/px4_macros.h"
-#include "px4_log.h"
-
-/****************************************************************************
- * Pre-Processor Definitions
- ****************************************************************************/
-
-
-/************************************************************************************
- * Name: board_query_manifest
- *
- * Description:
- *   Optional returns manifest item.
- *
- * Input Parameters:
- *   manifest_id - the ID for the manifest item to retrieve
- *
- * Returned Value:
- *   0 - item is not in manifest => assume legacy operations
- *   pointer to a manifest item
- *
- ************************************************************************************/
-
-__EXPORT px4_hw_mft_item board_query_manifest(px4_hw_mft_item_id_t id)
-{
-	return px4_hw_mft_unsupported;
-}
+static constexpr bool unused = validateSPIConfig(px4_spi_buses);
@@ -0,0 +1,80 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#include <px4_arch/io_timer_hw_description.h>
+
+/* Timer allocation
+ *
+ * TIM5_CH4  T FMU_CH1
+ * TIM5_CH3  T FMU_CH2
+ * TIM5_CH2  T FMU_CH3
+ * TIM5_CH1  T FMU_CH4
+ *
+ * TIM4_CH2  T FMU_CH5
+ * TIM4_CH3  T FMU_CH6
+ *
+ * TIM12_CH1 T FMU_CH7
+ * TIM12_CH2 T FMU_CH8
+ *
+ * TIM1_CH2  T FMU_CAP1               < Capture
+ * TIM1_CH3  T SPI2_DRDY2_ISM330_INT2 < Capture or GPIO INT
+ * TIM1_CH1  T SPIX_SYNC              > Pulse or GPIO strobe
+ *
+ * TIM2_CH3  T HEATER                 > PWM OUT or GPIO
+ *
+ * TIM14_CH1 T BUZZER_1              - Driven by other driver
+ * TIM8_CH1_IN T FMU_PPM_INPUT       - Sampled byt HRT by other driver
+ */
+
+constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
+	initIOTimer(Timer::Timer5, DMA{DMA::Index1}),
+	initIOTimer(Timer::Timer4, DMA{DMA::Index1}),
+	initIOTimer(Timer::Timer12),
+	initIOTimer(Timer::Timer1),
+	initIOTimer(Timer::Timer2),
+};
+
+constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
+	initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel4}, {GPIO::PortI, GPIO::Pin0}),
+	initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel3}, {GPIO::PortH, GPIO::Pin12}),
+	initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel2}, {GPIO::PortH, GPIO::Pin11}),
+	initIOTimerChannel(io_timers, {Timer::Timer5, Timer::Channel1}, {GPIO::PortH, GPIO::Pin10}),
+	initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel2}, {GPIO::PortD, GPIO::Pin13}),
+	initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel3}, {GPIO::PortD, GPIO::Pin14}),
+	initIOTimerChannel(io_timers, {Timer::Timer12, Timer::Channel1}, {GPIO::PortH, GPIO::Pin6}),
+	initIOTimerChannel(io_timers, {Timer::Timer12, Timer::Channel2}, {GPIO::PortH, GPIO::Pin9}),
+	initIOTimerChannelCapture(io_timers, {Timer::Timer1, Timer::Channel2}, {GPIO::PortE, GPIO::Pin11}),
+};
+
+constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
+	initIOTimerChannelMapping(io_timers, timer_io_channels);
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
- *   Copyright (C) 2024 PX4 Development Team. All rights reserved.
+ *   Copyright (C) 2016 PX4 Development Team. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -32,7 +32,7 @@
 ****************************************************************************/

 /**
- * @file usb.c
+ * @file px4fmu_usb.c
 *
 * Board-specific USB functions.
 */
@@ -53,9 +53,9 @@

 #include <arm_internal.h>
 #include <chip.h>
-#include <hardware/imxrt_usb_analog.h>
+#include <stm32_gpio.h>
+#include <stm32_otg.h>
 #include "board_config.h"
-#include "imxrt_periphclks.h"

 /************************************************************************************
 * Definitions
@@ -68,62 +68,38 @@
 /************************************************************************************
 * Public Functions
 ************************************************************************************/
-int imxrt_usb_initialize(void)
-{
-	imxrt_clockall_usboh3();
-	return 0;
-}
+
 /************************************************************************************
- * Name:  imxrt_usbpullup
+ * Name: stm32_usbinitialize
 *
 * Description:
- *   If USB is supported and the board supports a pullup via GPIO (for USB software
- *   connect and disconnect), then the board software must provide imxrt_usbpullup.
- *   See include/nuttx/usb/usbdev.h for additional description of this method.
- *   Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
- *   NULL.
+ *   Called to setup USB-related GPIO pins for the PX4FMU board.
 *
 ************************************************************************************/

-__EXPORT
-int imxrt_usbpullup(FAR struct usbdev_s *dev, bool enable)
+__EXPORT void stm32_usbinitialize(void)
 {
-	usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
+	/* The OTG FS has an internal soft pull-up */

-	return OK;
+	/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
+
+#ifdef CONFIG_STM32H7_OTGFS
+	stm32_configgpio(GPIO_OTGFS_VBUS);
+#endif
 }

 /************************************************************************************
- * Name:  imxrt_usbsuspend
+ * Name:  stm32_usbsuspend
 *
 * Description:
- *   Board logic must provide the imxrt_usbsuspend logic if the USBDEV driver is
+ *   Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
 *   used.  This function is called whenever the USB enters or leaves suspend mode.
 *   This is an opportunity for the board logic to shutdown clocks, power, etc.
 *   while the USB is suspended.
 *
 ************************************************************************************/

-__EXPORT
-void imxrt_usbsuspend(FAR struct usbdev_s *dev, bool resume)
+__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
 {
 	uinfo("resume: %d\n", resume);
 }
-
-/************************************************************************************
- * Name: board_read_VBUS_state
- *
- * Description:
- *   All boards must provide a way to read the state of VBUS, this my be simple
- *   digital input on a GPIO. Or something more complicated like a Analong input
- *   or reading a bit from a USB controller register.
- *
- * Returns -  0 if connected.
- *
- ************************************************************************************/
-
-int board_read_VBUS_state(void)
-{
-
-	return (getreg32(IMXRT_USB_ANALOG_USB1_VBUS_DETECT_STAT) & USB_ANALOG_USB_VBUS_DETECT_STAT_VBUS_VALID) ? 0 : 1;
-}
@@ -187,6 +187,7 @@
      - [Radiolink PIX6](flight_controller/radiolink_pix6.md)
      - [Sky-Drones AIRLink](flight_controller/airlink.md)
      - [SPRacing SPRacingH7EXTREME](flight_controller/spracingh7extreme.md)
+      - [SVehicle E2](flight_controller/svehicle_e2.md)
      - [ThePeach FCC-K1](flight_controller/thepeach_k1.md)
      - [ThePeach FCC-R1](flight_controller/thepeach_r1.md)
    - [Experimental Autopilots](flight_controller/autopilot_experimental.md)
@@ -74,7 +74,7 @@ For example, you might have the following settings to assign the gimbal roll, pi

 ![Gimbal Actuator config](../../assets/config/actuators/qgc_actuators_gimbal.png)

-The PWM values to use for the disarmed, maximum, center and minimum values can be determined in the same way as other servo, using the [Actuator Test sliders](../config/actuators.md#actuator-testing) to confirm that each slider moves the appropriate axis, and changing the values so that the gimbal is in the appropriate position at the disarmed, low, center and high position in the slider.
+The PWM values to use for the disarmed, maximum and minimum values can be determined in the same way as other servo, using the [Actuator Test sliders](../config/actuators.md#actuator-testing) to confirm that each slider moves the appropriate axis, and changing the values so that the gimbal is in the appropriate position at the disarmed, low and high position in the slider.
 The values may also be provided in gimbal documentation.

 ## Gimbal Control in Missions
@@ -159,7 +159,7 @@ The fields are:
 - `Yaw Torque`: Effectiveness of actuator around yaw axis (normalised: -1 to 1).
  [Generally you should use the default actuator value](#actuator-roll-pitch-and-yaw-scaling).
 - `Trim`: An offset added to the actuator so that it is centered without input.
-  This might be determined by trial and error. Prefer using the improved `PWM_CENT` instead: [PWM control surfaces](./actuators.md#pwm-control-surfaces-that-move-both-directions-about-a-neutral-point)
+  This might be determined by trial and error.
 - <a id="slew_rate"></a>(Advanced) `Slew Rate`: Limits the minimum time in which the motor/servo signal is allowed to pass through its full output range, in seconds.
  - The setting limits the rate of change of an actuator (if not specified then no rate limit is applied).
    It is intended for actuators that may be damaged or cause flight disturbance if they move too fast — such as the tilting actuators on a tiltrotor VTOL vehicle, or fast moving flaps, respectively.
@@ -535,40 +535,12 @@ If you're using PWM servos, PWM50 is far more common.
 If a high rate servo is _really_ needed, DShot offers better value.
 :::

-##### PWM: Control surfaces that move both directions about a neutral point
-
-To facilitate setting the neutral point of the servos, a bilinear curve function can be defined using the following parameters `PWM_MAIM_CENTx` / `PWM_AUX_CENTx` for each servo. This allows for unequal deflections in the positive and negative direction:
-![Asymetric Servo Deflections](../../assets/config/actuators/servo_pwm_center.png)
-
-To set this up:
-
-1. Set all surface `Trim` to `0.00` for all surfaces:
-
-     ![PWM Trimming](../../assets/config/actuators/control_surface_trim.png)
-
-1. Set the `PWM_MAIN_CENTx` / `PWM_AUX_CENTx` value so that the surface will stay at the neutral (aligned with airfoil) position.
-This is usually around `1500` for PWM servos (near the center of the servo range).
-
-![Control Surface Trimming](../../assets/config/actuators/pwm_center_output.png)
-
-2. Gradualy increase the `Maximum` for each servo until the desired deflection is reached. Check the deflection with a remote manual mode while  [`COM_PREARM_MODE`](../advanced_config/parameter_reference.md#COM_PREARM_MODE) is set to `Always` or use the sliders.
-3. Gradualy decrease the `Minimum` for each servo, until the desired deflection is reached.
-4. Set `Disarmed` value to the desired value. It is usually desirable to have it the same as the `Center` value.
-
-::: info
-If you want to retain the linear behaviour of the servo after setting the `Center`, make sure to adjust the `Minimum` or `Maximum`, such that both invervals (`min` to `cent` & `cent` to `max`) are equally lare.
-
-![Linear PWM Adjustment](../../assets/config/actuators/servo_pwm_linear.png)
-:::
-
-#### Non-PWM: Control surfaces that move both directions about a neutral point
+#### Control surfaces that move both directions about a neutral point

 Control surfaces that move either direction around a neutral point include: ailerons, elevons, V-tails, A-tails, and rudders.

 To set these up:

-0. Set all `PWM_MAIN_CENTx` and `PWM_AUX_CENTx` to default (-1), or trimming will not be possible.
-
 1. Set the `Disarmed` value so that the surfaces will stay at neutral position when disarmed.
   This is usually around `1500` for PWM servos (near the centre of the servo range).

@@ -587,20 +559,14 @@ To set these up:
 3. Move the slider again to the middle and check if the Control Surfaces are aligned in the neutral position of the wing.
   - If it is not aligned, you can set the **Trim** value for the control surface.

-    ::: info
-    This is done in the `Trim` setting of the Geometry panel, usually by "trial and error".
-    ![Control Surface Trimming](../../assets/config/actuators/control_surface_trim.png)
-    :::
+     ::: info
+     This is done in the `Trim` setting of the Geometry panel, usually by "trial and error".
+     ![Control Surface Trimming](../../assets/config/actuators/control_surface_trim.png)
+     :::

   - After setting the trim for a control surface, move its slider away from the centre, release, and then back into disarmed (middle) position.
     Confirm that surface is in the neutral position.

-
-
-::: tip
-If any servo has a `PWM_MAIN_CENTx` or `PWM_AUX_CENTx` not set to default (-1), the system will automatically remove `Trim` from all surfaces. This is done to prevent mixing of old and new trimming tools.
-:::
-
 ::: info
 Another way to test without using the sliders would be to set the [`COM_PREARM_MODE`](../advanced_config/parameter_reference.md#COM_PREARM_MODE) parameter to `Always`:

@@ -609,8 +575,6 @@ Another way to test without using the sliders would be to set the [`COM_PREARM_M

 :::

-
-
 #### Control surfaces that move from neutral to full deflection

 Control surfaces that move only one direction from neutral include: airbrakes, spoilers, and flaps.
@@ -621,7 +585,6 @@ For a flap, that is when the flap is fully retracted and flush with the wing.

 One approach for setting these up is:

-0. Set all `PWM_MAIN_CENTx` and `PWM_AUX_CENTx` to default (-1), or trimming will not be possible.
 1. Set values `Disarmed` to `1500`, `Min` to `1200`, `Max` to `1700` so that the values are around the centre of the servo range.
 2. Move the corresponding slider up and check the control moves and that it is extending (moving away from the disarmed position).
   If not, click on the `Rev Range` checkbox to reverse the range.
@@ -631,7 +594,6 @@ One approach for setting these up is:
   - If the value was increased towards `Max`, then set `Max` to match `Disarmed`.
 4. The value that you did _not_ set to match `Disarmed` controls the maximum amount that the control surface can extend.
   Set the slider to the top of the control, then change the value (`Max` or `Min`) so that the control surface is fully extended when the slider is at top.
-5. (Only PWM servos) Set the `Center` value to the middle between `Min` and `Max`.

 ::: info Special note for flaps
 In some vehicle builds, flaps may be configured such that both flaps are controlled from a single output.
@@ -669,9 +631,6 @@ For each of the tilt servos:
  - Standard VTOL : Motors defined as multicopter motors will be turned off
  - Tiltrotors : Motors that have no associated tilt servo will turn off
  - Tailsitters do not turn off any motors in fixed-wing flight
- The following formula can be used to migrate from surface trim to PWM trim:
-
-  `PWM_MAIN_CENTx = ((PWM_MAX - PWM_MIN) / 2) * CA_SV_CSx_TRIM + PWM_MIN + ((PWM_MAX - PWM_MIN) / 2)`

 ### Reversing Motors

@@ -83,9 +83,10 @@ This is done using the the parameters named like `UAVCAN_SUB_*` in the parameter

 On the ARK CANnode, you may need to configure the following parameters:

-| Parameter                                                                                       | Description                   |
-| ----------------------------------------------------------------------------------------------- | ----------------------------- |
-| <a id="CANNODE_TERM"></a>[CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM) | CAN built-in bus termination. |
+| Parameter                                                                                             | Description                                                                                                                                        |
+| ----------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------------------------------------------------------- |
+| <a id="CANNODE_NODE_ID"></a>[CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID) | CAN node ID (0 for dynamic allocation). If set to 0 (default), dynamic node allocation is used. Set to 1-127 to use a static node ID.            |
+| <a id="CANNODE_TERM"></a>[CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM)       | CAN built-in bus termination.                                                                                                                      |

 ## LED Meanings

@@ -110,9 +110,10 @@ When optical flow is the only source of horizontal position/velocity, then lower

 On the ARK Flow, you may need to configure the following parameters:

-| Parameter                                                                                       | Description                   |
-| ----------------------------------------------------------------------------------------------- | ----------------------------- |
-| <a id="CANNODE_TERM"></a>[CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM) | CAN built-in bus termination. |
+| Parameter                                                                                             | Description                                                                                                                                        |
+| ----------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------------------------------------------------------- |
+| <a id="CANNODE_NODE_ID"></a>[CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID) | CAN node ID (0 for dynamic allocation). If set to 0 (default), dynamic node allocation is used. Set to 1-127 to use a static node ID.            |
+| <a id="CANNODE_TERM"></a>[CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM)       | CAN built-in bus termination.                                                                                                                      |

 ## LED Meanings

@@ -105,9 +105,10 @@ Set the following parameters in _QGroundControl_:

 You may need to [configure the following parameters](../dronecan/index.md#qgc-cannode-parameter-configuration) on the ARK Flow MR itself:

-| Parameter                                                                                       | Description                   |
-| ----------------------------------------------------------------------------------------------- | ----------------------------- |
-| <a id="CANNODE_TERM"></a>[CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM) | CAN built-in bus termination. |
+| Parameter                                                                                             | Description                                                                                                                                        |
+| ----------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------------------------------------------------------- |
+| <a id="CANNODE_NODE_ID"></a>[CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID) | CAN node ID (0 for dynamic allocation). If set to 0 (default), dynamic node allocation is used. Set to 1-127 to use a static node ID.            |
+| <a id="CANNODE_TERM"></a>[CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM)       | CAN built-in bus termination.                                                                                                                      |

 ## LED Meanings

@@ -91,9 +91,17 @@ If the sensor is not centred within the vehicle you will also need to define sen

 - Enable GPS yaw fusion by setting bit 3 of [EKF2_GPS_CTRL](../advanced_config/parameter_reference.md#EKF2_GPS_CTRL) to true.
 - Enable [UAVCAN_SUB_GPS](../advanced_config/parameter_reference.md#UAVCAN_SUB_GPS), [UAVCAN_SUB_MAG](../advanced_config/parameter_reference.md#UAVCAN_SUB_MAG), and [UAVCAN_SUB_BARO](../advanced_config/parameter_reference.md#UAVCAN_SUB_BARO).
- Set [CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM) to `1` if this is that last node on the CAN bus.
 - The parameters [EKF2_GPS_POS_X](../advanced_config/parameter_reference.md#EKF2_GPS_POS_X), [EKF2_GPS_POS_Y](../advanced_config/parameter_reference.md#EKF2_GPS_POS_Y) and [EKF2_GPS_POS_Z](../advanced_config/parameter_reference.md#EKF2_GPS_POS_Z) can be set to account for the offset of the ARK GPS from the vehicles centre of gravity.

+### ARK GPS Configuration
+
+You may need to [configure the following parameters](../dronecan/index.md#qgc-cannode-parameter-configuration) on the ARK GPS itself:
+
+| Parameter                                                                                             | Description                                                                                                                                        |
+| ----------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------------------------------------------------------- |
+| <a id="CANNODE_NODE_ID"></a>[CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID) | CAN node ID (0 for dynamic allocation). If set to 0 (default), dynamic node allocation is used. Set to 1-127 to use a static node ID.            |
+| <a id="CANNODE_TERM"></a>[CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM)       | CAN built-in bus termination. Set to `1` if this is the last node on the CAN bus.                                                                 |
+
 ## LED Meanings

 You will see green, blue and red LEDs on the ARK GPS when it is being flashed, and a blinking green LED if it is running properly.
@@ -85,7 +85,15 @@ You need to set necessary [DroneCAN](index.md) parameters and define offsets if
 - Enable GPS blending to ensure the heading is always published by setting [SENS_GPS_MASK](../advanced_config/parameter_reference.md#SENS_GPS_MASK) to 7 (all three bits checked).
 - Enable [UAVCAN_SUB_GPS](../advanced_config/parameter_reference.md#UAVCAN_SUB_GPS), [UAVCAN_SUB_MAG](../advanced_config/parameter_reference.md#UAVCAN_SUB_MAG), and [UAVCAN_SUB_BARO](../advanced_config/parameter_reference.md#UAVCAN_SUB_BARO).
 - The parameters [EKF2_GPS_POS_X](../advanced_config/parameter_reference.md#EKF2_GPS_POS_X), [EKF2_GPS_POS_Y](../advanced_config/parameter_reference.md#EKF2_GPS_POS_Y) and [EKF2_GPS_POS_Z](../advanced_config/parameter_reference.md#EKF2_GPS_POS_Z) can be set to account for the offset of the ARK RTK GPS from the vehicles centre of gravity.
- Set [CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM) to `1` on the GPS if this it that last node on the CAN bus.
+
+### ARK RTK GPS Configuration
+
+You may need to [configure the following parameters](../dronecan/index.md#qgc-cannode-parameter-configuration) on the ARK RTK GPS itself:
+
+| Parameter                                                                                             | Description                                                                                                                                        |
+| ----------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------------------------------------------------------- |
+| <a id="CANNODE_NODE_ID"></a>[CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID) | CAN node ID (0 for dynamic allocation). If set to 0 (default), dynamic node allocation is used. Set to 1-127 to use a static node ID.            |
+| <a id="CANNODE_TERM"></a>[CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM)       | CAN built-in bus termination. Set to `1` if this is the last node on the CAN bus.                                                                 |

 ### Setting Up Rover and Fixed Base

@@ -96,6 +96,10 @@ If the DNA is still running and certain devices need to be manually configured,
 ::: info
 The PX4 node ID can be configured using the [UAVCAN_NODE_ID](../advanced_config/parameter_reference.md#UAVCAN_NODE_ID) parameter.
 The parameter is set to 1 by default.
+
+Devices running the [PX4 DroneCAN firmware](px4_cannode_fw.md) (such as [ARK CANnode](ark_cannode.md)) can use the
+[CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID) parameter to set a static node ID.
+Set it to 0 (default) for dynamic allocation, or to a value between 1-127 to use a specific static node ID.
 :::

 :::warning
@@ -282,6 +286,11 @@ For example, the screenshot below shows the parameters for a CAN GPS with node i

 ![QGC Parameter showing selected DroneCAN node](../../assets/can/dronecan/qgc_can_parameters.png)

+Common CANNODE parameters that you can configure include:
+
+- [CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID): Set a static node ID (1-127) or use 0 for dynamic allocation. See [PX4 DroneCAN Firmware > Static Node ID](px4_cannode_fw.md#static-node-id) for more information.
+- [CANNODE_TERM](../advanced_config/parameter_reference.md#CANNODE_TERM): Enable CAN bus termination on the last node in the bus.
+
 ## Device Specific Setup

 Most DroneCAN nodes require no further setup, unless specifically noted in their device-specific documentation.
@@ -20,6 +20,26 @@ make ark_can-flow_default

 This will create an output in **build/ark_can-flow_default** named **XX-X.X.XXXXXXXX.uavcan.bin**. Follow the instructions at [DroneCAN firmware update](index.md#firmware-update) to flash the firmware.

+## Configuration
+
+### Static Node ID
+
+By default, DroneCAN devices use [Dynamic Node Allocation (DNA)](index.md#node-id-allocation) to automatically obtain a unique node ID from the flight controller.
+However, you can configure a static node ID using the [CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID) parameter.
+
+To configure a static node ID:
+
+1. Set [CANNODE_NODE_ID](../advanced_config/parameter_reference.md#CANNODE_NODE_ID) to a value between 1-127 using [QGroundControl](index.md#qgc-cannode-parameter-configuration)
+2. Reboot the device
+
+To return to dynamic allocation, set `CANNODE_NODE_ID` back to 0.
+Note that when switching back to dynamic allocation, the flight controller will typically continue to allocate the same node ID that was previously used (this is normal DNA behavior).
+
+:::warning
+When using static node IDs, you must ensure that each device on the CAN bus has a unique node ID.
+Configuring two devices with the same ID will cause communication conflicts.
+:::
+
 ## Developer Information

 This section has information that is relevant to developers who want to add support for new DroneCAN hardware to the PX4 Autopilot.
@@ -35,5 +35,6 @@ The boards in this category are:
 - [Radiolink PIX6](../flight_controller/radiolink_pix6.md)
 - [Sky-Drones AIRLink](../flight_controller/airlink.md)
 - [SPRacing SPRacingH7EXTREME](../flight_controller/spracingh7extreme.md)
+- [Svehicle E2](../flight_controller/svehicle_e2.md)
 - [ThePeach FCC-K1](../flight_controller/thepeach_k1.md)
 - [ThePeach FCC-R1](../flight_controller/thepeach_r1.md)
@@ -0,0 +1,175 @@
+# S-Vehicle E2
+
+:::warning
+PX4 does not manufacture this (or any) autopilot.
+:::
+
+The _E2_ is an advanced autopilot manufactured by S-Vehicle<sup>&reg;</sup>.
+
+The autopilot is recommended for commercial system integration, but is also suitable for academic research and any other applications.
+It brings you ultimate performance, stability, and reliability in every aspect.
+
+![SVehicle-E2](../../assets/flight_controller/svehicle_e2/main.png)
+
+::: info
+These flight controllers are [manufacturer supported](../flight_controller/autopilot_manufacturer_supported.md).
+:::
+
+### Processors & Sensors
+
+- FMU Processor: STM32H753IIK6
+  - 32 Bit Arm® Cortex®-M7, 480MHz, 2MB flash memory, 1MB RAM
+- IO Processor: STM32F103
+  - 32 Bit Arm® Cortex®-M3, 72MHz, 20KB SRAM
+- On-board sensors
+  - Accel/Gyro: BMI088
+  - Accel/Gyro: ICM-42688-P
+  - Accel/Gyro: ICM-20649
+  - Mag: RM3100
+  - Barometer: 2x ICP-20100
+
+### Interfaces
+
+- 14x PWM Servo Outputs
+- 1x Dedicated R/C Input for Spektrum / DSM and S.Bus
+- 1x Analog/PWM RSSI Input
+- 2x TELEM Ports (with full flow control)
+- 1x UART4 Port
+- 2x GPS Ports
+  - 1x Full GPS plus Safety Switch Port (GPS1)
+  - 1x Basic GPS Port (with I2C, GPS2)
+- 1x USB Port (TYPE-C)
+- 1x Ethernet Port
+  - Transformerless application
+  - 100Mbps
+- 3x I2C Bus Ports
+- 1x SPI Bus
+  - 1x Chip Select Line
+  - 1x Data Ready Line
+  - 1x SPI Reset Line
+- 2x CAN Ports
+- 3x Power Input Ports
+  - ADC Power Input
+  - I2C Power Input
+  - DroneCAN/UAVCAN Power Input
+- 2x AD Ports
+  - Analog Input (3.3V)
+  - Analog Input (6.6V - not supported by PX4)
+- 1x Dedicated Debug Port
+  - FMU Debug
+
+## Purchase Channels
+
+Order from [S-Vehicle](https://svehicle.cn/).
+
+## Radio Control
+A Radio Control (RC) system is required if you want to manually control your vehicle (PX4 does not require a radio system for autonomous flight modes).
+
+You will need to select a compatible transmitter/receiver and then bind them so that they communicate (read the instructions that come with your specific transmitter/receiver).
+
+Spektrum/DSM receivers connect to the DSM/SBUS RC input.
+PPM or SBUS receivers connect to the RC IN input port.
+CRSF receiver must be wired to a spare port (UART) on the Flight Controller. Then you can bind the transmitter and receiver together.
+
+## Serial Port Mapping
+
+| UART   | Device     | Port          |
+| ------ | ---------- | ------------- |
+| USART1 | /dev/ttyS0 | GPS           |
+| USART2 | /dev/ttyS1 | TELEM3        |
+| USART3 | /dev/ttyS2 | Debug Console |
+| UART4  | /dev/ttyS3 | UART4         |
+| UART5  | /dev/ttyS4 | TELEM2        |
+| USART6 | /dev/ttyS5 | PX4IO/RC      |
+| UART7  | /dev/ttyS6 | TELEM1        |
+| UART8  | /dev/ttyS7 | GPS2          |
+
+## PWM Output
+
+The E2-Plus flight controller supports up to 14 PWM outputs.
+The first 8 outputs (labelled M1 to M8) are controlled by a dedicated STM32F103 IOMCU controller.
+The remaining 6 outputs (labelled 9 to 14) are the "auxiliary" outputs.
+These are directly attached to the STM32H753 FMU controller .
+
+The 14 PWM outputs are:
+
+M1 - M8 are connected to the IOMCU
+A1 - A6 are connected to the FMU
+
+M1 - M8 support DShot and are in 3 groups:
+
+- M1, M2 in group 1
+- M3, M4 in group 2
+- M5, M6, M7, M8 in group 3
+
+The 6 FMU PWM outputs are in 2 groups:
+
+A1 - A4 are in one group.
+A5, A6 are in a 2nd group.
+
+Channels within the same group need to use the same output rate.
+If any channel in a group uses DShot then all channels in the group need to use DShot.
+
+### Electrical data
+
+- Voltage Ratings:
+  - Max input voltage: 5.7V
+  - USB Power Input: 4.75\~5.25V
+  - Servo Rail Input: 0\~9.9V
+- Current Ratings:
+  - TELEM1 and GPS2 combined output current limiter: 1.5A
+  - All other port combined output current limiter: 1.5A
+
+## Battery Monitoring
+
+The board has connectors for 3 power monitors.
+
+- POWER1 -- ADC
+- POWER2 -- DroneCAN
+- POWER3 -- I2C
+
+The board is configure by default for a analog power monitor, and also has DroneCAN power monitor and I2C defaults configured which is enabled.
+
+The default PDB included with the E2+ is analog and must be connected to `POWER1`.
+
+## Building Firmware
+
+To [build PX4](../dev_setup/building_px4.md) for this target, execute:
+
+```sh
+make svehicle_e2_default
+```
+
+## Debug Port
+
+The [PX4 System Console](../debug/system_console.md) and [SWD Interface](../debug/swd_debug.md) operate on the **FMU Debug** port.
+
+| Pin     | Signal         | Volt  |
+| ------- | -------------- | ----- |
+| 1 (red) | 5V+            | +5V   |
+| 2 (blk) | DEBUG TX (OUT) | +3.3V |
+| 3 (blk) | DEBUG RX (IN)  | +3.3V |
+| 4 (blk) | FMU_SWDIO      | +3.3V |
+| 5 (blk) | FMU_SWCLK      | +3.3V |
+| 6 (blk) | GND            | GND   |
+
+For information about using this port see:
+
+- [SWD Debug Port](../debug/swd_debug.md)
+- [PX4 System Console](../debug/system_console.md) (Note, the FMU console maps to USART3).
+- All ports use GH1.25 ,power ports use ports on E2 uses the 6 circuit [2.00mm Pitch CLIK-Mate Wire-to-Board PCB Receptacle](https://www.molex.com/en-us/products/part-detail/5024430670).
+
+## Pinouts
+
+![SVehicle-E2 Top Down Photo](../../assets/flight_controller/svehicle_e2/top.png)
+
+![SVehicle-E2 Bottom Photo](../../assets/flight_controller/svehicle_e2/back.jpeg)
+
+![SVehicle-E2 left Photo](../../assets/flight_controller/svehicle_e2/left.png)
+
+![SVehicle-E2 right Photo](../../assets/flight_controller/svehicle_e2/right.png)
+
+## Supported Platforms / Airframes
+
+Any multirotor/airplane/rover or boat that can be controlled using normal RC servos or Futaba S-Bus servos.
+The complete set of supported configurations can be found in the [Airframe Reference](../airframes/airframe_reference.md).
@@ -1,6 +1,6 @@
 # Zenoh (PX4 ROS 2 rmw_zenoh)

-<Badge type="tip" text="main (PX4 v1.17)" /> <Badge type="warning" text="Experimental" />
+<Badge type="tip" text="main (planned for: PX4 v1.17)" /> <Badge type="warning" text="Experimental" />

 :::warning Experimental
 At the time of writing, PX4 Zenoh-pico is experimental, and hence subject to change.
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Hamish Willee	728b10e0e0	Update src/modules/mavlink/mavlink_receiver.cpp	2025-10-23 16:11:44 +11:00
Hamish Willee	36bbb4a190	Autotune mavlink - reject invalid param1 or 2 with fail	2025-10-22 10:12:42 +11:00
Andrew Brahim	1297780d28	add cmake variant and px4board file to ark flow mr target (#25793 ) * add cmake variant and px4board file Signed-off-by: dirksavage88 <dirksavage88@gmail.com> * boards: ark flow mr update default.px4board and rc.board_sensors --------- Signed-off-by: dirksavage88 <dirksavage88@gmail.com> Co-authored-by: alexklimaj <alex@arkelectron.com>	2025-10-21 13:20:55 -06:00
Marco Hauswirth	59f6c69067	EKF2: rotate vel on heading reset (#25753 ) * correct NED velocity according to yaw reset to keep "body-velocity" consistent * add unit test velocityRotationOnYawReset * '[AUTO COMMIT] update change indication' * dont adjust velocity on yaw-reset when NE aiding active --------- Co-authored-by: haumarco <haumarco@users.noreply.github.com>	2025-10-21 11:48:03 +02:00
Tobias Fenner	71f56df23b	adsb: Fix vertical separation check using wrong parameter The collision detection incorrectly used crosstrack_separation (horizontal radius) for both horizontal and vertical checks. This resulted in the vertical separation threshold being ignored, creating a spherical detection zone instead of the intended cylindrical "hockey puck" shape. Fixed by using vertical_separation parameter for altitude difference check on line 80. The bug was likely introduced as a copy-paste error when creating the vertical check from the horizontal check template. The existing unit test uses identical values for both parameters (500.0f), which masked this bug. Testing: Code review. The existing unit tests pass, but they don't catch this bug due to using equal values. Future test improvement would be to use different crosstrack_separation and vertical_separation values. Signed-off-by: Tobias Fenner <tobyrfenner@gmail.com>	2025-10-21 11:21:27 +02:00
Jacob Dahl	d30fa62f40	mavlink: take in @dakejahl 's refactoring and extend it	2025-10-21 10:24:30 +02:00
Matthias Grob	65c5bd6906	Fix (dis)arm reason enumeration (#25766 )	2025-10-20 09:12:36 -04:00
mahima-yoga	056289892c	fw_defaults: bump default EKF2_REQ_PDOP to 4	2025-10-20 08:54:55 +02:00
PX4 Build Bot	ead1cf00ff	New Crowdin translations - ko (#25780 ) Co-authored-by: Crowdin Bot <support+bot@crowdin.com>	2025-10-20 08:17:05 +11:00
PX4 Build Bot	0d0bfc1937	New Crowdin translations - uk (#25781 ) Co-authored-by: Crowdin Bot <support+bot@crowdin.com>	2025-10-20 08:16:57 +11:00
GC-20-20	66e73528a2	boards: add new SVehicle-E2 (#25578 ) * boards: add new svehicle e2 * add SVehicle-E2 documentation * Add new documents * Subedit - shrink images * Supplementary documentation based on discussion --------- Co-authored-by: Hamish Willee <hamishwillee@gmail.com> Co-authored-by: Andrew Brahim <35986980+dirksavage88@users.noreply.github.com>	2025-10-18 20:32:10 -04:00
Jacob Dahl	444b31be21	uavcan: fix logic for static node id	2025-10-17 18:35:20 -08:00
Jacob Dahl	b3acde4899	use uavcan::NodeID::Max	2025-10-17 18:35:20 -08:00
Jacob Dahl	8ca8f12a24	docs: uavcannode: document CANNODE_NODE_ID for static node ID	2025-10-17 18:35:20 -08:00
Jacob Dahl	0b63b8317a	uavcannode: add CANNODE_NODE_ID to allow setting static node ID	2025-10-17 18:35:20 -08:00
Alexander Sherikov	6e8f61c551	various cmake fixes (#25748 ) - enable building in a cmake subdirectory: - use consistent path to "etc" in build directory - add a quick fix for mavlink inclusion with `mavlink/<version>/mavlink.h`, presumably the problem does not appear normally since somewhere the build root directory is added to include paths. - install gazebo config and plugins, the goal is to enable packaging of PX4 sitl binaries. - fix dependency on dds_topics.h generation in uxrce_dds_client: *** No rule to make target 'PX4-Autopilot/src/modules/uxrce_dds_client/dds_topics.h', needed by 'PX4-Autopilot/events/px4.json'. Stop. https://github.com/PX4/PX4-Autopilot/issues/21788 Co-authored-by: Jacob Dahl <37091262+dakejahl@users.noreply.github.com>	2025-10-17 11:11:00 -08:00
Vladimir Letunovskiu	d2d433290a	Update copyright year to 2025 in LICENSE file (#25778 )	2025-10-17 10:49:41 -08:00
Henry Kotzé	7418d84001	ekf2: ev vel, use measurement timestamp to update aid_src timestamp_sample (#25774 ) - the estimator_aid_src::sample_timestamp would use its own timestamp to update, this would cause the estimator_aid_src for ev velocity not to log, since the timestamp_sample would always equal to zero and thus never be greater than the previous published time Co-authored-by: henrykotze <henry@autonosky.com>	2025-10-17 10:43:34 -08:00
Phil-Engljaehringer	dc0af1ab9d	health: Fix displayed value in power check (#25751 ) * Changed the healthFailure call in the PowerChecks to ensure that no value above the low_error_threshold or below the high_error_threshold is reported in AMC * fix format * made _latest_low_failure and _latest_low_failure member variables. Only update them when hystersis state changes from false to true.	2025-10-17 14:54:16 +02:00
Hamish Willee	f03131cfd3	MAVLink PARAM_ERROR support (#25699 ) Co-authored-by: PX4BuildBot <bot@pixhawk.org>	2025-10-17 13:29:23 +11:00
Peter van der Perk	faee1da630	docs: Zenoh middleware guide (#25737 )	2025-10-16 20:48:12 +11:00
Hamish Willee	104759b90c	Update mavlink with more PARAM_ERROR values (#25772 )	2025-10-16 14:09:02 +11:00
Jacob Dahl	42c4e6b4fb	gz: submodule update (#25771 )	2025-10-15 13:28:52 -08:00
Jacob Dahl	54866b886e	gz: fix gimbal message type (#25770 )	2025-10-15 13:28:14 -08:00
Jacob Dahl	9c1f3306a4	mission: delay until: mark next setpoint invalid (#25728 ) Fixes bug with the NAV_CMD_DELAY where the copter would "pace" back and forth while waiting at the delay waypoint	2025-10-15 13:21:28 -08:00
Jacob Dahl	1ca80ae6f6	astyle: remove max line length (#25717 )	2025-10-16 07:08:02 +11:00
Matthias Grob	3e3bb82331	navigator: increase stack by 30 bytes (#25769 )	2025-10-15 11:21:26 -08:00
Erkki Eilonen	f32c3024b8	gazebo: fix unused variables warning ([-Wunused-private-field])	2025-10-15 11:32:16 -04:00
Erkki Eilonen	2297e66a9d	gazebo: fix implicit conversion errors ([-Wdouble-promotion])	2025-10-15 11:32:16 -04:00