The form of the PX4 GUID is as follows:
offset:0 1 2 - 17
<ARCH MSD><ARCH LSD><MSD CPU UUID>...<LSD CPU UUID>
Where <ARCH MSD><ARCH LSD> are a monotonic ordinal number assigned by
PX4 to a chip architecture (PX4_SOC_ARCH_ID). The 2 bytes are used to
create a globally unique ID when prepended to a padded CPU ID.
In the case where the CPU's UUID is shorter than 16 bytes it will be
padded with 0's starting at offset [2] until
PX4_CPU_MFGUID_BYTE_LENGTH-PX4_CPU_UUID_BYTE_LENGTH -1
I.E. For the STM32
offset:0 1 2 3 4 5 6 - 17
<ARCH MSD><ARCH LSD>[0][0][0][0]<MSD CPU UUID>...<LSD CPU UUID>
I.E. For as CPU with a 16 byte UUID
offset:0 1 2 - 17
<ARCH MSD><ARCH LSD><MSD CPU UUID>...<LSD CPU UUID>
This uses now the same sleep time logic as mavlink, depending on the
baudrate.
CPU usage on a Pixracer for different sleep times:
#num reads/sec sleep time CPU usage
17-18 2.8ms 0.233-0.31% (this PR)
12 5ms 0.155-0.3%
9-10 10ms 0.155-0.233%
6 20ms 0.155-0.233% (previous)
A hardfault was happening on:
fmu stop
fmu mode_pwm
pwm info
The _mixer was null and being dereferenced to access the trim
setting that were moved to the mixer from the fmu.
This commit fixes that but making the getter issue a warning
and the setter fail.
The code was forcing the CV reload, but not resettting the count
this would cause short and long blinks during breathing.
this change allows the CV to update at 50Hz (20 ms) asynchronously.
So the LED update rate of 40Hz (25) will take effect on the next
FTM counter change, end of the prescaler counting, after CnV register
was written.update.
a b c d
LED PWM ___-___-___-___-___-___-___-___-___-___
LED Data ____-____-____-____-____-____-____-____-
a b c d
This will disable the fxos8701cq internal mag on
the NXPHlite. There are random noise spikes on the
HIGHRES_IMU.[x|y|x]mag. Even with all other SPI
devices shut down, the noise is still present.
Since tune control came in this driver does not have a
have a test based interface. The module Documentation
has been moved to tune_control
minor cleanup and assert on workque delay of 0
David Sidrane