- when the mpu9250 mag is active it disrupts IMU sampling
- this change modifies the simple mpu9250 FIFO integrity checks (comparing duplicate accel samples) to tolerate these samples that don't match if the mag is active
- fixes#17615
- increase SPI stall time slightly
- tolerate mag self test failure (could be due to local magnetic field)
- register configuration compatible with older ADIS16448AMLZ
- don't publish duplicate accel/gyro
- only allocate CRC perf counter if using CRC
- include icm20948 on most boards by default
- create more test variants for default boards near flash limit (cuav_nora_test, cuav_x7pro_test, holybro_durandal-v1_test)
- new IMU driver structure with state machine (no sleeps in bus thread)
- verify all configured registers and trigger reset on failure
- detect if DIO1 or DIO2 are actually connected for data ready interrupt usage
- don't use CRC-16 on burst transfers except for verified lots
- track consecutive failures and trigger reset aggressively
- only count missed drdy interrupts, not time
- reset wait times consistent with other drivers
- accel improve FIFO count check if DRDY isn't available
- track consecutive failures and trigger reset aggressively
- only count missed drdy interrupts, not time
- reset wait times consistent with other drivers
- perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc)
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc)
- only track consecutive errors (not total) to trigger full reset if necessary
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc)
- only track consecutive errors (not total) to trigger full reset if necessary
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- perform reset as per the datasheet (wakeup accel/gyro and wait before proceeding)
- add register bank selection (not yet used)
- track consecutive errors to trigger full reset if necessary
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- perform reset as per the datasheet (wakeup accel/gyro and wait before proceeding)
- add register bank selection (not yet used)
- track consecutive errors to trigger full reset if necessary
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc)
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc)
- only track consecutive errors (not total) to trigger full reset if necessary
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- update copyright year
- perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc)
- only track consecutive errors (not total) to trigger full reset if necessary
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc)
- track consecutive errors and trigger full reset if necessary
- remove interrupt perf counter and instead only count misses
- minor style changes to stay in sync with the other Invensense drivers
- read FIFO count along with full transfer as a sanity check
- the latch would actually cause more problems if the backup schedule hit
- this reduces the number of cycles where the FIFO is actually empty at max rate (when there's only 1 sample in the FIFO expected)
Daniel Agar