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https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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imu/invensense/icm20649: minor cleanup to keep in sync with icm20948
This commit is contained in:
Daniel Agar
@@ -48,6 +48,10 @@ ICM20649::ICM20649(I2CSPIBusOption bus_option, int bus, uint32_t device, enum Ro
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_px4_accel(get_device_id(), ORB_PRIO_HIGH, rotation),
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_px4_gyro(get_device_id(), ORB_PRIO_HIGH, rotation)
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{
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if (drdy_gpio != 0) {
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_drdy_interval_perf = perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval");
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}
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ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
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}
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@@ -77,6 +81,7 @@ int ICM20649::init()
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bool ICM20649::Reset()
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{
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_state = STATE::RESET;
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DataReadyInterruptDisable();
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ScheduleClear();
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ScheduleNow();
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return true;
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@@ -91,8 +96,8 @@ void ICM20649::exit_and_cleanup()
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void ICM20649::print_status()
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{
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I2CSPIDriverBase::print_status();
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PX4_INFO("FIFO empty interval: %d us (%.3f Hz)", _fifo_empty_interval_us,
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static_cast<double>(1000000 / _fifo_empty_interval_us));
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PX4_INFO("FIFO empty interval: %d us (%.1f Hz)", _fifo_empty_interval_us, 1e6 / _fifo_empty_interval_us);
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perf_print_counter(_transfer_perf);
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perf_print_counter(_bad_register_perf);
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@@ -118,13 +123,16 @@ int ICM20649::probe()
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void ICM20649::RunImpl()
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{
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const hrt_abstime now = hrt_absolute_time();
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switch (_state) {
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case STATE::RESET:
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// PWR_MGMT_1: Device Reset
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RegisterWrite(Register::BANK_0::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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_reset_timestamp = hrt_absolute_time();
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_reset_timestamp = now;
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_consecutive_failures = 0;
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_state = STATE::WAIT_FOR_RESET;
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ScheduleDelayed(10_ms);
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ScheduleDelayed(100_ms);
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break;
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case STATE::WAIT_FOR_RESET:
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@@ -133,13 +141,17 @@ void ICM20649::RunImpl()
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if ((RegisterRead(Register::BANK_0::WHO_AM_I) == WHOAMI)
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&& (RegisterRead(Register::BANK_0::PWR_MGMT_1) == 0x41)) {
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// Wakeup and reset
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RegisterWrite(Register::BANK_0::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0);
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RegisterWrite(Register::BANK_0::USER_CTRL, USER_CTRL_BIT::I2C_IF_DIS | USER_CTRL_BIT::SRAM_RST);
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// if reset succeeded then configure
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_state = STATE::CONFIGURE;
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ScheduleNow();
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ScheduleDelayed(100_ms);
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} else {
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// RESET not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 100_ms) {
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if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) {
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PX4_DEBUG("Reset failed, retrying");
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_state = STATE::RESET;
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ScheduleDelayed(100_ms);
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@@ -161,7 +173,7 @@ void ICM20649::RunImpl()
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_data_ready_interrupt_enabled = true;
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// backup schedule as a watchdog timeout
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ScheduleDelayed(10_ms);
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ScheduleDelayed(100_ms);
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} else {
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_data_ready_interrupt_enabled = false;
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@@ -171,85 +183,90 @@ void ICM20649::RunImpl()
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FIFOReset();
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} else {
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PX4_DEBUG("Configure failed, retrying");
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// try again in 10 ms
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ScheduleDelayed(10_ms);
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// CONFIGURE not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) {
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PX4_DEBUG("Configure failed, resetting");
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_state = STATE::RESET;
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} else {
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PX4_DEBUG("Configure failed, retrying");
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}
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ScheduleDelayed(100_ms);
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}
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break;
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case STATE::FIFO_READ: {
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hrt_abstime timestamp_sample = 0;
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uint8_t samples = 0;
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if (_data_ready_interrupt_enabled) {
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// re-schedule as watchdog timeout
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ScheduleDelayed(10_ms);
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// timestamp set in data ready interrupt
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if (!_force_fifo_count_check) {
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samples = _fifo_read_samples.load();
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} else {
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const uint16_t fifo_count = FIFOReadCount();
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samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) * SAMPLES_PER_TRANSFER; // round down to nearest
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// scheduled from interrupt if _drdy_fifo_read_samples was set
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if (_drdy_fifo_read_samples.fetch_and(0) == _fifo_gyro_samples) {
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perf_count_interval(_drdy_interval_perf, now);
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}
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timestamp_sample = _fifo_watermark_interrupt_timestamp;
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// push backup schedule back
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ScheduleDelayed(_fifo_empty_interval_us * 2);
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}
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bool failure = false;
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// always check current FIFO count
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bool success = false;
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const uint16_t fifo_count = FIFOReadCount();
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// manually check FIFO count if no samples from DRDY or timestamp looks bogus
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if (!_data_ready_interrupt_enabled || (samples == 0)
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|| (hrt_elapsed_time(×tamp_sample) > (_fifo_empty_interval_us / 2))) {
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// use the time now roughly corresponding with the last sample we'll pull from the FIFO
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timestamp_sample = hrt_absolute_time();
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const uint16_t fifo_count = FIFOReadCount();
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samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) * SAMPLES_PER_TRANSFER; // round down to nearest
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}
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if (samples > FIFO_MAX_SAMPLES) {
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// not technically an overflow, but more samples than we expected or can publish
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perf_count(_fifo_overflow_perf);
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failure = true;
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if (fifo_count >= FIFO::SIZE) {
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FIFOReset();
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perf_count(_fifo_overflow_perf);
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} else if (samples >= SAMPLES_PER_TRANSFER) {
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// require at least SAMPLES_PER_TRANSFER (we want at least 1 new accel sample per transfer)
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if (!FIFORead(timestamp_sample, samples)) {
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failure = true;
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_px4_accel.increase_error_count();
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_px4_gyro.increase_error_count();
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}
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} else if (samples == 0) {
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failure = true;
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} else if (fifo_count == 0) {
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perf_count(_fifo_empty_perf);
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} else {
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// FIFO count (size in bytes) should be a multiple of the FIFO::DATA structure
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const uint8_t samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) *
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SAMPLES_PER_TRANSFER; // round down to nearest
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if (samples > FIFO_MAX_SAMPLES) {
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// not technically an overflow, but more samples than we expected or can publish
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FIFOReset();
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perf_count(_fifo_overflow_perf);
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} else if (samples >= 1) {
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if (FIFORead(now, samples)) {
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success = true;
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_consecutive_failures = 0;
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}
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}
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}
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if (failure || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) {
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// check BANK_0 & BANK_2 registers incrementally
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if (RegisterCheck(_register_bank0_cfg[_checked_register_bank0], true)
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&& RegisterCheck(_register_bank2_cfg[_checked_register_bank2], true)) {
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if (!success) {
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_consecutive_failures++;
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_last_config_check_timestamp = timestamp_sample;
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// full reset if things are failing consistently
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if (_consecutive_failures > 10) {
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Reset();
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return;
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}
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}
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if (!success || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) {
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// check configuration registers periodically or immediately following any failure
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if (RegisterCheck(_register_bank0_cfg[_checked_register_bank0])
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&& RegisterCheck(_register_bank2_cfg[_checked_register_bank2])
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) {
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_last_config_check_timestamp = now;
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_checked_register_bank0 = (_checked_register_bank0 + 1) % size_register_bank0_cfg;
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_checked_register_bank2 = (_checked_register_bank2 + 1) % size_register_bank2_cfg;
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} else {
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// register check failed, force reconfigure
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PX4_DEBUG("Health check failed, reconfiguring");
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_state = STATE::CONFIGURE;
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ScheduleNow();
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// register check failed, force reset
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perf_count(_bad_register_perf);
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Reset();
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}
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} else {
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// periodically update temperature (1 Hz)
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if (hrt_elapsed_time(&_temperature_update_timestamp) > 1_s) {
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// periodically update temperature (~1 Hz)
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if (hrt_elapsed_time(&_temperature_update_timestamp) >= 1_s) {
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UpdateTemperature();
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_temperature_update_timestamp = timestamp_sample;
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_temperature_update_timestamp = now;
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}
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}
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}
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@@ -320,15 +337,13 @@ void ICM20649::ConfigureSampleRate(int sample_rate)
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}
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// round down to nearest FIFO sample dt * SAMPLES_PER_TRANSFER
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const float min_interval = SAMPLES_PER_TRANSFER * FIFO_SAMPLE_DT;
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const float min_interval = FIFO_SAMPLE_DT * SAMPLES_PER_TRANSFER;
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_fifo_empty_interval_us = math::max(roundf((1e6f / (float)sample_rate) / min_interval) * min_interval, min_interval);
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_fifo_gyro_samples = roundf(math::min((float)_fifo_empty_interval_us / (1e6f / GYRO_RATE), (float)FIFO_MAX_SAMPLES));
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// recompute FIFO empty interval (us) with actual gyro sample limit
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_fifo_empty_interval_us = _fifo_gyro_samples * (1e6f / GYRO_RATE);
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_fifo_accel_samples = roundf(math::min(_fifo_empty_interval_us / (1e6f / ACCEL_RATE), (float)FIFO_MAX_SAMPLES));
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}
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void ICM20649::SelectRegisterBank(enum REG_BANK_SEL_BIT bank)
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@@ -346,16 +361,27 @@ void ICM20649::SelectRegisterBank(enum REG_BANK_SEL_BIT bank)
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bool ICM20649::Configure()
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{
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// first set and clear all configured register bits
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for (const auto ®_cfg : _register_bank0_cfg) {
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RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
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}
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for (const auto ®_cfg : _register_bank2_cfg) {
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RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
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}
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// now check that all are configured
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bool success = true;
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for (const auto ® : _register_bank0_cfg) {
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if (!RegisterCheck(reg)) {
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for (const auto ®_cfg : _register_bank0_cfg) {
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if (!RegisterCheck(reg_cfg)) {
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success = false;
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}
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}
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for (const auto ® : _register_bank2_cfg) {
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if (!RegisterCheck(reg)) {
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for (const auto ®_cfg : _register_bank2_cfg) {
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if (!RegisterCheck(reg_cfg)) {
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success = false;
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}
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}
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@@ -374,12 +400,13 @@ int ICM20649::DataReadyInterruptCallback(int irq, void *context, void *arg)
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void ICM20649::DataReady()
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{
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perf_count(_drdy_interval_perf);
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const uint8_t count = _drdy_count.fetch_add(1) + 1;
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if (_data_ready_count.fetch_add(1) >= (_fifo_gyro_samples - 1)) {
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_data_ready_count.store(0);
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_fifo_watermark_interrupt_timestamp = hrt_absolute_time();
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_fifo_read_samples.store(_fifo_gyro_samples);
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uint8_t expected = 0;
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// at least the required number of samples in the FIFO
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if ((count >= _fifo_gyro_samples) && _drdy_fifo_read_samples.compare_exchange(&expected, _fifo_gyro_samples)) {
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_drdy_count.store(0);
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ScheduleNow();
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}
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}
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@@ -388,29 +415,33 @@ bool ICM20649::DataReadyInterruptConfigure()
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{
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// TODO: enable data ready interrupt
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return false;
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#if 0
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// if (_drdy_gpio == 0) {
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// return false;
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// }
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if (_drdy_gpio == 0) {
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return false;
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}
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// // Setup data ready on falling edge
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// return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &DataReadyInterruptCallback, this) == 0;
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// Setup data ready on falling edge
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return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &DataReadyInterruptCallback, this) == 0;
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#endif
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}
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bool ICM20649::DataReadyInterruptDisable()
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{
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// TODO: enable data ready interrupt
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return false;
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#if 0
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// if (_drdy_gpio == 0) {
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// return false;
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// }
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if (_drdy_gpio == 0) {
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return false;
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}
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// return px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr) == 0;
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return px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr) == 0;
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#endif
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}
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template <typename T>
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bool ICM20649::RegisterCheck(const T ®_cfg, bool notify)
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bool ICM20649::RegisterCheck(const T ®_cfg)
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{
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bool success = true;
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@@ -426,26 +457,15 @@ bool ICM20649::RegisterCheck(const T ®_cfg, bool notify)
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success = false;
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}
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if (!success) {
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RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
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if (notify) {
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perf_count(_bad_register_perf);
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_px4_accel.increase_error_count();
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_px4_gyro.increase_error_count();
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}
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}
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return success;
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}
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template <typename T>
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uint8_t ICM20649::RegisterRead(T reg)
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{
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SelectRegisterBank(reg);
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uint8_t cmd[2] {};
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cmd[0] = static_cast<uint8_t>(reg) | DIR_READ;
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SelectRegisterBank(reg);
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transfer(cmd, cmd, sizeof(cmd));
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return cmd[1];
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}
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@@ -453,9 +473,8 @@ uint8_t ICM20649::RegisterRead(T reg)
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template <typename T>
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void ICM20649::RegisterWrite(T reg, uint8_t value)
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{
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SelectRegisterBank(reg);
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uint8_t cmd[2] { (uint8_t)reg, value };
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SelectRegisterBank(reg);
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transfer(cmd, cmd, sizeof(cmd));
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}
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@@ -463,26 +482,20 @@ template <typename T>
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void ICM20649::RegisterSetAndClearBits(T reg, uint8_t setbits, uint8_t clearbits)
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{
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const uint8_t orig_val = RegisterRead(reg);
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uint8_t val = orig_val;
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if (setbits) {
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val |= setbits;
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uint8_t val = (orig_val & ~clearbits) | setbits;
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if (orig_val != val) {
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RegisterWrite(reg, val);
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}
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if (clearbits) {
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val &= ~clearbits;
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}
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RegisterWrite(reg, val);
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}
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uint16_t ICM20649::FIFOReadCount()
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{
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SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
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// read FIFO count
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uint8_t fifo_count_buf[3] {};
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fifo_count_buf[0] = static_cast<uint8_t>(Register::BANK_0::FIFO_COUNTH) | DIR_READ;
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SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
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if (transfer(fifo_count_buf, fifo_count_buf, sizeof(fifo_count_buf)) != PX4_OK) {
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perf_count(_bad_transfer_perf);
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@@ -492,14 +505,12 @@ uint16_t ICM20649::FIFOReadCount()
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return combine(fifo_count_buf[1], fifo_count_buf[2]);
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}
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bool ICM20649::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
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bool ICM20649::FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples)
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{
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perf_begin(_transfer_perf);
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SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
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FIFOTransferBuffer buffer{};
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const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 3, FIFO::SIZE);
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SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
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if (transfer((uint8_t *)&buffer, (uint8_t *)&buffer, transfer_size) != PX4_OK) {
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perf_end(_transfer_perf);
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@@ -510,12 +521,6 @@ bool ICM20649::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
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perf_end(_transfer_perf);
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const uint16_t fifo_count_bytes = combine(buffer.FIFO_COUNTH, buffer.FIFO_COUNTL);
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const uint16_t fifo_count_samples = fifo_count_bytes / sizeof(FIFO::DATA);
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if (fifo_count_samples == 0) {
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perf_count(_fifo_empty_perf);
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return false;
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}
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if (fifo_count_bytes >= FIFO::SIZE) {
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perf_count(_fifo_overflow_perf);
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@@ -523,32 +528,23 @@ bool ICM20649::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
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return false;
|
||||
}
|
||||
|
||||
const uint16_t valid_samples = math::min(samples, fifo_count_samples);
|
||||
const uint8_t fifo_count_samples = fifo_count_bytes / sizeof(FIFO::DATA);
|
||||
|
||||
if (fifo_count_samples < samples) {
|
||||
// force check if there is somehow fewer samples actually in the FIFO (potentially a serious error)
|
||||
_force_fifo_count_check = true;
|
||||
|
||||
} else if (fifo_count_samples >= samples + 2) {
|
||||
// if we're more than a couple samples behind force FIFO_COUNT check
|
||||
_force_fifo_count_check = true;
|
||||
|
||||
} else {
|
||||
// skip earlier FIFO_COUNT and trust DRDY count if we're in sync
|
||||
_force_fifo_count_check = false;
|
||||
if (fifo_count_samples == 0) {
|
||||
perf_count(_fifo_empty_perf);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (valid_samples > 0) {
|
||||
ProcessGyro(timestamp_sample, buffer, valid_samples);
|
||||
const uint16_t valid_samples = math::min(samples, fifo_count_samples);
|
||||
|
||||
if (ProcessAccel(timestamp_sample, buffer, valid_samples)) {
|
||||
if (valid_samples > 0) {
|
||||
ProcessGyro(timestamp_sample, buffer.f, valid_samples);
|
||||
|
||||
if (ProcessAccel(timestamp_sample, buffer.f, valid_samples)) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// force FIFO count check if there was any other error
|
||||
_force_fifo_count_check = true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
@@ -561,9 +557,8 @@ void ICM20649::FIFOReset()
|
||||
RegisterClearBits(Register::BANK_0::FIFO_RST, FIFO_RST_BIT::FIFO_RESET);
|
||||
|
||||
// reset while FIFO is disabled
|
||||
_data_ready_count.store(0);
|
||||
_fifo_watermark_interrupt_timestamp = 0;
|
||||
_fifo_read_samples.store(0);
|
||||
_drdy_count.store(0);
|
||||
_drdy_fifo_read_samples.store(0);
|
||||
}
|
||||
|
||||
static bool fifo_accel_equal(const FIFO::DATA &f0, const FIFO::DATA &f1)
|
||||
@@ -571,12 +566,12 @@ static bool fifo_accel_equal(const FIFO::DATA &f0, const FIFO::DATA &f1)
|
||||
return (memcmp(&f0.ACCEL_XOUT_H, &f1.ACCEL_XOUT_H, 6) == 0);
|
||||
}
|
||||
|
||||
bool ICM20649::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer,
|
||||
const uint8_t samples)
|
||||
bool ICM20649::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples)
|
||||
{
|
||||
sensor_accel_fifo_s accel{};
|
||||
accel.timestamp_sample = timestamp_sample;
|
||||
accel.dt = _fifo_empty_interval_us / _fifo_accel_samples;
|
||||
accel.samples = 0;
|
||||
accel.dt = FIFO_SAMPLE_DT * SAMPLES_PER_TRANSFER;
|
||||
|
||||
bool bad_data = false;
|
||||
|
||||
@@ -584,58 +579,57 @@ bool ICM20649::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTrans
|
||||
int accel_first_sample = 1;
|
||||
|
||||
if (samples >= 4) {
|
||||
if (fifo_accel_equal(buffer.f[0], buffer.f[1]) && fifo_accel_equal(buffer.f[2], buffer.f[3])) {
|
||||
if (fifo_accel_equal(fifo[0], fifo[1]) && fifo_accel_equal(fifo[2], fifo[3])) {
|
||||
// [A0, A1, A2, A3]
|
||||
// A0==A1, A2==A3
|
||||
accel_first_sample = 1;
|
||||
|
||||
} else if (fifo_accel_equal(buffer.f[1], buffer.f[2])) {
|
||||
} else if (fifo_accel_equal(fifo[1], fifo[2])) {
|
||||
// [A0, A1, A2, A3]
|
||||
// A0, A1==A2, A3
|
||||
accel_first_sample = 0;
|
||||
|
||||
} else {
|
||||
perf_count(_bad_transfer_perf);
|
||||
// no matching accel samples is an error
|
||||
bad_data = true;
|
||||
perf_count(_bad_transfer_perf);
|
||||
}
|
||||
}
|
||||
|
||||
int accel_samples = 0;
|
||||
|
||||
for (int i = accel_first_sample; i < samples; i = i + 2) {
|
||||
const FIFO::DATA &fifo_sample = buffer.f[i];
|
||||
int16_t accel_x = combine(fifo_sample.ACCEL_XOUT_H, fifo_sample.ACCEL_XOUT_L);
|
||||
int16_t accel_y = combine(fifo_sample.ACCEL_YOUT_H, fifo_sample.ACCEL_YOUT_L);
|
||||
int16_t accel_z = combine(fifo_sample.ACCEL_ZOUT_H, fifo_sample.ACCEL_ZOUT_L);
|
||||
for (int i = accel_first_sample; i < samples; i = i + SAMPLES_PER_TRANSFER) {
|
||||
int16_t accel_x = combine(fifo[i].ACCEL_XOUT_H, fifo[i].ACCEL_XOUT_L);
|
||||
int16_t accel_y = combine(fifo[i].ACCEL_YOUT_H, fifo[i].ACCEL_YOUT_L);
|
||||
int16_t accel_z = combine(fifo[i].ACCEL_ZOUT_H, fifo[i].ACCEL_ZOUT_L);
|
||||
|
||||
// sensor's frame is +x forward, +y left, +z up
|
||||
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
||||
accel.x[accel_samples] = accel_x;
|
||||
accel.y[accel_samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y;
|
||||
accel.z[accel_samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z;
|
||||
accel_samples++;
|
||||
accel.x[accel.samples] = accel_x;
|
||||
accel.y[accel.samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y;
|
||||
accel.z[accel.samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z;
|
||||
accel.samples++;
|
||||
}
|
||||
|
||||
accel.samples = accel_samples;
|
||||
_px4_accel.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf) +
|
||||
perf_event_count(_fifo_empty_perf) + perf_event_count(_fifo_overflow_perf));
|
||||
|
||||
_px4_accel.updateFIFO(accel);
|
||||
if (accel.samples > 0) {
|
||||
_px4_accel.updateFIFO(accel);
|
||||
}
|
||||
|
||||
return !bad_data;
|
||||
}
|
||||
|
||||
void ICM20649::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples)
|
||||
void ICM20649::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples)
|
||||
{
|
||||
sensor_gyro_fifo_s gyro{};
|
||||
gyro.timestamp_sample = timestamp_sample;
|
||||
gyro.samples = samples;
|
||||
gyro.dt = _fifo_empty_interval_us / _fifo_gyro_samples;
|
||||
gyro.dt = FIFO_SAMPLE_DT;
|
||||
|
||||
for (int i = 0; i < samples; i++) {
|
||||
const FIFO::DATA &fifo_sample = buffer.f[i];
|
||||
|
||||
const int16_t gyro_x = combine(fifo_sample.GYRO_XOUT_H, fifo_sample.GYRO_XOUT_L);
|
||||
const int16_t gyro_y = combine(fifo_sample.GYRO_YOUT_H, fifo_sample.GYRO_YOUT_L);
|
||||
const int16_t gyro_z = combine(fifo_sample.GYRO_ZOUT_H, fifo_sample.GYRO_ZOUT_L);
|
||||
const int16_t gyro_x = combine(fifo[i].GYRO_XOUT_H, fifo[i].GYRO_XOUT_L);
|
||||
const int16_t gyro_y = combine(fifo[i].GYRO_YOUT_H, fifo[i].GYRO_YOUT_L);
|
||||
const int16_t gyro_z = combine(fifo[i].GYRO_ZOUT_H, fifo[i].GYRO_ZOUT_L);
|
||||
|
||||
// sensor's frame is +x forward, +y left, +z up
|
||||
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
||||
@@ -644,16 +638,18 @@ void ICM20649::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransf
|
||||
gyro.z[i] = (gyro_z == INT16_MIN) ? INT16_MAX : -gyro_z;
|
||||
}
|
||||
|
||||
_px4_gyro.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf) +
|
||||
perf_event_count(_fifo_empty_perf) + perf_event_count(_fifo_overflow_perf));
|
||||
|
||||
_px4_gyro.updateFIFO(gyro);
|
||||
}
|
||||
|
||||
void ICM20649::UpdateTemperature()
|
||||
{
|
||||
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
|
||||
|
||||
// read current temperature
|
||||
uint8_t temperature_buf[3] {};
|
||||
temperature_buf[0] = static_cast<uint8_t>(Register::BANK_0::TEMP_OUT_H) | DIR_READ;
|
||||
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
|
||||
|
||||
if (transfer(temperature_buf, temperature_buf, sizeof(temperature_buf)) != PX4_OK) {
|
||||
perf_count(_bad_transfer_perf);
|
||||
|
||||
@@ -74,9 +74,9 @@ private:
|
||||
|
||||
// Sensor Configuration
|
||||
static constexpr float FIFO_SAMPLE_DT{1e6f / 9000.f};
|
||||
static constexpr uint32_t SAMPLES_PER_TRANSFER{2}; // ensure at least 1 new accel sample per transfer
|
||||
static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 9000 Hz gyro
|
||||
static constexpr float ACCEL_RATE{GYRO_RATE / 2.f}; // 4500 Hz accel
|
||||
static constexpr uint32_t SAMPLES_PER_TRANSFER{2}; // ensure at least 1 new accel sample per transfer
|
||||
static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 9000 Hz gyro
|
||||
static constexpr float ACCEL_RATE{GYRO_RATE / SAMPLES_PER_TRANSFER}; // 4500 Hz accel
|
||||
|
||||
// maximum FIFO samples per transfer is limited to the size of sensor_accel_fifo/sensor_gyro_fifo
|
||||
static constexpr uint32_t FIFO_MAX_SAMPLES{math::min(math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(sensor_gyro_fifo_s::x) / sizeof(sensor_gyro_fifo_s::x[0])), sizeof(sensor_accel_fifo_s::x) / sizeof(sensor_accel_fifo_s::x[0]) * (int)(GYRO_RATE / ACCEL_RATE))};
|
||||
@@ -121,7 +121,7 @@ private:
|
||||
bool DataReadyInterruptConfigure();
|
||||
bool DataReadyInterruptDisable();
|
||||
|
||||
template <typename T> bool RegisterCheck(const T ®_cfg, bool notify = false);
|
||||
template <typename T> bool RegisterCheck(const T ®_cfg);
|
||||
template <typename T> uint8_t RegisterRead(T reg);
|
||||
template <typename T> void RegisterWrite(T reg, uint8_t value);
|
||||
template <typename T> void RegisterSetAndClearBits(T reg, uint8_t setbits, uint8_t clearbits);
|
||||
@@ -129,11 +129,11 @@ private:
|
||||
template <typename T> void RegisterClearBits(T reg, uint8_t clearbits) { RegisterSetAndClearBits(reg, 0, clearbits); }
|
||||
|
||||
uint16_t FIFOReadCount();
|
||||
bool FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples);
|
||||
bool FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples);
|
||||
void FIFOReset();
|
||||
|
||||
bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
|
||||
void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
|
||||
bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples);
|
||||
void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples);
|
||||
void UpdateTemperature();
|
||||
|
||||
const spi_drdy_gpio_t _drdy_gpio;
|
||||
@@ -147,19 +147,18 @@ private:
|
||||
perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO empty")};
|
||||
perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO overflow")};
|
||||
perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO reset")};
|
||||
perf_counter_t _drdy_interval_perf{perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval")};
|
||||
perf_counter_t _drdy_interval_perf{nullptr};
|
||||
|
||||
hrt_abstime _reset_timestamp{0};
|
||||
hrt_abstime _last_config_check_timestamp{0};
|
||||
hrt_abstime _fifo_watermark_interrupt_timestamp{0};
|
||||
hrt_abstime _temperature_update_timestamp{0};
|
||||
unsigned _consecutive_failures{0};
|
||||
|
||||
enum REG_BANK_SEL_BIT _last_register_bank {REG_BANK_SEL_BIT::USER_BANK_0};
|
||||
|
||||
px4::atomic<uint8_t> _data_ready_count{0};
|
||||
px4::atomic<uint8_t> _fifo_read_samples{0};
|
||||
px4::atomic<uint8_t> _drdy_fifo_read_samples{0};
|
||||
px4::atomic<uint8_t> _drdy_count{0};
|
||||
bool _data_ready_interrupt_enabled{false};
|
||||
bool _force_fifo_count_check{true};
|
||||
|
||||
enum class STATE : uint8_t {
|
||||
RESET,
|
||||
@@ -172,26 +171,24 @@ private:
|
||||
|
||||
uint16_t _fifo_empty_interval_us{1250}; // default 1250 us / 800 Hz transfer interval
|
||||
uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
|
||||
uint8_t _fifo_accel_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))};
|
||||
|
||||
uint8_t _checked_register_bank0{0};
|
||||
static constexpr uint8_t size_register_bank0_cfg{6};
|
||||
register_bank0_config_t _register_bank0_cfg[size_register_bank0_cfg] {
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::BANK_0::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::I2C_IF_DIS, USER_CTRL_BIT::I2C_MST_EN },
|
||||
{ Register::BANK_0::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::DEVICE_RESET | PWR_MGMT_1_BIT::SLEEP },
|
||||
{ Register::BANK_0::INT_PIN_CFG, INT_PIN_CFG_BIT::INT1_ACTL, 0 },
|
||||
{ Register::BANK_0::INT_ENABLE_1, INT_ENABLE_1_BIT::RAW_DATA_0_RDY_EN, 0 },
|
||||
{ Register::BANK_0::FIFO_EN_2, FIFO_EN_2_BIT::ACCEL_FIFO_EN | FIFO_EN_2_BIT::GYRO_Z_FIFO_EN | FIFO_EN_2_BIT::GYRO_Y_FIFO_EN | FIFO_EN_2_BIT::GYRO_X_FIFO_EN, FIFO_EN_2_BIT::TEMP_FIFO_EN },
|
||||
{ Register::BANK_0::FIFO_MODE, FIFO_MODE_BIT::Snapshot, 0 },
|
||||
// { Register::BANK_0::FIFO_CFG, FIFO_CFG_BIT::FIFO_CFG, 0 }, // TODO: enable data ready interrupt
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::BANK_0::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::I2C_IF_DIS, USER_CTRL_BIT::DMP_EN | USER_CTRL_BIT::I2C_MST_EN },
|
||||
{ Register::BANK_0::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::DEVICE_RESET | PWR_MGMT_1_BIT::SLEEP },
|
||||
{ Register::BANK_0::INT_PIN_CFG, INT_PIN_CFG_BIT::INT1_ACTL, 0 },
|
||||
{ Register::BANK_0::INT_ENABLE_1, INT_ENABLE_1_BIT::RAW_DATA_0_RDY_EN, 0 },
|
||||
{ Register::BANK_0::FIFO_EN_2, FIFO_EN_2_BIT::ACCEL_FIFO_EN | FIFO_EN_2_BIT::GYRO_Z_FIFO_EN | FIFO_EN_2_BIT::GYRO_Y_FIFO_EN | FIFO_EN_2_BIT::GYRO_X_FIFO_EN, FIFO_EN_2_BIT::TEMP_FIFO_EN },
|
||||
{ Register::BANK_0::FIFO_MODE, FIFO_MODE_BIT::Snapshot, 0 },
|
||||
};
|
||||
|
||||
uint8_t _checked_register_bank2{0};
|
||||
static constexpr uint8_t size_register_bank2_cfg{2};
|
||||
register_bank2_config_t _register_bank2_cfg[size_register_bank2_cfg] {
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::BANK_2::GYRO_CONFIG_1, GYRO_CONFIG_1_BIT::GYRO_FS_SEL_4000_DPS, GYRO_CONFIG_1_BIT::GYRO_FCHOICE },
|
||||
{ Register::BANK_2::ACCEL_CONFIG, ACCEL_CONFIG_BIT::ACCEL_FS_SEL_30G, ACCEL_CONFIG_BIT::ACCEL_FCHOICE },
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::BANK_2::GYRO_CONFIG_1, GYRO_CONFIG_1_BIT::GYRO_FS_SEL_4000_DPS, GYRO_CONFIG_1_BIT::GYRO_FCHOICE },
|
||||
{ Register::BANK_2::ACCEL_CONFIG, ACCEL_CONFIG_BIT::ACCEL_FS_SEL_30G, ACCEL_CONFIG_BIT::ACCEL_FCHOICE },
|
||||
};
|
||||
};
|
||||
|
||||
@@ -105,9 +105,12 @@ enum class BANK_2 : uint8_t {
|
||||
//---------------- BANK0 Register bits
|
||||
// USER_CTRL
|
||||
enum USER_CTRL_BIT : uint8_t {
|
||||
DMP_EN = Bit7,
|
||||
FIFO_EN = Bit6,
|
||||
I2C_MST_EN = Bit5,
|
||||
I2C_MST_EN = Bit5, // Enable the I2C Master I/F module
|
||||
I2C_IF_DIS = Bit4, // Reset I2C Slave module and put the serial interface in SPI mode only
|
||||
|
||||
SRAM_RST = Bit2, // Reset SRAM module. Reset is asynchronous. This bit auto clears after one clock cycle of the internal 20 MHz clock.
|
||||
};
|
||||
|
||||
// PWR_MGMT_1
|
||||
|
||||
Reference in New Issue
Block a user