This commit fixed a bug were the mag was orphened on a reset.
That resulted in MAG timeouts on reset or test operations and
left the mag in a broken state.
We want to setup the mag interface with retries and report
failurs.
Move retry logic to contol point, instead of hiding re-reading
the ID in ak8963_check_id.
Allow it to fail once to overcome a read of 0 on firt read.
after 2 failure report error to console and reset the
mpu9250's I2C master (SPI to I2C bridge)
The same retry logic is used on the ak8963_read_adjustments
with a reset of the I2C master module after 5 fails. If it
fails fter 10 retires. Disabel the mad and report the failure
on the console, stating it is disabled.
On initialization, if after 3 retries to re-init the mpu9250 from
the checked registers values, it fails. Ensure thath the fact the
driver is exitting is logged to console.
Check that the mpu9250's configured registers match the settings
written to them. Attempt to fix any that do not up to 3 times.
printing erros to the console on mismatches and returning
faliure if after 3 attempts the any of the values are
still wrong.
Given the original poster's comment that "It happens very consistently for us." I suspect the motor spin observed in https://github.com/PX4/Firmware/issues/7457 is not caused by the original issue of slow decay on the PWM pins at reset, but the post reset pulse of 3.1 Ms arriving in a window that the ESC considers it valid.
The results from testing, indicated that the if the PWM pins were clamped low for > 300 Ms, prior to reset the motors did not spin. This would delay the the post reset pulse of 3.1 Ms out by > 300 Ms.
This change delays the reset and therefore the pulse by at least 400 Ms.
problem: previously when connecting power to Power 1, commander refused
to arm (no power source error), and when connecting to Power 2, arming
works, but power consumption was not measured (& shown in QGC).
Swapping Brick1 with Brick2 makes sure both works when connecting to
power 1.
Ideally we will have support for both power sources (including fail-over)
