board_get_px4_guid() called board_get_uuid() with a 2 bytes offset into an
uint8_t array. This gives no guarantees on alignment, and board_get_uuid()
casts it to an uint32_t array, leading to potentially unaligned accesses.
The form of the PX4 GUID is as follows:
offset:0 1 2 - 17
<ARCH MSD><ARCH LSD><MSD CPU UUID>...<LSD CPU UUID>
Where <ARCH MSD><ARCH LSD> are a monotonic ordinal number assigned by
PX4 to a chip architecture (PX4_SOC_ARCH_ID). The 2 bytes are used to
create a globally unique ID when prepended to a padded CPU ID.
In the case where the CPU's UUID is shorter than 16 bytes it will be
padded with 0's starting at offset [2] until
PX4_CPU_MFGUID_BYTE_LENGTH-PX4_CPU_UUID_BYTE_LENGTH -1
I.E. For the STM32
offset:0 1 2 3 4 5 6 - 17
<ARCH MSD><ARCH LSD>[0][0][0][0]<MSD CPU UUID>...<LSD CPU UUID>
I.E. For as CPU with a 16 byte UUID
offset:0 1 2 - 17
<ARCH MSD><ARCH LSD><MSD CPU UUID>...<LSD CPU UUID>
This will disable the fxos8701cq internal mag on
the NXPHlite. There are random noise spikes on the
HIGHRES_IMU.[x|y|x]mag. Even with all other SPI
devices shut down, the noise is still present.
The Simple HW detection was detecting the
Pixhack V3 as a mini.
This commit adds further discrimination, based on
the fact the Pixhack V3 left VDD_5V_PERIPH_EN
floating. Where a mini ,V2, V3 HW has it connected
to the active low enable of the VDD_5V_PERIPH and
VDD_5V_HIGHPOWER via a 10K pull down.
The detection enables the 40K pull up and samples
the pin. This reads back as a logical one on the
Pixhack V3, and a logical zero on the Mini.
Since the float is applied some 3.3 Ms post pin setting
at reset the 10 us should leave the 5 Volt supplies in
the on state because of the 10K pull down.
This is assuming typical 40K pullup 10K pull down
This results in typical 0.66V (.875V max) on the /EN pin
which should not be detected as a high on the TPS2041.
David Sidrane