- minor scheduling improvements
- if expected number of samples larger than expected adjust timestamp sample and save sample for next iteration
- when scheduling via data ready interrupt (with no FIFO watermark) count continuously without clearing
- increase SPI stall time slightly
- tolerate mag self test failure (could be due to local magnetic field)
- register configuration compatible with older ADIS16448AMLZ
- don't publish duplicate accel/gyro
- only allocate CRC perf counter if using CRC
- new IMU driver structure with state machine (no sleeps in bus thread)
- verify all configured registers and trigger reset on failure
- detect if DIO1 or DIO2 are actually connected for data ready interrupt usage
- don't use CRC-16 on burst transfers except for verified lots