Commit Graph

97 Commits

Author SHA1 Message Date
David Sidrane 1c212e3f84 M7 dcache ctrl via a parameter (#11769)
* Support for armv7-m_dcache control via parameter

  The FORCE_F7_DCACHE parameter can be set to
   0 - (default) if Eratta exits turn dcache off else leave it on
   1 -  Force it off
   2 -  Force it on

   At boot the system will disable the d-cache if the silicon
   has the 1259864 Data corruption in a sequence of Write-Through
   stores and loads eratta.

   Post nsh script execution the FORCE_F7_DCACHE paramater
   will be used to set the d-cache to the state indicated
   above.
2019-04-03 16:14:19 -04:00
mcsauder e6f1a2db12 Delete trailing whitespace, extra newlines, to quiet git hooks and add an extra = so that it does not appear to git as a merge conflict marker. 2019-04-02 15:31:37 -04:00
David Sidrane fd31091fdb bmm150:Restored lost internal i2C 2019-04-02 13:40:17 -04:00
Julian Oes 187f3f2834 SITL: interim fix for replay
The replay functionality was broken with lockstep. This is an interim
fix for the replay functionality.

In the longer term it would be nice to leverage the lockstep speedup
for the replay.
2019-03-27 12:55:37 +01:00
Daniel Agar f402f68fb1 px4_fmu-v3 include icm20948 (Here+ compass) 2019-03-24 00:53:33 -04:00
Daniel Agar 5e6bfe1ad8 vscode updates
* working debugging (one click build and debug)
   * SITL jmavsim
   * SITL gazebo
   * jlink px4_fmu-v{2-5}
 * improved syntax highlighting
   * GNU linker files
   * ROS message files msg/*.msg
   * jinja2 template files
 * fixed intellisense support
2019-03-22 20:55:39 -04:00
Daniel Agar 82737f4d2e px4_esc-v1 nsh compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar 9d8c4c2945 px4_cannode-v1 nsh compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar 3f890b6ab1 px4_fmu-v5 stackcheck compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar f6cd70bcc5 px4_fmu-v5 nsh compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar 7ccaf1068b px4_fmu-v4pro nsh compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar 8f32f3a0c8 px4_fmu-v4 stackcheck compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar 41ff6c60ba px4_fmu-v4 nsh compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar f1f84e52c7 px4_fmu-v3 stackcheck compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar d5b617deac px4_fmu-v3 nsh compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar fa2142d06e px4_fmu-v2 nsh compress defconfig 2019-03-21 08:41:01 -04:00
Daniel Agar de7df621d7 px4_io-v2 nsh compress defconfig 2019-03-21 08:41:01 -04:00
David Sidrane 3938574a4a px4_fmuv5:Extend probes to CAP pins
This also fixes a typo in the GPIO defines
2019-03-18 16:16:23 -04:00
Hamish Willee 257b90958f Correct links to example docs 2019-03-15 08:05:54 +01:00
Vasily Evseenko f8c50f442f Fix RSSI in on FMUv4 (pixracer) 2019-03-11 10:55:57 -07:00
mcsauder d60d802194 Correct board-config PIN1/PIN0 typo in fmu-v5/src/board_config.h. 2019-03-02 14:31:02 -08:00
David Sidrane edd9f91a19 board:Set larger stack margin 2019-03-01 23:45:48 -05:00
David Sidrane 12d442e8dd px4_fmuv5:Stack Check build Increase to 2624
The cause of the stack detection fault is because of the
   level of nesting in the start up script. We need to
   determine the worst case configuration and set the
   bar there.

   This fault occurred some 42 calls deep due to script
   calling script (repeat).

   The HW stack check requires as a margin of 204 bytes. That is
   ISR HW stacking of CPU(8) FPU(18) registers and SW stacking of
   CPU(11) and FPU(16) registers. Total CPU(19) registers is
   68 bytes and the total FPU(34) registers is 136 bytes.  On
   a system with a separate ISR stack This only needs to be 104
   so there is 100 bytes of headroom. But as coded the detection
   will give a false positive detection and fault. This does not
   mean that the stack will be corrupted.

   Adjustments to that stack can have no effect due to rounding.
   A stack size of 2608 and 2616 can yield the exact same size stack.
   So even when the failure is due to a 4 byte overflow, it can take
   greater than a 16 bytes increase to fix it. Because the final
   stack size is calculated with an 8 byte alignment after a 4 byte
   decrease. So 2624 becomes 2620 at runtime and will boot
   with SYS_AUTOSTART=4001.
2019-03-01 23:45:48 -05:00
David Sidrane 0846059646 fmuv5:Repurpose TIM5_SPARE_4 as nARMED
nARMED is a Digital OUTPUT. GPIO will be set as input while not
   armed HW will have Pull UP. While armed it will be configured
   as a GPIO OUT set LOW.
2019-02-26 15:34:10 -05:00
fpvaspassion cefffe652f Correted list of serial ports for lpe target for fmu v2 board 2019-02-25 10:41:05 -05:00
Mohammed Kabir 20e44aa320 Analog Device ADIS16497 IMU initial support 2019-02-25 09:34:58 -05:00
Beat Küng 6d2849f4ef fmu-v4 rc.board_extras: use 'if ! ' instead if 'if then else' 2019-02-19 10:55:55 +01:00
Daniel Agar f1d17c9003 camera_capture add to all boards 2019-02-11 14:15:28 -05:00
David Sidrane b40f8d52a8 STM32F7 disable d-cache as a precaution (#11374)
- see 1259864 Data corruption in a sequence of Write-Through stores and loads
 - if we can be certain this sequence won't occur in PX4 then the d-cache will be re-enabled
2019-02-10 18:25:16 -05:00
DanielePettenuzzo b12b4e1222 fixes after rebase 2019-02-10 18:07:44 -05:00
Daniel Agar adad624572 px4_fmu-v5 remove PX4_FMUV5_RC00 2019-02-08 20:52:15 -05:00
Daniel Agar 06f5a782f4 px4_fmu-v5 board spi cleanup 2019-02-08 20:52:15 -05:00
Daniel Agar 1a4d31140e create example vehicle type build configs for fmu-v2 and fmu-v5 (#10963)
- update navigator precision landing to build without multicopter
2019-02-05 19:53:54 -05:00
Daniel Agar 8dc0509989 mpu9250: split icm20948 support out into new separate driver 2019-01-30 09:29:08 +01:00
Daniel Agar 298049b0fb px4_fmu-v4_stackcheck sync with default and increase pmw3901 main stack 2019-01-29 14:14:29 -05:00
David Sidrane 6f9a9b3d2c px4_fmu-v4: add runtime external SPI4 detection to support pmw3901 (#11301)
* The build is built with SPI4. At run time the signal GPIO_8266_GPIO2 it tested. If it is low the SPI4 is configured. If it is high SPI4 is not configured.
 * board_common: Add Notion of Board has bus manifest
2019-01-29 13:44:15 -05:00
mcsauder dc5f18bdcd ToneAlarm class refactoring to implement an interface for hardware specific methods and a single ToneAlarm class. 2019-01-28 18:58:04 -08:00
Daniel Agar 23617fb880 px4_fmu-v2_default disable constained flash options 2019-01-27 19:48:38 -05:00
Daniel Agar 739a02022b position_estimator_inav: move to examples (start deprecation) 2019-01-27 22:15:39 +01:00
David Sidrane 0f5f4814bb px4_fmu-v5: Inital commit NuttX 7.27+ 2019-01-25 06:32:37 -08:00
David Sidrane 7e863456c4 px4_fmu-v4pro: Inital commit NuttX 7.27+ 2019-01-25 06:32:37 -08:00
David Sidrane 938f1453fe px4_fmu-v4: Inital commit NuttX 7.27+ 2019-01-25 06:32:37 -08:00
David Sidrane 9430854404 px4_fmu-v3: Inital commit NuttX 7.27+ 2019-01-25 06:32:37 -08:00
David Sidrane b31f29b983 px4_fmu-v2: Inital commit NuttX 7.27+ 2019-01-25 06:32:37 -08:00
David Sidrane 09d279b1e0 px4_esc-v1: Inital commit NuttX 7.27+ 2019-01-25 06:32:37 -08:00
David Sidrane f943aa5d26 px4_cannode-v1:Inital commit NuttX 7.27+ 2019-01-25 06:32:37 -08:00
David Sidrane 2d7effa342 px4_io-v2: Inital commit NuttX 7.27+ 2019-01-25 06:32:37 -08:00
David Sidrane 8f308efa88 upstram NuttX CONFIG_EXAMPLES_NSH_CXXINITIALIZE->CONFIG_SYSTEM_NSH_CXXINITIALIZE 2019-01-25 06:32:37 -08:00
David Sidrane 5c23099eed board_button_irq: API change in upstream 2019-01-25 06:32:37 -08:00
David Sidrane f2208171d5 Add callout for CONFIG_BOARDCTL_FINALINIT 2019-01-25 06:32:37 -08:00