if _ftp_on is true, message_buffer was created and read, but it was
actually never written to, so this is not needed. It can only ever be
written to if _forwarding_on is true.
And the maximum number of configured file descriptors.
Note that this is per group, not per thread, so that e.g. logger and
log_writer_file show the same number.
VDev::getDev() is used in px4_access, which is used in orb_exists. And if
the topic does not exist, it iterates over all 500 indexes, which is slow.
It was slow even if the topic existed, the map reduces runtime from linear
to logarithmic (there are around 80 items in the container).
This is only used on posix.
This allows to run a command / function once when being deactivated. This avoids having flight modes which are not active run unnecessary code all the time.
inverted S.bus signal and fetch the data of each channel and publish it
2. Fix the bug of linux_pwm_out, when the protocol is pca9685,
after the init method is executed,the method of determining the return
value of init method is incorrect,this will cause the driver to fail
3. Add linux_sbus driver to other posix prefixes cmake files
This is a back port of upstream NuttX PX4 contrib of
ef42c25 stm32f7:SDMMC add dcache alignment check in dma{recv|send}setup
In the where CONFIG_SDIO_PREFLIGHT is not used and dcache
write-buffed mode is used (not write-through) buffer alignment
is required for DMA transfers because a) arch_invalidate_dcache
could lose buffered writes data and b) arch_flush_dcache could
corrupt adjacent memory if the buffer and the bufflen, are not on
ARMV7M_DCACHE_LINESIZE boundaries.
1e7ddfe stm32f7:SDMMC remove widebus limitation on DMA
There is no documantation for the STM32F7 that limits DMA on
1 bit vrs 4 bit mode.
dffab2f stm32f7:DMA add dcache alignment check in stm32_dmacapable
In the case dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data and
b) arch_flush_dcache could corrupt adjacent memory if the
maddr and the mend+1, the next next address are not on
ARMV7M_DCACHE_LINESIZE boundaries.
38cbf1f stm32f7:DMA correct comments and document stm32_dmacapable
Updated comment to proper refernce manual for STM32F7 not STM32F4.
Added stm32_dmacapable input paramaters documentation.
Beat Küng