Commit Graph
831 Commits
Author SHA1 Message Date
Simone Guscetti 0f47272628 board_common: fix typo 2018-10-05 07:54:44 -07:00
mcsauder 2d208b1524 Edited aerofc-v1 file comments to not reference tap-v1. 2018-10-03 15:47:04 -04:00
Beat Küng 6c34407d57 version: rebase fixes & add bbblue 2018-10-03 10:30:10 +02:00
Beat Küng 703a5376bb bebop board config: add a separate SOC_ARCH_ID 2018-10-03 10:30:10 +02:00
Beat Küng b9a99969a7 board_get_uuid: fix alignment issues
board_get_px4_guid() called board_get_uuid() with a 2 bytes offset into an
uint8_t array. This gives no guarantees on alignment, and board_get_uuid()
casts it to an uint32_t array, leading to potentially unaligned accesses.
2018-10-03 10:30:10 +02:00
David Sidrane a934d6e3f2 samv7:Fixed incorrect index populating px4_guid 2018-10-03 10:30:10 +02:00
David Sidrane 03948c1ad3 kinetis:Fixed incorrect index populating px4_guid 2018-10-03 10:30:10 +02:00
Beat Küng daf05b3854 board_common: add PX4_SOC_ARCH_ID_UNUSED = 0 to PX4_SOC_ARCH_ID_t
Just to make sure we never have an UUID == 0
2018-10-03 10:30:10 +02:00
David Sidrane 0b17995e81 eagle:revert CMakeLists.txt to wrong sitl, add board identity API
This file was clearly clearly but built.
2018-10-03 10:30:10 +02:00
David Sidrane bdaff018b7 samv7:Add PX4 GUID API 2018-10-03 10:30:10 +02:00
David Sidrane 43f6c4df77 kinetis:Add PX4 GUID API 2018-10-03 10:30:10 +02:00
David Sidrane 4e32ca45f1 sitl:Use PX4_SOC_ARCH_ID_t from board common 2018-10-03 10:30:10 +02:00
David Sidrane d85452863d rpi:Use PX4_SOC_ARCH_ID_t from board common 2018-10-03 10:30:10 +02:00
David Sidrane 3d96e2ef60 ocpoc:Use PX4_SOC_ARCH_ID_t from board common 2018-10-03 10:30:10 +02:00
David Sidrane 5fea494a2d eagle:Use PX4_SOC_ARCH_ID_t from board common 2018-10-03 10:30:10 +02:00
David Sidrane dc59e19bbb Moved PX4_SOC_ARCH_ID from px4_micro_hal to board_common 2018-10-03 10:30:10 +02:00
David Sidrane 695a7f6839 board_common:Added missing END_DECLS from rebase 2018-10-03 10:30:10 +02:00
David Sidrane 594da6247b board_common:Make board indenty API required. 2018-10-03 10:30:10 +02:00
David Sidrane 73552bdd64 sim:Use Non Arch specific Board identity API 2018-10-03 10:30:10 +02:00
David Sidrane a96acbb04d ocpoc:Use Non Arch specific Board identity API 2018-10-03 10:30:10 +02:00
David Sidrane 82dcfeb576 eagle:Use Non Arch specific Board identity API 2018-10-03 10:30:10 +02:00
David Sidrane 1c779d58fb bebop:Use Non Arch specific Board identity API 2018-10-03 10:30:10 +02:00
David Sidrane bc075208d5 rpi:Use Non Arch specific Board identity API 2018-10-03 10:30:10 +02:00
David Sidrane a1abd1b632 sitil:Use Non Arch specific Board identity API 2018-10-03 10:30:10 +02:00
David Sidrane ed9223edaf board_identity:Added common no-arch specific board_identity API
This common code can be used byt posix based boars to provide
   the board_identity API.
2018-10-03 10:30:10 +02:00
David Sidrane 1ac54f977e board_common:Documentation clean up 2018-10-03 10:30:10 +02:00
David Sidrane a16ca0ccf9 sitl:Added BOARD_OVERRIDE_PX4_GUID 2018-10-03 10:30:10 +02:00
David Sidrane ba336bd19e rpi:Added BOARD_OVERRIDE_PX4_GUID 2018-10-03 10:30:10 +02:00
David Sidrane a1d5cb766a ocpoc:Added BOARD_OVERRIDE_PX4_GUID 2018-10-03 10:30:10 +02:00
David Sidrane cca2fd8471 eagle:Added BOARD_OVERRIDE_PX4_GUID 2018-10-03 10:30:10 +02:00
David Sidrane 7050657a6e board_identity:Add stm32 board_get_px4_guid and board_get_px4_guid_formated API 2018-10-03 10:30:10 +02:00
David Sidrane 1c2f8bd4c4 board_identity:Fix potential buffer over flow 2018-10-03 10:30:10 +02:00
David Sidrane f24a052355 board_common:Add PX4 GUID, deprecate other UUID API
The form of the PX4  GUID is as follows:
   offset:0         1         2         -           17
      <ARCH MSD><ARCH LSD><MSD CPU UUID>...<LSD CPU UUID>

   Where <ARCH MSD><ARCH LSD> are a monotonic ordinal number assigned by
   PX4 to a chip architecture (PX4_SOC_ARCH_ID). The 2 bytes are used to
   create a globally unique ID when prepended to a padded CPU ID.

   In the case where the CPU's UUID is shorter than 16 bytes it will be
   padded with 0's starting at offset [2] until
   PX4_CPU_MFGUID_BYTE_LENGTH-PX4_CPU_UUID_BYTE_LENGTH -1
   I.E. For the STM32
   offset:0         1     2  3  4  5  6             -            17
     <ARCH MSD><ARCH LSD>[0][0][0][0]<MSD CPU UUID>...<LSD CPU UUID>

   I.E. For as CPU with a 16 byte UUID
   offset:0         1         2         -           17
     <ARCH MSD><ARCH LSD><MSD CPU UUID>...<LSD CPU UUID>
2018-10-03 10:30:10 +02:00
Beat Küng 546886259f boards: remove GPS_DEFAULT_UART_PORT
Not required anymore.
2018-09-25 07:53:29 +02:00
Daniel Agar 73fe4ecd20 AV-X enable GPS for rev C board 2018-09-12 02:39:03 -04:00
David Sidrane 520a81a951 nxphlite-v3:Disable internal mag due to random spikes.
This will disable the fxos8701cq internal mag on
  the NXPHlite. There are random noise spikes on the
  HIGHRES_IMU.[x|y|x]mag. Even with all other SPI
  devices shut down, the noise is still present.
2018-09-11 06:58:35 -07:00
mcsauder e7666aa5d8 Added an imu heater driver, formatted whitespace, standardized comments, and added doxy documentation. 2018-09-06 12:03:26 +02:00
Kevin Lopez Alvarez c10ea132b4 PNI RM3100 magnetometer driver (#10302)
* tested on SPI (px4fmu-v4pro)
 * WIP I2C support
2018-08-28 11:44:34 -04:00
David Sidrane b721b6a54a kinetis:Fixed hard fault when called with nullptr for errata
Logger was hard faulting on start due to a write to
  null pointer dereferece of errata
2018-08-23 14:26:32 -07:00
mcsauder 3a22ee48db Correct trailing whitespaces. 2018-08-18 15:15:41 -04:00
David Sidrane 84f121ce0a px4fmu-v2:CAN2 GPIO init was over written
hardware detection was overwriting the CAN2 GPIO setting
2018-08-16 00:06:25 +02:00
David Sidrane 18ccf8dbd2 px4fmu-v2: Add detection for Pixhack V3 (#10231)
The Simple HW detection was detecting the
  Pixhack V3 as a mini.

  This commit adds further discrimination, based on
  the fact the Pixhack V3 left VDD_5V_PERIPH_EN
  floating. Where a mini ,V2, V3 HW has it connected
  to the active low enable of the VDD_5V_PERIPH and
  VDD_5V_HIGHPOWER via a 10K pull down.

  The detection enables the 40K pull up and samples
  the pin. This reads back as a logical one on the
  Pixhack V3, and a logical zero on the Mini.

  Since the float is applied some 3.3 Ms post pin setting
  at reset the 10 us should leave the 5 Volt supplies in
  the on state because of the 10K pull down.
  This is assuming typical 40K pullup 10K pull down
  This results in typical 0.66V (.875V max) on the /EN pin
  which should not be detected as a high on the TPS2041.
2018-08-15 09:24:18 -04:00
David Sidrane 011ebd43b8 nxphlite-v3:Enable CAN transceivers 2018-08-14 09:38:15 -04:00
David Sidrane 5044426949 nxphlite-v3:Use non data time RTC configuration.
One a 32.768 is added (RC16) to the board this will keep time.
2018-08-14 09:38:15 -04:00
David Sidrane d466a09708 kinetis:Add MCU version decoding 2018-08-14 09:38:15 -04:00
David Sidrane 35960fb012 NXPHlite-V3:Add reset to bootloader detection
On the K66 we use the first word of the Battery backed up RAM
   as the bootloader - app communication location.
2018-08-14 09:38:15 -04:00
David Sidrane e35be68fd4 NXPhlite work arround to internal i2c routed to external connector.
Since the only device on the bus is the barro, int or ext does
   not apply. This will be fixed on the rev > RC15.
   This defines an alias that can be used to condition the buss logic
   connection logic px4_i2c_bus_external to return external.
2018-08-14 09:38:15 -04:00
David Sidrane 5d9a0cfc82 nxphlite-v3:Fix RGB ordering Red and Green were swapped. 2018-08-14 09:38:15 -04:00
Jan Okle 0754b3566c Enable DMA based serial driver and add polling serial driver for more data. 2018-08-14 09:38:15 -04:00
David Sidrane e88bad3b47 px4cannode-v1:Board does CAN GPIO init 2018-08-08 15:09:01 -04:00