9064f8bf09
px4io: fixed the io_reg_{set,get} errors
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this fixes the PX4IO state machine to avoid the io errors we were
seeing. There are still some open questions with this code, but it now
seems to give zero errors, which is an improvement!
2013-10-28 13:10:23 +01:00
e2458677c9
Tweak IO serial packet error handling slightly; on reception of a serial error send a line break back to FMU. This should cause FMU to stop sending immediately.
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Flag these cases and discard the packet rather than processing it, rather than simply dropping the received packet and letting FMU time out.
2013-07-07 20:42:03 -07:00
b4029dd824
Pull v2 pieces up to build with the merge
2013-07-07 17:53:55 -07:00
4d400aa7e7
Enable UART error handling on PX4IO.
2013-07-06 12:27:37 -07:00
87a4f1507a
Move the common definitions for the PX4IO serial protocol into the shared header.
2013-07-06 00:16:37 -07:00
19b2e1de85
Copy the correct number of bytes back for register read operations. Basic PX4IO comms are working now.
2013-07-06 00:00:44 -07:00
3c8c596ac7
Enable handling for short-packet reception on FMU using the line-idle interrupt from the UART. Enable short packets at both ends.
2013-07-05 20:37:05 -07:00
bcfb713fe9
Enable handling for short-packet reception on IO using the line-idle interrupt from the UART.
2013-07-05 20:35:55 -07:00
f9a85ac7e6
Remove the TX completion callback on the IO side.
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Report CRC, read and protocol errors.
2013-07-05 19:16:25 -07:00
10e673aa4b
Send error response if register write fails.
2013-07-05 19:02:42 -07:00
46a4a44321
Be more consistent with the packet format definition.
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Free perf counters in ~PX4IO_serial
2013-07-05 18:36:00 -07:00
50cae347b4
Check packet CRCs and count errors; don't reject packets yet.
2013-07-05 17:13:54 -07:00
5a8f874166
Add an 8-bit CRC to each transmitted packet.
2013-07-05 16:56:47 -07:00
313231566c
Encode the packet type and result in the unused high bits of the word count.
2013-07-05 16:41:27 -07:00
e55a37697d
Always send and expect a reply for every message.
2013-07-05 16:34:44 -07:00
83213c66df
Reset the PX4IO rx DMA if we haven't seen any traffic in a while; this gets us back into sync.
2013-07-04 23:22:59 -07:00
94b638d848
One more piece of paranoia when resetting DMA
2013-07-04 23:19:24 -07:00
43210413a9
More test work on the px4io side of the serial interface.
2013-07-04 23:17:55 -07:00
be6ad7af3b
Rework the FMU<->IO connection to use a simple fixed-size DMA packet; this should let us reduce overall latency and bump the bitrate up.
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Will still require some tuning.
2013-07-03 00:08:12 -07:00
d1562f926f
More implementation for the serial side on IO; fix a couple of bugs on the FMU side.
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Still needs serial init and some more testing/config on the FMU side, but closer to being ready to test.
2013-06-28 23:39:35 -07:00
308ec6001a
Add serial read-length handling.
2013-05-22 22:09:00 +02:00
e67022f874
Serial interface for IOv2
2013-04-28 18:14:46 -07:00
Andrew Tridgell