Commit Graph
9 Commits
Author SHA1 Message Date
Daniel Agar 5d7a82b8e2 av/x-v1 support PMW3901 on SPI2 (now treated as external) 2019-04-30 02:27:29 -04:00
Daniel Agar db5dbb25b3 av/x-v1 board support cleanup and sync with fmu-v5 2019-04-30 02:27:29 -04:00
David Sidrane 46c4a68b62 fmu-v5: Move stage 0 dcache disable to later in boot (#11791) 2019-04-04 11:07:28 -04:00
David Sidrane 1c212e3f84 M7 dcache ctrl via a parameter (#11769)
* Support for armv7-m_dcache control via parameter

  The FORCE_F7_DCACHE parameter can be set to
   0 - (default) if Eratta exits turn dcache off else leave it on
   1 -  Force it off
   2 -  Force it on

   At boot the system will disable the d-cache if the silicon
   has the 1259864 Data corruption in a sequence of Write-Through
   stores and loads eratta.

   Post nsh script execution the FORCE_F7_DCACHE paramater
   will be used to set the d-cache to the state indicated
   above.
2019-04-03 16:14:19 -04:00
Daniel Agar 2ffb49b734 delete px4_includes.h header and update boards/ to use syslog 2019-01-23 18:25:18 -05:00
Daniel Agar 320d2e9383 create PX4 platform layer initialization helper (#11269)
- starts requirements for PX4 modules (hrt, param, etc)
2019-01-22 14:13:20 -05:00
Daniel Agar d4e06e517a delete drv_gpio.h, modules/gpio_led, and fmu GPIO ioctls 2018-12-03 16:30:39 +01:00
Daniel Agar ec4c9da253 remove BOARD_NAME from board_config.h and set automatically 2018-11-26 14:40:14 -08:00
Daniel Agar f692ad04d0 boards organization 2018-11-26 14:40:14 -08:00