Commit Graph

789 Commits

Author SHA1 Message Date
David Sidrane 5148d2d94f px4fmu-v2 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane b606897743 px4flow-v2 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane ee28b9aa69 px4esc-v1 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 65322c98ca px4cannode-v1 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 384a1dcf66 px4cannode-v1 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane eaec63a747 px4cannode-v1 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 233d116aee px4-stm32f4discovery nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 7c3850902f omnibus-f4sd nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 053fecbf20 nxphlite-v3 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 0bd2a0be05 mindpx-v2 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 197940eadd esc35-v1 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 907d478f3e crazyflie nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane debb8afa0d av-x-v1 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane fe591aee5c auav-x21 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane e893aaec48 aerofc-v1 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
David Sidrane 0829e3c654 aerocore2 nsh: Disable ARCH_IRQPRIO & ARCH_HIPRI_INTERRUP
This insures the common exception handler will not be
   re-entered. The handler does not support nested interrupts
   and the interrupt stack pointer and context will be overwritten
   resulting in hard to debug hardfaults.

   If all the priorities are equal the NVIC prevents the
   preemption. The startup code defaults all the priorities
   to the same value 128.

   This change safeguards in 2 ways 1) By disabling
   CONFIG_ ARCH_IRQPRIO: up_prioritize_irq cannot be called.
   This will insure that all HW interrupts are at the same
   priority.

   2) By disabling CONFIG_ARCH_HIPRI_INTERRUP, the common
   exception will disable any interrupts during interrupt
   processing.
2018-09-25 12:28:03 -04:00
Daniel Agar 610ec9f854 Update submodule nuttx to latest Sun Sep 23 08:37:24 EDT 2018 (#10550)
- nuttx in PX4/Firmware (f3cbd3c744e9224bd55597fbfae23c56ce296544): https://github.com/PX4-NuttX/nuttx/commit/98a89513060c42215e9cd14f52a7fd7dcc08dacc
    - nuttx current upstream: https://github.com/PX4-NuttX/nuttx/commit/e31e94f5bd3cf68b9ed0f010724ac9122730dd21
    - Changes: https://github.com/PX4-NuttX/nuttx/compare/98a89513060c42215e9cd14f52a7fd7dcc08dacc...e31e94f5bd3cf68b9ed0f010724ac9122730dd21

    e31e94f 2018-09-21 David Sidrane - [REJECTED] kinetis:usbdev use CONFIG_KINETIS_USBOTG_PRIO at default
2018-09-23 10:07:42 -04:00
mcsauder a1af7ffdcf Remove whitespaces to quiet git commit trailing whitespace warnings. 2018-09-21 23:28:31 +02:00
David Sidrane d2faf5f31d platforms/nuttx/NuttX/nuttx with hardfault fix 2018-09-21 22:34:38 +02:00
David Sidrane eb4f847322 nxphlite-v3:Set UART4 to have the same bufffer sizes as TELEM1
Bring UART4 bufffer sizes in alignment with FMUv2 Telem1
2018-09-14 15:38:56 -04:00
David Sidrane 698590a5b2 Update nuttx with hardfault fix for kinetis on i2c reset 2018-09-13 06:56:00 -07:00
Daniel Agar 73fe4ecd20 AV-X enable GPS for rev C board 2018-09-12 02:39:03 -04:00
Daniel Agar 56723b2ece AV-X initial networking support 2018-09-07 16:50:32 -07:00
Daniel Agar d7580aa676 px4fmu-v5 increase CONFIG_USERMAIN_STACKSIZE slightly 2018-09-02 16:41:41 -04:00
Daniel Agar ac298664c7 nuttx-configs increase idle thread stack size to 750 bytes 2018-09-02 15:31:54 -04:00
Daniel Agar 7cc0e69fcd add px4fmu-v{3,4,5} stackcheck configs 2018-09-02 14:16:04 -04:00
Daniel Agar c76187dbbb Update submodule nuttx to latest Fri Aug 31 21:30:51 UTC 2018 (#10385)
- nuttx in PX4/Firmware (0a1a2025402a387cde88132c6f8d8cc7237d2e6b): https://github.com/PX4-NuttX/nuttx/commit/bf8cce85c3f9310bcff8cdd1d979270419782a6e
    - nuttx current upstream: https://github.com/PX4-NuttX/nuttx/commit/e3b5b667aee16a699ecd6605f2d2a4adc6e95c17
    - Changes: https://github.com/PX4-NuttX/nuttx/compare/bf8cce85c3f9310bcff8cdd1d979270419782a6e...e3b5b667aee16a699ecd6605f2d2a4adc6e95c17

e3b5b66 2018-08-31 Daniel Agar - [BACKPORT] Merged in dagar/nuttx/pr-stm32f7_stackcheck-upstream (pull request #714)
2018-08-31 18:44:34 -04:00
David Sidrane 1b6e933176 Make.defs.in:Runtime Stack Checking in Nuttx Build
Use CONFIG_ARMV7M_STACKCHECK to add the instrumentation
  for runtime stack checking
2018-08-31 13:03:39 -07:00
David Sidrane 4f2aa51767 px4_impl_os:Use the defconfig CONFIG_ARMV7M_STACKCHECK
To enable coherent runtime stack checking use the boards
  CONFIG_ARMV7M_STACKCHECK setting
2018-08-31 13:03:39 -07:00
PX4 Build Bot 2164ef8fb6 Update submodule nuttx to latest Sat Aug 25 15:12:57 UTC 2018
- nuttx in PX4/Firmware (72792cef43): https://github.com/PX4-NuttX/nuttx/commit/bf8cce85c3f9310bcff8cdd1d979270419782a6e
    - nuttx current upstream: https://github.com/PX4-NuttX/nuttx/commit/bf8cce85c3f9310bcff8cdd1d979270419782a6e
    - Changes: https://github.com/PX4-NuttX/nuttx/compare/bf8cce85c3f9310bcff8cdd1d979270419782a6e...bf8cce85c3f9310bcff8cdd1d979270419782a6e
2018-08-25 11:23:25 -04:00
David Sidrane e79b9a2c1b Update nuttx with backport Kinetis i2c fix (#10325) 2018-08-25 10:10:02 -04:00
David Sidrane 790356ef6d NXPHlite-v3:Ensure bin file sizes in mtpl of 8 2018-08-23 14:26:32 -07:00
David Sidrane 19d3e562e9 NXPHlite:Track kinetis upstream CONFIG changes 2018-08-23 14:26:32 -07:00
David Sidrane add7484083 Nuttx with Missing Backports 2018-08-23 14:26:32 -07:00
Daniel Agar 01744a9efc Jenkins px4fmu-v2 hardware test 2018-08-14 23:12:26 -04:00
Daniel Agar a2059acde5 NuttX stm32f7 configs unset ADC1 DMA 2018-08-14 20:32:28 -04:00
David Sidrane 03000bb0ef Updated apps nuttx of platforms/nuttx 2018-08-14 09:38:15 -04:00
David Sidrane 4d3aff23d7 NXPflite-v3:Hack-Fixes USB not enumerating on Virtual Box VM 2018-08-14 09:38:15 -04:00
David Sidrane 346224a0c6 NXPhlite:Fix init stack warning 2018-08-14 09:38:15 -04:00
David Sidrane 0e382aec71 Update NuttX with Kinetis Backports 2018-08-14 09:38:15 -04:00
David Sidrane f0663fb143 nxphlite-v3:Match probes to V3 HW 2018-08-14 09:38:15 -04:00
David Sidrane 5c7cbc4d30 nxphlite-v3:Add uavcan 2018-08-14 09:38:15 -04:00
David Sidrane c6cab03319 nxphlite-v3:Add Probes to defconfig 2018-08-14 09:38:15 -04:00
David Sidrane b9f2530688 Update nuttx submodule with FlexCan and PIT contrib 2018-08-14 09:38:15 -04:00
David Sidrane 9f96aa7a1e nxphlite-v3:Match bootloader VENDORSTR 2018-08-14 09:38:15 -04:00
David Sidrane 5044426949 nxphlite-v3:Use non data time RTC configuration.
One a 32.768 is added (RC16) to the board this will keep time.
2018-08-14 09:38:15 -04:00
David Sidrane f0c981312f nxphlite-v3:SDIO DMA working.
The fix ix in nuttx. This is just the defconfig changes to use
   it.

   There were 2 problems. The first was that the interrupt did
   test DINT and raise a completion events. But since DINT is
   just an indication of DMA completion, TC is a valid way to
   determine that the transfer is complete.

   The second problem is that Software Reset For DAT Line
   SDHC_SYSCTL[RSTD] clears the bits 24-0 in SDHC_PROTO
   this looses the wide bus setting DTW
2018-08-14 09:38:15 -04:00
David Sidrane 26bc2d90d8 Upates nuttx Submodule - backport USB fix 2018-08-14 09:38:15 -04:00
David Sidrane f8085423fe Updated platforms/nuttx/NuttX/nuttx:as rebased on px4_firmware_nuttx-7.22+ 2018-08-14 09:38:15 -04:00
David Sidrane 9ccb9345be nxphlite-v3:bin file must be padded to multiple of 8
Flash programing on the K66 has to be units of 8 bytes. So we cache
   the write of words until there are 2 written. Then the 2 words are
   written to FLASH. This change ensure the bin file has an even
   number of (4 byte) words by padding the last section in progflash
   with 0xffffffff if needed.
2018-08-14 09:38:15 -04:00