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Update UCANS32K146 clocking to use XTAL and support higher pheriphal freq

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This commit is contained in:
Peter van der Perk
2022-05-11 11:13:55 +02:00
committed by David Sidrane
parent ea2c1095c2
commit e62e8b58d1
2 changed files with 5 additions and 5 deletions
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boards/nxp/ucans32k146/src/clockconfig.c
+1 -1
View File
@@ -110,7 +110,7 @@ const struct clock_configuration_s g_initial_clkconfig = {
{
.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_2, /* SPLLDIV2 */
.prediv = 1, /* PREDIV */
.mult = 40, /* MULT */
.src = 0, /* SOURCE */
boards/nxp/ucans32k146/src/periphclocks.c
+4 -4
View File
@@ -101,7 +101,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = {
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
.clksrc = CLK_SRC_SPLL_DIV2,
},
{
.clkname = LPSPI0_CLK,
@@ -110,7 +110,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = {
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
.clksrc = CLK_SRC_SPLL_DIV2,
},
{
.clkname = LPUART0_CLK,
@@ -119,7 +119,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = {
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
.clksrc = CLK_SRC_SPLL_DIV2,
},
{
.clkname = LPUART1_CLK,
@@ -128,7 +128,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = {
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
.clksrc = CLK_SRC_SPLL_DIV2,
},
{
.clkname = RTC0_CLK,