From e62e8b58d1311f06864a1dfe4de2d684ea94d55b Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Wed, 11 May 2022 11:13:55 +0200 Subject: [PATCH] Update UCANS32K146 clocking to use XTAL and support higher pheriphal freq --- boards/nxp/ucans32k146/src/clockconfig.c | 2 +- boards/nxp/ucans32k146/src/periphclocks.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/boards/nxp/ucans32k146/src/clockconfig.c b/boards/nxp/ucans32k146/src/clockconfig.c index 95e91ed28e..e197dfc555 100644 --- a/boards/nxp/ucans32k146/src/clockconfig.c +++ b/boards/nxp/ucans32k146/src/clockconfig.c @@ -110,7 +110,7 @@ const struct clock_configuration_s g_initial_clkconfig = { { .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ - .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_2, /* SPLLDIV2 */ .prediv = 1, /* PREDIV */ .mult = 40, /* MULT */ .src = 0, /* SOURCE */ diff --git a/boards/nxp/ucans32k146/src/periphclocks.c b/boards/nxp/ucans32k146/src/periphclocks.c index b805597d82..5dd570199b 100644 --- a/boards/nxp/ucans32k146/src/periphclocks.c +++ b/boards/nxp/ucans32k146/src/periphclocks.c @@ -101,7 +101,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = { #else .clkgate = false, #endif - .clksrc = CLK_SRC_SIRC_DIV2, + .clksrc = CLK_SRC_SPLL_DIV2, }, { .clkname = LPSPI0_CLK, @@ -110,7 +110,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = { #else .clkgate = false, #endif - .clksrc = CLK_SRC_SIRC_DIV2, + .clksrc = CLK_SRC_SPLL_DIV2, }, { .clkname = LPUART0_CLK, @@ -119,7 +119,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = { #else .clkgate = false, #endif - .clksrc = CLK_SRC_SIRC_DIV2, + .clksrc = CLK_SRC_SPLL_DIV2, }, { .clkname = LPUART1_CLK, @@ -128,7 +128,7 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = { #else .clkgate = false, #endif - .clksrc = CLK_SRC_SIRC_DIV2, + .clksrc = CLK_SRC_SPLL_DIV2, }, { .clkname = RTC0_CLK,