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Mpu9250:Allow internal reset to complete, when started from VDD of 0V

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Per the data sheet: Start-up time for register read/write from power-up is
   Typically 11 ms and the Maximum is 100 ms.

   It seems the power up reset is only triggered at VDD < 150 mV. So the
   symptom reported: Failure is only happening after a long power down is
   consistent with VDD not dropping below 150 mV, therefore not generating
   a POR and being ready to be written with out delay.

  This fix adds a delay of 110 ms to ensure the reset has ended with some.
  margin.
This commit is contained in:
David Sidrane 2017-07-14 13:48:46 -10:00 committed by Lorenz Meier
parent d10116e54a
commit c8bd60bef8
1 changed files with 9 additions and 1 deletions
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10
src/drivers/mpu9250/mpu9250.cpp
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@ -386,6 +386,15 @@ int MPU9250::reset()
{
irqstate_t state;
/* When the mpu9250 starts from 0V the internal power on circuit
* per the data sheet will require:
*
* Start-up time for register read/write From power-up Typ:11 max:100 ms
*
*/
usleep(110000);
// Hold off sampling until done (100 MS will be shortened)
state = px4_enter_critical_section();
_reset_wait = hrt_absolute_time() + 100000;
@ -410,7 +419,6 @@ int MPU9250::reset()
int MPU9250::reset_mpu()
{
write_reg(MPUREG_PWR_MGMT_1, BIT_H_RESET);
write_checked_reg(MPUREG_PWR_MGMT_1, MPU_CLK_SEL_AUTO);
write_checked_reg(MPUREG_PWR_MGMT_2, 0);