From c8bd60bef84f9bca6d6e5cc6710075cd577ae5c6 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 14 Jul 2017 13:48:46 -1000 Subject: [PATCH] Mpu9250:Allow internal reset to complete, when started from VDD of 0V Per the data sheet: Start-up time for register read/write from power-up is Typically 11 ms and the Maximum is 100 ms. It seems the power up reset is only triggered at VDD < 150 mV. So the symptom reported: Failure is only happening after a long power down is consistent with VDD not dropping below 150 mV, therefore not generating a POR and being ready to be written with out delay. This fix adds a delay of 110 ms to ensure the reset has ended with some. margin. --- src/drivers/mpu9250/mpu9250.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/drivers/mpu9250/mpu9250.cpp b/src/drivers/mpu9250/mpu9250.cpp index 5f76d8273a..3fd1d18b27 100644 --- a/src/drivers/mpu9250/mpu9250.cpp +++ b/src/drivers/mpu9250/mpu9250.cpp @@ -386,6 +386,15 @@ int MPU9250::reset() { irqstate_t state; + /* When the mpu9250 starts from 0V the internal power on circuit + * per the data sheet will require: + * + * Start-up time for register read/write From power-up Typ:11 max:100 ms + * + */ + + usleep(110000); + // Hold off sampling until done (100 MS will be shortened) state = px4_enter_critical_section(); _reset_wait = hrt_absolute_time() + 100000; @@ -410,7 +419,6 @@ int MPU9250::reset() int MPU9250::reset_mpu() { write_reg(MPUREG_PWR_MGMT_1, BIT_H_RESET); - write_checked_reg(MPUREG_PWR_MGMT_1, MPU_CLK_SEL_AUTO); write_checked_reg(MPUREG_PWR_MGMT_2, 0);