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[board] Increase CPU speed to 480MHz for FMUv6s

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The Ethernet clock output is not used anymore so there are no
restrictions on the clock tree configuration.
This aligns the clock speeds with FMUv6x.
This commit is contained in:
Niklas Hauser
2025-08-19 11:18:49 +02:00
committed by Niklas Hauser
parent 68fa5fc312
commit 450f1d33f6
1 changed files with 9 additions and 9 deletions
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boards/auterion/fmu-v6s/nuttx-config/include/board.h
+9 -9
View File
@@ -98,11 +98,11 @@
/* PLL1, wide 2 - 4 MHz input, enable DIVP, DIVQ, DIVR
*
* PLL1_VCO = (24,000,000 / 12) * 450 = 900 MHz
* PLL1_VCO = (24,000,000 / 6) * 240 = 960 MHz
*
* PLL1P = PLL1_VCO/2 = 900 MHz / 2 = 450 MHz
* PLL1Q = PLL1_VCO/9 = 900 MHz / 9 = 100 MHz **used for ETH REF CLK via MCO1/2**
* PLL1R = PLL1_VCO/8 = 900 MHz / 8 = 112.5 MHz
* PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 480 MHz
* PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 240 MHz
* PLL1R = PLL1_VCO/8 = 960 MHz / 8 = 120 MHz
*/
#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
@@ -110,15 +110,15 @@
RCC_PLLCFGR_DIVP1EN | \
RCC_PLLCFGR_DIVQ1EN | \
RCC_PLLCFGR_DIVR1EN)
#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(12)
#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(450)
#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(6)
#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(240)
#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2)
#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(9)
#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4)
#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8)
#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 12) * 450)
#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 6) * 240)
#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 9)
#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8)
/* PLL2 */