From 450f1d33f65045d54bff34921377a8248872b194 Mon Sep 17 00:00:00 2001 From: Niklas Hauser Date: Mon, 11 Aug 2025 17:52:27 +0200 Subject: [PATCH] [board] Increase CPU speed to 480MHz for FMUv6s The Ethernet clock output is not used anymore so there are no restrictions on the clock tree configuration. This aligns the clock speeds with FMUv6x. --- .../fmu-v6s/nuttx-config/include/board.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/boards/auterion/fmu-v6s/nuttx-config/include/board.h b/boards/auterion/fmu-v6s/nuttx-config/include/board.h index 0bb284be5c..4ef32275c4 100644 --- a/boards/auterion/fmu-v6s/nuttx-config/include/board.h +++ b/boards/auterion/fmu-v6s/nuttx-config/include/board.h @@ -98,11 +98,11 @@ /* PLL1, wide 2 - 4 MHz input, enable DIVP, DIVQ, DIVR * - * PLL1_VCO = (24,000,000 / 12) * 450 = 900 MHz + * PLL1_VCO = (24,000,000 / 6) * 240 = 960 MHz * - * PLL1P = PLL1_VCO/2 = 900 MHz / 2 = 450 MHz - * PLL1Q = PLL1_VCO/9 = 900 MHz / 9 = 100 MHz **used for ETH REF CLK via MCO1/2** - * PLL1R = PLL1_VCO/8 = 900 MHz / 8 = 112.5 MHz + * PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 480 MHz + * PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 240 MHz + * PLL1R = PLL1_VCO/8 = 960 MHz / 8 = 120 MHz */ #define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \ @@ -110,15 +110,15 @@ RCC_PLLCFGR_DIVP1EN | \ RCC_PLLCFGR_DIVQ1EN | \ RCC_PLLCFGR_DIVR1EN) -#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(12) -#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(450) +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(6) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(240) #define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) -#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(9) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) #define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) -#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 12) * 450) +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 6) * 240) #define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) -#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 9) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) #define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) /* PLL2 */