mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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imxrt_flexspi_nor_octal->imxrt_flexspi_nor
This commit is contained in:
David Sidrane
@@ -1,150 +0,0 @@
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/****************************************************************************
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* boards/arm/imxrt/imxrt1170-evk/scripts/flash.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Specify the memory areas */
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MEMORY
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{
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flash (rx) : ORIGIN = 0x30000000, LENGTH = 16M
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sram (rwx) : ORIGIN = 0x20240000 + 32K, LENGTH = 1024K - 32K /* OCRAM1 + OCRAM2*/
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itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 0K /* TODO FlexRAM partition */
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dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 0K
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}
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OUTPUT_ARCH(arm)
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EXTERN(_vectors)
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EXTERN(g_flash_config)
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EXTERN(g_image_vector_table)
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EXTERN(g_boot_data)
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ENTRY(_stext)
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SECTIONS
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{
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/* Image Vector Table and Boot Data for booting from external flash */
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.boot_hdr : ALIGN(4)
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{
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FILL(0xff)
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. = 0x400 ;
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__boot_hdr_start__ = ABSOLUTE(.) ;
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KEEP(*(.boot_hdr.conf))
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. = 0x1000 ;
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KEEP(*(.boot_hdr.ivt))
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. = 0x1020 ;
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KEEP(*(.boot_hdr.boot_data))
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. = 0x1030 ;
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KEEP(*(.boot_hdr.dcd_data))
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__boot_hdr_end__ = ABSOLUTE(.) ;
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. = 0x2000 ;
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} >flash
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/* The RAM vector table (if present) should lie at the beginning of SRAM */
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.ram_vectors (COPY) : {
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*(.ram_vectors)
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} > dtcm
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.text : ALIGN(4)
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{
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_stext = ABSOLUTE(.);
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*(.vectors)
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > flash
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.init_section :
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{
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_sinit = ABSOLUTE(.);
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*(.init_array .init_array.*)
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_einit = ABSOLUTE(.);
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} > flash
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.ARM.extab :
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{
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*(.ARM.extab*)
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} > flash
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.ARM.exidx :
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{
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__exidx_start = ABSOLUTE(.);
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*(.ARM.exidx*)
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__exidx_end = ABSOLUTE(.);
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} > flash
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_eronly = ABSOLUTE(.);
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.data :
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{
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > sram AT > flash
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.ramfunc ALIGN(4):
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{
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_sramfuncs = ABSOLUTE(.);
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*(.ramfunc .ramfunc.*)
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_eramfuncs = ABSOLUTE(.);
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} > sram AT > flash
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_framfuncs = LOADADDR(.ramfunc);
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.bss :
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{
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = ABSOLUTE(.);
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} > sram
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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_boot_loadaddr = ORIGIN(flash);
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_boot_size = LENGTH(flash);
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_ram_size = LENGTH(sram);
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}
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@@ -22,7 +22,7 @@
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MEMORY
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{
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flash (rx) : ORIGIN = 0x30000000, LENGTH = 16M
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flash (rx) : ORIGIN = 0x30000000, LENGTH = 3M /* We have 64M but we do not want to wait to program it all */
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sram (rwx) : ORIGIN = 0x20240000 + 0xBFFF, LENGTH = 1024K - 0xBFFF /* OCRAM1 + OCRAM2*/
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itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 256K /* TODO FlexRAM partition */
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dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
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@@ -42,8 +42,8 @@ const struct ivt_s g_image_vector_table = {
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locate_data(".boot_hdr.boot_data")
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const struct boot_data_s g_boot_data = {
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BOOT_IMAGE_BASE, /* boot start location */
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BOOT_IMAGE_SIZE, /* size */
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IMAGE_DEST, /* boot start location */
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(IMAGE_DEST_END - IMAGE_DEST), /* size */
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PLUGIN_FLAG, /* Plugin flag */
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0xffffffff /* empty - extra data word */
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};
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@@ -58,8 +58,8 @@
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#define DCD_VERSION (0x40)
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#define DCD_ARRAY_SIZE 1
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#define BOOT_IMAGE_BASE 0x30000000
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#define BOOT_IMAGE_SIZE ((uint32_t)_boot_size)
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#define FLASH_BASE 0x30000000
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#define FLASH_END FLASH_BASE + (3 * (1024*1024)) // We have 64M but we do not want to wait to program it all
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/* This needs to take into account the memory configuration at boot bootloader */
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@@ -70,7 +70,7 @@
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#define SCLK 1
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#if defined(CONFIG_BOOT_RUNFROMFLASH)
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# define IMAGE_DEST BOOT_IMAGE_BASE
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# define IMAGE_DEST FLASH_BASE
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# define IMAGE_DEST_END FLASH_END
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# define IMAGE_DEST_OFFSET 0
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#else
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@@ -79,8 +79,8 @@
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# define IMAGE_DEST_OFFSET IVT_SIZE
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#endif
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#define LOCATE_IN_DEST(x) (((uint32_t)(x)) - BOOT_IMAGE_BASE + IMAGE_DEST)
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#define LOCATE_IN_SRC(x) (((uint32_t)(x)) - IMAGE_DEST + BOOT_IMAGE_BASE)
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#define LOCATE_IN_DEST(x) (((uint32_t)(x)) - FLASH_BASE + IMAGE_DEST)
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#define LOCATE_IN_SRC(x) (((uint32_t)(x)) - IMAGE_DEST + FLASH_BASE)
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#define DCD_ADDRESS 0
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#define BOOT_DATA_ADDRESS LOCATE_IN_DEST(&g_boot_data)
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@@ -154,7 +154,5 @@ struct boot_data_s {
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extern const struct boot_data_s g_boot_data;
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extern const uint8_t g_dcd_data[];
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extern const uint32_t _vectors[];
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extern const uint32_t _boot_loadaddr[];
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extern const uint32_t _boot_size[];
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#endif /* __BOARDS_ARM_IMXRT_IMXRT1170_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */
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@@ -28,57 +28,83 @@
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* Public Data
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****************************************************************************/
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locate_data(".boot_hdr.conf")
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const struct flexspi_nor_config_s g_flash_config = {
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.mem_config =
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD,
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.cs_hold_time = 3u,
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.cs_setup_time = 3u,
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/* Enable DDR mode, Wordaddassable, Safe configuration, Differential clock */
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.controller_misc_option = 0x10,
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.device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
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.sflash_pad_type = SERIAL_FLASH_4PADS,
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.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz,
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.sflash_a1size = 16u * 1024u * 1024u,
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.lookup_table =
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
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.csHoldTime = 3,
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.csSetupTime = 3,
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.deviceModeCfgEnable = 1,
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.deviceModeType = kDeviceConfigCmdType_Spi2Xpi,
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.waitTimeCfgCommands = 1,
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.deviceModeSeq =
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{
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/* LUTs */
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// Read LUTs
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[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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.seqNum = 1,
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.seqId = 6, /* See Lookup table for more details */
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.reserved = 0,
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},
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.deviceModeArg = 2, /* Enable OPI DDR mode */
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.controllerMiscOption =
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(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DdrModeEnable),
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_8Pads,
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.serialClkFreq = kFlexSpiSerialClk_133MHz,
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.sflashA1Size = 64ul * 1024u * 1024u,
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.dataValidTime =
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{
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[0] = {.time_100ps = 0},
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},
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.busyOffset = 0u,
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.busyBitPolarity = 0u,
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.lookupTable =
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{
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/* Read */// EEH+11H+32bit addr+20dummy cycles+ 4Bytes read data //133Mhz 20 dummy=10+10
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[0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), //0x871187ee,
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[0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x0a),//0xb30a8b20,
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[0 + 2] = FLEXSPI_LUT_SEQ(DUMMY_DDR, FLEXSPI_8PAD, 0x0A, READ_DDR, FLEXSPI_8PAD, 0x04),//0xa704b30a,
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// Read Status LUTs
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[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
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/* Read Status SPI */// SPI 05h+ status data 0X24 maybe 0X04
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[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x24),//0x24040405,
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// Write Enable LUTs
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[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
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/* Read Status OPI *///05H+FAH+ 4byte 00H(addr)+4Byte read
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[4 * 2 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x05, CMD_DDR, FLEXSPI_8PAD, 0xFA),//0x87fa8705,
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[4 * 2 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x00, CMD_DDR, FLEXSPI_8PAD, 0x00),//0x87008700,
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[4 * 2 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x00, CMD_DDR, FLEXSPI_8PAD, 0x00),//0x87008700,
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[4 * 2 + 3] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00),//0x0000a704,
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// Erase Sector LUTs
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[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),
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/* Write enable SPI *///06h
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[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP_EXE, FLEXSPI_1PAD, 0x00),//0x00000406,
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// Erase Block LUTs
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[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
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/* Write enable OPI *///06h+F9H
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[4 * 4 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x06, CMD_DDR, FLEXSPI_8PAD, 0xF9),//0x87f98706,
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// Pape Program LUTs
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[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
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[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
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/* Erase sector */ //21H+DEH + 32bit address
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[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x21, CMD_DDR, FLEXSPI_8PAD, 0xDE),//0x87de8721,
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[4 * 5 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00),//0x00008b20,
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/*Write Configuration Register 2 =01, Enable OPI DDR mode*/ //72H +32bit address + CR20x00000000 = 0x01
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[4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00),//0x04000472,
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[4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00),//0x04000400,
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[4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01),//0x20010400,
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/*block erase*/ //DCH+23H+32bit address
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[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xDC, CMD_DDR, FLEXSPI_8PAD, 0x23),//0x872387dc,
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[4 * 8 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00), //0x00008b20,
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/*page program*/ //12H+EDH+32bit address+ write data 4bytes
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[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x12, CMD_DDR, FLEXSPI_8PAD, 0xED),//0x87ed8712,
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[4 * 9 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, WRITE_DDR, FLEXSPI_8PAD, 0x04), //0xa3048b20,
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/* Chip Erase (CE) Sequence *///60H+9FH
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[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x60, CMD_DDR, FLEXSPI_8PAD, 0x9F),//0x879f8760,
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// Erase Chip LUTs
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[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
|
||||
},
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||||
},
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.page_size = 256u,
|
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.sector_size = 4u * 1024u,
|
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.ipcmd_serial_clkfreq = 0x1,
|
||||
.blocksize = 64u * 1024u,
|
||||
.is_uniform_blocksize = false,
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.blockSize = 64u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
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||||
/****************************************************************************
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||||
* Public Functions
|
||||
****************************************************************************/
|
||||
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||||
@@ -32,316 +32,283 @@
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* Pre-processor Definitions
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||||
****************************************************************************/
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||||
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||||
/* FLEXSPI memory config block related definitions */
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||||
/*! @name Driver version */
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/*@{*/
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||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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||||
/*@}*/
|
||||
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||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346ul)
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#define FLEXSPI_CFG_BLK_VERSION (0x56010400ul)
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#define FLEXSPI_CFG_BLK_SIZE (512)
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/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
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/* FLEXSPI Feature related definitions */
|
||||
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||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
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||||
/* Lookup table related definitions */
|
||||
/* Lookup table related defintions */
|
||||
#define CMD_INDEX_READ 0
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||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
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||||
#define CMD_INDEX_READ 0
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||||
#define CMD_INDEX_READSTATUS 1
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||||
#define CMD_INDEX_WRITEENABLE 2
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||||
#define CMD_INDEX_WRITE 4
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||||
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||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
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||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
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||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0a
|
||||
#define LEARN_DDR 0x2a
|
||||
#define DATSZ_SDR 0x0b
|
||||
#define DATSZ_DDR 0x2b
|
||||
#define DUMMY_SDR 0x0c
|
||||
#define DUMMY_DDR 0x2c
|
||||
#define DUMMY_RWDS_SDR 0x0d
|
||||
#define DUMMY_RWDS_DDR 0x2d
|
||||
#define JMP_ON_CS 0x1f
|
||||
#define STOP 0
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP_EXE 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_OPERAND0_MASK (0xffu)
|
||||
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
|
||||
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t) \
|
||||
(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & \
|
||||
FLEXSPI_LUT_OPERAND0_MASK)
|
||||
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300u)
|
||||
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8u)
|
||||
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t) \
|
||||
(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & \
|
||||
FLEXSPI_LUT_NUM_PADS0_MASK)
|
||||
#define FLEXSPI_LUT_OPCODE0_MASK (0xfc00u)
|
||||
#define FLEXSPI_LUT_OPCODE0_SHIFT (10u)
|
||||
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t) \
|
||||
(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & \
|
||||
FLEXSPI_LUT_OPCODE0_MASK)
|
||||
#define FLEXSPI_LUT_OPERAND1_MASK (0xff0000u)
|
||||
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
|
||||
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t) \
|
||||
(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & \
|
||||
FLEXSPI_LUT_OPERAND1_MASK)
|
||||
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000u)
|
||||
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24u)
|
||||
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t) \
|
||||
(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & \
|
||||
FLEXSPI_LUT_NUM_PADS1_MASK)
|
||||
#define FLEXSPI_LUT_OPCODE1_MASK (0xfc000000u)
|
||||
#define FLEXSPI_LUT_OPCODE1_SHIFT (26u)
|
||||
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & \
|
||||
FLEXSPI_LUT_OPCODE1_MASK)
|
||||
/*! @name LUT - LUT 0..LUT 63 */
|
||||
/*! @{ */
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \
|
||||
FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
|
||||
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
|
||||
/*! OPERAND0 - OPERAND0
|
||||
*/
|
||||
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
|
||||
|
||||
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
|
||||
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
|
||||
/*! NUM_PADS0 - NUM_PADS0
|
||||
*/
|
||||
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
|
||||
|
||||
#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
|
||||
#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
|
||||
/*! OPCODE0 - OPCODE
|
||||
*/
|
||||
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
|
||||
|
||||
#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
|
||||
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
|
||||
/*! OPERAND1 - OPERAND1
|
||||
*/
|
||||
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
|
||||
|
||||
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
|
||||
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
|
||||
/*! NUM_PADS1 - NUM_PADS1
|
||||
*/
|
||||
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
|
||||
|
||||
#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
|
||||
#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
|
||||
/*! OPCODE1 - OPCODE1
|
||||
*/
|
||||
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
|
||||
/*! @} */
|
||||
|
||||
/* The count of FLEXSPI_LUT */
|
||||
#define FLEXSPI_LUT_COUNT (64U)
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
/* */
|
||||
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq {
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_80MHz = 4,
|
||||
kFlexSpiSerialClk_100MHz = 5,
|
||||
kFlexSpiSerialClk_120MHz = 6,
|
||||
kFlexSpiSerialClk_133MHz = 7,
|
||||
kFlexSpiSerialClk_166MHz = 8,
|
||||
kFlexSpiSerialClk_200MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5
|
||||
#define NOR_CMD_INDEX_DUMMY 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7
|
||||
|
||||
/* READ LUT sequence id in lookupTable stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
|
||||
|
||||
/* Read Status LUT sequence id in lookupTable stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
|
||||
|
||||
/* 2 Read status DPI/QPI/OPI sequence id in LUT stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2
|
||||
|
||||
/* 3 Write Enable sequence id in lookupTable stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
|
||||
|
||||
/* 4 Write Enable DPI/QPI/OPI sequence id in LUT stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
|
||||
|
||||
/* 5 Erase Sector sequence id in lookupTable stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
|
||||
|
||||
/* 8 Erase Block sequence id in lookupTable stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
|
||||
|
||||
/* 9 Program sequence id in lookupTable stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
|
||||
|
||||
/* 11 Chip Erase sequence in lookupTable id stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
|
||||
|
||||
/* 13 Read SFDP sequence in lookupTable id stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
|
||||
|
||||
/* 14 Restore 0-4-4/0-8-8 mode sequence id in LUT stored in config block */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
|
||||
|
||||
/* 15 Exit 0-4-4/0-8-8 mode sequence id in LUT stored in config blobk */
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* Definitions for FlexSPI Serial Clock Frequency */
|
||||
|
||||
enum flexspi_serial_clkfreq_e {
|
||||
FLEXSPI_SERIAL_CLKFREQ_30MHz = 1,
|
||||
FLEXSPI_SERIAL_CLKFREQ_50MHz = 2,
|
||||
FLEXSPI_SERIAL_CLKFREQ_60MHz = 3,
|
||||
FLEXSPI_SERIAL_CLKFREQ_75MHz = 4,
|
||||
FLEXSPI_SERIAL_CLKFREQ_80MHz = 5,
|
||||
FLEXSPI_SERIAL_CLKFREQ_100MHz = 6,
|
||||
FLEXSPI_SERIAL_CLKFREQ_133MHz = 7,
|
||||
FLEXSPI_SERIAL_CLKFREQ_166MHz = 8,
|
||||
FLEXSPI_SERIAL_CLKFREQ_200MHz = 9,
|
||||
//!@brief FlexSPI clock configuration type
|
||||
enum {
|
||||
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
/* FlexSPI clock configuration type */
|
||||
//!@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource {
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
enum flexspi_serial_clockmode_e {
|
||||
FLEXSPI_CLKMODE_SDR,
|
||||
FLEXSPI_CLKMODE_DDR,
|
||||
//!@brief Misc feature bit definitions
|
||||
enum {
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
/* FlexSPI Read Sample Clock Source definition */
|
||||
|
||||
enum flash_read_sample_clk_e {
|
||||
FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY = 0,
|
||||
FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD = 1,
|
||||
FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD = 2,
|
||||
FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD = 3,
|
||||
//!@brief Flash Type Definition
|
||||
enum {
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
/* Misc feature bit definitions */
|
||||
|
||||
enum flash_misc_feature_e {
|
||||
FLEXSPIMISC_OFFSET_DIFFCLKEN = 0, /* Bit for Differential clock enable */
|
||||
FLEXSPIMISC_OFFSET_CK2EN = 1, /* Bit for CK2 enable */
|
||||
FLEXSPIMISC_OFFSET_PARALLELEN = 2, /* Bit for Parallel mode enable */
|
||||
FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */
|
||||
FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */
|
||||
FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */
|
||||
FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */
|
||||
//!@brief Flash Pad Definitions
|
||||
enum {
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
/* Flash Type Definition */
|
||||
|
||||
enum flash_flash_type_e {
|
||||
FLEXSPI_DEVICE_TYPE_SERIAL_NOR = 1, /* Flash devices are Serial NOR */
|
||||
FLEXSPI_DEVICE_TYPE_SERIAL_NAND = 2, /* Flash devices are Serial NAND */
|
||||
FLEXSPI_DEVICE_TYPE_SERIAL_RAM = 3, /* Flash devices are Serial RAM/HyperFLASH */
|
||||
FLEXSPI_DEVICE_TYPE_MCP_NOR_NAND = 0x12, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */
|
||||
FLEXSPI_DEVICE_TYPE_MCP_NOR_RAM = 0x13, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */
|
||||
};
|
||||
|
||||
/* Flash Pad Definitions */
|
||||
|
||||
enum flash_flash_pad_e {
|
||||
SERIAL_FLASH_1PAD = 1,
|
||||
SERIAL_FLASH_2PADS = 2,
|
||||
SERIAL_FLASH_4PADS = 4,
|
||||
SERIAL_FLASH_8PADS = 8,
|
||||
};
|
||||
|
||||
/* Flash Configuration Command Type */
|
||||
|
||||
enum flash_config_cmd_e {
|
||||
DEVICE_CONFIG_CMD_TYPE_GENERIC, /* Generic command, for example: configure dummy cycles, drive strength, etc */
|
||||
DEVICE_CONFIG_CMD_TYPE_QUADENABLE, /* Quad Enable command */
|
||||
DEVICE_CONFIG_CMD_TYPE_SPI2XPI, /* Switch from SPI to DPI/QPI/OPI mode */
|
||||
DEVICE_CONFIG_CMD_TYPE_XPI2SPI, /* Switch from DPI/QPI/OPI to SPI mode */
|
||||
DEVICE_CONFIG_CMD_TYPE_SPI2NO_CMD, /* Switch to 0-4-4/0-8-8 mode */
|
||||
DEVICE_CONFIG_CMD_TYPE_RESET, /* Reset device command */
|
||||
};
|
||||
|
||||
/* FlexSPI LUT Sequence structure */
|
||||
|
||||
struct flexspi_lut_seq_s {
|
||||
uint8_t seq_num; /* Sequence Number, valid number: 1-16 */
|
||||
uint8_t seq_id; /* Sequence Index, valid number: 0-15 */
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence {
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum {
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
/* FlexSPI Memory Configuration Block */
|
||||
typedef struct {
|
||||
uint8_t time_100ps; /* Data valid time, in terms of 100ps */
|
||||
uint8_t delay_cells; /* Data valid time, in terms of delay cells */
|
||||
} flexspi_dll_time_t;
|
||||
|
||||
struct flexspi_mem_config_s {
|
||||
uint32_t tag;
|
||||
uint32_t version;
|
||||
uint32_t reserved0;
|
||||
uint8_t read_sample_clksrc;
|
||||
uint8_t cs_hold_time;
|
||||
uint8_t cs_setup_time;
|
||||
uint8_t column_address_width; /* [0x00f-0x00f] Column Address with, for
|
||||
* HyperBus protocol, it is fixed to 3,
|
||||
* For Serial NAND, need to refer to
|
||||
* datasheet
|
||||
*/
|
||||
uint8_t device_mode_cfg_enable;
|
||||
uint8_t device_mode_type;
|
||||
uint16_t wait_time_cfg_commands;
|
||||
struct flexspi_lut_seq_s device_mode_seq;
|
||||
uint32_t device_mode_arg;
|
||||
uint8_t config_cmd_enable;
|
||||
uint8_t config_mode_type[3];
|
||||
struct flexspi_lut_seq_s config_cmd_seqs[3];
|
||||
uint32_t reserved1;
|
||||
uint32_t config_cmd_args[3];
|
||||
uint32_t reserved2;
|
||||
uint32_t controller_misc_option;
|
||||
uint8_t device_type;
|
||||
uint8_t sflash_pad_type;
|
||||
uint8_t serial_clk_freq;
|
||||
uint8_t lut_custom_seq_enable;
|
||||
uint32_t reserved3[2];
|
||||
uint32_t sflash_a1size;
|
||||
uint32_t sflash_a2size;
|
||||
uint32_t sflash_b1size;
|
||||
uint32_t sflash_b2size;
|
||||
uint32_t cspad_setting_override;
|
||||
uint32_t sclkpad_setting_override;
|
||||
uint32_t datapad_setting_override;
|
||||
uint32_t dqspad_setting_override;
|
||||
uint32_t timeout_in_ms;
|
||||
uint32_t command_interval;
|
||||
uint16_t data_valid_time[2];
|
||||
uint16_t busy_offset;
|
||||
uint16_t busybit_polarity;
|
||||
uint32_t lookup_table[64];
|
||||
struct flexspi_lut_seq_s lut_customseq[12];
|
||||
uint32_t reserved4[4];
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
struct mem_config_s {
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t
|
||||
deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
flexspi_dll_time_t
|
||||
dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
};
|
||||
|
||||
/* Serial NOR configuration block */
|
||||
/* */
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
struct flexspi_nor_config_s {
|
||||
struct flexspi_mem_config_s mem_config; /* Common memory configuration info
|
||||
* via FlexSPI
|
||||
*/
|
||||
|
||||
uint32_t page_size; /* Page size of Serial NOR */
|
||||
uint32_t sector_size; /* Sector size of Serial NOR */
|
||||
uint8_t ipcmd_serial_clkfreq; /* Clock frequency for IP command */
|
||||
uint8_t is_uniform_blocksize; /* Sector/Block size is the same */
|
||||
uint8_t reserved0[2]; /* Reserved for future use */
|
||||
uint8_t serial_nor_type; /* Serial NOR Flash type: 0/1/2/3 */
|
||||
uint8_t need_exit_nocmdmode; /* Need to exit NoCmd mode before
|
||||
* other IP command
|
||||
*/
|
||||
|
||||
uint8_t halfclk_for_nonreadcmd; /* Half the Serial Clock for non-read
|
||||
* command: true/false
|
||||
*/
|
||||
|
||||
uint8_t need_restore_nocmdmode; /* Need to Restore NoCmd mode after IP
|
||||
* command execution
|
||||
*/
|
||||
|
||||
uint32_t blocksize; /* Block size */
|
||||
uint32_t reserve2[11]; /* Reserved for future use */
|
||||
struct mem_config_s memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t reserve2[11]; //!< Reserved for future use
|
||||
};
|
||||
|
||||
|
||||
#endif /* __BOARDS_ARM_IMXRT_IMXRT1170_EVK_SRC_IMXRT_FLEXSPI_NOR_FLASH_H */
|
||||
|
||||
Reference in New Issue
Block a user