diff --git a/boards/nxp/fmurt1170-v1/nuttx-config/scripts/flash.ld b/boards/nxp/fmurt1170-v1/nuttx-config/scripts/flash.ld deleted file mode 100644 index 599e22f335..0000000000 --- a/boards/nxp/fmurt1170-v1/nuttx-config/scripts/flash.ld +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/imxrt/imxrt1170-evk/scripts/flash.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Specify the memory areas */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x30000000, LENGTH = 16M - sram (rwx) : ORIGIN = 0x20240000 + 32K, LENGTH = 1024K - 32K /* OCRAM1 + OCRAM2*/ - itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 0K /* TODO FlexRAM partition */ - dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 0K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -EXTERN(g_flash_config) -EXTERN(g_image_vector_table) -EXTERN(g_boot_data) - -ENTRY(_stext) - -SECTIONS -{ - /* Image Vector Table and Boot Data for booting from external flash */ - - .boot_hdr : ALIGN(4) - { - FILL(0xff) - . = 0x400 ; - __boot_hdr_start__ = ABSOLUTE(.) ; - KEEP(*(.boot_hdr.conf)) - . = 0x1000 ; - KEEP(*(.boot_hdr.ivt)) - . = 0x1020 ; - KEEP(*(.boot_hdr.boot_data)) - . = 0x1030 ; - KEEP(*(.boot_hdr.dcd_data)) - __boot_hdr_end__ = ABSOLUTE(.) ; - . = 0x2000 ; - } >flash - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors (COPY) : { - *(.ram_vectors) - } > dtcm - - .text : ALIGN(4) - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : - { - _sinit = ABSOLUTE(.); - *(.init_array .init_array.*) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : - { - *(.ARM.extab*) - } > flash - - .ARM.exidx : - { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .ramfunc ALIGN(4): - { - _sramfuncs = ABSOLUTE(.); - *(.ramfunc .ramfunc.*) - _eramfuncs = ABSOLUTE(.); - } > sram AT > flash - - _framfuncs = LOADADDR(.ramfunc); - - .bss : - { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } - - _boot_loadaddr = ORIGIN(flash); - _boot_size = LENGTH(flash); - _ram_size = LENGTH(sram); -} diff --git a/boards/nxp/fmurt1170-v1/nuttx-config/scripts/script.ld b/boards/nxp/fmurt1170-v1/nuttx-config/scripts/script.ld index fd73f80263..751c3dc3ef 100644 --- a/boards/nxp/fmurt1170-v1/nuttx-config/scripts/script.ld +++ b/boards/nxp/fmurt1170-v1/nuttx-config/scripts/script.ld @@ -22,7 +22,7 @@ MEMORY { - flash (rx) : ORIGIN = 0x30000000, LENGTH = 16M + flash (rx) : ORIGIN = 0x30000000, LENGTH = 3M /* We have 64M but we do not want to wait to program it all */ sram (rwx) : ORIGIN = 0x20240000 + 0xBFFF, LENGTH = 1024K - 0xBFFF /* OCRAM1 + OCRAM2*/ itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 256K /* TODO FlexRAM partition */ dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K diff --git a/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_boot.c b/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_boot.c index 9deee5a087..a8fb87d61f 100644 --- a/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_boot.c +++ b/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_boot.c @@ -42,8 +42,8 @@ const struct ivt_s g_image_vector_table = { locate_data(".boot_hdr.boot_data") const struct boot_data_s g_boot_data = { - BOOT_IMAGE_BASE, /* boot start location */ - BOOT_IMAGE_SIZE, /* size */ + IMAGE_DEST, /* boot start location */ + (IMAGE_DEST_END - IMAGE_DEST), /* size */ PLUGIN_FLAG, /* Plugin flag */ 0xffffffff /* empty - extra data word */ }; \ No newline at end of file diff --git a/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_boot.h b/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_boot.h index 0e3d22f4a0..f8358a5571 100644 --- a/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_boot.h +++ b/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_boot.h @@ -58,8 +58,8 @@ #define DCD_VERSION (0x40) #define DCD_ARRAY_SIZE 1 -#define BOOT_IMAGE_BASE 0x30000000 -#define BOOT_IMAGE_SIZE ((uint32_t)_boot_size) +#define FLASH_BASE 0x30000000 +#define FLASH_END FLASH_BASE + (3 * (1024*1024)) // We have 64M but we do not want to wait to program it all /* This needs to take into account the memory configuration at boot bootloader */ @@ -70,7 +70,7 @@ #define SCLK 1 #if defined(CONFIG_BOOT_RUNFROMFLASH) -# define IMAGE_DEST BOOT_IMAGE_BASE +# define IMAGE_DEST FLASH_BASE # define IMAGE_DEST_END FLASH_END # define IMAGE_DEST_OFFSET 0 #else @@ -79,8 +79,8 @@ # define IMAGE_DEST_OFFSET IVT_SIZE #endif -#define LOCATE_IN_DEST(x) (((uint32_t)(x)) - BOOT_IMAGE_BASE + IMAGE_DEST) -#define LOCATE_IN_SRC(x) (((uint32_t)(x)) - IMAGE_DEST + BOOT_IMAGE_BASE) +#define LOCATE_IN_DEST(x) (((uint32_t)(x)) - FLASH_BASE + IMAGE_DEST) +#define LOCATE_IN_SRC(x) (((uint32_t)(x)) - IMAGE_DEST + FLASH_BASE) #define DCD_ADDRESS 0 #define BOOT_DATA_ADDRESS LOCATE_IN_DEST(&g_boot_data) @@ -154,7 +154,5 @@ struct boot_data_s { extern const struct boot_data_s g_boot_data; extern const uint8_t g_dcd_data[]; extern const uint32_t _vectors[]; -extern const uint32_t _boot_loadaddr[]; -extern const uint32_t _boot_size[]; #endif /* __BOARDS_ARM_IMXRT_IMXRT1170_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */ diff --git a/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_flash.c b/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_flash.c index 355f58785e..c8c9376dfc 100644 --- a/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_flash.c +++ b/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_flash.c @@ -28,57 +28,83 @@ * Public Data ****************************************************************************/ - locate_data(".boot_hdr.conf") const struct flexspi_nor_config_s g_flash_config = { - .mem_config = + .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD, - .cs_hold_time = 3u, - .cs_setup_time = 3u, - /* Enable DDR mode, Wordaddassable, Safe configuration, Differential clock */ - .controller_misc_option = 0x10, - .device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR, - .sflash_pad_type = SERIAL_FLASH_4PADS, - .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz, - .sflash_a1size = 16u * 1024u * 1024u, - .lookup_table = + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3, + .csSetupTime = 3, + .deviceModeCfgEnable = 1, + .deviceModeType = kDeviceConfigCmdType_Spi2Xpi, + .waitTimeCfgCommands = 1, + .deviceModeSeq = { - /* LUTs */ - // Read LUTs - [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + .seqNum = 1, + .seqId = 6, /* See Lookup table for more details */ + .reserved = 0, + }, + .deviceModeArg = 2, /* Enable OPI DDR mode */ + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DdrModeEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64ul * 1024u * 1024u, + .dataValidTime = + { + [0] = {.time_100ps = 0}, + }, + .busyOffset = 0u, + .busyBitPolarity = 0u, + .lookupTable = + { + /* Read */// EEH+11H+32bit addr+20dummy cycles+ 4Bytes read data //133Mhz 20 dummy=10+10 + [0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), //0x871187ee, + [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x0a),//0xb30a8b20, + [0 + 2] = FLEXSPI_LUT_SEQ(DUMMY_DDR, FLEXSPI_8PAD, 0x0A, READ_DDR, FLEXSPI_8PAD, 0x04),//0xa704b30a, - // Read Status LUTs - [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + /* Read Status SPI */// SPI 05h+ status data 0X24 maybe 0X04 + [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x24),//0x24040405, - // Write Enable LUTs - [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0), + /* Read Status OPI *///05H+FAH+ 4byte 00H(addr)+4Byte read + [4 * 2 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x05, CMD_DDR, FLEXSPI_8PAD, 0xFA),//0x87fa8705, + [4 * 2 + 1] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x00, CMD_DDR, FLEXSPI_8PAD, 0x00),//0x87008700, + [4 * 2 + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x00, CMD_DDR, FLEXSPI_8PAD, 0x00),//0x87008700, + [4 * 2 + 3] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00),//0x0000a704, - // Erase Sector LUTs - [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + /* Write enable SPI *///06h + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP_EXE, FLEXSPI_1PAD, 0x00),//0x00000406, - // Erase Block LUTs - [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + /* Write enable OPI *///06h+F9H + [4 * 4 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x06, CMD_DDR, FLEXSPI_8PAD, 0xF9),//0x87f98706, - // Pape Program LUTs - [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), - [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + /* Erase sector */ //21H+DEH + 32bit address + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x21, CMD_DDR, FLEXSPI_8PAD, 0xDE),//0x87de8721, + [4 * 5 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00),//0x00008b20, + + /*Write Configuration Register 2 =01, Enable OPI DDR mode*/ //72H +32bit address + CR20x00000000 = 0x01 + [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00),//0x04000472, + [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00),//0x04000400, + [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01),//0x20010400, + + /*block erase*/ //DCH+23H+32bit address + [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xDC, CMD_DDR, FLEXSPI_8PAD, 0x23),//0x872387dc, + [4 * 8 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00), //0x00008b20, + + /*page program*/ //12H+EDH+32bit address+ write data 4bytes + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x12, CMD_DDR, FLEXSPI_8PAD, 0xED),//0x87ed8712, + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, WRITE_DDR, FLEXSPI_8PAD, 0x04), //0xa3048b20, + + /* Chip Erase (CE) Sequence *///60H+9FH + [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x60, CMD_DDR, FLEXSPI_8PAD, 0x9F),//0x879f8760, - // Erase Chip LUTs - [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0), }, }, - - .page_size = 256u, - .sector_size = 4u * 1024u, - .ipcmd_serial_clkfreq = 0x1, - .blocksize = 64u * 1024u, - .is_uniform_blocksize = false, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, }; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_flash.h b/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_flash.h index c5ffdb4c29..391d5d81b8 100644 --- a/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_flash.h +++ b/boards/nxp/fmurt1170-v1/src/imxrt_flexspi_nor_flash.h @@ -32,316 +32,283 @@ * Pre-processor Definitions ****************************************************************************/ -/* FLEXSPI memory config block related definitions */ +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ -#define FLEXSPI_CFG_BLK_TAG (0x42464346ul) -#define FLEXSPI_CFG_BLK_VERSION (0x56010400ul) -#define FLEXSPI_CFG_BLK_SIZE (512) +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) /* FLEXSPI Feature related definitions */ - #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 -/* Lookup table related definitions */ +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 +#define CMD_LUT_SEQ_IDX_WRITE 9 -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0a -#define LEARN_DDR 0x2a -#define DATSZ_SDR 0x0b -#define DATSZ_DDR 0x2b -#define DUMMY_SDR 0x0c -#define DUMMY_DDR 0x2c -#define DUMMY_RWDS_SDR 0x0d -#define DUMMY_RWDS_DDR 0x2d -#define JMP_ON_CS 0x1f -#define STOP 0 +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP_EXE 0 -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 -#define FLEXSPI_LUT_OPERAND0_MASK (0xffu) -#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) -#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t) \ - (((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & \ - FLEXSPI_LUT_OPERAND0_MASK) -#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300u) -#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8u) -#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t) \ - (((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & \ - FLEXSPI_LUT_NUM_PADS0_MASK) -#define FLEXSPI_LUT_OPCODE0_MASK (0xfc00u) -#define FLEXSPI_LUT_OPCODE0_SHIFT (10u) -#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t) \ - (((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & \ - FLEXSPI_LUT_OPCODE0_MASK) -#define FLEXSPI_LUT_OPERAND1_MASK (0xff0000u) -#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) -#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t) \ - (((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & \ - FLEXSPI_LUT_OPERAND1_MASK) -#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000u) -#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24u) -#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t) \ - (((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & \ - FLEXSPI_LUT_NUM_PADS1_MASK) -#define FLEXSPI_LUT_OPCODE1_MASK (0xfc000000u) -#define FLEXSPI_LUT_OPCODE1_SHIFT (26u) -#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & \ - FLEXSPI_LUT_OPCODE1_MASK) +/*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ - FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +/*! OPERAND0 - OPERAND0 + */ +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) + +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +/*! NUM_PADS0 - NUM_PADS0 + */ +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) + +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +/*! OPCODE0 - OPCODE + */ +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) + +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +/*! OPERAND1 - OPERAND1 + */ +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) + +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +/*! NUM_PADS1 - NUM_PADS1 + */ +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) + +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +/*! OPCODE1 - OPCODE1 + */ +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (64U) + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) -/* */ +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; -#define NOR_CMD_INDEX_READ CMD_INDEX_READ -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE -#define NOR_CMD_INDEX_ERASESECTOR 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE -#define NOR_CMD_INDEX_CHIPERASE 5 -#define NOR_CMD_INDEX_DUMMY 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 - -/* READ LUT sequence id in lookupTable stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ - -/* Read Status LUT sequence id in lookupTable stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS - -/* 2 Read status DPI/QPI/OPI sequence id in LUT stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 - -/* 3 Write Enable sequence id in lookupTable stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE - -/* 4 Write Enable DPI/QPI/OPI sequence id in LUT stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 - -/* 5 Erase Sector sequence id in lookupTable stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 - -/* 8 Erase Block sequence id in lookupTable stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 - -/* 9 Program sequence id in lookupTable stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE - -/* 11 Chip Erase sequence in lookupTable id stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 - -/* 13 Read SFDP sequence in lookupTable id stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 - -/* 14 Restore 0-4-4/0-8-8 mode sequence id in LUT stored in config block */ - -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 - -/* 15 Exit 0-4-4/0-8-8 mode sequence id in LUT stored in config blobk */ - -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Definitions for FlexSPI Serial Clock Frequency */ - -enum flexspi_serial_clkfreq_e { - FLEXSPI_SERIAL_CLKFREQ_30MHz = 1, - FLEXSPI_SERIAL_CLKFREQ_50MHz = 2, - FLEXSPI_SERIAL_CLKFREQ_60MHz = 3, - FLEXSPI_SERIAL_CLKFREQ_75MHz = 4, - FLEXSPI_SERIAL_CLKFREQ_80MHz = 5, - FLEXSPI_SERIAL_CLKFREQ_100MHz = 6, - FLEXSPI_SERIAL_CLKFREQ_133MHz = 7, - FLEXSPI_SERIAL_CLKFREQ_166MHz = 8, - FLEXSPI_SERIAL_CLKFREQ_200MHz = 9, +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode }; -/* FlexSPI clock configuration type */ +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; -enum flexspi_serial_clockmode_e { - FLEXSPI_CLKMODE_SDR, - FLEXSPI_CLKMODE_DDR, +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. }; -/* FlexSPI Read Sample Clock Source definition */ - -enum flash_read_sample_clk_e { - FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY = 0, - FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD = 1, - FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD = 2, - FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD = 3, +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs }; -/* Misc feature bit definitions */ - -enum flash_misc_feature_e { - FLEXSPIMISC_OFFSET_DIFFCLKEN = 0, /* Bit for Differential clock enable */ - FLEXSPIMISC_OFFSET_CK2EN = 1, /* Bit for CK2 enable */ - FLEXSPIMISC_OFFSET_PARALLELEN = 2, /* Bit for Parallel mode enable */ - FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */ - FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */ - FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */ - FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */ +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, }; -/* Flash Type Definition */ - -enum flash_flash_type_e { - FLEXSPI_DEVICE_TYPE_SERIAL_NOR = 1, /* Flash devices are Serial NOR */ - FLEXSPI_DEVICE_TYPE_SERIAL_NAND = 2, /* Flash devices are Serial NAND */ - FLEXSPI_DEVICE_TYPE_SERIAL_RAM = 3, /* Flash devices are Serial RAM/HyperFLASH */ - FLEXSPI_DEVICE_TYPE_MCP_NOR_NAND = 0x12, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ - FLEXSPI_DEVICE_TYPE_MCP_NOR_RAM = 0x13, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ -}; - -/* Flash Pad Definitions */ - -enum flash_flash_pad_e { - SERIAL_FLASH_1PAD = 1, - SERIAL_FLASH_2PADS = 2, - SERIAL_FLASH_4PADS = 4, - SERIAL_FLASH_8PADS = 8, -}; - -/* Flash Configuration Command Type */ - -enum flash_config_cmd_e { - DEVICE_CONFIG_CMD_TYPE_GENERIC, /* Generic command, for example: configure dummy cycles, drive strength, etc */ - DEVICE_CONFIG_CMD_TYPE_QUADENABLE, /* Quad Enable command */ - DEVICE_CONFIG_CMD_TYPE_SPI2XPI, /* Switch from SPI to DPI/QPI/OPI mode */ - DEVICE_CONFIG_CMD_TYPE_XPI2SPI, /* Switch from DPI/QPI/OPI to SPI mode */ - DEVICE_CONFIG_CMD_TYPE_SPI2NO_CMD, /* Switch to 0-4-4/0-8-8 mode */ - DEVICE_CONFIG_CMD_TYPE_RESET, /* Reset device command */ -}; - -/* FlexSPI LUT Sequence structure */ - -struct flexspi_lut_seq_s { - uint8_t seq_num; /* Sequence Number, valid number: 1-16 */ - uint8_t seq_id; /* Sequence Index, valid number: 0-15 */ +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command }; -/* FlexSPI Memory Configuration Block */ +typedef struct { + uint8_t time_100ps; /* Data valid time, in terms of 100ps */ + uint8_t delay_cells; /* Data valid time, in terms of delay cells */ +} flexspi_dll_time_t; -struct flexspi_mem_config_s { - uint32_t tag; - uint32_t version; - uint32_t reserved0; - uint8_t read_sample_clksrc; - uint8_t cs_hold_time; - uint8_t cs_setup_time; - uint8_t column_address_width; /* [0x00f-0x00f] Column Address with, for - * HyperBus protocol, it is fixed to 3, - * For Serial NAND, need to refer to - * datasheet - */ - uint8_t device_mode_cfg_enable; - uint8_t device_mode_type; - uint16_t wait_time_cfg_commands; - struct flexspi_lut_seq_s device_mode_seq; - uint32_t device_mode_arg; - uint8_t config_cmd_enable; - uint8_t config_mode_type[3]; - struct flexspi_lut_seq_s config_cmd_seqs[3]; - uint32_t reserved1; - uint32_t config_cmd_args[3]; - uint32_t reserved2; - uint32_t controller_misc_option; - uint8_t device_type; - uint8_t sflash_pad_type; - uint8_t serial_clk_freq; - uint8_t lut_custom_seq_enable; - uint32_t reserved3[2]; - uint32_t sflash_a1size; - uint32_t sflash_a2size; - uint32_t sflash_b1size; - uint32_t sflash_b2size; - uint32_t cspad_setting_override; - uint32_t sclkpad_setting_override; - uint32_t datapad_setting_override; - uint32_t dqspad_setting_override; - uint32_t timeout_in_ms; - uint32_t command_interval; - uint16_t data_valid_time[2]; - uint16_t busy_offset; - uint16_t busybit_polarity; - uint32_t lookup_table[64]; - struct flexspi_lut_seq_s lut_customseq[12]; - uint32_t reserved4[4]; +//!@brief FlexSPI Memory Configuration Block +struct mem_config_s { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t + deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + flexspi_dll_time_t + dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use }; -/* Serial NOR configuration block */ +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ struct flexspi_nor_config_s { - struct flexspi_mem_config_s mem_config; /* Common memory configuration info - * via FlexSPI - */ - - uint32_t page_size; /* Page size of Serial NOR */ - uint32_t sector_size; /* Sector size of Serial NOR */ - uint8_t ipcmd_serial_clkfreq; /* Clock frequency for IP command */ - uint8_t is_uniform_blocksize; /* Sector/Block size is the same */ - uint8_t reserved0[2]; /* Reserved for future use */ - uint8_t serial_nor_type; /* Serial NOR Flash type: 0/1/2/3 */ - uint8_t need_exit_nocmdmode; /* Need to exit NoCmd mode before - * other IP command - */ - - uint8_t halfclk_for_nonreadcmd; /* Half the Serial Clock for non-read - * command: true/false - */ - - uint8_t need_restore_nocmdmode; /* Need to Restore NoCmd mode after IP - * command execution - */ - - uint32_t blocksize; /* Block size */ - uint32_t reserve2[11]; /* Reserved for future use */ + struct mem_config_s memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use }; + #endif /* __BOARDS_ARM_IMXRT_IMXRT1170_EVK_SRC_IMXRT_FLEXSPI_NOR_FLASH_H */