WIP: device tree MVP

dts/bindings/timer/arm,armv8-timer.yaml

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+description: per-core ARM architected timer
+
+compatible: "arm,armv8-timer"
+
+include: base.yaml
+
+properties:
+    interrupts:
+      required: true
+
+    label:
+      required: true

dts/bindings/timer/arm,cmsdk-dtimer.yaml

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+description: ARM CMSDK dual timer
+
+compatible: "arm,cmsdk-dtimer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true

dts/bindings/timer/arm,cmsdk-timer.yaml

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+description: ARM CMSDK timer
+
+compatible: "arm,cmsdk-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true

dts/bindings/timer/atmel,sam-tc.yaml

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+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Timer Counter (TC) node
+
+compatible: "atmel,sam-tc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    peripheral-id:
+      type: array
+      description: peripheral ID
+      required: true
+
+    channel:
+      type: int
+      required: false
+      description: |
+        Timer / Counter channel to use, channel 0 is the default.
+        Valid range: 0 - 2
+
+    clk:
+      type: int
+      required: false
+      description: |
+        Clock source selection as defined by TCCLKS bit-field of TC_CMR
+        register. Consult the datasheet for the details.
+
+    nodivclk:
+      type: boolean
+      required: false
+      description: |
+        If set to true the `clk` property is ignored. Instead the TC module is
+        driven directly via MCLK. Only supported on sam4e, same70, same70b,
+        samv71, samv71b SoC series.
+
+    reg-cmr:
+      type: int
+      required: false
+      description: |
+        Alternate value of the CMR (Channel Mode Register) register.
+        If specified this value will be written to the register during driver
+        instance initialization instead of the default. It can be used to
+        configure the timer / counter in the custom mode. Together with other
+        properties like channel-num, pinctrl-0 this allows e.g. to configure
+        the driver to count events generated on the TIOA, TIOB signal connected
+        to the external pin.
+
+    pinctrl-0:
+      type: phandles
+      required: false
+      description: |
+        PIO pin configuration for Timer Counter signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the TC0 on SAME7x would be
+           pinctrl-0 = <&pa0b_tc0_tioa0 &pa1b_tc0_tiob0>;

dts/bindings/timer/atmel,sam0-tc32.yaml

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+# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 basic timer counter (TC) operating in 32-bit wide mode
+
+compatible: "atmel,sam0-tc32"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clocks:
+    required: true
+
+  clock-names:
+    required: true
+
+  label:
+    required: true
+
+  prescaler:
+    type: int
+    required: false
+    description: Timer prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 64
+      - 256
+      - 1024

dts/bindings/timer/espressif,esp32-systimer.yaml

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+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Espressif ESP32 Systimer peripheral
+
+compatible: "espressif,esp32-systimer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true

dts/bindings/timer/gaisler,gptimer.yaml

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+description: GRLIB GPTIMER
+
+compatible: "gaisler,gptimer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true

dts/bindings/timer/intel,hpet.yaml

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+# Copyright (c) 2019 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: HPET (High-Precision Event Timer)
+
+compatible: "intel,hpet"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true

dts/bindings/timer/ite,it8xxx2-timer.yaml

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+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE Ext-timer
+
+compatible: "ite,it8xxx2-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true

dts/bindings/timer/litex,timer0.yaml

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+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX timer
+
+compatible: "litex,timer0"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true

dts/bindings/timer/microchip,xec-rtos-timer.yaml

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+# Copyright (c) 2019 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC RTOS timer
+
+compatible: "microchip,xec-rtos-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    girqs:
+      type: array
+      required: true
+      description: Array of GIRQ numbers [8:26] and bit positions [0:31].
+
+    "#girq-cells":
+      type: int
+      const: 2
+
+girq-cells:
+    - girq_num
+    - bitpos

dts/bindings/timer/nordic,nrf-timer.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF timer node
+
+compatible: "nordic,nrf-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    cc-num:
+      type: int
+      required: true
+      description: Number of capture/compare (CC) registers available
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    prescaler:
+      type: int
+      required: true
+      description: Prescaler value determines frequency (16MHz/2^prescaler)

dts/bindings/timer/nuvoton,npcx-itim-timer.yaml

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+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Internal Timer (ITIM) node
+
+compatible: "nuvoton,npcx-itim-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
+
+    interrupts:
+        required: true
+
+    label:
+        required: true

dts/bindings/timer/nxp,imx-gpt.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUX General-Purpose Timer (GPT)
+
+compatible: "nxp,imx-gpt"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    gptfreq:
+      type: int
+      required: true
+      description: gpt frequences

dts/bindings/timer/nxp,lpc-ctimer.yaml

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+# Copyright (c) 2021 Toby Firth
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUX Standard Timer/Counter
+
+compatible: "nxp,lpc-ctimer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    clk-source:
+      type: int
+      required: true
+      description: clock to use
+
+    mode:
+      type: int
+      required: true
+      description: timer mode
+
+    input:
+      type: int
+      required: true
+      description: input channel
+
+    prescale:
+      type: int
+      required: true
+      description: prescale value

dts/bindings/timer/openisa,rv32m1-lptmr.yaml

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+description: OpenISA RV32M1 LPTMR peripheral
+
+compatible: "openisa,rv32m1-lptmr"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true

dts/bindings/timer/renesas,rcar-cmt.yaml

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+description: Renesas R-Car CMT timer
+
+compatible: "renesas,rcar-cmt"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    clock-frequency:
+      type: int
+      required: true
+      description: Clock frequency information for Timer operation
+
+    clocks:
+      required: true
+
+    interrupts:
+      required: true

dts/bindings/timer/riscv,machine-timer.yaml

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+# Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: RISC-V Machine timer
+
+compatible: "nuclei,machine-timer"
+
+include: base.yaml
+
+properties:
+    clk-divider:
+      type: int
+      required: false
+      description: |
+        clk-divider specifies the division ratio to the CPU frequency that
+        clock used by machine timer.
+        This property supports the case that the machine timer and CPU use
+        different clock sources.
+        This configuration is used sometimes for such as low power consumption.
+
+        For example, the CPU clock frequency is 108MHz, and the machine timer
+        uses 27MHz, which is the CPU clock divided by 4.
+        In this case, the CPU clock frequency is defined in the CPU node
+        as follows
+
+           clock-frequency = <108000000>;
+
+        This property takes exponent of the power of 2.
+        The relationship with the frequency division ratio is as
+        following equation.
+
+           division_ratio = 2^n
+           n = log_2(division_ratio)
+
+        Setting clk-divider to 2 specifies the machine timer uses the clock
+        that CPU clock frequency divided by (2^2=)4, or 27MHz.
+
+        Devision ratio constants can be found in the
+        dt-bindings/timer/nuclei-machine-timer.h header file.

dts/bindings/timer/silabs,gecko-timer.yaml

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+# Copyright (c) 2021, Sun Amar
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silabs gecko timer node
+
+compatible: "silabs,gecko-timer"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true

dts/bindings/timer/st,stm32-lptim.yaml

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+# Copyright (c) 2020, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 lptim
+
+compatible: "st,stm32-lptim"
+
+include:
+  - name: st,stm32-timers.yaml
+    property-blocklist:
+        - st,prescaler

dts/bindings/timer/st,stm32-timers.yaml

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+# Copyright (c) 2020, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 timers
+
+compatible: "st,stm32-timers"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+    interrupts:
+      required: false
+
+    st,prescaler:
+      type: int
+      required: true
+      description: |
+        Clock prescaler at the input of the timer
+        Could be in range [0 .. 0xFFFF] for STM32 General Purpose Timers (CLK/(prescaler+1) )

dts/bindings/timer/xlnx,ttcps.yaml

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+description: Xilinx ZynqMP PS TTC timer
+
+compatible: "xlnx,ttcps"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    clock-frequency:
+      type: int
+      required: true
+      description: Clock frequency information for Timer operation