WIP: device tree MVP

.gitmodules

@@ -64,3 +64,6 @@
 	path = src/lib/crypto/libtommath
 	url = https://github.com/PX4/libtommath.git
 	branch = px4
+[submodule "platforms/nuttx/src/px4/stm/hal_stm32"]
+	path = platforms/nuttx/src/px4/stm/hal_stm32
+	url = git@github.com:zephyrproject-rtos/hal_stm32.git

CMakeLists.txt

@@ -413,6 +413,8 @@ add_subdirectory(src/lib EXCLUDE_FROM_ALL)
 add_subdirectory(platforms/${PX4_PLATFORM}/src/px4)
 add_subdirectory(platforms EXCLUDE_FROM_ALL)
 
+include(dts)
+
 if(EXISTS "${PX4_BOARD_DIR}/CMakeLists.txt")
 	add_subdirectory(${PX4_BOARD_DIR})
 endif()

Tools/astyle/files_to_check_code_style.sh

@@ -10,6 +10,7 @@ fi
 exec find boards msg src platforms test \
     -path msg/templates/urtps -prune -o \
     -path platforms/nuttx/NuttX -prune -o \
+    -path platforms/nuttx/src/px4/stm/hal_stm32 -prune -o \
     -path platforms/qurt/dspal -prune -o \
     -path src/drivers/uavcan/libuavcan -prune -o \
     -path src/drivers/uavcan/uavcan_drivers/kinetis/driver/include/uavcan_kinetis -prune -o \

Tools/dts/README.txt

@@ -0,0 +1,32 @@
+This directory used to contain the edtlib.py and dtlib.py libraries
+and tests, alongside the gen_defines.py script that uses them for
+converting DTS to the C macros used by Zephyr.
+
+The libraries and tests have now been moved to the 'python-devicetree'
+subdirectory.
+
+We are now in the process of extracting edtlib and dtlib into a
+standalone source code library that we intend to share with other
+projects.
+
+Links related to the work making this standalone:
+
+    https://pypi.org/project/devicetree/
+    https://python-devicetree.readthedocs.io/en/latest/
+    https://github.com/zephyrproject-rtos/python-devicetree
+
+The 'python-devicetree' subdirectory you find here next to this
+README.txt matches the standalone python-devicetree repository linked
+above.
+
+For now, the 'main' copy will continue to be hosted here in the zephyr
+repository. We will mirror changes into the standalone repository as
+needed; you can just ignore it for now.
+
+Code in the zephyr repository which needs these libraries will import
+devicetree.edtlib from now on, but the code will continue to be found
+by manipulating sys.path for now.
+
+Eventually, as APIs stabilize, the python-devicetree code in this
+repository will disappear, and a standalone repository will be the
+'main' one.

Tools/dts/gen_dts_cmake.py

@@ -0,0 +1,151 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+'''
+This script uses edtlib and the devicetree data in the build directory
+to generate a CMake file which contains devicetree data.
+
+That data can then be used in the rest of the build system.
+
+The generated CMake file looks like this:
+
+  add_custom_target(devicetree_target)
+  set_target_properties(devicetree_target PROPERTIES
+                        "DT_PROP|/soc|compatible" "vnd,soc;")
+  ...
+
+It defines a special CMake target, and saves various values in the
+devicetree as CMake target properties.
+
+Be careful:
+
+  "Property" here can refer to a CMake target property or a
+  DTS property. DTS property values are stored inside
+  CMake target properties, along with other devicetree data.
+
+The build system includes this generated file early on, so
+devicetree values can be used at CMake processing time.
+
+Accss is not done directly, but with Zephyr CMake extension APIs,
+like this:
+
+  # sets 'compat' to "vnd,soc" in CMake
+  dt_prop(compat PATH "/soc" PROPERTY compatible INDEX 0)
+
+This is analogous to how DTS values are encoded as C macros,
+which can be read in source code using C APIs like
+DT_PROP(node_id, foo) from devicetree.h.
+'''
+
+import argparse
+import os
+import pickle
+import sys
+
+sys.path.append(os.path.join(os.path.dirname(__file__), 'python-devicetree',
+                             'src'))
+
+
+def parse_args():
+    # Returns parsed command-line arguments
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--cmake-out", required=True,
+                        help="path to write the CMake property file")
+    parser.add_argument("--edt-pickle", required=True,
+                        help="path to read the pickled edtlib.EDT object from")
+
+    return parser.parse_args()
+
+
+def main():
+    args = parse_args()
+
+    with open(args.edt_pickle, 'rb') as f:
+        edt = pickle.load(f)
+
+    # In what looks like an undocumented implementation detail, CMake
+    # target properties are stored in a C++ standard library map whose
+    # keys and values are each arbitrary strings, so we can use
+    # whatever we want as target property names.
+    #
+    # We therefore use '|' as a field separator character below within
+    # because it's not a valid character in DTS node paths or property
+    # names. This lets us store the "real" paths and property names
+    # without conversion to lowercase-and-underscores like we have to
+    # do in C.
+    #
+    # If CMake adds restrictions on target property names later, we
+    # can just tweak the generated file to use a more restrictive
+    # property encoding, perhaps reusing the same style documented in
+    # macros.bnf for C macros.
+
+    cmake_props = []
+    chosen_nodes = edt.chosen_nodes
+    for node in chosen_nodes:
+        path = chosen_nodes[node].path
+        cmake_props.append(f'"DT_CHOSEN|{node}" "{path}"')
+
+    # The separate loop over edt.nodes here is meant to keep
+    # all of the alias-related properties in one place.
+    for node in edt.nodes:
+        path = node.path
+        for alias in node.aliases:
+            cmake_props.append(f'"DT_ALIAS|{alias}" "{path}"')
+
+    for node in edt.nodes:
+        cmake_props.append(f'"DT_NODE|{node.path}" TRUE')
+
+        for label in node.labels:
+            cmake_props.append(f'"DT_NODELABEL|{label}" "{node.path}"')
+
+        for item in node.props:
+            # We currently do not support phandles for edt -> cmake conversion.
+            if "phandle" not in node.props[item].type:
+                if "array" in node.props[item].type:
+                    # Convert array to CMake list
+                    cmake_value = ''
+                    for val in node.props[item].val:
+                        cmake_value = f'{cmake_value}{val};'
+                else:
+                    cmake_value = node.props[item].val
+
+                # Encode node's property 'item' as a CMake target property
+                # with a name like 'DT_PROP|<path>|<property>'.
+                cmake_prop = f'DT_PROP|{node.path}|{item}'
+                cmake_props.append(f'"{cmake_prop}" "{cmake_value}"')
+
+        if node.regs is not None:
+            cmake_props.append(f'"DT_REG|{node.path}|NUM" "{len(node.regs)}"')
+            cmake_addr = ''
+            cmake_size = ''
+
+            for reg in node.regs:
+                if reg.addr is None:
+                    cmake_addr = f'{cmake_addr}NONE;'
+                else:
+                    cmake_addr = f'{cmake_addr}{hex(reg.addr)};'
+
+                if reg.size is None:
+                    cmake_size = f'{cmake_size}NONE;'
+                else:
+                    cmake_size = f'{cmake_size}{hex(reg.size)};'
+
+            cmake_props.append(f'"DT_REG|{node.path}|ADDR" "{cmake_addr}"')
+            cmake_props.append(f'"DT_REG|{node.path}|SIZE" "{cmake_size}"')
+
+    with open(args.cmake_out, "w", encoding="utf-8") as cmake_file:
+        print('add_custom_target(devicetree_target)', file=cmake_file)
+        print(file=cmake_file)
+
+        for prop in cmake_props:
+            print(
+                f'set_target_properties(devicetree_target PROPERTIES {prop})',
+                file=cmake_file
+            )
+
+
+if __name__ == "__main__":
+    main()

Tools/dts/python-devicetree/.gitignore

@@ -0,0 +1,7 @@
+dist/
+src/devicetree.egg-info/
+build/
+devicetree.egg-info/
+__pycache__/
+.tox/
+doc/build/

Tools/dts/python-devicetree/requirements.txt

@@ -0,0 +1 @@
+sphinx_rtd_theme                # docs

Tools/dts/python-devicetree/setup.py

@@ -0,0 +1,42 @@
+# Copyright (c) 2021, Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import setuptools
+
+long_description = '''
+Placeholder
+===========
+
+This is just a placeholder for moving Zephyr's devicetree libraries
+to PyPI.
+'''
+
+version = '0.0.1'
+
+setuptools.setup(
+    # TBD, just use these for now.
+    author='Zephyr Project',
+    author_email='devel@lists.zephyrproject.org',
+
+    name='devicetree',
+    version=version,
+    description='Python libraries for devicetree',
+    long_description=long_description,
+    # http://docutils.sourceforge.net/FAQ.html#what-s-the-official-mime-type-for-restructuredtext-data
+    long_description_content_type="text/x-rst",
+    url='https://github.com/zephyrproject-rtos/python-devicetree',
+    packages=setuptools.find_packages(where='src'),
+    package_dir={'': 'src'},
+    classifiers=[
+        'Programming Language :: Python :: 3 :: Only',
+        'License :: OSI Approved :: Apache Software License',
+        'Operating System :: POSIX :: Linux',
+        'Operating System :: MacOS :: MacOS X',
+        'Operating System :: Microsoft :: Windows',
+    ],
+    install_requires=[
+        'PyYAML>=5.1',
+    ],
+    python_requires='>=3.6',
+)

Tools/dts/python-devicetree/src/devicetree/__init__.py

@@ -0,0 +1,4 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+__all__ = ['edtlib', 'dtlib']

Tools/dts/python-devicetree/src/devicetree/grutils.py

@@ -0,0 +1,161 @@
+# Copyright 2009-2013, 2019 Peter A. Bigot
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# This implementation is derived from the one in
+# [PyXB](https://github.com/pabigot/pyxb), stripped down and modified
+# specifically to manage edtlib Node instances.
+
+import collections
+
+class Graph:
+    """
+    Represent a directed graph with edtlib Node objects as nodes.
+
+    This is used to determine order dependencies among nodes in a
+    devicetree.  An edge from C{source} to C{target} indicates that
+    some aspect of C{source} requires that some aspect of C{target}
+    already be available.
+    """
+
+    def __init__(self, root=None):
+        self.__roots = None
+        if root is not None:
+            self.__roots = {root}
+        self.__edge_map = collections.defaultdict(set)
+        self.__reverse_map = collections.defaultdict(set)
+        self.__nodes = set()
+
+    def add_edge(self, source, target):
+        """
+        Add a directed edge from the C{source} to the C{target}.
+
+        The nodes are added to the graph if necessary.
+        """
+        self.__edge_map[source].add(target)
+        if source != target:
+            self.__reverse_map[target].add(source)
+        self.__nodes.add(source)
+        self.__nodes.add(target)
+
+    def roots(self):
+        """
+        Return the set of nodes calculated to be roots (i.e., those
+        that have no incoming edges).
+
+        This caches the roots calculated in a previous invocation.
+
+        @rtype: C{set}
+        """
+        if not self.__roots:
+            self.__roots = set()
+            for n in self.__nodes:
+                if n not in self.__reverse_map:
+                    self.__roots.add(n)
+        return self.__roots
+
+    def _tarjan(self):
+        # Execute Tarjan's algorithm on the graph.
+        #
+        # Tarjan's algorithm
+        # (http://en.wikipedia.org/wiki/Tarjan%27s_strongly_connected_components_algorithm)
+        # computes the strongly-connected components
+        # (http://en.wikipedia.org/wiki/Strongly_connected_component)
+        # of the graph: i.e., the sets of nodes that form a minimal
+        # closed set under edge transition.  In essence, the loops.
+        # We use this to detect groups of components that have a
+        # dependency cycle, and to impose a total order on components
+        # based on dependencies.
+
+        self.__stack = []
+        self.__scc_order = []
+        self.__index = 0
+        self.__tarjan_index = {}
+        self.__tarjan_low_link = {}
+        for v in self.__nodes:
+            self.__tarjan_index[v] = None
+        roots = sorted(self.roots(), key=node_key)
+        if self.__nodes and not roots:
+            raise Exception('TARJAN: No roots found in graph with {} nodes'.format(len(self.__nodes)))
+
+        for r in roots:
+            self._tarjan_root(r)
+
+        # Assign ordinals for edtlib
+        ordinal = 0
+        for scc in self.__scc_order:
+            # Zephyr customization: devicetree Node graphs should have
+            # no loops, so all SCCs should be singletons.  That may
+            # change in the future, but for now we only give an
+            # ordinal to singletons.
+            if len(scc) == 1:
+                scc[0].dep_ordinal = ordinal
+                ordinal += 1
+
+    def _tarjan_root(self, v):
+        # Do the work of Tarjan's algorithm for a given root node.
+
+        if self.__tarjan_index.get(v) is not None:
+            # "Root" was already reached.
+            return
+        self.__tarjan_index[v] = self.__tarjan_low_link[v] = self.__index
+        self.__index += 1
+        self.__stack.append(v)
+        source = v
+        for target in sorted(self.__edge_map[source], key=node_key):
+            if self.__tarjan_index[target] is None:
+                self._tarjan_root(target)
+                self.__tarjan_low_link[v] = min(self.__tarjan_low_link[v], self.__tarjan_low_link[target])
+            elif target in self.__stack:
+                self.__tarjan_low_link[v] = min(self.__tarjan_low_link[v], self.__tarjan_low_link[target])
+
+        if self.__tarjan_low_link[v] == self.__tarjan_index[v]:
+            scc = []
+            while True:
+                scc.append(self.__stack.pop())
+                if v == scc[-1]:
+                    break
+            self.__scc_order.append(scc)
+
+    def scc_order(self):
+        """Return the strongly-connected components in order.
+
+        The data structure is a list, in dependency order, of strongly
+        connected components (which can be single nodes).  Appearance
+        of a node in a set earlier in the list indicates that it has
+        no dependencies on any node that appears in a subsequent set.
+        This order is preferred over a depth-first-search order for
+        code generation, since it detects loops.
+        """
+        if not self.__scc_order:
+            self._tarjan()
+        return self.__scc_order
+    __scc_order = None
+
+    def depends_on(self, node):
+        """Get the nodes that 'node' directly depends on."""
+        return sorted(self.__edge_map[node], key=node_key)
+
+    def required_by(self, node):
+        """Get the nodes that directly depend on 'node'."""
+        return sorted(self.__reverse_map[node], key=node_key)
+
+def node_key(node):
+    # This sort key ensures that sibling nodes with the same name will
+    # use unit addresses as tiebreakers. That in turn ensures ordinals
+    # for otherwise indistinguishable siblings are in increasing order
+    # by unit address, which is convenient for displaying output.
+
+    if node.parent:
+        parent_path = node.parent.path
+    else:
+        parent_path = '/'
+
+    if node.unit_addr is not None:
+        name = node.name.rsplit('@', 1)[0]
+        unit_addr = node.unit_addr
+    else:
+        name = node.name
+        unit_addr = -1
+
+    return (parent_path, name, unit_addr)

Tools/dts/python-devicetree/tests/test-bindings-2/multidir.yaml

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Binding in test-bindings-2/
+
+compatible: "in-dir-2"

Tools/dts/python-devicetree/tests/test-bindings-include/README.rst

@@ -0,0 +1 @@
+This directory contains bindings used to test the 'include:' feature.

Tools/dts/python-devicetree/tests/test-bindings-include/allow-and-blocklist-child.yaml

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  An include must not give both an allowlist and a blocklist in a
+  child binding. This binding should cause an error.
+compatible: allow-and-blocklist-child
+include:
+  - name: include.yaml
+    child-binding:
+      property-blocklist: [x]
+      property-allowlist: [y]

Tools/dts/python-devicetree/tests/test-bindings-include/allow-and-blocklist.yaml

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  An include must not give both an allowlist and a blocklist.
+  This binding should cause an error.
+compatible: allow-and-blocklist
+include:
+  - name: include.yaml
+    property-blocklist: [x]
+    property-allowlist: [y]

Tools/dts/python-devicetree/tests/test-bindings-include/allow-not-list.yaml

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  A property-allowlist, if given, must be a list. This binding should
+  cause an error.
+compatible: allow-not-list
+include:
+  - name: include.yaml
+    property-allowlist:
+      foo:

Tools/dts/python-devicetree/tests/test-bindings-include/allowlist.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Valid property-allowlist.
+compatible: allowlist
+include:
+  - name: include.yaml
+    property-allowlist: [x]

Tools/dts/python-devicetree/tests/test-bindings-include/block-not-list.yaml

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  A property-blocklist, if given, must be a list. This binding should
+  cause an error.
+compatible: block-not-list
+include:
+  - name: include.yaml
+    property-blocklist:
+      foo:

Tools/dts/python-devicetree/tests/test-bindings-include/blocklist.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Valid property-blocklist.
+compatible: blocklist
+include:
+  - name: include.yaml
+    property-blocklist: [x]

Tools/dts/python-devicetree/tests/test-bindings-include/empty-allowlist.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: An empty property-allowlist is valid.
+compatible: empty-allowlist
+include:
+  - name: include.yaml
+    property-allowlist: []

Tools/dts/python-devicetree/tests/test-bindings-include/empty-blocklist.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: An empty property-blocklist is valid.
+compatible: empty-blocklist
+include:
+  - name: include.yaml
+    property-blocklist: []

Tools/dts/python-devicetree/tests/test-bindings-include/filter-child-bindings.yaml

@@ -0,0 +1,11 @@
+description: Test binding for filtering 'child-binding' properties
+
+include:
+  - name: include.yaml
+    property-allowlist: [x]
+    child-binding:
+      property-blocklist: [child-prop-1]
+      child-binding:
+        property-allowlist: [grandchild-prop-1]
+
+compatible: filter-child-bindings

Tools/dts/python-devicetree/tests/test-bindings-include/include-2.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Second file for testing "intermixed" includes.
+compatible: include-2
+properties:
+  a:
+    type: int

Tools/dts/python-devicetree/tests/test-bindings-include/include-invalid-keys.yaml

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  Invalid include element: invalid keys are present.
+compatible: include-invalid-keys
+include:
+  - name: include.yaml
+    property-allowlist: [x]
+    bad-key-1: 3
+    bad-key-2: 3

Tools/dts/python-devicetree/tests/test-bindings-include/include-invalid-type.yaml

@@ -0,0 +1,5 @@
+description: |
+  Invalid include: wrong top level type.
+compatible: include-invalid-type
+include:
+  a-map-is-not-allowed-here: 3

Tools/dts/python-devicetree/tests/test-bindings-include/include-no-list.yaml

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: A map element with just a name is valid, and has no filters.
+compatible: include-no-list
+include:
+  - name: include.yaml

Tools/dts/python-devicetree/tests/test-bindings-include/include-no-name.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  Invalid include element: no name key is present.
+compatible: include-no-name
+include:
+  - property-allowlist: [x]

Tools/dts/python-devicetree/tests/test-bindings-include/include.yaml

@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Test file for including other bindings
+compatible: include
+properties:
+  x:
+    type: int
+  y:
+    type: int
+  z:
+    type: int
+child-binding:
+  properties:
+    child-prop-1:
+      type: int
+    child-prop-2:
+      type: int
+
+  child-binding:
+    properties:
+      grandchild-prop-1:
+        type: int
+      grandchild-prop-2:
+        type: int

Tools/dts/python-devicetree/tests/test-bindings-include/intermixed.yaml

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Including intermixed file names and maps is valid.
+compatible: intermixed
+include:
+  - name: include.yaml
+    property-allowlist: [x]
+  - include-2.yaml

Tools/dts/python-devicetree/tests/test-bindings/bar-bus.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Bar bus controller
+
+compatible: "bar-bus"
+
+bus: "bar"

Tools/dts/python-devicetree/tests/test-bindings/child-binding-with-compat.yaml

@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: child-binding with separate compatible than the parent
+
+compatible: "top-binding-with-compat"
+
+child-binding:
+    compatible: child-compat
+    description: child node
+    properties:
+        child-prop:
+            type: int
+            required: true
+
+    child-binding:
+        description: grandchild node
+        properties:
+            grandchild-prop:
+                type: int
+                required: true

Tools/dts/python-devicetree/tests/test-bindings/child-binding.yaml

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: child-binding test
+
+compatible: "top-binding"
+
+child-binding:
+    description: child node
+    properties:
+        child-prop:
+            type: int
+            required: true
+
+    child-binding:
+        description: grandchild node
+        properties:
+            grandchild-prop:
+                type: int
+                required: true

Tools/dts/python-devicetree/tests/test-bindings/child.yaml

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+include: [grandchild-1.yaml, grandchild-2.yaml, grandchild-3.yaml]
+
+properties:
+    bar:
+        required: true
+        type: int

Tools/dts/python-devicetree/tests/test-bindings/defaults.yaml

@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Property default value test
+
+compatible: "defaults"
+
+properties:
+    int:
+        type: int
+        required: false
+        default: 123
+
+    array:
+        type: array
+        required: false
+        default: [1, 2, 3]
+
+    uint8-array:
+        type: uint8-array
+        required: false
+        default: [0x89, 0xAB, 0xCD]
+
+    string:
+        type: string
+        required: false
+        default: "hello"
+
+    string-array:
+        type: string-array
+        required: false
+        default: ["hello", "there"]
+
+    default-not-used:
+        type: int
+        required: false
+        default: 123

Tools/dts/python-devicetree/tests/test-bindings/deprecated.yaml

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Property deprecated value test
+
+compatible: "test-deprecated"
+
+properties:
+    oldprop:
+        type: int
+        deprecated: true
+        required: false
+
+    curprop:
+        type: int
+        required: false

Tools/dts/python-devicetree/tests/test-bindings/device-on-any-bus.yaml

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device on any bus
+
+compatible: "on-any-bus"

Tools/dts/python-devicetree/tests/test-bindings/device-on-bar-bus.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device on bar bus
+
+compatible: "on-bus"
+
+on-bus: "bar"

Tools/dts/python-devicetree/tests/test-bindings/device-on-foo-bus.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device on foo bus
+
+compatible: "on-bus"
+
+on-bus: "foo"

Tools/dts/python-devicetree/tests/test-bindings/enums.yaml

@@ -0,0 +1,36 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Property enum test
+
+compatible: "enums"
+
+properties:
+  int-enum:
+    type: int
+    enum:
+      - 1
+      - 2
+      - 3
+
+  string-enum:                  # not tokenizable
+    type: string
+    enum:
+      - foo bar
+      - foo_bar
+
+  tokenizable-lower-enum:       # tokenizable in lowercase only
+    type: string
+    enum:
+      - bar
+      - BAR
+
+  tokenizable-enum:             # tokenizable in lower and uppercase
+    type: string
+    enum:
+      - bar
+      - whitespace is ok
+      - 123 is ok
+
+  no-enum:
+    type: string

Tools/dts/python-devicetree/tests/test-bindings/false-positive.yaml

@@ -0,0 +1,4 @@
+# A file that mentions a 'compatible' string without actually implementing it.
+# Used to check for issues with how we optimize binding loading.
+
+# props

Tools/dts/python-devicetree/tests/test-bindings/foo-bus.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Foo bus controller
+
+compatible: "foo-bus"
+
+bus: "foo"

Tools/dts/python-devicetree/tests/test-bindings/foo-optional.yaml

@@ -0,0 +1,4 @@
+properties:
+    foo:
+        type: int
+        required: false

Tools/dts/python-devicetree/tests/test-bindings/foo-required.yaml

@@ -0,0 +1,4 @@
+properties:
+    foo:
+        type: int
+        required: true

Tools/dts/python-devicetree/tests/test-bindings/gpio-dst.yaml

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: GPIO destination for mapping test
+
+compatible: "gpio-dst"
+
+gpio-cells:
+    - val

Tools/dts/python-devicetree/tests/test-bindings/gpio-src.yaml

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: GPIO source for mapping test
+
+compatible: "gpio-src"
+
+properties:
+    foo-gpios:
+        type: phandle-array

Tools/dts/python-devicetree/tests/test-bindings/grandchild-1.yaml

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+properties:
+    foo:
+        required: false
+        type: int
+
+    baz:
+        required: true
+        type: int

Tools/dts/python-devicetree/tests/test-bindings/grandchild-2.yaml

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+properties:
+    baz:
+        required: true
+        type: int

Tools/dts/python-devicetree/tests/test-bindings/grandchild-3.yaml

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+properties:
+    qaz:
+        required: true
+        type: int

Tools/dts/python-devicetree/tests/test-bindings/interrupt-1-cell.yaml

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Interrupt controller with one cell
+
+compatible: "interrupt-one-cell"
+
+interrupt-cells:
+    - one

Tools/dts/python-devicetree/tests/test-bindings/interrupt-2-cell.yaml

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Interrupt controller with two cells
+
+compatible: "interrupt-two-cell"
+
+interrupt-cells:
+    - one
+    - two

Tools/dts/python-devicetree/tests/test-bindings/interrupt-3-cell.yaml

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Interrupt controller with three cells
+
+compatible: "interrupt-three-cell"
+
+interrupt-cells:
+    - one
+    - two
+    - three

Tools/dts/python-devicetree/tests/test-bindings/multidir.yaml

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Binding in test-bindings/
+
+compatible: "in-dir-1"

Tools/dts/python-devicetree/tests/test-bindings/order-1.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Include ordering test
+
+compatible: "order-1"
+
+include: ["foo-required.yaml", "foo-optional.yaml"]

Tools/dts/python-devicetree/tests/test-bindings/order-2.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Include ordering test
+
+compatible: "order-2"
+
+include: ["foo-optional.yaml", "foo-required.yaml"]

Tools/dts/python-devicetree/tests/test-bindings/parent.yaml

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Parent binding
+
+compatible: "binding-include-test"
+
+include: child.yaml
+
+properties:
+    foo:
+        # Changed from not being required in grandchild-1.yaml
+        required: true
+        # Type set in grandchild

Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-0.yaml

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Controller with zero data values
+
+compatible: "phandle-array-controller-0"
+
+phandle-array-foo-cells: []

Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-1.yaml

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Controller with one data value
+
+compatible: "phandle-array-controller-1"
+
+phandle-array-foo-cells:
+    - one
+
+gpio-cells:
+    - gpio-one

Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-2.yaml

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Controller with two data values
+
+compatible: "phandle-array-controller-2"
+
+phandle-array-foo-cells:
+    - one
+    - two

Tools/dts/python-devicetree/tests/test-bindings/props.yaml

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device.props test
+
+compatible: "props"
+
+properties:
+    nonexistent-boolean:
+        type: boolean
+
+    existent-boolean:
+        type: boolean
+
+    int:
+        type: int
+        const: 1
+
+    array:
+        type: array
+
+    uint8-array:
+        type: uint8-array
+
+    string:
+        type: string
+        const: "foo"
+
+    string-array:
+        type: string-array
+
+    phandle-ref:
+        type: phandle
+
+    phandle-refs:
+        type: phandles
+
+    phandle-array-foos:
+        type: phandle-array
+
+    phandle-array-foo-names:
+        type: string-array
+
+    # There's some slight special-casing for GPIOs in that 'foo-gpios = ...'
+    # gets resolved to #gpio-cells rather than #foo-gpio-cells, so test that
+    # too
+    foo-gpios:
+        type: phandle-array
+
+    path:
+        type: path

Tools/dts/python-devicetree/tests/test-multidir.dts

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// Used by testedtlib.py. Dedicated file for testing having multiple binding
+// directories.
+
+/dts-v1/;
+
+/ {
+	in-dir-1 {
+		compatible = "in-dir-1";
+	};
+	in-dir-2 {
+		compatible = "in-dir-2";
+	};
+};

Tools/dts/python-devicetree/tests/test-wrong-bindings/wrong-phandle-array-name.yaml

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device.wrong_phandle_array_name test
+
+compatible: "wrong_phandle_array_name"
+
+properties:
+    wrong-phandle-array-name:
+        type: phandle-array

Tools/dts/python-devicetree/tests/test-wrong-bindings/wrong-specifier-space-type.yaml

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device.wrong_specifier_space_type test
+
+compatible: "wrong_specifier_space_type"
+
+properties:
+    wrong-type-for-specifier-space:
+        type: phandle
+        specifier-space: foobar

Tools/dts/python-devicetree/tests/test.dts

@@ -0,0 +1,534 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// Used by testedtlib.py
+
+/dts-v1/;
+
+/ {
+	//
+	// Interrupts
+	//
+
+	interrupt-parent-test {
+		controller {
+			compatible = "interrupt-three-cell";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+		node {
+			interrupts = <1 2 3 4 5 6>;
+			interrupt-names = "foo", "bar";
+			interrupt-parent = <&{/interrupt-parent-test/controller}>;
+		};
+	};
+	interrupts-extended-test {
+		controller-0 {
+			compatible = "interrupt-one-cell";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+		controller-1 {
+			compatible = "interrupt-two-cell";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+		controller-2 {
+			compatible = "interrupt-three-cell";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+		node {
+			interrupts-extended = <
+				&{/interrupts-extended-test/controller-0} 1
+				&{/interrupts-extended-test/controller-1} 2 3
+				&{/interrupts-extended-test/controller-2} 4 5 6>;
+		};
+	};
+	interrupt-map-test {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		controller-0 {
+			compatible = "interrupt-one-cell";
+			#address-cells = <1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+		controller-1 {
+			compatible = "interrupt-two-cell";
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+		controller-2 {
+			compatible = "interrupt-three-cell";
+			#address-cells = <3>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+		nexus {
+			#interrupt-cells = <2>;
+			interrupt-map = <
+				0 0  0 0  &{/interrupt-map-test/controller-0}  0      0
+				0 0  0 1  &{/interrupt-map-test/controller-1}  0 0    0 1
+				0 0  0 2  &{/interrupt-map-test/controller-2}  0 0 0  0 0 2
+				0 1  0 0  &{/interrupt-map-test/controller-0}  0      3
+				0 1  0 1  &{/interrupt-map-test/controller-1}  0 0    0 4
+				0 1  0 2  &{/interrupt-map-test/controller-2}  0 0 0  0 0 5>;
+		};
+		node@0 {
+			reg = <0 0>;
+			interrupts = <0 0 0 1 0 2>;
+			interrupt-parent = <&{/interrupt-map-test/nexus}>;
+		};
+		node@1 {
+			reg = <0 1>;
+			interrupts-extended = <
+			    &{/interrupt-map-test/nexus} 0 0
+			    &{/interrupt-map-test/nexus} 0 1
+			    &{/interrupt-map-test/nexus} 0 2>;
+		};
+	};
+	interrupt-map-bitops-test {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		controller {
+			compatible = "interrupt-two-cell";
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+		nexus {
+			#interrupt-cells = <2>;
+			interrupt-map = <
+			    6 6  6 6  &{/interrupt-map-bitops-test/controller}  2 1
+			>;
+			interrupt-map-mask = <0xE 0x7 0xE 0x7>;
+			// Not specified in the DT spec., but shows up due to
+			// common code with GPIO. Might as well test it here.
+			interrupt-map-pass-thru = <1 2 3 3>;
+		};
+		// Child unit specifier: 00000007 0000000E 00000007 0000000E
+		// Mask:                 0000000E 00000007 0000000E 00000007
+		// Pass-thru:            00000001 00000002 00000003 00000003
+		node@70000000E {
+			reg = <0x7 0xE>;
+			interrupt-parent = <&{/interrupt-map-bitops-test/nexus}>;
+			interrupts = <0x7 0xE>;
+		};
+	};
+
+	//
+	// 'ranges'
+	//
+
+	ranges-zero-cells {
+		#address-cells = <0>;
+
+		node {
+			#address-cells = <0>;
+			#size-cells = <0>;
+
+			ranges;
+		};
+	};
+
+	ranges-zero-parent-cells {
+		#address-cells = <0>;
+
+		node {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ranges = <0xA>,
+				 <0x1A>,
+				 <0x2A>;
+		};
+	};
+
+	ranges-one-address-cells {
+		#address-cells = <0>;
+
+		node {
+			reg = <1>;
+			#address-cells = <1>;
+
+			ranges = <0xA 0xB>,
+				 <0x1A 0x1B>,
+				 <0x2A 0x2B>;
+		};
+	};
+
+	ranges-one-address-two-size-cells {
+		#address-cells = <0>;
+
+		node {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <2>;
+
+			ranges = <0xA 0xB 0xC>,
+				 <0x1A 0x1B 0x1C>,
+				 <0x2A 0x2B 0x2C>;
+		};
+	};
+
+	ranges-two-address-cells {
+		#address-cells = <1>;
+
+		node@1 {
+			reg = <1 2>;
+
+			ranges = <0xA 0xB 0xC 0xD>,
+				 <0x1A 0x1B 0x1C 0x1D>,
+				 <0x2A 0x2B 0x2C 0x2D>;
+		};
+	};
+
+	ranges-two-address-two-size-cells {
+		#address-cells = <1>;
+
+		node@1 {
+			reg = <1 2>;
+			#size-cells = <2>;
+
+			ranges = <0xA 0xB 0xC 0xD 0xE>,
+				 <0x1A 0x1B 0x1C 0x1D 0x1E>,
+				 <0x2A 0x2B 0x2C 0x2D 0x1D>;
+		};
+	};
+
+	ranges-three-address-cells {
+		node@1 {
+			reg = <0 1 2>;
+			#address-cells = <3>;
+
+			ranges = <0xA 0xB 0xC 0xD 0xE 0xF>,
+				 <0x1A 0x1B 0x1C 0x1D 0x1E 0x1F>,
+				 <0x2A 0x2B 0x2C 0x2D 0x2E 0x2F>;
+		};
+	};
+
+	ranges-three-address-two-size-cells {
+		node@1 {
+			reg = <0 1 2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0xA 0xB 0xC 0xD 0xE 0xF 0x10>,
+				 <0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x110>,
+				 <0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x210>;
+		};
+	};
+
+
+	//
+	// 'reg'
+	//
+
+	reg-zero-address-cells {
+		#address-cells = <0>;
+		#size-cells = <1>;
+
+		node {
+			reg = <1 2>;
+		};
+	};
+	reg-zero-size-cells {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		node {
+			reg = <1 2>;
+		};
+	};
+	// Use implied #size-cells = <1>
+	reg-ranges {
+		#address-cells = <2>;
+
+		parent {
+			#address-cells = <1>;
+			ranges = <1  0xA 0xB  1 /* 1    -> 0xA 0xB */
+				  2  0xC 0xD  2 /* 2..3 -> 0xC 0xD */
+				  4  0xE 0xF  1 /* 4    -> 0xE 0xF */
+				 >;
+
+			node {
+				reg = <5 1 /* Matches no range */
+				       4 1 /* Matches third range */
+				       3 1 /* Matches second range */
+				       2 1 /* Matches second range */
+				       1 1 /* Matches first range */
+				       0 1 /* Matches no range */
+				       >;
+			};
+		};
+	};
+	// Build up <3 2 1> address with nested 'ranges'
+	reg-nested-ranges {
+		#address-cells = <3>;
+
+		grandparent {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0  3 0 0  2 2>;
+
+			parent {
+				#address-cells = <1>;
+				ranges = <0  2 0  2>;
+
+				node {
+					reg = <1 1>;
+				};
+			};
+		};
+	};
+
+	//
+	// 'pinctrl-<index>'
+	//
+
+	pinctrl {
+		dev {
+			pinctrl-0 = <>;
+			pinctrl-1 = <&{/pinctrl/pincontroller/state-1}>;
+			pinctrl-2 = <&{/pinctrl/pincontroller/state-1}
+				     &{/pinctrl/pincontroller/state-2}>;
+			pinctrl-names = "zero", "one", "two";
+		};
+		pincontroller {
+			state-1 {
+			};
+			state-2 {
+			};
+		};
+	};
+
+	//
+	// For testing Node.parent and Node.children
+	//
+
+	parent {
+		child-1 {
+		};
+		child-2 {
+			grandchild {
+			};
+		};
+	};
+
+	//
+	// For testing 'include:'
+	//
+
+	binding-include {
+		compatible = "binding-include-test";
+		foo = <0>;
+		bar = <1>;
+		baz = <2>;
+		qaz = <3>;
+	};
+
+	//
+	// For testing Node.props (derived from 'properties:' in the binding)
+	//
+
+	props {
+		compatible = "props";
+		existent-boolean;
+		int = <1>;
+		array = <1 2 3>;
+		uint8-array = [ 12 34 ];
+		string = "foo";
+		string-array = "foo", "bar", "baz";
+		phandle-ref = < &{/ctrl-1} >;
+		phandle-refs = < &{/ctrl-1} &{/ctrl-2} >;
+		phandle-array-foos = < &{/ctrl-1} 1 &{/ctrl-2} 2 3 >;
+		foo-gpios = < &{/ctrl-1} 1 >;
+		path = &{/ctrl-1};
+	};
+
+	ctrl-1 {
+		compatible = "phandle-array-controller-1";
+		#phandle-array-foo-cells = <1>;
+		#gpio-cells = <1>;
+	};
+
+	ctrl-2 {
+		compatible = "phandle-array-controller-2";
+		#phandle-array-foo-cells = <2>;
+	};
+
+	props-2 {
+		compatible = "props";
+		phandle-array-foos = < &{/ctrl-0-1} 0 &{/ctrl-0-2} >;
+		phandle-array-foo-names = "a", "missing", "b";
+	};
+
+	ctrl-0-1 {
+		compatible = "phandle-array-controller-0";
+		#phandle-array-foo-cells = <0>;
+	};
+
+	ctrl-0-2 {
+		compatible = "phandle-array-controller-0";
+		#phandle-array-foo-cells = <0>;
+	};
+
+	//
+	// Test <prefix>-map, via gpio-map
+	//
+
+	gpio-map {
+		source {
+			compatible = "gpio-src";
+			foo-gpios = <&{/gpio-map/connector} 3 4
+				     &{/gpio-map/connector} 1 2>;
+		};
+		connector {
+			#gpio-cells = <2>;
+			// Use different data lengths for source and
+			// destination to make it a bit trickier
+			gpio-map = <1 2 &{/gpio-map/destination} 5
+				    3 4 &{/gpio-map/destination} 6>;
+		};
+		destination {
+			compatible = "gpio-dst";
+			gpio-controller;
+			#gpio-cells = <1>;
+		};
+	};
+
+	//
+	// For testing Node.props with 'default:' values in binding
+	//
+
+	defaults {
+		compatible = "defaults";
+		// Should override the 'default:' in the binding
+		default-not-used = <234>;
+	};
+
+	//
+	// For testing 'enum:'
+	//
+
+	enums {
+		compatible = "enums";
+		int-enum = <1>;
+		string-enum = "foo_bar";
+		tokenizable-enum = "123 is ok";
+		tokenizable-lower-enum = "bar";
+		no-enum = "baz";
+	};
+
+	//
+	// For testing 'bus:' and 'on-bus:'
+	//
+
+	buses {
+		// The 'node' nodes below will map to different bindings since
+		// they appear on different buses
+		foo-bus {
+			compatible = "foo-bus";
+			node1 {
+				compatible = "on-bus", "on-any-bus";
+				nested {
+					compatible = "on-bus";
+				};
+			};
+			node2 {
+				compatible = "on-any-bus", "on-bus";
+			};
+		};
+		bar-bus {
+			compatible = "bar-bus";
+			node {
+				compatible = "on-bus";
+			};
+		};
+		no-bus-node {
+			compatible = "on-any-bus";
+		};
+	};
+
+	//
+	// Node with 'child-binding:' in binding (along with a recursive
+	// 'child-binding:')
+	//
+
+	child-binding {
+		compatible = "top-binding";
+		child-1 {
+			child-prop = <1>;
+			grandchild {
+				grandchild-prop = <2>;
+			};
+		};
+		child-2 {
+			child-prop = <3>;
+		};
+	};
+
+	//
+	// zephyr,user binding inference
+	//
+
+	zephyr,user {
+		boolean;
+		bytes = [81 82 83];
+		number = <23>;
+		numbers = <1>, <2>, <3>;
+		string = "text";
+		strings = "a", "b", "c";
+		handle = <&{/ctrl-1}>;
+		phandles = <&{/ctrl-1}>, <&{/ctrl-2}>;
+		phandle-array-foos = <&{/ctrl-2} 1 2>;
+	};
+
+	//
+	// For testing that neither 'include: [foo.yaml, bar.yaml]' nor
+	// 'include: [bar.yaml, foo.yaml]' causes errors when one of the files
+	// has 'required: true' and the other 'required: false'
+	//
+
+	include-order {
+		node-1 {
+			compatible = "order-1";
+			foo = <1>;
+		};
+		node-2 {
+			compatible = "order-2";
+			foo = <2>;
+		};
+	};
+
+	//
+	// For testing deprecated property
+	//
+	test-deprecated {
+		compatible = "test-deprecated";
+		oldprop = <4>;	/* deprecated property */
+		curprop = <5>;
+	};
+
+
+	//
+	// For testing deprecated features
+	//
+
+	deprecated {
+		compatible = "deprecated";
+		required = <1>;
+		required-2 = <2>;
+		#foo-cells = <2>;
+		sub-node {
+			foos = <&{/deprecated} 1 2>;
+		};
+	};
+};

Tools/dts/python-devicetree/tests/test_edtlib.py

@@ -0,0 +1,588 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: BSD-3-Clause
+
+import contextlib
+import io
+from logging import WARNING
+import os
+from pathlib import Path
+
+import pytest
+
+from devicetree import edtlib
+
+# Test suite for edtlib.py.
+#
+# Run it using pytest (https://docs.pytest.org/en/stable/usage.html):
+#
+#   $ pytest testedtlib.py
+#
+# See the comment near the top of testdtlib.py for additional pytest advice.
+#
+# test.dts is the main test file. test-bindings/ and test-bindings-2/ has
+# bindings. The tests mostly use string comparisons via the various __repr__()
+# methods.
+
+HERE = os.path.dirname(__file__)
+
+@contextlib.contextmanager
+def from_here():
+    # Convenience hack to minimize diff from zephyr.
+    cwd = os.getcwd()
+    try:
+        os.chdir(HERE)
+        yield
+    finally:
+        os.chdir(cwd)
+
+def hpath(filename):
+    '''Convert 'filename' to the host path syntax.'''
+    return os.fspath(Path(filename))
+
+def test_warnings(caplog):
+    '''Tests for situations that should cause warnings.'''
+
+    with from_here(): edtlib.EDT("test.dts", ["test-bindings"])
+
+    enums_hpath = hpath('test-bindings/enums.yaml')
+    expected_warnings = [
+        f"'oldprop' is marked as deprecated in 'properties:' in {hpath('test-bindings/deprecated.yaml')} for node /test-deprecated.",
+        "unit address and first address in 'reg' (0x1) don't match for /reg-zero-size-cells/node",
+        "unit address and first address in 'reg' (0x5) don't match for /reg-ranges/parent/node",
+        "unit address and first address in 'reg' (0x30000000200000001) don't match for /reg-nested-ranges/grandparent/parent/node",
+        f"compatible 'enums' in binding '{enums_hpath}' has non-tokenizable enum for property 'string-enum': 'foo bar', 'foo_bar'",
+        f"compatible 'enums' in binding '{enums_hpath}' has enum for property 'tokenizable-lower-enum' that is only tokenizable in lowercase: 'bar', 'BAR'",
+    ]
+    assert caplog.record_tuples == [('devicetree.edtlib', WARNING, warning_message)
+                                    for warning_message in expected_warnings]
+
+def test_interrupts():
+    '''Tests for the interrupts property.'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    filenames = {i: hpath(f'test-bindings/interrupt-{i}-cell.yaml')
+                 for i in range(1, 4)}
+
+    assert str(edt.get_node("/interrupt-parent-test/node").interrupts) == \
+        f"[<ControllerAndData, name: foo, controller: <Node /interrupt-parent-test/controller in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 1), ('two', 2), ('three', 3)])>, <ControllerAndData, name: bar, controller: <Node /interrupt-parent-test/controller in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 4), ('two', 5), ('three', 6)])>]"
+
+    assert str(edt.get_node("/interrupts-extended-test/node").interrupts) == \
+        f"[<ControllerAndData, controller: <Node /interrupts-extended-test/controller-0 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('one', 1)])>, <ControllerAndData, controller: <Node /interrupts-extended-test/controller-1 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 2), ('two', 3)])>, <ControllerAndData, controller: <Node /interrupts-extended-test/controller-2 in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 4), ('two', 5), ('three', 6)])>]"
+
+    assert str(edt.get_node("/interrupt-map-test/node@0").interrupts) == \
+        f"[<ControllerAndData, controller: <Node /interrupt-map-test/controller-0 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('one', 0)])>, <ControllerAndData, controller: <Node /interrupt-map-test/controller-1 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 0), ('two', 1)])>, <ControllerAndData, controller: <Node /interrupt-map-test/controller-2 in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 0), ('two', 0), ('three', 2)])>]"
+
+    assert str(edt.get_node("/interrupt-map-test/node@1").interrupts) == \
+        f"[<ControllerAndData, controller: <Node /interrupt-map-test/controller-0 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('one', 3)])>, <ControllerAndData, controller: <Node /interrupt-map-test/controller-1 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 0), ('two', 4)])>, <ControllerAndData, controller: <Node /interrupt-map-test/controller-2 in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 0), ('two', 0), ('three', 5)])>]"
+
+    assert str(edt.get_node("/interrupt-map-bitops-test/node@70000000E").interrupts) == \
+        f"[<ControllerAndData, controller: <Node /interrupt-map-bitops-test/controller in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 3), ('two', 2)])>]"
+
+def test_ranges():
+    '''Tests for the ranges property'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/reg-ranges/parent").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0x1, parent-bus-cells: 0x2, parent-bus-addr: 0xa0000000b, length-cells 0x1, length 0x1>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x2, parent-bus-cells: 0x2, parent-bus-addr: 0xc0000000d, length-cells 0x1, length 0x2>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x4, parent-bus-cells: 0x2, parent-bus-addr: 0xe0000000f, length-cells 0x1, length 0x1>]"
+
+    assert str(edt.get_node("/reg-nested-ranges/grandparent").ranges) == \
+        "[<Range, child-bus-cells: 0x2, child-bus-addr: 0x0, parent-bus-cells: 0x3, parent-bus-addr: 0x30000000000000000, length-cells 0x2, length 0x200000002>]"
+
+    assert str(edt.get_node("/reg-nested-ranges/grandparent/parent").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0x0, parent-bus-cells: 0x2, parent-bus-addr: 0x200000000, length-cells 0x1, length 0x2>]"
+
+    assert str(edt.get_node("/ranges-zero-cells/node").ranges) == "[]"
+
+    assert str(edt.get_node("/ranges-zero-parent-cells/node").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0xa, parent-bus-cells: 0x0, length-cells 0x0>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x1a, parent-bus-cells: 0x0, length-cells 0x0>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x2a, parent-bus-cells: 0x0, length-cells 0x0>]"
+
+    assert str(edt.get_node("/ranges-one-address-cells/node").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0xa, parent-bus-cells: 0x0, length-cells 0x1, length 0xb>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x1a, parent-bus-cells: 0x0, length-cells 0x1, length 0x1b>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x2a, parent-bus-cells: 0x0, length-cells 0x1, length 0x2b>]"
+
+    assert str(edt.get_node("/ranges-one-address-two-size-cells/node").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0xa, parent-bus-cells: 0x0, length-cells 0x2, length 0xb0000000c>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x1a, parent-bus-cells: 0x0, length-cells 0x2, length 0x1b0000001c>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x2a, parent-bus-cells: 0x0, length-cells 0x2, length 0x2b0000002c>]"
+
+    assert str(edt.get_node("/ranges-two-address-cells/node@1").ranges) == \
+        "[<Range, child-bus-cells: 0x2, child-bus-addr: 0xa0000000b, parent-bus-cells: 0x1, parent-bus-addr: 0xc, length-cells 0x1, length 0xd>, <Range, child-bus-cells: 0x2, child-bus-addr: 0x1a0000001b, parent-bus-cells: 0x1, parent-bus-addr: 0x1c, length-cells 0x1, length 0x1d>, <Range, child-bus-cells: 0x2, child-bus-addr: 0x2a0000002b, parent-bus-cells: 0x1, parent-bus-addr: 0x2c, length-cells 0x1, length 0x2d>]"
+
+    assert str(edt.get_node("/ranges-two-address-two-size-cells/node@1").ranges) == \
+        "[<Range, child-bus-cells: 0x2, child-bus-addr: 0xa0000000b, parent-bus-cells: 0x1, parent-bus-addr: 0xc, length-cells 0x2, length 0xd0000000e>, <Range, child-bus-cells: 0x2, child-bus-addr: 0x1a0000001b, parent-bus-cells: 0x1, parent-bus-addr: 0x1c, length-cells 0x2, length 0x1d0000001e>, <Range, child-bus-cells: 0x2, child-bus-addr: 0x2a0000002b, parent-bus-cells: 0x1, parent-bus-addr: 0x2c, length-cells 0x2, length 0x2d0000001d>]"
+
+    assert str(edt.get_node("/ranges-three-address-cells/node@1").ranges) == \
+        "[<Range, child-bus-cells: 0x3, child-bus-addr: 0xa0000000b0000000c, parent-bus-cells: 0x2, parent-bus-addr: 0xd0000000e, length-cells 0x1, length 0xf>, <Range, child-bus-cells: 0x3, child-bus-addr: 0x1a0000001b0000001c, parent-bus-cells: 0x2, parent-bus-addr: 0x1d0000001e, length-cells 0x1, length 0x1f>, <Range, child-bus-cells: 0x3, child-bus-addr: 0x2a0000002b0000002c, parent-bus-cells: 0x2, parent-bus-addr: 0x2d0000002e, length-cells 0x1, length 0x2f>]"
+
+    assert str(edt.get_node("/ranges-three-address-two-size-cells/node@1").ranges) == \
+        "[<Range, child-bus-cells: 0x3, child-bus-addr: 0xa0000000b0000000c, parent-bus-cells: 0x2, parent-bus-addr: 0xd0000000e, length-cells 0x2, length 0xf00000010>, <Range, child-bus-cells: 0x3, child-bus-addr: 0x1a0000001b0000001c, parent-bus-cells: 0x2, parent-bus-addr: 0x1d0000001e, length-cells 0x2, length 0x1f00000110>, <Range, child-bus-cells: 0x3, child-bus-addr: 0x2a0000002b0000002c, parent-bus-cells: 0x2, parent-bus-addr: 0x2d0000002e, length-cells 0x2, length 0x2f00000210>]"
+
+def test_reg():
+    '''Tests for the regs property'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/reg-zero-address-cells/node").regs) == \
+        "[<Register, size: 0x1>, <Register, size: 0x2>]"
+
+    assert str(edt.get_node("/reg-zero-size-cells/node").regs) == \
+        "[<Register, addr: 0x1>, <Register, addr: 0x2>]"
+
+    assert str(edt.get_node("/reg-ranges/parent/node").regs) == \
+        "[<Register, addr: 0x5, size: 0x1>, <Register, addr: 0xe0000000f, size: 0x1>, <Register, addr: 0xc0000000e, size: 0x1>, <Register, addr: 0xc0000000d, size: 0x1>, <Register, addr: 0xa0000000b, size: 0x1>, <Register, addr: 0x0, size: 0x1>]"
+
+    assert str(edt.get_node("/reg-nested-ranges/grandparent/parent/node").regs) == \
+        "[<Register, addr: 0x30000000200000001, size: 0x1>]"
+
+def test_pinctrl():
+    '''Test 'pinctrl-<index>'.'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/pinctrl/dev").pinctrls) == \
+        "[<PinCtrl, name: zero, configuration nodes: []>, <PinCtrl, name: one, configuration nodes: [<Node /pinctrl/pincontroller/state-1 in 'test.dts', no binding>]>, <PinCtrl, name: two, configuration nodes: [<Node /pinctrl/pincontroller/state-1 in 'test.dts', no binding>, <Node /pinctrl/pincontroller/state-2 in 'test.dts', no binding>]>]"
+
+def test_hierarchy():
+    '''Test Node.parent and Node.children'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert edt.get_node("/").parent is None
+
+    assert str(edt.get_node("/parent/child-1").parent) == \
+        "<Node /parent in 'test.dts', no binding>"
+
+    assert str(edt.get_node("/parent/child-2/grandchild").parent) == \
+        "<Node /parent/child-2 in 'test.dts', no binding>"
+
+    assert str(edt.get_node("/parent").children) == \
+        "OrderedDict([('child-1', <Node /parent/child-1 in 'test.dts', no binding>), ('child-2', <Node /parent/child-2 in 'test.dts', no binding>)])"
+
+    assert edt.get_node("/parent/child-1").children == {}
+
+def test_include():
+    '''Test 'include:' and the legacy 'inherits: !include ...' in bindings'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/binding-include").description) == \
+        "Parent binding"
+
+    assert str(edt.get_node("/binding-include").props) == \
+        "OrderedDict([('foo', <Property, name: foo, type: int, value: 0>), ('bar', <Property, name: bar, type: int, value: 1>), ('baz', <Property, name: baz, type: int, value: 2>), ('qaz', <Property, name: qaz, type: int, value: 3>)])"
+
+def test_include_filters():
+    '''Test property-allowlist and property-blocklist in an include.'''
+
+    fname2path = {'include.yaml': 'test-bindings-include/include.yaml',
+                  'include-2.yaml': 'test-bindings-include/include-2.yaml'}
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            edtlib.Binding("test-bindings-include/allow-and-blocklist.yaml", fname2path)
+    assert ("should not specify both 'property-allowlist:' and 'property-blocklist:'"
+            in str(e.value))
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            edtlib.Binding("test-bindings-include/allow-and-blocklist-child.yaml", fname2path)
+    assert ("should not specify both 'property-allowlist:' and 'property-blocklist:'"
+            in str(e.value))
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            edtlib.Binding("test-bindings-include/allow-not-list.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith("'property-allowlist' value")
+    assert value_str.endswith("should be a list")
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            edtlib.Binding("test-bindings-include/block-not-list.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith("'property-blocklist' value")
+    assert value_str.endswith("should be a list")
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            binding = edtlib.Binding("test-bindings-include/include-invalid-keys.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith(
+        "'include:' in test-bindings-include/include-invalid-keys.yaml should not have these "
+        "unexpected contents: ")
+    assert 'bad-key-1' in value_str
+    assert 'bad-key-2' in value_str
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            binding = edtlib.Binding("test-bindings-include/include-invalid-type.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith(
+        "'include:' in test-bindings-include/include-invalid-type.yaml "
+        "should be a string or list, but has type ")
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            binding = edtlib.Binding("test-bindings-include/include-no-name.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith("'include:' element")
+    assert value_str.endswith(
+        "in test-bindings-include/include-no-name.yaml should have a 'name' key")
+
+    with from_here():
+        binding = edtlib.Binding("test-bindings-include/allowlist.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'x'}  # 'x' is allowed
+
+        binding = edtlib.Binding("test-bindings-include/empty-allowlist.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == set()  # nothing is allowed
+
+        binding = edtlib.Binding("test-bindings-include/blocklist.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'y', 'z'}  # 'x' is blocked
+
+        binding = edtlib.Binding("test-bindings-include/empty-blocklist.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'x', 'y', 'z'}  # nothing is blocked
+
+        binding = edtlib.Binding("test-bindings-include/intermixed.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'x', 'a'}
+
+        binding = edtlib.Binding("test-bindings-include/include-no-list.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'x', 'y', 'z'}
+
+        binding = edtlib.Binding("test-bindings-include/filter-child-bindings.yaml", fname2path)
+        child = binding.child_binding
+        grandchild = child.child_binding
+        assert set(binding.prop2specs.keys()) == {'x'}
+        assert set(child.prop2specs.keys()) == {'child-prop-2'}
+        assert set(grandchild.prop2specs.keys()) == {'grandchild-prop-1'}
+
+
+def test_bus():
+    '''Test 'bus:' and 'on-bus:' in bindings'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert edt.get_node("/buses/foo-bus").bus == "foo"
+
+    # foo-bus does not itself appear on a bus
+    assert edt.get_node("/buses/foo-bus").on_bus is None
+    assert edt.get_node("/buses/foo-bus").bus_node is None
+
+    # foo-bus/node1 is not a bus node...
+    assert edt.get_node("/buses/foo-bus/node1").bus is None
+    # ...but is on a bus
+    assert edt.get_node("/buses/foo-bus/node1").on_bus == "foo"
+    assert edt.get_node("/buses/foo-bus/node1").bus_node.path == \
+        "/buses/foo-bus"
+
+    # foo-bus/node2 is not a bus node...
+    assert edt.get_node("/buses/foo-bus/node2").bus is None
+    # ...but is on a bus
+    assert edt.get_node("/buses/foo-bus/node2").on_bus == "foo"
+
+    # no-bus-node is not a bus node...
+    assert edt.get_node("/buses/no-bus-node").bus is None
+    # ... and is not on a bus
+    assert edt.get_node("/buses/no-bus-node").on_bus is None
+
+    # Same compatible string, but different bindings from being on different
+    # buses
+    assert str(edt.get_node("/buses/foo-bus/node1").binding_path) == \
+        hpath("test-bindings/device-on-foo-bus.yaml")
+    assert str(edt.get_node("/buses/foo-bus/node2").binding_path) == \
+        hpath("test-bindings/device-on-any-bus.yaml")
+    assert str(edt.get_node("/buses/bar-bus/node").binding_path) == \
+        hpath("test-bindings/device-on-bar-bus.yaml")
+    assert str(edt.get_node("/buses/no-bus-node").binding_path) == \
+        hpath("test-bindings/device-on-any-bus.yaml")
+
+    # foo-bus/node/nested also appears on the foo-bus bus
+    assert edt.get_node("/buses/foo-bus/node1/nested").on_bus == "foo"
+    assert str(edt.get_node("/buses/foo-bus/node1/nested").binding_path) == \
+        hpath("test-bindings/device-on-foo-bus.yaml")
+
+def test_child_binding():
+    '''Test 'child-binding:' in bindings'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    child1 = edt.get_node("/child-binding/child-1")
+    child2 = edt.get_node("/child-binding/child-2")
+    grandchild = edt.get_node("/child-binding/child-1/grandchild")
+
+    assert str(child1.binding_path) == hpath("test-bindings/child-binding.yaml")
+    assert str(child1.description) == "child node"
+    assert str(child1.props) == "OrderedDict([('child-prop', <Property, name: child-prop, type: int, value: 1>)])"
+
+    assert str(child2.binding_path) == hpath("test-bindings/child-binding.yaml")
+    assert str(child2.description) == "child node"
+    assert str(child2.props) == "OrderedDict([('child-prop', <Property, name: child-prop, type: int, value: 3>)])"
+
+    assert str(grandchild.binding_path) == hpath("test-bindings/child-binding.yaml")
+    assert str(grandchild.description) == "grandchild node"
+    assert str(grandchild.props) == "OrderedDict([('grandchild-prop', <Property, name: grandchild-prop, type: int, value: 2>)])"
+
+    with from_here():
+        binding_file = Path("test-bindings/child-binding.yaml").resolve()
+        top = edtlib.Binding(binding_file, {})
+    child = top.child_binding
+    assert Path(top.path) == binding_file
+    assert Path(child.path) == binding_file
+    assert top.compatible == 'top-binding'
+    assert child.compatible is None
+
+    with from_here():
+        binding_file = Path("test-bindings/child-binding-with-compat.yaml").resolve()
+        top = edtlib.Binding(binding_file, {})
+    child = top.child_binding
+    assert Path(top.path) == binding_file
+    assert Path(child.path) == binding_file
+    assert top.compatible == 'top-binding-with-compat'
+    assert child.compatible == 'child-compat'
+
+def test_props():
+    '''Test Node.props (derived from DT and 'properties:' in the binding)'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    filenames = {i: hpath(f'test-bindings/phandle-array-controller-{i}.yaml')
+                 for i in range(0, 4)}
+
+    assert str(edt.get_node("/props").props["int"]) == \
+        "<Property, name: int, type: int, value: 1>"
+
+    assert str(edt.get_node("/props").props["existent-boolean"]) == \
+        "<Property, name: existent-boolean, type: boolean, value: True>"
+
+    assert str(edt.get_node("/props").props["nonexistent-boolean"]) == \
+        "<Property, name: nonexistent-boolean, type: boolean, value: False>"
+
+    assert str(edt.get_node("/props").props["array"]) == \
+        "<Property, name: array, type: array, value: [1, 2, 3]>"
+
+    assert str(edt.get_node("/props").props["uint8-array"]) == \
+        r"<Property, name: uint8-array, type: uint8-array, value: b'\x124'>"
+
+    assert str(edt.get_node("/props").props["string"]) == \
+        "<Property, name: string, type: string, value: 'foo'>"
+
+    assert str(edt.get_node("/props").props["string-array"]) == \
+        "<Property, name: string-array, type: string-array, value: ['foo', 'bar', 'baz']>"
+
+    assert str(edt.get_node("/props").props["phandle-ref"]) == \
+        f"<Property, name: phandle-ref, type: phandle, value: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>>"
+
+    assert str(edt.get_node("/props").props["phandle-refs"]) == \
+        f"<Property, name: phandle-refs, type: phandles, value: [<Node /ctrl-1 in 'test.dts', binding {filenames[1]}>, <Node /ctrl-2 in 'test.dts', binding {filenames[2]}>]>"
+
+    assert str(edt.get_node("/props").props["phandle-array-foos"]) == \
+        f"<Property, name: phandle-array-foos, type: phandle-array, value: [<ControllerAndData, controller: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('one', 1)])>, <ControllerAndData, controller: <Node /ctrl-2 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 2), ('two', 3)])>]>"
+
+    assert str(edt.get_node("/props-2").props["phandle-array-foos"]) == \
+        ("<Property, name: phandle-array-foos, type: phandle-array, value: ["
+         f"<ControllerAndData, name: a, controller: <Node /ctrl-0-1 in 'test.dts', binding {filenames[0]}>, data: OrderedDict()>, "
+         "None, "
+         f"<ControllerAndData, name: b, controller: <Node /ctrl-0-2 in 'test.dts', binding {filenames[0]}>, data: OrderedDict()>]>")
+
+    assert str(edt.get_node("/props").props["foo-gpios"]) == \
+        f"<Property, name: foo-gpios, type: phandle-array, value: [<ControllerAndData, controller: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('gpio-one', 1)])>]>"
+
+    assert str(edt.get_node("/props").props["path"]) == \
+        f"<Property, name: path, type: path, value: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>>"
+
+def test_nexus():
+    '''Test <prefix>-map via gpio-map (the most common case).'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    filename = hpath('test-bindings/gpio-dst.yaml')
+
+    assert str(edt.get_node("/gpio-map/source").props["foo-gpios"]) == \
+        f"<Property, name: foo-gpios, type: phandle-array, value: [<ControllerAndData, controller: <Node /gpio-map/destination in 'test.dts', binding {filename}>, data: OrderedDict([('val', 6)])>, <ControllerAndData, controller: <Node /gpio-map/destination in 'test.dts', binding {filename}>, data: OrderedDict([('val', 5)])>]>"
+
+    assert str(edt.get_node("/gpio-map/source").props["foo-gpios"].val[0].basename) == f"gpio"
+
+def test_prop_defaults():
+    '''Test property default values given in bindings'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/defaults").props) == \
+        r"OrderedDict([('int', <Property, name: int, type: int, value: 123>), ('array', <Property, name: array, type: array, value: [1, 2, 3]>), ('uint8-array', <Property, name: uint8-array, type: uint8-array, value: b'\x89\xab\xcd'>), ('string', <Property, name: string, type: string, value: 'hello'>), ('string-array', <Property, name: string-array, type: string-array, value: ['hello', 'there']>), ('default-not-used', <Property, name: default-not-used, type: int, value: 234>)])"
+
+def test_prop_enums():
+    '''test properties with enum: in the binding'''
+
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    props = edt.get_node('/enums').props
+    int_enum = props['int-enum']
+    string_enum = props['string-enum']
+    tokenizable_enum = props['tokenizable-enum']
+    tokenizable_lower_enum = props['tokenizable-lower-enum']
+    no_enum = props['no-enum']
+
+    assert int_enum.val == 1
+    assert int_enum.enum_index == 0
+    assert not int_enum.spec.enum_tokenizable
+    assert not int_enum.spec.enum_upper_tokenizable
+
+    assert string_enum.val == 'foo_bar'
+    assert string_enum.enum_index == 1
+    assert not string_enum.spec.enum_tokenizable
+    assert not string_enum.spec.enum_upper_tokenizable
+
+    assert tokenizable_enum.val == '123 is ok'
+    assert tokenizable_enum.val_as_token == '123_is_ok'
+    assert tokenizable_enum.enum_index == 2
+    assert tokenizable_enum.spec.enum_tokenizable
+    assert tokenizable_enum.spec.enum_upper_tokenizable
+
+    assert tokenizable_lower_enum.val == 'bar'
+    assert tokenizable_lower_enum.val_as_token == 'bar'
+    assert tokenizable_lower_enum.enum_index == 0
+    assert tokenizable_lower_enum.spec.enum_tokenizable
+    assert not tokenizable_lower_enum.spec.enum_upper_tokenizable
+
+    assert no_enum.enum_index is None
+    assert not no_enum.spec.enum_tokenizable
+    assert not no_enum.spec.enum_upper_tokenizable
+
+def test_binding_inference():
+    '''Test inferred bindings for special zephyr-specific nodes.'''
+    warnings = io.StringIO()
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"], warnings)
+
+    assert str(edt.get_node("/zephyr,user").props) == r"OrderedDict()"
+
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"], warnings,
+                         infer_binding_for_paths=["/zephyr,user"])
+    filenames = {i: hpath(f'test-bindings/phandle-array-controller-{i}.yaml')
+                 for i in range(1, 3)}
+
+    assert str(edt.get_node("/zephyr,user").props) == \
+        rf"OrderedDict([('boolean', <Property, name: boolean, type: boolean, value: True>), ('bytes', <Property, name: bytes, type: uint8-array, value: b'\x81\x82\x83'>), ('number', <Property, name: number, type: int, value: 23>), ('numbers', <Property, name: numbers, type: array, value: [1, 2, 3]>), ('string', <Property, name: string, type: string, value: 'text'>), ('strings', <Property, name: strings, type: string-array, value: ['a', 'b', 'c']>), ('handle', <Property, name: handle, type: phandle, value: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>>), ('phandles', <Property, name: phandles, type: phandles, value: [<Node /ctrl-1 in 'test.dts', binding {filenames[1]}>, <Node /ctrl-2 in 'test.dts', binding {filenames[2]}>]>), ('phandle-array-foos', <Property, name: phandle-array-foos, type: phandle-array, value: [<ControllerAndData, controller: <Node /ctrl-2 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 1), ('two', 2)])>]>)])"
+
+def test_multi_bindings():
+    '''Test having multiple directories with bindings'''
+    with from_here():
+        edt = edtlib.EDT("test-multidir.dts", ["test-bindings", "test-bindings-2"])
+
+    assert str(edt.get_node("/in-dir-1").binding_path) == \
+        hpath("test-bindings/multidir.yaml")
+
+    assert str(edt.get_node("/in-dir-2").binding_path) == \
+        hpath("test-bindings-2/multidir.yaml")
+
+def test_dependencies():
+    ''''Test dependency relations'''
+    with from_here():
+        edt = edtlib.EDT("test-multidir.dts", ["test-bindings", "test-bindings-2"])
+
+    assert edt.get_node("/").dep_ordinal == 0
+    assert edt.get_node("/in-dir-1").dep_ordinal == 1
+    assert edt.get_node("/") in edt.get_node("/in-dir-1").depends_on
+    assert edt.get_node("/in-dir-1") in edt.get_node("/").required_by
+
+def test_slice_errs(tmp_path):
+    '''Test error messages from the internal _slice() helper'''
+
+    dts_file = tmp_path / "error.dts"
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <2>;
+
+	sub {
+		reg = <3>;
+	};
+};
+""",
+                 dts_file,
+                 f"'reg' property in <Node /sub in '{dts_file}'> has length 4, which is not evenly divisible by 12 (= 4*(<#address-cells> (= 1) + <#size-cells> (= 2))). Note that #*-cells properties come either from the parent node or from the controller (in the case of 'interrupts').")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	sub {
+		interrupts = <1>;
+		interrupt-parent = < &{/controller} >;
+	};
+	controller {
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+""",
+                 dts_file,
+                 f"'interrupts' property in <Node /sub in '{dts_file}'> has length 4, which is not evenly divisible by 8 (= 4*<#interrupt-cells>). Note that #*-cells properties come either from the parent node or from the controller (in the case of 'interrupts').")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+
+	sub-1 {
+		#address-cells = <2>;
+		#size-cells = <3>;
+		ranges = <4 5>;
+
+		sub-2 {
+			reg = <1 2 3 4 5>;
+		};
+	};
+};
+""",
+                 dts_file,
+                 f"'ranges' property in <Node /sub-1 in '{dts_file}'> has length 8, which is not evenly divisible by 24 (= 4*(<#address-cells> (= 2) + <#address-cells for parent> (= 1) + <#size-cells> (= 3))). Note that #*-cells properties come either from the parent node or from the controller (in the case of 'interrupts').")
+
+def test_bad_compatible(tmp_path):
+    # An invalid compatible should cause an error, even on a node with
+    # no binding.
+
+    dts_file = tmp_path / "error.dts"
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo {
+		compatible = "no, whitespace";
+	};
+};
+""",
+                 dts_file,
+                 r"node '/foo' compatible 'no, whitespace' must match this regular expression: '^[a-zA-Z][a-zA-Z0-9,+\-._]+$'")
+
+def test_wrong_props():
+    '''Test Node.wrong_props (derived from DT and 'properties:' in the binding)'''
+
+    with from_here():
+        with pytest.raises(edtlib.EDTError) as e:
+            edtlib.Binding("test-wrong-bindings/wrong-specifier-space-type.yaml", None)
+        assert ("'specifier-space' in 'properties: wrong-type-for-specifier-space' has type 'phandle', expected 'phandle-array'"
+            in str(e.value))
+
+        with pytest.raises(edtlib.EDTError) as e:
+            edtlib.Binding("test-wrong-bindings/wrong-phandle-array-name.yaml", None)
+        value_str = str(e.value)
+        assert value_str.startswith("'wrong-phandle-array-name' in 'properties:'")
+        assert value_str.endswith("but no 'specifier-space' was provided.")
+
+
+def verify_error(dts, dts_file, expected_err):
+    # Verifies that parsing a file 'dts_file' with the contents 'dts'
+    # (a string) raises an EDTError with the message 'expected_err'.
+    #
+    # The path 'dts_file' is written with the string 'dts' before the
+    # test is run.
+
+    with open(dts_file, "w", encoding="utf-8") as f:
+        f.write(dts)
+        f.flush()  # Can't have unbuffered text IO, so flush() instead
+
+    with pytest.raises(edtlib.EDTError) as e:
+        edtlib.EDT(dts_file, [])
+
+    assert str(e.value) == expected_err

Tools/dts/python-devicetree/tox.ini

@@ -0,0 +1,19 @@
+[tox]
+envlist=py3
+
+[testenv]
+deps =
+    setuptools-scm
+    pytest
+    types-PyYAML
+    mypy
+setenv =
+    TOXTEMPDIR={envtmpdir}
+commands =
+  python -m pytest {posargs:tests}
+  python -m mypy --config-file={toxinidir}/tox.ini --package=devicetree
+
+[mypy]
+mypy_path=src
+ignore_missing_imports=True
+

boards/px4/fmu-v5x/board.dts

@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2021 PX4
+ *
+ * SPDX-License-Identifier:
+ */
+
+/dts-v1/;
+
+#include <mem.h> // DT_SIZE_K()
+
+#include <st/f7/stm32f765.dtsi>
+#include <st/f7/stm32f765i(g-i)tx-pinctrl.dtsi>
+
+/ {
+	model = "PX4 FMUv5x";
+	compatible = "px4,px4_fmu-v5x";
+
+	chosen {
+		//zephyr,console = &usart1;
+		//zephyr,shell-uart = &usart1;
+		//zephyr,sram = &sram0;
+		//zephyr,flash = &flash0;
+		//zephyr,dtcm = &dtcm;
+		//zephyr,flash-controller = &mx25l51245g;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		red_led_1:led_1 {
+			gpios = <&gpioe 3 GPIO_ACTIVE_LOW>;
+			label = "LED RED";
+		};
+		green_led_2:led_2 {
+			gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+			label = "LED GREEN";
+		};
+		blue_led_3:led_3 {
+			gpios = <&gpioe 5 GPIO_ACTIVE_LOW>;
+			label = "LED BLUE";
+		};
+	};
+
+	aliases {
+		led0 = &red_led_1;
+		led1 = &green_led_2;
+		led2 = &blue_led_3;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(16)>;
+	status = "okay";
+};
+
+&pll {
+	div-m = <8>;
+	mul-n = <216>;
+	div-p = <2>;
+	div-q = <9>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(216)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <4>;
+	apb2-prescaler = <2>;
+};
+
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usart2 {
+	pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pa3>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usart3 {
+	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_ph14>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-0 = <&uart5_tx_pb9 &uart5_rx_pd2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usart6 {
+	pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-0 = <&uart7_tx_pe8 &uart7_rx_pf6>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart8 {
+	pinctrl-0 = <&uart8_tx_pe1 &uart8_rx_pe0>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3 {
+	pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c4 {
+	pinctrl-0 = <&i2c4_scl_pf14 &i2c4_sda_pf15>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pb4 &spi1_mosi_pb5>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi2 {
+	pinctrl-0 = <&spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi3 {
+	pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pb2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi5 {
+	pinctrl-0 = <&spi5_sck_pf7 &spi5_miso_pf8 &spi5_mosi_pf11>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi6 {
+	pinctrl-0 = <&spi6_sck_pb3 &spi6_miso_pa6 &spi6_mosi_pg14>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+
+&mac {
+	status = "okay";
+	pinctrl-0 = <&eth_mdc_pc1
+		     &eth_rxd0_pc4
+		     &eth_rxd1_pc5
+		     &eth_ref_clk_pa1
+		     &eth_mdio_pa2
+		     &eth_crs_dv_pa7
+		     &eth_tx_en_pb11
+		     &eth_txd0_pg13
+		     &eth_txd1_pb13>;
+	pinctrl-names = "default";
+};
+
+
+&sdmmc2 {
+	status = "okay";
+	pinctrl-0 = <&sdmmc2_d0_pg9  &sdmmc2_d1_pg10
+		     &sdmmc2_d2_pg11 &sdmmc2_d3_pg12
+		     &sdmmc2_ck_pd6  &sdmmc2_cmd_pd7>;
+	pinctrl-names = "default";
+	cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
+};

boards/px4/fmu-v5x/src/init.cpp

@@ -77,6 +77,8 @@ extern "C" {
 #include <px4_platform/board_dma_alloc.h>
 #include <px4_platform/gpio/mcp23009.hpp>
 
+#include <include/devicetree.h>
+
 /****************************************************************************
  * Pre-Processor Definitions
  ****************************************************************************/
@@ -296,5 +298,8 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 		}
 	}
 
+	printf("DT_LABEL: %s\n", DT_LABEL(DT_NODELABEL(usart1)));
+
+
 	return OK;
 }

cmake/dts.cmake

@@ -0,0 +1,281 @@
+# SPDX-License-Identifier: Apache-2.0
+
+file(MAKE_DIRECTORY ${PX4_BINARY_DIR}/dts/include/generated)
+
+function(check_dtc_flag flag ok)
+  execute_process(
+    COMMAND
+    ${DTC} ${flag} -v
+    ERROR_QUIET
+    OUTPUT_QUIET
+    RESULT_VARIABLE dtc_check_ret
+  )
+  if (dtc_check_ret EQUAL 0)
+    set(${ok} 1 PARENT_SCOPE)
+  else()
+    set(${ok} 0 PARENT_SCOPE)
+  endif()
+endfunction()
+
+# Zephyr code can configure itself based on a KConfig'uration with the
+# header file autoconf.h. There exists an analogous file devicetree_unfixed.h
+# that allows configuration based on information encoded in DTS.
+#
+# Here we call on dtc, the gcc preprocessor and
+# scripts/dts/gen_defines.py to generate various DT-related files at
+# CMake configure-time.
+#
+# See the Devicetree user guide in the Zephyr documentation for details.
+set(GEN_DEFINES_SCRIPT          ${PX4_SOURCE_DIR}/Tools/dts/gen_defines.py)
+set(BOARD_DTS                   ${PX4_BINARY_DIR}/dts/board.dts)
+# This contains the edtlib.EDT object created from zephyr.dts in Python's
+# pickle data marshalling format (https://docs.python.org/3/library/pickle.html)
+#
+# Its existence is an implementation detail used to speed up further
+# use of the devicetree by processes that run later on in the build,
+# and should not be made part of the documentation.
+set(EDT_PICKLE                  ${PX4_BINARY_DIR}/dts/edt.pickle)
+set(DEVICETREE_UNFIXED_H        ${PX4_BINARY_DIR}/dts/include/generated/devicetree_unfixed.h)
+set(DEVICE_EXTERN_H             ${PX4_BINARY_DIR}/dts/include/generated/device_extern.h)
+set(DTS_POST_CPP                ${PX4_BINARY_DIR}/dts/px4.dts.pre)
+set(DTS_DEPS                    ${PX4_BINARY_DIR}/dts/px4.dts.d)
+# The location of a list of known vendor prefixes.
+# This is relative to each element of DTS_ROOT.
+set(VENDOR_PREFIXES             dts/bindings/vendor-prefixes.txt)
+
+# Devicetree in CMake.
+set(DTS_CMAKE_SCRIPT            ${PX4_SOURCE_DIR}/Tools/dts/gen_dts_cmake.py)
+set(DTS_CMAKE                   ${PX4_BINARY_DIR}/dts/dts.cmake)
+
+set(DTS_SOURCE ${PX4_BOARD_DIR}/board.dts)
+
+# 'DTS_ROOT' is a list of directories where a directory tree with DT
+# files may be found. It always includes the application directory,
+# the board directory, and ${ZEPHYR_BASE}.
+list(APPEND DTS_ROOT
+  ${PX4_BOARD_DIR}
+  ${PX4_SOURCE_DIR}
+)
+list(REMOVE_DUPLICATES DTS_ROOT)
+
+# TODO: What to do about non-posix platforms where NOT CONFIG_HAS_DTS (xtensa)?
+# Drop support for NOT CONFIG_HAS_DTS perhaps?
+if(EXISTS ${DTS_SOURCE})
+  set(SUPPORTS_DTS 1)
+  if(BOARD_REVISION AND EXISTS ${PX4_BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.overlay)
+    list(APPEND DTS_SOURCE ${PX4_BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.overlay)
+  endif()
+else()
+  set(SUPPORTS_DTS 0)
+endif()
+
+set(dts_files
+  ${DTS_SOURCE}
+  ${shield_dts_files}
+  )
+
+if(SUPPORTS_DTS)
+  if(DTC_OVERLAY_FILE)
+    # Convert from space-separated files into file list
+    string(REPLACE " " ";" DTC_OVERLAY_FILE_RAW_LIST "${DTC_OVERLAY_FILE}")
+    foreach(file ${DTC_OVERLAY_FILE_RAW_LIST})
+      file(TO_CMAKE_PATH "${file}" cmake_path_file)
+      list(APPEND DTC_OVERLAY_FILE_AS_LIST ${cmake_path_file})
+    endforeach()
+    list(APPEND
+      dts_files
+      ${DTC_OVERLAY_FILE_AS_LIST}
+      )
+  endif()
+
+  set(i 0)
+  unset(DTC_INCLUDE_FLAG_FOR_DTS)
+  foreach(dts_file ${dts_files})
+    list(APPEND DTC_INCLUDE_FLAG_FOR_DTS
+         -include ${dts_file})
+
+    if(i EQUAL 0)
+      message(STATUS "Found BOARD.dts: ${dts_file}")
+    else()
+      message(STATUS "Found devicetree overlay: ${dts_file}")
+    endif()
+
+    math(EXPR i "${i}+1")
+  endforeach()
+
+  unset(DTS_ROOT_SYSTEM_INCLUDE_DIRS)
+  unset(DTS_ROOT_BINDINGS)
+  foreach(dts_root ${DTS_ROOT})
+    foreach(dts_root_path
+        src/include
+        dts/common
+        dts/${CONFIG_ARCH}
+        dts
+        platforms/nuttx/src/px4/stm/hal_stm32/dts
+        )
+      get_filename_component(full_path ${dts_root}/${dts_root_path} REALPATH)
+      if(EXISTS ${full_path})
+        list(APPEND
+          DTS_ROOT_SYSTEM_INCLUDE_DIRS
+          -isystem ${full_path}
+          )
+      endif()
+    endforeach()
+
+    set(bindings_path ${dts_root}/dts/bindings)
+    if(EXISTS ${bindings_path})
+      list(APPEND
+        DTS_ROOT_BINDINGS
+        ${bindings_path}
+        )
+    endif()
+
+    set(vendor_prefixes ${dts_root}/${VENDOR_PREFIXES})
+    if(EXISTS ${vendor_prefixes})
+      list(APPEND EXTRA_GEN_DEFINES_ARGS --vendor-prefixes ${vendor_prefixes})
+    endif()
+  endforeach()
+
+  # Cache the location of the root bindings so they can be used by
+  # scripts which use the build directory.
+  set(CACHED_DTS_ROOT_BINDINGS ${DTS_ROOT_BINDINGS} CACHE INTERNAL
+    "DT bindings root directories")
+
+  if(NOT DEFINED CMAKE_DTS_PREPROCESSOR)
+    set(CMAKE_DTS_PREPROCESSOR ${CMAKE_C_COMPILER})
+  endif()
+
+  # TODO: Cut down on CMake configuration time by avoiding
+  # regeneration of devicetree_unfixed.h on every configure. How
+  # challenging is this? What are the dts dependencies? We run the
+  # preprocessor, and it seems to be including all kinds of
+  # directories with who-knows how many header files.
+
+  # Run the preprocessor on the DTS input files. We are leaving
+  # linemarker directives enabled on purpose. This tells dtlib where
+  # each line actually came from, which improves error reporting.
+  execute_process(
+    COMMAND ${CMAKE_DTS_PREPROCESSOR}
+    -x assembler-with-cpp
+    -nostdinc
+    ${DTS_ROOT_SYSTEM_INCLUDE_DIRS}
+    ${DTC_INCLUDE_FLAG_FOR_DTS}  # include the DTS source and overlays
+    ${NOSYSDEF_CFLAG}
+    -D__DTS__
+    ${DTS_EXTRA_CPPFLAGS}
+    -E   # Stop after preprocessing
+    -MD  # Generate a dependency file as a side-effect
+    -MF ${DTS_DEPS}
+    -o ${DTS_POST_CPP}
+    ${PX4_SOURCE_DIR}/platforms/common/empty.c
+    WORKING_DIRECTORY ${PX4_SOURCE_DIR}
+    RESULT_VARIABLE ret
+    )
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "command failed with return code: ${ret}")
+  endif()
+
+  # Parse the generated dependency file to find the DT sources that
+  # were included, including any transitive includes, and then add
+  # them to the list of files that trigger a re-run of CMake.
+  # toolchain_parse_make_rule(${DTS_DEPS}
+  #   include_files # Output parameter
+  #   )
+
+  # set_property(DIRECTORY APPEND PROPERTY
+  #   CMAKE_CONFIGURE_DEPENDS
+  #   ${include_files}
+  #   ${GEN_DEFINES_SCRIPT}
+  #   ${DTS_CMAKE_SCRIPT}
+  #   )
+
+  #
+  # Run gen_defines.py to create a header file, zephyr.dts, and edt.pickle.
+  #
+
+  string(REPLACE ";" " " EXTRA_DTC_FLAGS_RAW "${EXTRA_DTC_FLAGS}")
+  set(CMD_EXTRACT ${PYTHON_EXECUTABLE} ${GEN_DEFINES_SCRIPT}
+  --dts ${DTS_POST_CPP}
+  --dtc-flags '${EXTRA_DTC_FLAGS_RAW}'
+  --bindings-dirs ${DTS_ROOT_BINDINGS}
+  --header-out ${DEVICETREE_UNFIXED_H}
+  --device-header-out ${DEVICE_EXTERN_H}
+  --dts-out ${BOARD_DTS} # for debugging and dtc
+  --edt-pickle-out ${EDT_PICKLE}
+  ${EXTRA_GEN_DEFINES_ARGS}
+  )
+
+  execute_process(
+    COMMAND ${CMD_EXTRACT}
+    WORKING_DIRECTORY ${PX4_BINARY_DIR}
+    RESULT_VARIABLE ret
+    )
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "gen_defines.py failed with return code: ${ret}")
+  else()
+    message(STATUS "Generated zephyr.dts: ${BOARD_DTS}")
+    message(STATUS "Generated devicetree_unfixed.h: ${DEVICETREE_UNFIXED_H}")
+    message(STATUS "Generated device_extern.h: ${DEVICE_EXTERN_H}")
+  endif()
+
+  execute_process(
+    COMMAND ${PYTHON_EXECUTABLE} ${DTS_CMAKE_SCRIPT}
+    --edt-pickle ${EDT_PICKLE}
+    --cmake-out ${DTS_CMAKE}
+    WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+    RESULT_VARIABLE ret
+    )
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "gen_dts_cmake.py failed with return code: ${ret}")
+  else()
+    message(STATUS "Including generated dts.cmake file: ${DTS_CMAKE}")
+    include(${DTS_CMAKE})
+  endif()
+
+  #
+  # Run dtc on the final devicetree source, just to catch any
+  # warnings/errors from it. dtlib and edtlib parse the devicetree files
+  # themselves, so we don't rely on dtc otherwise.
+  #
+
+  if(DTC)
+  set(DTC_WARN_UNIT_ADDR_IF_ENABLED "")
+  check_dtc_flag("-Wunique_unit_address_if_enabled" check)
+  if (check)
+    set(DTC_WARN_UNIT_ADDR_IF_ENABLED "-Wunique_unit_address_if_enabled")
+  endif()
+  set(DTC_NO_WARN_UNIT_ADDR "")
+  check_dtc_flag("-Wno-unique_unit_address" check)
+  if (check)
+    set(DTC_NO_WARN_UNIT_ADDR "-Wno-unique_unit_address")
+  endif()
+  set(VALID_EXTRA_DTC_FLAGS "")
+  foreach(extra_opt ${EXTRA_DTC_FLAGS})
+    check_dtc_flag(${extra_opt} check)
+    if (check)
+      list(APPEND VALID_EXTRA_DTC_FLAGS ${extra_opt})
+    endif()
+  endforeach()
+  set(EXTRA_DTC_FLAGS ${VALID_EXTRA_DTC_FLAGS})
+  execute_process(
+    COMMAND ${DTC}
+    -O dts
+    -o - # Write output to stdout, which we discard below
+    -b 0
+    -E unit_address_vs_reg
+    ${DTC_NO_WARN_UNIT_ADDR}
+    ${DTC_WARN_UNIT_ADDR_IF_ENABLED}
+    ${EXTRA_DTC_FLAGS} # User settable
+    ${BOARD_DTS}
+    OUTPUT_QUIET # Discard stdout
+    WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+    RESULT_VARIABLE ret
+    )
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "command failed with return code: ${ret}")
+  endif()
+  endif(DTC)
+else()
+  file(WRITE ${DEVICETREE_UNFIXED_H} "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */")
+  file(WRITE ${DEVICE_EXTERN_H} "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */")
+endif(SUPPORTS_DTS)

dts/Kconfig

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+
+config HAS_DTS
+	bool
+	help
+	  This option specifies that the target platform supports device tree
+	  configuration.
+
+config HAS_DTS_GPIO
+	bool
+	depends on HAS_DTS
+	help
+	  This option specifies that the target platform supports device tree
+	  configuration for GPIO.
+
+config HAS_DTS_WDT
+	bool
+	depends on HAS_DTS
+	help
+	  This option specifies that the target platform supports device tree
+	  configuration for WDT.

dts/arm/armv6-m.dtsi

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&nvic>;
+		ranges;
+
+		nvic: interrupt-controller@e000e100  {
+			#address-cells = <1>;
+			compatible = "arm,v6m-nvic";
+			reg = <0xe000e100 0xc00>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		systick: timer@e000e010 {
+			compatible = "arm,armv6m-systick";
+			reg = <0xe000e010 0x10>;
+		};
+	};
+};
+

dts/arm/armv7-a.dtsi

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};

dts/arm/armv7-m.dtsi

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&nvic>;
+		ranges;
+
+		nvic: interrupt-controller@e000e100  {
+			#address-cells = <1>;
+			compatible = "arm,v7m-nvic";
+			reg = <0xe000e100 0xc00>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		systick: timer@e000e010 {
+			compatible = "arm,armv7m-systick";
+			reg = <0xe000e010 0x10>;
+		};
+	};
+};
+

dts/arm/armv7-r.dtsi

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};

dts/arm/nxp/nxp_k66.dtsi

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020 DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <nxp/nxp_k6x.dtsi>
+
+&flash0 {
+	reg = <0x00000000 DT_SIZE_M(2)>;
+};
+
+/ {
+	soc {
+		lpuart0: lpuart@400c4000 {
+			compatible = "nxp,kinetis-lpuart";
+			reg = <0x400c4000 0x14>;
+			interrupts = <86 0>;
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>;
+			label = "LPUART_0";
+			status = "disabled";
+		};
+
+		flexcan1: can@400a4000 {
+			compatible = "nxp,kinetis-flexcan";
+			reg = <0x400a4000 0x1000>;
+			interrupts = <94 0>, <95 0>, <96 0>, <97 0>, <98 0>, <99 0>;
+			interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning",
+			    "rx-warning", "wake-up";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 4>;
+			clk-source = <1>;
+			label = "CAN_1";
+			sjw = <1>;
+			prop-seg = <1>;
+			phase-seg1 = <3>;
+			phase-seg2 = <2>;
+			status = "disabled";
+		  };
+	};
+};

dts/arm/nxp/nxp_k6x.dtsi

@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <mem.h>
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/kinetis_sim.h>
+#include <dt-bindings/clock/kinetis_mcg.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+	aliases {
+		watchdog0 = &wdog;
+	};
+
+	chosen {
+		zephyr,entropy = &rnga;
+		zephyr,flash-controller = &ftfe;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
+	 * contiguous block in the memory map, however misaligned accesses
+	 * across the 0x2000_0000 boundary are not supported in the Arm
+	 * Cortex-M4 architecture. For clarity and to avoid the temptation for
+	 * someone to extend sram0 without solving this issue, we define two
+	 * separate memory nodes here and only use the upper one for now. A
+	 * potential solution has been proposed in binutils:
+	 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
+	 */
+	sram_l: memory@1fff0000 {
+		compatible = "mmio-sram";
+		reg = <0x1fff0000 DT_SIZE_K(64)>;
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	temp0: temp0 {
+		compatible = "nxp,kinetis-temperature";
+		io-channels = <&adc0 26>, <&adc0 27>;
+		io-channel-names = "SENSOR", "BANDGAP";
+		bandgap-voltage = <1000000>;
+		vtemp25 = <716000>;
+		sensor-slope-cold = <1620>;
+		sensor-slope-hot = <1620>;
+		label = "TEMP0";
+		status = "disabled";
+	};
+
+	temp1: temp1 {
+		compatible = "nxp,kinetis-temperature";
+		io-channels = <&adc1 26>, <&adc1 27>;
+		io-channel-names = "SENSOR", "BANDGAP";
+		bandgap-voltage = <1000000>;
+		vtemp25 = <716000>;
+		sensor-slope-cold = <1620>;
+		sensor-slope-hot = <1620>;
+		label = "TEMP1";
+		status = "disabled";
+	};
+
+	soc {
+		mpu: mpu@4000d000 {
+			compatible = "nxp,k64f-mpu";
+			reg = <0x4000d000 0x824>;
+
+			status = "disabled";
+		};
+
+		mcg: clock-controller@40064000 {
+			compatible = "nxp,kinetis-mcg";
+			reg = <0x40064000 0xd>;
+			label = "MCG";
+			#clock-cells = <1>;
+		};
+
+		osc: clock-controller@40065000 {
+			compatible = "nxp,k64f-osc";
+			reg = <0x40065000 0x4>;
+
+			enable-external-reference;
+		};
+
+		rtc: rtc@4003d000 {
+			compatible = "nxp,kinetis-rtc";
+			reg = <0x4003d000 0x1000>;
+			interrupts = <46 0>, <47 0>;
+			interrupt-names = "alarm", "seconds";
+			clock-frequency = <32768>;
+			prescaler = <32768>;
+			label = "RTC_0";
+		};
+
+		sim: sim@40047000 {
+			compatible = "nxp,kinetis-sim";
+			reg = <0x40047000 0x1060>;
+			label = "SIM";
+			#clock-cells = <3>;
+
+			core_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <1>;
+				#clock-cells = <0>;
+			};
+
+			bus_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <2>;
+				#clock-cells = <0>;
+			};
+
+			flexbus_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <3>;
+				#clock-cells = <0>;
+			};
+
+			flash_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <5>;
+				#clock-cells = <0>;
+			};
+		};
+
+		ftfe: flash-controller@40020000 {
+			compatible = "nxp,kinetis-ftfe";
+			label = "FLASH_CTRL";
+			reg = <0x40020000 0x18>;
+			interrupts = <18 0>, <19 0>;
+			interrupt-names = "command-complete", "read-collision";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				label = "MCUX_FLASH";
+				reg = <0 DT_SIZE_M(1)>;
+				erase-block-size = <4096>;
+				write-block-size = <8>;
+			};
+		};
+
+		i2c0: i2c@40066000 {
+			compatible = "nxp,kinetis-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40066000 0x1000>;
+			interrupts = <24 0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
+			label = "I2C_0";
+			status = "disabled";
+		};
+
+		i2c1: i2c@40067000 {
+			compatible = "nxp,kinetis-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40067000 0x1000>;
+			interrupts = <25 0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
+			label = "I2C_1";
+			status = "disabled";
+		};
+
+		i2c2: i2c@400e6000 {
+			compatible = "nxp,kinetis-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x400e6000 0x1000>;
+			interrupts = <74 0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
+			label = "I2C_2";
+			status = "disabled";
+		};
+
+		uart0: uart@4006a000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006a000 0x1000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
+			label = "UART_0";
+
+			status = "disabled";
+		};
+
+		uart1: uart@4006b000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006b000 0x1000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
+			label = "UART_1";
+
+			status = "disabled";
+		};
+
+		uart2: uart@4006c000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006c000 0x1000>;
+			interrupts = <35 0>, <36 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
+			label = "UART_2";
+
+			status = "disabled";
+		};
+
+		uart3: uart@4006d000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006d000 0x1000>;
+			interrupts = <37 0>, <38 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
+			label = "UART_3";
+
+			status = "disabled";
+		};
+
+		uart4: uart@400ea000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x400ea000 0x1000>;
+			interrupts = <66 0>, <67 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
+			label = "UART_4";
+
+			status = "disabled";
+		};
+
+		uart5: uart@400eb000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x400eb000 0x1000>;
+			interrupts = <68 0>, <69 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
+			label = "UART_5";
+
+			status = "disabled";
+		};
+
+		porta: pinmux@40049000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x40049000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
+		};
+
+		portb: pinmux@4004a000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004a000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
+		};
+
+		portc: pinmux@4004b000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004b000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
+		};
+
+		portd: pinmux@4004c000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004c000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
+		};
+
+		porte: pinmux@4004d000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004d000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
+		};
+
+		gpioa: gpio@400ff000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff000 0x40>;
+			interrupts = <59 2>;
+			label = "GPIO_0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porta>;
+		};
+
+		gpiob: gpio@400ff040 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff040 0x40>;
+			interrupts = <60 2>;
+			label = "GPIO_1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portb>;
+		};
+
+		gpioc: gpio@400ff080 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff080 0x40>;
+			interrupts = <61 2>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portc>;
+		};
+
+		gpiod: gpio@400ff0c0 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff0c0 0x40>;
+			interrupts = <62 2>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portd>;
+		};
+
+		gpioe: gpio@400ff100 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff100 0x40>;
+			interrupts = <63 2>;
+			label = "GPIO_4";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porte>;
+		};
+
+		spi0: spi@4002c000 {
+			compatible = "nxp,kinetis-dspi";
+			reg = <0x4002c000 0x88>;
+			interrupts = <26 3>;
+			label = "SPI_0";
+			dmas = <&edma0 0 14>, <&edma0 0 15>;
+			dma-names = "rx", "tx";
+			rx-fifo-size = <4>;
+			tx-fifo-size = <4>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@4002d000 {
+			compatible = "nxp,kinetis-dspi";
+			reg = <0x4002d000 0x88>;
+			interrupts = <27 3>;
+			label = "SPI_1";
+			dmas = <&edma0 0 16>, <&edma0 0 16>;
+			dma-names = "rx", "tx";
+			rx-fifo-size = <1>;
+			tx-fifo-size = <1>;
+			nxp,rx-tx-chn-share;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi@400ac000 {
+			compatible = "nxp,kinetis-dspi";
+			reg = <0x400ac000 0x88>;
+			interrupts = <65 3>;
+			label = "SPI_2";
+			dmas = <&edma0 0 17>, <&edma0 0 17>;
+			dma-names = "rx", "tx";
+			rx-fifo-size = <1>;
+			tx-fifo-size = <1>;
+			nxp,rx-tx-chn-share;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		wdog: watchdog@40052000 {
+			compatible = "nxp,kinetis-wdog";
+			reg = <0x40052000 16>;
+			interrupts = <22 0>;
+			clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
+			label = "WDT_0";
+		};
+
+		ftm0: ftm@40038000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x40038000 0x98>;
+			interrupts = <42 0>;
+			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
+			prescaler = <16>;
+			label = "FTM_0";
+			status = "disabled";
+		};
+
+		ftm1: ftm@40039000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x40039000 0x98>;
+			interrupts = <43 0>;
+			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
+			prescaler = <16>;
+			label = "FTM_1";
+			status = "disabled";
+		};
+
+		ftm2: ftm@4003a000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x4003a000 0x98>;
+			interrupts = <44 0>;
+			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
+			prescaler = <16>;
+			label = "FTM_2";
+			status = "disabled";
+		};
+
+		ftm3: ftm@400b9000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x400b9000 0x98>;
+			interrupts = <71 0>;
+			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
+			prescaler = <16>;
+			label = "FTM_3";
+			status = "disabled";
+		};
+
+		adc0: adc@4003b000{
+			compatible = "nxp,kinetis-adc16";
+			reg = <0x4003b000 0x70>;
+			clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>,
+				<&sim KINETIS_SIM_SIM_SOPT7 7 0x80>;
+			dmas = <&edma0 0 40>;
+			dma-names = "adc0";
+			clk-source = <0>;
+			interrupts = <39 0>;
+			label = "ADC_0";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		adc1: adc@400bb000{
+			compatible = "nxp,kinetis-adc16";
+			reg = <0x400bb000 0x70>;
+			clocks = <&sim KINETIS_SIM_SIM_SOPT7 8 0xF00>,
+				<&sim KINETIS_SIM_SIM_SOPT7 15 0x8000>;
+			dmas = <&edma0 0 41>;
+			dma-names = "adc1";
+			clk-source = <0>;
+			interrupts = <73 0>;
+			label = "ADC_1";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		dac0: dac@400cc000 {
+			compatible = "nxp,kinetis-dac";
+			reg = <0x400cc000 0x1000>;
+			interrupts = <56 0>;
+			voltage-reference = <1>;
+			label = "DAC_0";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		dac1: dac@400cd000 {
+			compatible = "nxp,kinetis-dac";
+			reg = <0x400cd000 0x1000>;
+			interrupts = <72 0>;
+			voltage-reference = <1>;
+			label = "DAC_1";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		usbotg: usbd@40072000 {
+			compatible = "nxp,kinetis-usbd";
+			reg = <0x40072000 0x1000>;
+			interrupts = <53 1>;
+			interrupt-names = "usb_otg";
+			num-bidir-endpoints = <16>;
+			status = "disabled";
+			label = "USBD";
+		};
+
+		enet: ethernet@400c0000 {
+			compatible = "nxp,kinetis-ethernet";
+			reg = <0x400c0000 0x620>;
+			interrupts = <83 0>, <84 0>, <85 0>;
+			interrupt-names = "TX", "RX", "ERR";
+			status = "disabled";
+			label = "ETH_0";
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0 0>;
+			ptp {
+				compatible = "nxp,kinetis-ptp";
+				status = "disabled";
+				interrupts = <82 0>;
+				interrupt-names = "IEEE1588_TMR";
+			};
+		};
+
+		rnga: random@40029000 {
+			compatible = "nxp,kinetis-rnga";
+			reg = <0x40029000 0x1000>;
+			status = "okay";
+			interrupts = <23 0>;
+			label = "RNGA";
+		};
+
+		flexcan0: can@40024000 {
+			compatible = "nxp,kinetis-flexcan";
+			reg = <0x40024000 0x1000>;
+			interrupts = <75 0>, <76 0>, <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", "rx-warning", "wake-up";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 4>;
+			clk-source = <1>;
+			label = "CAN_0";
+			sjw = <1>;
+			sample-point = <875>;
+			status = "disabled";
+		};
+
+		edma0: dma-controller@40008000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <16>;
+			dma-requests = <64>;
+			nxp,mem2mem;
+			reg = <0x40008000 0x1000>,
+				<0x40021000 0x1000>;
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+			clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>,
+				<&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>;
+			status = "disabled";
+			label = "DMA_0";
+		};
+
+		pit0: pit@40037000 {
+			compatible = "nxp,kinetis-pit";
+			reg = <0x40037000 0x1000>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
+			interrupts = <48 0>, <49 0>, <50 0>, <51 0>;
+			status = "disabled";
+			pit-channel = <0>;
+			pit-period = <1000000>;
+			clock-frequency = <60000000>;
+			label = "PIT0";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

dts/arm/nxp/nxp_rt1060.dtsi

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019, Linaro
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt.dtsi>
+
+/* i.MX rt1060 has two continuous on-chip RAM, one is part of the
+ * FlexRAM mapped at 0x20280000 (vs 0x20280000 on rt1050) and is
+ * configurable (256KB by defaults), the other one is dedicated 512KB
+ * ram (OCRAM2) mapped at 0x20200000. In order to have a continuous
+ * region, we describe them in one 768Kb unique node.
+ */
+&ocram {
+	compatible = "mmio-sram";
+	reg = <0x20200000 DT_SIZE_K(768)>;
+};
+
+/* i.MX rt1060 has a second Ethernet controller. */
+/ {
+	soc {
+		enet2: ethernet@402d4000 {
+			compatible = "nxp,kinetis-ethernet";
+			reg = <0x402D4000 0x628>;
+			interrupts = <152 0>;
+			interrupt-names = "COMMON";
+			status = "disabled";
+			label = "ETH_1";
+			ptp {
+				compatible = "nxp,kinetis-ptp";
+				status = "disabled";
+				interrupts = <153 0>;
+				interrupt-names = "IEEE1588_TMR";
+			};
+		};
+	};
+};

dts/arm/nxp/nxp_rt1064.dtsi

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019, Linaro
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt1060.dtsi>
+
+&flexspi2 {
+	reg = <0x402a4000 0x4000>, <0x70000000 DT_SIZE_M(4)>;
+	/* WINBOND */
+	w25q32jvwj0: w25q32jvwj@0 {
+		compatible = "nxp,imx-flexspi-nor";
+		size = <33554432>;
+		label = "W25Q32JVWJ0";
+		reg = <0>;
+		spi-max-frequency = <133000000>;
+		status = "okay";
+		jedec-id = [ef 40 16];
+		erase-block-size = <4096>;
+		write-block-size = <1>;
+	};
+};

dts/arm/nxp/nxp_rt1160_cm4.dtsi

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt11xx.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	/*
+	 * SRAM0 & SRAM1 are available only to the M4 core. EDMA_LPSR interrupts are connected
+	 * to the M4 core alone, hence this EDMA controller has been designated M4 only.
+	 * GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are
+	 * only accesssible to the M4.
+	 *
+	 * Refer to Chapter 3 of the Reference Manual
+	 */
+	soc {
+		sram0: memory@1ffe0000 {
+			compatible = "mmio-sram";
+			reg = <0x1ffe0000 DT_SIZE_K(128)>;
+		};
+
+		sram1: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(128)>;
+		};
+
+		/*
+		 * M4 uses different addresses from the M7 core for GPIO2 and
+		 * GPIO3, see pg. 1364 of RT1160 ref manual for example
+		 */
+		gpio2: gpio@40130000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x40130000 0x4000>;
+			interrupts = <102 0>, <103 0>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@40134000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x40134000 0x4000>;
+			interrupts = <104 0>, <105 0>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		edma_lpsr0: dma-controller@40c14000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <32>;
+			dma-requests = <208>;
+			nxp,mem2mem;
+			nxp,a_on;
+			reg = <0x40c14000 0x4000>,
+				<0x40c18000 0x4000>;
+			clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
+			status = "disabled";
+			label = "DMA_0";
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+		};
+
+	};
+
+};
+
+
+&gpio9 {
+	interrupts = <99 0>;
+};
+
+&gpio11 {
+	/* GPIO 7-11 share the same interrupt on the CM4 */
+	interrupts = <99 0>;
+	status = "disabled";
+};

dts/arm/nxp/nxp_rt1160_cm7.dtsi

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt11xx.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+	/*
+	 * ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected
+	 * to the M7 core alone, hence this EDMA controller has been designated M7 only.
+	 * GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is
+	 * only accesssible to the M7.
+	 *
+	 * Refer to Chapter 3 of the Reference Manual
+	 */
+	soc {
+		flexram: flexram@40028000 {
+			reg = <0x40028000 0x4000>;
+			interrupts = <50 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itcm: itcm@0 {
+				compatible = "nxp,imx-itcm";
+				reg = <0x00000000 DT_SIZE_K(256)>;
+			};
+
+			dtcm: dtcm@20000000 {
+				compatible = "nxp,imx-dtcm";
+				reg = <0x20000000 DT_SIZE_K(256)>;
+			};
+		};
+
+		/*
+		 * M7 uses different addresses from the M4 core for GPIO2 and
+		 * GPIO3, see pg. 1460 of RT1160 ref manual for example
+		 */
+		gpio2: gpio@42008000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x42008000 0x4000>;
+			interrupts = <102 0>, <103 0>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@4200c000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x4200c000 0x4000>;
+			interrupts = <104 0>, <105 0>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		edma0: dma-controller@40070000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <32>;
+			dma-requests = <208>;
+			nxp,mem2mem;
+			nxp,a_on;
+			reg = <0x40070000 0x4000>,
+				<0x40074000 0x4000>;
+			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
+				status = "disabled";
+			label = "DMA_0";
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+		};
+	};
+};
+
+&gpio6 {
+	interrupts = <61 0>, <62 0>;
+};

dts/arm/nxp/nxp_rt1170_cm4.dtsi

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt11xx.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	/*
+	 * SRAM0 & SRAM1 are available only to the M4 core. EDMA_LPSR interrupts are connected
+	 * to the M4 core alone, hence this EDMA controller has been designated M4 only.
+	 * GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are
+	 * only accesssible to the M4.
+	 *
+	 * Refer to Chapter 3 of the Reference Manual
+	 */
+	soc {
+		sram0: memory@1ffe0000 {
+			compatible = "mmio-sram";
+			reg = <0x1ffe0000 DT_SIZE_K(128)>;
+		};
+
+		sram1: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(128)>;
+			zephyr,memory-region = "SRAM1";
+		};
+
+		/*
+		 * M4 uses different addresses from the M7 core for GPIO2 and
+		 * GPIO3, see pg. 1410 of RT1170 ref manual for example
+		 */
+		gpio2: gpio@40130000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x40130000 0x4000>;
+			interrupts = <102 0>, <103 0>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@40134000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x40134000 0x4000>;
+			interrupts = <104 0>, <105 0>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		edma_lpsr0: dma-controller@40c14000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <32>;
+			dma-requests = <208>;
+			nxp,mem2mem;
+			nxp,a_on;
+			reg = <0x40c14000 0x4000>,
+				<0x40c18000 0x4000>;
+			clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
+			status = "disabled";
+			label = "DMA_0";
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+		};
+	};
+};
+
+&gpio9 {
+	interrupts = <99 0>;
+};
+
+&gpio11 {
+	/* GPIO 7-11 share the same interrupt on the CM4 */
+	interrupts = <99 0>;
+	status = "disabled";
+};

dts/arm/nxp/nxp_rt1170_cm7.dtsi

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt11xx.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+	/*
+	 * ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected
+	 * to the M7 core alone, hence this EDMA controller has been designated M7 only.
+	 * GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is
+	 * only accesssible to the M7.
+	 *
+	 * Refer to Chapter 3 of the Reference Manual
+	 */
+	soc {
+		flexram: flexram@40028000 {
+			reg = <0x40028000 0x4000>;
+			interrupts = <50 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itcm: itcm@0 {
+				compatible = "nxp,imx-itcm";
+				reg = <0x00000000 DT_SIZE_K(256)>;
+				zephyr,memory-region = "ITCM";
+			};
+
+			dtcm: dtcm@20000000 {
+				compatible = "nxp,imx-dtcm";
+				reg = <0x20000000 DT_SIZE_K(256)>;
+				zephyr,memory-region = "DTCM";
+			};
+		};
+
+		/*
+		 * M7 uses different addresses from the M4 core for GPIO2 and
+		 * GPIO3, see pg. 1460 of RT1170 ref manual for example
+		 */
+		gpio2: gpio@42008000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x42008000 0x4000>;
+			interrupts = <102 0>, <103 0>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@4200c000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x4200c000 0x4000>;
+			interrupts = <104 0>, <105 0>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		edma0: dma-controller@40070000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <32>;
+			dma-requests = <208>;
+			nxp,mem2mem;
+			nxp,a_on;
+			reg = <0x40070000 0x4000>,
+				<0x40074000 0x4000>;
+			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
+				status = "disabled";
+			label = "DMA_0";
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+		};
+	};
+};
+
+&gpio6 {
+	interrupts = <61 0>, <62 0>;
+};

dts/arm/st/f0/stm32f0.dtsi

@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2017 RnDity Sp. z o.o.
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv6-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m0";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(40)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f0-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32f0-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <3 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <2>;
+				/* maximum erase time for a 2K sector */
+				max-erase-time = <40>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32f0-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@40010400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40010400 0x400>;
+		};
+
+		pinctrl: pin-controller@48000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x48000000 0x1800>;
+
+			gpioa: gpio@48000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@48000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@48000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
+				label = "GPIOD";
+			};
+
+			gpiof: gpio@48001400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
+				label = "GPIOF";
+			};
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
+			interrupts = <27 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <28 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <23 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
+			interrupts = <25 3>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			interrupts = <2 0>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 2>;
+			status = "disabled";
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
+			interrupts = <13 0>, <14 0>;
+			interrupt-names = "brk_up_trg_com", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <16 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <17 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <18 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <19 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
+			interrupts = <20 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
+			interrupts = <21 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
+			interrupts = <22 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
+			interrupts = <12 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			interrupts = <9 0 10 0 10 0 11 0 11 0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>;
+};

dts/arm/st/f0/stm32f030.dtsi

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <1024>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f030X4.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f0/stm32f030.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(4)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(16)>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f030X8.dtsi

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f030.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+	};
+};

dts/arm/st/f0/stm32f030Xc.dtsi

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f0/stm32f030.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		/*
+		 * USARTs 3-6 share the same IRQ on stm32f030Xc devices. This
+		 * configuration is not currently supported, so at most one of
+		 * these may be enabled at a time. Enabling more than one will
+		 * result in a build failure.
+		 */
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		usart4: serial@40004c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		usart5: serial@40005000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		usart6: serial@40011400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+	};
+};

dts/arm/st/f0/stm32f031.dtsi

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <1024>;
+			};
+		};
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <15 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f031X6.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f0/stm32f031.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(4)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f051.dtsi

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018 Nathan Tsoi <nathan@vertile.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <1024>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f051X8.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f051.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f070.dtsi

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <2048>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <31 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			status = "disabled";
+			label= "USB";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};

dts/arm/st/f0/stm32f070Xb.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f070.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f072.dtsi

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <2048>;
+			};
+		};
+
+		pinctrl: pin-controller@48000000 {
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				label = "GPIOE";
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <15 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <31 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			status = "disabled";
+			label= "USB";
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <30 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <250000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};

dts/arm/st/f0/stm32f072Xb.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f072.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f091.dtsi

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) Bobby Noelte
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <2048>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <15 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		pinctrl: pin-controller@48000000 {
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				label = "GPIOE";
+			};
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020400 0x400>;
+			interrupts = <10 0 10 0 11 0 11 0 11 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+	};
+};

dts/arm/st/f0/stm32f091Xc.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f091.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};

dts/arm/st/f0/stm32f098Xc.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2019 The Chromium OS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f091.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};