From 1f39b42525bf3ed8535927353449fd64c3bb0cf4 Mon Sep 17 00:00:00 2001
From: Daniel Agar <daniel@agar.ca>
Date: Wed, 5 Jan 2022 16:59:19 -0500
Subject: [PATCH] WIP: device tree MVP

---
 .gitmodules                                   |    3 +
 CMakeLists.txt                                |    2 +
 Tools/astyle/files_to_check_code_style.sh     |    1 +
 Tools/dts/README.txt                          |   32 +
 Tools/dts/gen_defines.py                      | 1032 ++++++
 Tools/dts/gen_dts_cmake.py                    |  151 +
 Tools/dts/python-devicetree/.gitignore        |    7 +
 Tools/dts/python-devicetree/requirements.txt  |    1 +
 Tools/dts/python-devicetree/setup.py          |   42 +
 .../src/devicetree/__init__.py                |    4 +
 .../python-devicetree/src/devicetree/dtlib.py | 2022 +++++++++++
 .../src/devicetree/edtlib.py                  | 2996 ++++++++++++++++
 .../src/devicetree/grutils.py                 |  161 +
 .../tests/test-bindings-2/multidir.yaml       |    5 +
 .../tests/test-bindings-include/README.rst    |    1 +
 .../allow-and-blocklist-child.yaml            |   11 +
 .../allow-and-blocklist.yaml                  |   10 +
 .../test-bindings-include/allow-not-list.yaml |   10 +
 .../test-bindings-include/allowlist.yaml      |    7 +
 .../test-bindings-include/block-not-list.yaml |   10 +
 .../test-bindings-include/blocklist.yaml      |    7 +
 .../empty-allowlist.yaml                      |    7 +
 .../empty-blocklist.yaml                      |    7 +
 .../filter-child-bindings.yaml                |   11 +
 .../test-bindings-include/include-2.yaml      |    7 +
 .../include-invalid-keys.yaml                 |   10 +
 .../include-invalid-type.yaml                 |    5 +
 .../include-no-list.yaml                      |    6 +
 .../include-no-name.yaml                      |    7 +
 .../tests/test-bindings-include/include.yaml  |   24 +
 .../test-bindings-include/intermixed.yaml     |    8 +
 .../tests/test-bindings/bar-bus.yaml          |    7 +
 .../child-binding-with-compat.yaml            |   20 +
 .../tests/test-bindings/child-binding.yaml    |   19 +
 .../tests/test-bindings/child.yaml            |    8 +
 .../tests/test-bindings/defaults.yaml         |   36 +
 .../tests/test-bindings/deprecated.yaml       |   15 +
 .../test-bindings/device-on-any-bus.yaml      |    5 +
 .../test-bindings/device-on-bar-bus.yaml      |    7 +
 .../test-bindings/device-on-foo-bus.yaml      |    7 +
 .../tests/test-bindings/enums.yaml            |   36 +
 .../tests/test-bindings/false-positive.yaml   |    4 +
 .../tests/test-bindings/foo-bus.yaml          |    7 +
 .../tests/test-bindings/foo-optional.yaml     |    4 +
 .../tests/test-bindings/foo-required.yaml     |    4 +
 .../tests/test-bindings/gpio-dst.yaml         |    8 +
 .../tests/test-bindings/gpio-src.yaml         |    9 +
 .../tests/test-bindings/grandchild-1.yaml     |   10 +
 .../tests/test-bindings/grandchild-2.yaml     |    6 +
 .../tests/test-bindings/grandchild-3.yaml     |    6 +
 .../tests/test-bindings/interrupt-1-cell.yaml |    8 +
 .../tests/test-bindings/interrupt-2-cell.yaml |    9 +
 .../tests/test-bindings/interrupt-3-cell.yaml |   10 +
 .../tests/test-bindings/multidir.yaml         |    5 +
 .../tests/test-bindings/order-1.yaml          |    7 +
 .../tests/test-bindings/order-2.yaml          |    7 +
 .../tests/test-bindings/parent.yaml           |   13 +
 .../phandle-array-controller-0.yaml           |    7 +
 .../phandle-array-controller-1.yaml           |   11 +
 .../phandle-array-controller-2.yaml           |    9 +
 .../tests/test-bindings/props.yaml            |   50 +
 .../python-devicetree/tests/test-multidir.dts |   19 +
 .../wrong-phandle-array-name.yaml             |    9 +
 .../wrong-specifier-space-type.yaml           |   10 +
 Tools/dts/python-devicetree/tests/test.dts    |  534 +++
 .../dts/python-devicetree/tests/test_dtlib.py | 2272 ++++++++++++
 .../python-devicetree/tests/test_edtlib.py    |  588 ++++
 Tools/dts/python-devicetree/tox.ini           |   19 +
 boards/px4/fmu-v5x/board.dts                  |  204 ++
 boards/px4/fmu-v5x/src/init.cpp               |    5 +
 cmake/dts.cmake                               |  281 ++
 dts/Kconfig                                   |   21 +
 dts/arm/armv6-m.dtsi                          |   27 +
 dts/arm/armv7-a.dtsi                          |   16 +
 dts/arm/armv7-m.dtsi                          |   27 +
 dts/arm/armv7-r.dtsi                          |   16 +
 dts/arm/nxp/nxp_k66.dtsi                      |   41 +
 dts/arm/nxp/nxp_k6x.dtsi                      |  572 +++
 dts/arm/nxp/nxp_rt1060.dtsi                   |   38 +
 dts/arm/nxp/nxp_rt1064.dtsi                   |   23 +
 dts/arm/nxp/nxp_rt1160_cm4.dtsi               |   87 +
 dts/arm/nxp/nxp_rt1160_cm7.dtsi               |   85 +
 dts/arm/nxp/nxp_rt1170_cm4.dtsi               |   85 +
 dts/arm/nxp/nxp_rt1170_cm7.dtsi               |   87 +
 dts/arm/st/f0/stm32f0.dtsi                    |  390 +++
 dts/arm/st/f0/stm32f030.dtsi                  |   17 +
 dts/arm/st/f0/stm32f030X4.dtsi                |   22 +
 dts/arm/st/f0/stm32f030X8.dtsi                |   32 +
 dts/arm/st/f0/stm32f030Xc.dtsi                |   75 +
 dts/arm/st/f0/stm32f031.dtsi                  |   34 +
 dts/arm/st/f0/stm32f031X6.dtsi                |   22 +
 dts/arm/st/f0/stm32f051.dtsi                  |   26 +
 dts/arm/st/f0/stm32f051X8.dtsi                |   21 +
 dts/arm/st/f0/stm32f070.dtsi                  |   47 +
 dts/arm/st/f0/stm32f070Xb.dtsi                |   21 +
 dts/arm/st/f0/stm32f072.dtsi                  |  104 +
 dts/arm/st/f0/stm32f072Xb.dtsi                |   21 +
 dts/arm/st/f0/stm32f091.dtsi                  |   81 +
 dts/arm/st/f0/stm32f091Xc.dtsi                |   21 +
 dts/arm/st/f0/stm32f098Xc.dtsi                |   21 +
 dts/arm/st/f1/stm32f1.dtsi                    |  333 ++
 dts/arm/st/f1/stm32f100Xb.dtsi                |   46 +
 dts/arm/st/f1/stm32f100Xe.dtsi                |   35 +
 dts/arm/st/f1/stm32f103X8.dtsi                |   67 +
 dts/arm/st/f1/stm32f103Xb.dtsi                |   27 +
 dts/arm/st/f1/stm32f103Xc.dtsi                |  166 +
 dts/arm/st/f1/stm32f103Xd.dtsi                |   26 +
 dts/arm/st/f1/stm32f103Xe.dtsi                |   22 +
 dts/arm/st/f1/stm32f103Xg.dtsi                |  141 +
 dts/arm/st/f1/stm32f105.dtsi                  |  141 +
 dts/arm/st/f1/stm32f105Xc.dtsi                |   22 +
 dts/arm/st/f1/stm32f107.dtsi                  |   21 +
 dts/arm/st/f1/stm32f107Xc.dtsi                |   22 +
 dts/arm/st/f2/stm32f2.dtsi                    |  570 +++
 dts/arm/st/f2/stm32f205Xe.dtsi                |   22 +
 dts/arm/st/f2/stm32f207.dtsi                  |   25 +
 dts/arm/st/f2/stm32f207Xe.dtsi                |   21 +
 dts/arm/st/f2/stm32f207Xg.dtsi                |   22 +
 dts/arm/st/f3/stm32f3.dtsi                    |  413 +++
 dts/arm/st/f3/stm32f302.dtsi                  |   92 +
 dts/arm/st/f3/stm32f302X8.dtsi                |   24 +
 dts/arm/st/f3/stm32f303.dtsi                  |  134 +
 dts/arm/st/f3/stm32f303X8.dtsi                |   37 +
 dts/arm/st/f3/stm32f303Xc.dtsi                |   38 +
 dts/arm/st/f3/stm32f303Xe.dtsi                |   38 +
 dts/arm/st/f3/stm32f334.dtsi                  |   41 +
 dts/arm/st/f3/stm32f334X8.dtsi                |   37 +
 dts/arm/st/f3/stm32f373.dtsi                  |  194 ++
 dts/arm/st/f3/stm32f373Xc.dtsi                |   40 +
 dts/arm/st/f4/stm32f4.dtsi                    |  526 +++
 dts/arm/st/f4/stm32f401.dtsi                  |   72 +
 dts/arm/st/f4/stm32f401Xc.dtsi                |   22 +
 dts/arm/st/f4/stm32f401Xe.dtsi                |   22 +
 dts/arm/st/f4/stm32f405.dtsi                  |  275 ++
 dts/arm/st/f4/stm32f405Xg.dtsi                |   28 +
 dts/arm/st/f4/stm32f407.dtsi                  |   25 +
 dts/arm/st/f4/stm32f407Xe.dtsi                |   28 +
 dts/arm/st/f4/stm32f407Xg.dtsi                |   28 +
 dts/arm/st/f4/stm32f410.dtsi                  |  103 +
 dts/arm/st/f4/stm32f410Xb.dtsi                |   22 +
 dts/arm/st/f4/stm32f411.dtsi                  |   64 +
 dts/arm/st/f4/stm32f411Xe.dtsi                |   22 +
 dts/arm/st/f4/stm32f412.dtsi                  |  194 ++
 dts/arm/st/f4/stm32f412Xe.dtsi                |   22 +
 dts/arm/st/f4/stm32f412Xg.dtsi                |   22 +
 dts/arm/st/f4/stm32f413.dtsi                  |   74 +
 dts/arm/st/f4/stm32f413Xg.dtsi                |   22 +
 dts/arm/st/f4/stm32f413Xh.dtsi                |   22 +
 dts/arm/st/f4/stm32f415.dtsi                  |   20 +
 dts/arm/st/f4/stm32f415Rg.dtsi                |   28 +
 dts/arm/st/f4/stm32f417.dtsi                  |   20 +
 dts/arm/st/f4/stm32f417Xe.dtsi                |   28 +
 dts/arm/st/f4/stm32f417Xg.dtsi                |   28 +
 dts/arm/st/f4/stm32f427.dtsi                  |  107 +
 dts/arm/st/f4/stm32f427Xi.dtsi                |   28 +
 dts/arm/st/f4/stm32f427vX.dtsi                |   11 +
 dts/arm/st/f4/stm32f427vi.dtsi                |   29 +
 dts/arm/st/f4/stm32f429.dtsi                  |   20 +
 dts/arm/st/f4/stm32f429Xi.dtsi                |   28 +
 dts/arm/st/f4/stm32f429vX.dtsi                |   21 +
 dts/arm/st/f4/stm32f429vi.dtsi                |   29 +
 dts/arm/st/f4/stm32f437.dtsi                  |  113 +
 dts/arm/st/f4/stm32f437Xi.dtsi                |   28 +
 dts/arm/st/f4/stm32f437vX.dtsi                |   11 +
 dts/arm/st/f4/stm32f446.dtsi                  |  142 +
 dts/arm/st/f4/stm32f446Xe.dtsi                |   22 +
 dts/arm/st/f4/stm32f469.dtsi                  |   19 +
 dts/arm/st/f4/stm32f469Xi.dtsi                |   28 +
 dts/arm/st/f7/stm32f7.dtsi                    |  775 +++++
 dts/arm/st/f7/stm32f723.dtsi                  |   48 +
 dts/arm/st/f7/stm32f723Xe.dtsi                |   18 +
 dts/arm/st/f7/stm32f745.dtsi                  |   94 +
 dts/arm/st/f7/stm32f745Xe.dtsi                |   18 +
 dts/arm/st/f7/stm32f745Xg.dtsi                |   18 +
 dts/arm/st/f7/stm32f746.dtsi                  |    7 +
 dts/arm/st/f7/stm32f746Xg.dtsi                |   18 +
 dts/arm/st/f7/stm32f756.dtsi                  |    7 +
 dts/arm/st/f7/stm32f756Xg.dtsi                |   18 +
 dts/arm/st/f7/stm32f765.dtsi                  |   95 +
 dts/arm/st/f7/stm32f767.dtsi                  |   95 +
 dts/arm/st/f7/stm32f767Xi.dtsi                |   18 +
 dts/arm/st/f7/stm32f769.dtsi                  |    7 +
 dts/arm/st/f7/stm32f769Xi.dtsi                |   19 +
 dts/arm/st/g0/stm32g0.dtsi                    |  393 +++
 dts/arm/st/g0/stm32g030.dtsi                  |    7 +
 dts/arm/st/g0/stm32g030X6.dtsi                |   22 +
 dts/arm/st/g0/stm32g030X8.dtsi                |   22 +
 dts/arm/st/g0/stm32g031.dtsi                  |   39 +
 dts/arm/st/g0/stm32g031X4.dtsi                |   22 +
 dts/arm/st/g0/stm32g031X6.dtsi                |   22 +
 dts/arm/st/g0/stm32g031X8.dtsi                |   22 +
 dts/arm/st/g0/stm32g041.dtsi                  |    8 +
 dts/arm/st/g0/stm32g041X6.dtsi                |   22 +
 dts/arm/st/g0/stm32g041X8.dtsi                |   22 +
 dts/arm/st/g0/stm32g050.dtsi                  |   42 +
 dts/arm/st/g0/stm32g050X6.dtsi                |   22 +
 dts/arm/st/g0/stm32g050X8.dtsi                |   22 +
 dts/arm/st/g0/stm32g051.dtsi                  |   68 +
 dts/arm/st/g0/stm32g051X6.dtsi                |   22 +
 dts/arm/st/g0/stm32g051X8.dtsi                |   22 +
 dts/arm/st/g0/stm32g061.dtsi                  |    8 +
 dts/arm/st/g0/stm32g061X6.dtsi                |   22 +
 dts/arm/st/g0/stm32g061X8.dtsi                |   22 +
 dts/arm/st/g0/stm32g070.dtsi                  |   52 +
 dts/arm/st/g0/stm32g070Xb.dtsi                |   23 +
 dts/arm/st/g0/stm32g071.dtsi                  |   53 +
 dts/arm/st/g0/stm32g071X8.dtsi                |   22 +
 dts/arm/st/g0/stm32g071Xb.dtsi                |   23 +
 dts/arm/st/g0/stm32g081.dtsi                  |    8 +
 dts/arm/st/g0/stm32g081Xb.dtsi                |   22 +
 dts/arm/st/g0/stm32g0_crypt.dtsi              |   31 +
 dts/arm/st/g0/stm32g0b0.dtsi                  |  117 +
 dts/arm/st/g0/stm32g0b0Xe.dtsi                |   22 +
 dts/arm/st/g0/stm32g0b1.dtsi                  |  128 +
 dts/arm/st/g0/stm32g0b1Xb.dtsi                |   22 +
 dts/arm/st/g0/stm32g0b1Xc.dtsi                |   22 +
 dts/arm/st/g0/stm32g0b1Xe.dtsi                |   22 +
 dts/arm/st/g0/stm32g0c1.dtsi                  |    8 +
 dts/arm/st/g0/stm32g0c1Xc.dtsi                |   22 +
 dts/arm/st/g0/stm32g0c1Xe.dtsi                |   22 +
 dts/arm/st/g4/stm32g4.dtsi                    |  621 ++++
 dts/arm/st/g4/stm32g431.dtsi                  |   27 +
 dts/arm/st/g4/stm32g431X6.dtsi                |   22 +
 dts/arm/st/g4/stm32g431X8.dtsi                |   22 +
 dts/arm/st/g4/stm32g431Xb.dtsi                |   22 +
 dts/arm/st/g4/stm32g441.dtsi                  |    7 +
 dts/arm/st/g4/stm32g441Xb.dtsi                |   22 +
 dts/arm/st/g4/stm32g473.dtsi                  |   62 +
 dts/arm/st/g4/stm32g473Xb.dtsi                |   22 +
 dts/arm/st/g4/stm32g473Xc.dtsi                |   22 +
 dts/arm/st/g4/stm32g473Xe.dtsi                |   22 +
 dts/arm/st/g4/stm32g474.dtsi                  |  126 +
 dts/arm/st/g4/stm32g474Xb.dtsi                |   22 +
 dts/arm/st/g4/stm32g474Xc.dtsi                |   22 +
 dts/arm/st/g4/stm32g474Xe.dtsi                |   22 +
 dts/arm/st/g4/stm32g483.dtsi                  |   62 +
 dts/arm/st/g4/stm32g483Xe.dtsi                |   22 +
 dts/arm/st/g4/stm32g484.dtsi                  |   62 +
 dts/arm/st/g4/stm32g484Xe.dtsi                |   22 +
 dts/arm/st/g4/stm32g491.dtsi                  |   44 +
 dts/arm/st/g4/stm32g491Xc.dtsi                |   22 +
 dts/arm/st/g4/stm32g491Xe.dtsi                |   22 +
 dts/arm/st/g4/stm32g4a1.dtsi                  |   44 +
 dts/arm/st/g4/stm32g4a1Xe.dtsi                |   22 +
 dts/arm/st/h7/stm32h7.dtsi                    |  848 +++++
 dts/arm/st/h7/stm32h723.dtsi                  |   57 +
 dts/arm/st/h7/stm32h723Xe.dtsi                |   19 +
 dts/arm/st/h7/stm32h723Xg.dtsi                |   19 +
 dts/arm/st/h7/stm32h735.dtsi                  |   86 +
 dts/arm/st/h7/stm32h735Xg.dtsi                |   19 +
 dts/arm/st/h7/stm32h743.dtsi                  |   82 +
 dts/arm/st/h7/stm32h743Xi.dtsi                |   20 +
 dts/arm/st/h7/stm32h745.dtsi                  |   67 +
 dts/arm/st/h7/stm32h745Xi_m4.dtsi             |   34 +
 dts/arm/st/h7/stm32h745Xi_m7.dtsi             |   35 +
 dts/arm/st/h7/stm32h747.dtsi                  |    7 +
 dts/arm/st/h7/stm32h747Xi_m4.dtsi             |   34 +
 dts/arm/st/h7/stm32h747Xi_m7.dtsi             |   29 +
 dts/arm/st/h7/stm32h750.dtsi                  |   55 +
 dts/arm/st/h7/stm32h750Xb.dtsi                |   20 +
 dts/arm/st/h7/stm32h753.dtsi                  |    7 +
 dts/arm/st/h7/stm32h753Xi.dtsi                |   20 +
 dts/arm/st/h7/stm32h7_dualcore.dtsi           |   27 +
 dts/arm/st/l0/stm32l0.dtsi                    |  308 ++
 dts/arm/st/l0/stm32l010.dtsi                  |   15 +
 dts/arm/st/l0/stm32l010Xb.dtsi                |   39 +
 dts/arm/st/l0/stm32l011X4.dtsi                |   22 +
 dts/arm/st/l0/stm32l031.dtsi                  |   33 +
 dts/arm/st/l0/stm32l031X6.dtsi                |   22 +
 dts/arm/st/l0/stm32l051.dtsi                  |   77 +
 dts/arm/st/l0/stm32l051X8.dtsi                |   24 +
 dts/arm/st/l0/stm32l053.dtsi                  |   40 +
 dts/arm/st/l0/stm32l053X8.dtsi                |   22 +
 dts/arm/st/l0/stm32l071.dtsi                  |  148 +
 dts/arm/st/l0/stm32l071Xb.dtsi                |   22 +
 dts/arm/st/l0/stm32l072.dtsi                  |   53 +
 dts/arm/st/l0/stm32l072Xz.dtsi                |   22 +
 dts/arm/st/l0/stm32l073.dtsi                  |    8 +
 dts/arm/st/l0/stm32l073Xz.dtsi                |   22 +
 dts/arm/st/l1/stm32l1.dtsi                    |  440 +++
 dts/arm/st/l1/stm32l151.dtsi                  |    7 +
 dts/arm/st/l1/stm32l151X8-a.dtsi              |   25 +
 dts/arm/st/l1/stm32l151Xb-a.dtsi              |   25 +
 dts/arm/st/l1/stm32l151Xb.dtsi                |   25 +
 dts/arm/st/l1/stm32l151Xc.dtsi                |   44 +
 dts/arm/st/l1/stm32l152.dtsi                  |   11 +
 dts/arm/st/l1/stm32l152Xc.dtsi                |   44 +
 dts/arm/st/l1/stm32l152Xe.dtsi                |   44 +
 dts/arm/st/l4/stm32l4.dtsi                    |  409 +++
 dts/arm/st/l4/stm32l412.dtsi                  |   42 +
 dts/arm/st/l4/stm32l412X8.dtsi                |   22 +
 dts/arm/st/l4/stm32l412XB.dtsi                |   22 +
 dts/arm/st/l4/stm32l422.dtsi                  |    7 +
 dts/arm/st/l4/stm32l422Xb.dtsi                |   22 +
 dts/arm/st/l4/stm32l432.dtsi                  |   77 +
 dts/arm/st/l4/stm32l432Xc.dtsi                |   21 +
 dts/arm/st/l4/stm32l433.dtsi                  |   64 +
 dts/arm/st/l4/stm32l433Xb.dtsi                |   21 +
 dts/arm/st/l4/stm32l433Xc.dtsi                |   21 +
 dts/arm/st/l4/stm32l452.dtsi                  |  159 +
 dts/arm/st/l4/stm32l452Xc.dtsi                |   22 +
 dts/arm/st/l4/stm32l452Xe.dtsi                |   22 +
 dts/arm/st/l4/stm32l462.dtsi                  |    7 +
 dts/arm/st/l4/stm32l462Xe.dtsi                |   22 +
 dts/arm/st/l4/stm32l471.dtsi                  |  256 ++
 dts/arm/st/l4/stm32l471Xg.dtsi                |   21 +
 dts/arm/st/l4/stm32l475.dtsi                  |   31 +
 dts/arm/st/l4/stm32l475Xg.dtsi                |   21 +
 dts/arm/st/l4/stm32l476.dtsi                  |   21 +
 dts/arm/st/l4/stm32l476Xg.dtsi                |   21 +
 dts/arm/st/l4/stm32l496.dtsi                  |   47 +
 dts/arm/st/l4/stm32l496Xe.dtsi                |   21 +
 dts/arm/st/l4/stm32l496Xg.dtsi                |   21 +
 dts/arm/st/l4/stm32l4r5.dtsi                  |  317 ++
 dts/arm/st/l4/stm32l4r5Xi.dtsi                |   18 +
 dts/arm/st/l4/stm32l4r9.dtsi                  |    9 +
 dts/arm/st/l4/stm32l4r9Xi.dtsi                |   18 +
 dts/arm/st/l4/stm32l4s5.dtsi                  |    7 +
 dts/arm/st/l4/stm32l4s5Xi.dtsi                |   18 +
 dts/arm/st/l5/stm32l5.dtsi                    |  616 ++++
 dts/arm/st/l5/stm32l552.dtsi                  |    7 +
 dts/arm/st/l5/stm32l552Xe.dtsi                |   21 +
 dts/arm/st/l5/stm32l562.dtsi                  |   20 +
 dts/arm/st/l5/stm32l562Xe.dtsi                |   21 +
 dts/arm/st/mp1/stm32mp157.dtsi                |  311 ++
 dts/arm/st/u5/stm32u5.dtsi                    |  396 +++
 dts/arm/st/u5/stm32u575.dtsi                  |   32 +
 dts/arm/st/u5/stm32u575Xi.dtsi                |   21 +
 dts/arm/st/u5/stm32u585.dtsi                  |    7 +
 dts/arm/st/u5/stm32u585Xi.dtsi                |   21 +
 dts/arm/st/wb/stm32wb.dtsi                    |  460 +++
 dts/arm/st/wb/stm32wb55.dtsi                  |    7 +
 dts/arm/st/wb/stm32wb55Xg.dtsi                |   21 +
 dts/arm/st/wl/stm32wl.dtsi                    |  457 +++
 dts/arm/st/wl/stm32wl54Xc.dtsi                |   21 +
 dts/arm/st/wl/stm32wl55.dtsi                  |    7 +
 dts/arm/st/wl/stm32wl55Xc.dtsi                |   21 +
 dts/arm/st/wl/stm32wle4X8.dtsi                |   21 +
 dts/arm/st/wl/stm32wle4Xb.dtsi                |   21 +
 dts/arm/st/wl/stm32wle4Xc.dtsi                |   21 +
 dts/arm/st/wl/stm32wle5.dtsi                  |    7 +
 dts/arm/st/wl/stm32wle5X8.dtsi                |   21 +
 dts/arm/st/wl/stm32wle5Xb.dtsi                |   21 +
 dts/arm/st/wl/stm32wle5Xc.dtsi                |   21 +
 dts/binding-template.yaml                     |   10 +
 dts/bindings/adc/adc-controller.yaml          |   14 +
 dts/bindings/adc/arduino,uno-adc.yaml         |   34 +
 dts/bindings/adc/atmel,sam-afec.yaml          |   35 +
 dts/bindings/adc/atmel,sam0-adc.yaml          |   48 +
 dts/bindings/adc/ite,it8xxx2-adc.yaml         |   16 +
 dts/bindings/adc/microchip,mcp3204.yaml       |    5 +
 dts/bindings/adc/microchip,mcp3208.yaml       |    5 +
 dts/bindings/adc/microchip,mcp320x-base.yaml  |   10 +
 dts/bindings/adc/microchip,xec-adc-v2.yaml    |   48 +
 dts/bindings/adc/microchip,xec-adc.yaml       |   26 +
 dts/bindings/adc/nordic,nrf-adc.yaml          |   21 +
 dts/bindings/adc/nordic,nrf-saadc.yaml        |   21 +
 dts/bindings/adc/nxp,kinetis-adc12.yaml       |   41 +
 dts/bindings/adc/nxp,kinetis-adc16.yaml       |   63 +
 dts/bindings/adc/nxp,mcux-12b1msps-sar.yaml   |   31 +
 dts/bindings/adc/st,stm32-adc.yaml            |   31 +
 dts/bindings/adc/ti,cc32xx-adc.yaml           |   21 +
 dts/bindings/adc/ti,lmp90077.yaml             |    5 +
 dts/bindings/adc/ti,lmp90078.yaml             |    5 +
 dts/bindings/adc/ti,lmp90079.yaml             |    5 +
 dts/bindings/adc/ti,lmp90080.yaml             |    5 +
 dts/bindings/adc/ti,lmp90097.yaml             |    5 +
 dts/bindings/adc/ti,lmp90098.yaml             |    5 +
 dts/bindings/adc/ti,lmp90099.yaml             |    5 +
 dts/bindings/adc/ti,lmp90100.yaml             |    5 +
 dts/bindings/adc/ti,lmp90xxx-base.yaml        |   18 +
 dts/bindings/adc/ti,lmp90xxx-current.yaml     |    9 +
 dts/bindings/adc/voltage-divider.yaml         |   40 +
 dts/bindings/adc/zephyr,adc-emul.yaml         |   46 +
 dts/bindings/arc/arc,dccm.yaml                |   12 +
 dts/bindings/arc/arc,iccm.yaml                |   12 +
 dts/bindings/arm/arm,dtcm.yaml                |   11 +
 dts/bindings/arm/arm,itcm.yaml                |   11 +
 dts/bindings/arm/arm,scc.yaml                 |   12 +
 dts/bindings/arm/atmel,sam-ssc.yaml           |   52 +
 dts/bindings/arm/atmel,sam0-id.yaml           |   10 +
 dts/bindings/arm/atmel,sam0-sercom.yaml       |   15 +
 dts/bindings/arm/atmel,samd2x-pm.yaml         |   19 +
 dts/bindings/arm/nordic,nrf-dppic.yaml        |   13 +
 dts/bindings/arm/nordic,nrf-egu.yaml          |   15 +
 dts/bindings/arm/nordic,nrf-ficr.yaml         |    9 +
 dts/bindings/arm/nordic,nrf-kmu.yaml          |   15 +
 dts/bindings/arm/nordic,nrf-spu.yaml          |   12 +
 dts/bindings/arm/nordic,nrf-uicr.yaml         |    9 +
 dts/bindings/arm/nxp,imx-dtcm.yaml            |   12 +
 dts/bindings/arm/nxp,imx-epit.yaml            |   28 +
 dts/bindings/arm/nxp,imx-itcm.yaml            |   12 +
 dts/bindings/arm/nxp,imx-mu.yaml              |   23 +
 dts/bindings/arm/nxp,kinetis-ftm.yaml         |   29 +
 dts/bindings/arm/nxp,kinetis-ke1xf-sim.yaml   |   25 +
 dts/bindings/arm/nxp,kinetis-mcg.yaml         |   21 +
 dts/bindings/arm/nxp,kinetis-pcc.yaml         |   22 +
 dts/bindings/arm/nxp,kinetis-scg.yaml         |   26 +
 dts/bindings/arm/nxp,kinetis-sim.yaml         |   45 +
 dts/bindings/arm/nxp,lpc-flexcomm.yaml        |   15 +
 dts/bindings/arm/st,stm32-ccm.yaml            |   11 +
 dts/bindings/audio/intel,dmic.yaml            |   12 +
 dts/bindings/audio/nordic,nrf-pdm.yaml        |   52 +
 dts/bindings/audio/st,mpxxdtyy-i2s.yaml       |   12 +
 dts/bindings/audio/ti,tlv320dac.yaml          |   13 +
 dts/bindings/base/base.yaml                   |  110 +
 dts/bindings/base/mem-region.yaml             |   13 +
 dts/bindings/base/pm.yaml                     |   18 +
 dts/bindings/base/power.yaml                  |   33 +
 .../bluetooth/zephyr,bt-hci-spi-slave.yaml    |   34 +
 dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml |   19 +
 dts/bindings/can/bosch,m-can-base.yaml        |   28 +
 dts/bindings/can/bosch,m-can.yaml             |   12 +
 dts/bindings/can/can-controller.yaml          |   36 +
 dts/bindings/can/can-device.yaml              |   14 +
 dts/bindings/can/can-fd-controller.yaml       |   36 +
 dts/bindings/can/microchip,mcp2515.yaml       |   26 +
 dts/bindings/can/nxp,kinetis-flexcan.yaml     |   23 +
 dts/bindings/can/renesas,rcar-can.yaml        |   15 +
 dts/bindings/can/st,stm32-can.yaml            |   26 +
 dts/bindings/can/st,stm32-fdcan.yaml          |    5 +
 dts/bindings/clock/atmel,samd2x-gclk.yaml     |   18 +
 dts/bindings/clock/atmel,samd5x-gclk.yaml     |   18 +
 dts/bindings/clock/atmel,samd5x-mclk.yaml     |   19 +
 dts/bindings/clock/clock-controller.yaml      |   10 +
 dts/bindings/clock/espressif,esp32-rtc.yaml   |   31 +
 dts/bindings/clock/fixed-clock.yaml           |   27 +
 dts/bindings/clock/fixed-factor-clock.yaml    |   24 +
 dts/bindings/clock/litex,clk.yaml             |   93 +
 dts/bindings/clock/litex,clkout.yaml          |   67 +
 dts/bindings/clock/microchip,xec-pcr.yaml     |   52 +
 dts/bindings/clock/nordic,nrf-clock.yaml      |   27 +
 dts/bindings/clock/nuvoton,npcx-pcc.yaml      |  224 ++
 dts/bindings/clock/nxp,imx-anatop.yaml        |   38 +
 dts/bindings/clock/nxp,imx-ccm-rev2.yaml      |   23 +
 dts/bindings/clock/nxp,imx-ccm.yaml           |   23 +
 dts/bindings/clock/nxp,lpc-syscon.yaml        |   21 +
 dts/bindings/clock/nxp,lpc11u6x-syscon.yaml   |   31 +
 dts/bindings/clock/renesas,rcar-cpg-mssr.yaml |   19 +
 dts/bindings/clock/st,stm32-hse-clock.yaml    |   16 +
 dts/bindings/clock/st,stm32-msi-clock.yaml    |   36 +
 dts/bindings/clock/st,stm32-rcc.yaml          |   96 +
 dts/bindings/clock/st,stm32f0-pll-clock.yaml  |   40 +
 dts/bindings/clock/st,stm32f0-rcc.yaml        |   13 +
 dts/bindings/clock/st,stm32f1-pll-clock.yaml  |   47 +
 .../clock/st,stm32f100-pll-clock.yaml         |   36 +
 .../clock/st,stm32f105-pll-clock.yaml         |   55 +
 .../clock/st,stm32f105-pll2-clock.yaml        |   36 +
 dts/bindings/clock/st,stm32f2-pll-clock.yaml  |   61 +
 dts/bindings/clock/st,stm32f4-pll-clock.yaml  |   64 +
 dts/bindings/clock/st,stm32f7-pll-clock.yaml  |   59 +
 dts/bindings/clock/st,stm32g0-pll-clock.yaml  |   66 +
 dts/bindings/clock/st,stm32g4-pll-clock.yaml  |   44 +
 dts/bindings/clock/st,stm32h7-hsi-clock.yaml  |   20 +
 dts/bindings/clock/st,stm32h7-pll-clock.yaml  |   70 +
 dts/bindings/clock/st,stm32h7-rcc.yaml        |  137 +
 dts/bindings/clock/st,stm32l0-msi-clock.yaml  |   26 +
 dts/bindings/clock/st,stm32l0-pll-clock.yaml  |   59 +
 dts/bindings/clock/st,stm32l4-pll-clock.yaml  |   80 +
 dts/bindings/clock/st,stm32mp1-rcc.yaml       |   17 +
 dts/bindings/clock/st,stm32u5-msi-clock.yaml  |   37 +
 dts/bindings/clock/st,stm32u5-pll-clock.yaml  |   67 +
 dts/bindings/clock/st,stm32u5-rcc.yaml        |   22 +
 dts/bindings/clock/st,stm32wb-pll-clock.yaml  |   71 +
 dts/bindings/clock/st,stm32wb-rcc.yaml        |   77 +
 dts/bindings/clock/st,stm32wl-hse-clock.yaml  |   23 +
 dts/bindings/clock/st,stm32wl-rcc.yaml        |   55 +
 dts/bindings/counter/st,stm32-counter.yaml    |   12 +
 dts/bindings/cpu/altr,nios2f.yaml             |   15 +
 dts/bindings/cpu/arm,cortex-a53.yaml          |    8 +
 dts/bindings/cpu/arm,cortex-a72.yaml          |    7 +
 dts/bindings/cpu/arm,cortex-m.yaml            |   12 +
 dts/bindings/cpu/arm,cortex-m0+.yaml          |    8 +
 dts/bindings/cpu/arm,cortex-m0.yaml           |    8 +
 dts/bindings/cpu/arm,cortex-m1.yaml           |    8 +
 dts/bindings/cpu/arm,cortex-m23.yaml          |    8 +
 dts/bindings/cpu/arm,cortex-m3.yaml           |    8 +
 dts/bindings/cpu/arm,cortex-m33.yaml          |    8 +
 dts/bindings/cpu/arm,cortex-m33f.yaml         |    8 +
 dts/bindings/cpu/arm,cortex-m4.yaml           |    8 +
 dts/bindings/cpu/arm,cortex-m4f.yaml          |    8 +
 dts/bindings/cpu/arm,cortex-m7.yaml           |    8 +
 dts/bindings/cpu/arm,cortex-r4.yaml           |    8 +
 dts/bindings/cpu/arm,cortex-r4f.yaml          |    8 +
 dts/bindings/cpu/arm,cortex-r5.yaml           |    8 +
 dts/bindings/cpu/arm,cortex-r5f.yaml          |    8 +
 dts/bindings/cpu/arm,cortex-r7.yaml           |    8 +
 dts/bindings/cpu/arm,cortex-r82.yaml          |    8 +
 .../cpu/cdns,tensilica-xtensa-lx4.yaml        |    8 +
 .../cpu/cdns,tensilica-xtensa-lx6.yaml        |   14 +
 .../cpu/cdns,tensilica-xtensa-lx7.yaml        |   14 +
 dts/bindings/cpu/cpu.yaml                     |   24 +
 dts/bindings/cpu/espressif,riscv.yml          |   14 +
 dts/bindings/cpu/intel,apollo_lake.yaml       |    8 +
 dts/bindings/cpu/intel,atom.yaml              |    8 +
 dts/bindings/cpu/intel,elkhart_lake.yaml      |    8 +
 dts/bindings/cpu/intel,lakemont.yml           |    8 +
 dts/bindings/cpu/intel,x86.yaml               |    8 +
 dts/bindings/cpu/ite,riscv-ite.yaml           |    8 +
 dts/bindings/cpu/neorv32-cpu.yaml             |    8 +
 dts/bindings/cpu/nuclei,bumblebee.yaml        |   14 +
 dts/bindings/cpu/qemu,nios2-zephyr.yaml       |   15 +
 dts/bindings/cpu/sample_controller.yaml       |    8 +
 dts/bindings/cpu/snps,arcem.yaml              |    8 +
 dts/bindings/cpu/telink,b91.yaml              |    8 +
 dts/bindings/crypto/arm,cryptocell-310.yaml   |   18 +
 dts/bindings/crypto/arm,cryptocell-312.yaml   |   18 +
 dts/bindings/crypto/nordic,nrf-cc310.yaml     |   15 +
 dts/bindings/crypto/nordic,nrf-cc312.yaml     |   15 +
 dts/bindings/crypto/nordic,nrf-ecb.yaml       |   15 +
 dts/bindings/crypto/st,stm32-aes.yaml         |    8 +
 dts/bindings/crypto/st,stm32-cryp.yaml        |    8 +
 .../crypto/st,stm32-crypto-common.yaml        |   17 +
 dts/bindings/dac/atmel,sam-dac.yaml           |   34 +
 dts/bindings/dac/atmel,sam0-dac.yaml          |   33 +
 dts/bindings/dac/dac-controller.yaml          |   14 +
 dts/bindings/dac/gd,gd32-dac.yaml             |   34 +
 dts/bindings/dac/microchip,mcp4725.yaml       |   15 +
 dts/bindings/dac/nxp,kinetis-dac.yaml         |   28 +
 dts/bindings/dac/nxp,kinetis-dac32.yaml       |   33 +
 dts/bindings/dac/st,stm32-dac.yaml            |   27 +
 dts/bindings/dac/ti,dac43608.yaml             |    8 +
 dts/bindings/dac/ti,dac53608.yaml             |    8 +
 dts/bindings/dac/ti,dac60508.yaml             |    8 +
 dts/bindings/dac/ti,dac70508.yaml             |    8 +
 dts/bindings/dac/ti,dac80508.yaml             |    8 +
 dts/bindings/dac/ti,dacx0508-base.yaml        |   83 +
 dts/bindings/dac/ti,dacx3608-base.yaml        |   11 +
 dts/bindings/display/display-controller.yaml  |   20 +
 dts/bindings/display/fsl,imx6sx-lcdif.yaml    |   18 +
 dts/bindings/display/ftdi,ft800.yaml          |  107 +
 dts/bindings/display/gooddisplay,gd7965.yaml  |   56 +
 dts/bindings/display/ilitek,ili9340.yaml      |   97 +
 dts/bindings/display/ilitek,ili9341.yaml      |  146 +
 dts/bindings/display/ilitek,ili9488.yaml      |   84 +
 .../display/ilitek,ili9xxx-common.yaml        |   54 +
 .../display/nordic,nrf-led-matrix.yaml        |   82 +
 .../display/rocktech,rk043fn02h-ct.yaml       |    8 +
 dts/bindings/display/sharp,ls0xx.yaml         |   35 +
 dts/bindings/display/sitronix,st7735r.yaml    |  117 +
 dts/bindings/display/sitronix,st7789v.yaml    |  115 +
 .../display/solomon,ssd1306fb-common.yaml     |   54 +
 .../display/solomon,ssd1306fb-i2c.yaml        |    8 +
 .../display/solomon,ssd1306fb-spi.yaml        |   14 +
 dts/bindings/display/solomon,ssd16xxfb.yaml   |   93 +
 dts/bindings/display/zephyr,dummy-dc.yaml     |    8 +
 dts/bindings/display/zephyr,sdl-dc.yaml       |    8 +
 dts/bindings/dma/altr,msgdma.yaml             |   18 +
 dts/bindings/dma/arm,dma-pl330.yaml           |   45 +
 dts/bindings/dma/atmel,sam-xdmac.yaml         |   27 +
 dts/bindings/dma/atmel,sam0-dmac.yaml         |   39 +
 dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml   |   38 +
 dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml   |   38 +
 dts/bindings/dma/dma-controller.yaml          |   35 +
 dts/bindings/dma/dmamux-controller.yaml       |   34 +
 dts/bindings/dma/nxp,lpc-dma.yaml             |   29 +
 dts/bindings/dma/nxp,mcux-edma.yaml           |   54 +
 dts/bindings/dma/snps,designware-dma.yaml     |   21 +
 dts/bindings/dma/st,stm32-dma-v1.yaml         |   90 +
 dts/bindings/dma/st,stm32-dma-v2.yaml         |   83 +
 dts/bindings/dma/st,stm32-dma-v2bis.yaml      |   77 +
 dts/bindings/dma/st,stm32-dma.yaml            |   38 +
 dts/bindings/dma/st,stm32-dmamux.yaml         |   83 +
 dts/bindings/dsa/microchip,ksz8794.yaml       |   35 +
 dts/bindings/dsa/microchip,ksz8863.yaml       |    9 +
 dts/bindings/dsa/microchip_dsa.yaml           |   45 +
 .../zephyr,sim-ec-host-cmd-periph.yaml        |   11 +
 dts/bindings/edac/intel,ibecc.yaml            |   12 +
 dts/bindings/espi/espi-controller.yaml        |   12 +
 .../espi/microchip,xec-espi-host-dev.yaml     |   95 +
 dts/bindings/espi/microchip,xec-espi-saf.yaml |   44 +
 dts/bindings/espi/microchip,xec-espi-v2.yaml  |   44 +
 .../espi/microchip,xec-espi-vw-routing.yaml   |   25 +
 dts/bindings/espi/microchip,xec-espi.yaml     |   28 +
 .../espi/nuvoton,npcx-espi-vw-conf.yaml       |   22 +
 dts/bindings/espi/nuvoton,npcx-espi.yaml      |   31 +
 dts/bindings/espi/nuvoton,npcx-host-sub.yaml  |   27 +
 dts/bindings/espi/nuvoton,npcx-host-uart.yaml |   14 +
 .../espi/zephyr,espi-emul-controller.yaml     |   12 +
 dts/bindings/ethernet/atmel,gmac-common.yaml  |   73 +
 dts/bindings/ethernet/atmel,sam-gmac.yaml     |   18 +
 dts/bindings/ethernet/atmel,sam0-gmac.yaml    |    8 +
 .../ethernet/ethernet,fixed-link.yaml         |   18 +
 dts/bindings/ethernet/ethernet-phy.yaml       |   33 +
 dts/bindings/ethernet/ethernet.yaml           |   27 +
 dts/bindings/ethernet/intel,e1000.yaml        |   15 +
 dts/bindings/ethernet/litex,eth0.yaml         |   15 +
 dts/bindings/ethernet/microchip,enc28j60.yaml |   18 +
 .../ethernet/microchip,enc424j600.yaml        |   19 +
 .../ethernet/nxp,kinetis-ethernet.yaml        |   14 +
 dts/bindings/ethernet/nxp,kinetis-ptp.yaml    |   12 +
 dts/bindings/ethernet/phy.yaml                |    6 +
 .../ethernet/silabs,gecko-ethernet.yaml       |  101 +
 dts/bindings/ethernet/smsc,lan9220.yaml       |   15 +
 .../ethernet/snps,designware-ethernet.yaml    |   14 +
 dts/bindings/ethernet/st,stm32-ethernet.yaml  |   22 +
 .../ethernet/ti,stellaris-ethernet.yaml       |   14 +
 dts/bindings/ethernet/wiznet,w5500.yaml       |   26 +
 dts/bindings/ethernet/xlnx,gem.yaml           |  378 ++
 .../atmel,sam-flash-controller.yaml           |   14 +
 .../flash_controller/atmel,sam0-nvmctrl.yaml  |   11 +
 .../cypress,psoc6-flash-controller.yaml       |    8 +
 .../espressif,esp32-flash-controller.yaml     |    5 +
 .../flash_controller/flash-controller.yaml    |   10 +
 .../ite,it8xxx2-flash-controller.yaml         |    8 +
 .../flash_controller/nordic,nrf-qspi.yaml     |   76 +
 .../nordic,nrf51-flash-controller.yaml        |    5 +
 .../nordic,nrf52-flash-controller.yaml        |    5 +
 .../nordic,nrf53-flash-controller.yaml        |    5 +
 .../nordic,nrf91-flash-controller.yaml        |    5 +
 .../flash_controller/nxp,kinetis-ftfa.yaml    |    5 +
 .../flash_controller/nxp,kinetis-ftfe.yaml    |    5 +
 .../flash_controller/nxp,kinetis-ftfl.yaml    |    5 +
 .../flash_controller/nxp,lpc-iap.yaml         |    8 +
 .../flash_controller/openisa,rv32m1-ftfe.yaml |    5 +
 .../silabs,gecko-flash-controller.yaml        |    8 +
 .../st,stm32-flash-controller.yaml            |    5 +
 .../flash_controller/st,stm32-qspi-nor.yaml   |   35 +
 .../st,stm32f0-flash-controller.yaml          |    5 +
 .../st,stm32f1-flash-controller.yaml          |    5 +
 .../st,stm32f2-flash-controller.yaml          |    5 +
 .../st,stm32f3-flash-controller.yaml          |    5 +
 .../st,stm32f4-flash-controller.yaml          |    5 +
 .../st,stm32f7-flash-controller.yaml          |    5 +
 .../st,stm32g0-flash-controller.yaml          |    5 +
 .../st,stm32g4-flash-controller.yaml          |    5 +
 .../st,stm32h7-flash-controller.yaml          |    5 +
 .../st,stm32l0-flash-controller.yaml          |    8 +
 .../st,stm32l1-flash-controller.yaml          |    5 +
 .../st,stm32l4-flash-controller.yaml          |    5 +
 .../st,stm32l5-flash-controller.yaml          |    5 +
 .../st,stm32u5-flash-controller.yaml          |    5 +
 .../st,stm32wb-flash-controller.yaml          |   16 +
 .../telink,b91-flash-controller.yaml          |    5 +
 .../ti,stellaris-flash-controller.yaml        |    8 +
 .../flash_controller/zephyr,sim-flash.yaml    |   16 +
 dts/bindings/fs/zephyr,fstab,littlefs.yaml    |   78 +
 dts/bindings/fs/zephyr,fstab-common.yaml      |   51 +
 dts/bindings/fs/zephyr,fstab.yaml             |   12 +
 .../gpio/adafruit-feather-header.yaml         |   39 +
 dts/bindings/gpio/andestech,atcgpio100.yaml   |   27 +
 dts/bindings/gpio/arduino-header-r3.yaml      |   50 +
 dts/bindings/gpio/arm,cmsdk-gpio.yaml         |   22 +
 dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml   |   18 +
 dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml   |   18 +
 dts/bindings/gpio/atmel,sam-gpio.yaml         |   38 +
 dts/bindings/gpio/atmel,sam0-gpio.yaml        |   29 +
 dts/bindings/gpio/atmel,sam4l-gpio.yaml       |    5 +
 dts/bindings/gpio/atmel-xplained-header.yaml  |   45 +
 .../gpio/atmel-xplained-pro-header.yaml       |   49 +
 .../gpio/cypress,cy8c95xx-gpio-port.yaml      |   26 +
 dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml  |   15 +
 dts/bindings/gpio/cypress,psoc6-gpio.yaml     |   35 +
 dts/bindings/gpio/cypress,psoc6-hsiom.yaml    |   18 +
 dts/bindings/gpio/espressif,esp32-gpio.yaml   |   22 +
 dts/bindings/gpio/fcs,fxl6408.yaml            |   19 +
 dts/bindings/gpio/gd,gd32-gpio.yaml           |   27 +
 dts/bindings/gpio/gpio-controller.yaml        |   45 +
 dts/bindings/gpio/gpio-keys.yaml              |   17 +
 dts/bindings/gpio/gpio-leds.yaml              |   32 +
 dts/bindings/gpio/gpio-nexus.yaml             |   22 +
 dts/bindings/gpio/intel,gpio.yaml             |   38 +
 dts/bindings/gpio/ite,it8xxx2-gpio.yaml       |   19 +
 dts/bindings/gpio/linaro,96b-lscon-1v8.yaml   |    8 +
 dts/bindings/gpio/linaro,96b-lscon-3v3.yaml   |    9 +
 dts/bindings/gpio/litex,gpio.yaml             |   32 +
 .../gpio/microbit,edge-connector.yaml         |   25 +
 dts/bindings/gpio/microchip,mcp230xx.yaml     |   29 +
 dts/bindings/gpio/microchip,mcp23s17.yaml     |   29 +
 dts/bindings/gpio/microchip,mcp23sxx.yaml     |   32 +
 dts/bindings/gpio/microchip,xec-gpio-v2.yaml  |   35 +
 dts/bindings/gpio/microchip,xec-gpio.yaml     |   25 +
 dts/bindings/gpio/mikro-bus.yaml              |   33 +
 dts/bindings/gpio/neorv32-gpio.yaml           |   25 +
 dts/bindings/gpio/nordic,nrf-gpio.yaml        |   41 +
 dts/bindings/gpio/nordic,nrf-gpiote.yaml      |   18 +
 .../gpio/nuvoton,nct38xx-gpio-alert.yaml      |   32 +
 .../gpio/nuvoton,nct38xx-gpio-port.yaml       |   44 +
 dts/bindings/gpio/nuvoton,nct38xx-gpio.yaml   |   83 +
 dts/bindings/gpio/nuvoton,npcx-gpio.yaml      |   39 +
 dts/bindings/gpio/nuvoton,npcx-psl-out.yaml   |   19 +
 dts/bindings/gpio/nxp,imx-gpio.yaml           |   30 +
 dts/bindings/gpio/nxp,kinetis-gpio.yaml       |   26 +
 dts/bindings/gpio/nxp,lpc-gpio.yaml           |   31 +
 dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml      |   41 +
 dts/bindings/gpio/nxp,pca95xx.yaml            |   29 +
 dts/bindings/gpio/nxp,pcal6408a.yaml          |   35 +
 dts/bindings/gpio/openisa,rv32m1-gpio.yaml    |   29 +
 dts/bindings/gpio/particle-gen3-header.yaml   |   43 +
 dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml |   39 +
 dts/bindings/gpio/renesas,rcar-gpio.yaml      |   28 +
 dts/bindings/gpio/seeed-xiao-header.yaml      |   33 +
 dts/bindings/gpio/semtech,sx1509b.yaml        |   46 +
 dts/bindings/gpio/sifive,gpio0.yaml           |   25 +
 dts/bindings/gpio/silabs,gecko-gpio-port.yaml |   24 +
 dts/bindings/gpio/silabs,gecko-gpio.yaml      |   20 +
 dts/bindings/gpio/snps,creg-gpio.yaml         |   34 +
 dts/bindings/gpio/snps,designware-gpio.yaml   |   25 +
 dts/bindings/gpio/st,stm32-gpio.yaml          |   25 +
 dts/bindings/gpio/st,stmpe1600.yaml           |   19 +
 dts/bindings/gpio/telink,b91-gpio.yaml        |   22 +
 dts/bindings/gpio/ti,boosterpack-header.yaml  |   34 +
 dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml  |   25 +
 dts/bindings/gpio/ti,cc32xx-gpio.yaml         |   23 +
 dts/bindings/gpio/ti,lmp90xxx-gpio.yaml       |   18 +
 dts/bindings/gpio/ti,stellaris-gpio.yaml      |   24 +
 dts/bindings/gpio/ti,tca9538.yaml             |   33 +
 .../gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml      |   18 +
 dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml   |   79 +
 dts/bindings/gpio/zephyr,gpio-emul.yaml       |   38 +
 dts/bindings/hwinfo/atmel,sam4l-uid.yaml      |   12 +
 dts/bindings/hwinfo/cypress,psoc6-uid.yaml    |   12 +
 dts/bindings/hwinfo/litex,dna0.yaml           |   12 +
 dts/bindings/hwinfo/nxp,lpc-uid.yaml          |   12 +
 dts/bindings/i2c/altr,nios2-i2c.yaml          |   15 +
 dts/bindings/i2c/arm,versatile-i2c.yaml       |   12 +
 dts/bindings/i2c/asmedia,asm2364.yaml         |   16 +
 dts/bindings/i2c/atmel,sam-i2c-twi.yaml       |   32 +
 dts/bindings/i2c/atmel,sam-i2c-twihs.yaml     |   32 +
 dts/bindings/i2c/atmel,sam-i2c-twim.yaml      |  215 ++
 dts/bindings/i2c/atmel,sam0-i2c.yaml          |   38 +
 dts/bindings/i2c/espressif,esp32-i2c.yaml     |   35 +
 dts/bindings/i2c/fsl,imx21-i2c.yaml           |   20 +
 dts/bindings/i2c/gpio-i2c.yaml                |   18 +
 dts/bindings/i2c/i2c-controller.yaml          |   22 +
 dts/bindings/i2c/i2c-device.yaml              |   15 +
 dts/bindings/i2c/ite,it8xxx2-i2c.yaml         |   35 +
 dts/bindings/i2c/litex,i2c.yaml               |   15 +
 dts/bindings/i2c/microchip,xec-i2c-v2.yaml    |   43 +
 dts/bindings/i2c/microchip,xec-i2c.yaml       |   27 +
 dts/bindings/i2c/nordic,nrf-twi-common.yaml   |   37 +
 dts/bindings/i2c/nordic,nrf-twi.yaml          |   45 +
 dts/bindings/i2c/nordic,nrf-twim.yaml         |   63 +
 dts/bindings/i2c/nordic,nrf-twis.yaml         |   41 +
 dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml   |   16 +
 dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml   |   27 +
 dts/bindings/i2c/nxp,imx-lpi2c.yaml           |   20 +
 dts/bindings/i2c/nxp,kinetis-i2c.yaml         |   19 +
 dts/bindings/i2c/nxp,lpc-i2c.yaml             |    8 +
 dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml        |   28 +
 dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml    |   15 +
 dts/bindings/i2c/renesas,rcar-i2c.yaml        |   16 +
 dts/bindings/i2c/sifive,i2c0.yaml             |   17 +
 dts/bindings/i2c/silabs,gecko-i2c.yaml        |   28 +
 dts/bindings/i2c/snps,designware-i2c.yaml     |   15 +
 dts/bindings/i2c/st,stm32-i2c-v1.yaml         |   21 +
 dts/bindings/i2c/st,stm32-i2c-v2.yaml         |   46 +
 dts/bindings/i2c/telink,b91-i2c.yaml          |   16 +
 dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml    |   25 +
 dts/bindings/i2c/ti,cc32xx-i2c.yaml           |   12 +
 dts/bindings/i2c/ti,tca9546a.yaml             |   10 +
 dts/bindings/i2c/ti,tca9548a.yaml             |   10 +
 dts/bindings/i2c/ti,tca954x-base.yaml         |   60 +
 .../i2c/zephyr,i2c-emul-controller.yaml       |   12 +
 dts/bindings/i2s/i2s-controller.yaml          |   18 +
 dts/bindings/i2s/i2s-device.yaml              |   14 +
 dts/bindings/i2s/intel,cavs-i2s.yaml          |   25 +
 dts/bindings/i2s/litex,i2s.yaml               |   18 +
 dts/bindings/i2s/nordic,nrf-i2s.yaml          |   60 +
 dts/bindings/i2s/nxp,lpc-i2s.yaml             |    8 +
 dts/bindings/i2s/nxp,mcux-i2s.yaml            |   70 +
 dts/bindings/i2s/st,stm32-i2s.yaml            |   27 +
 dts/bindings/ieee802154/atmel,rf2xx.yaml      |   40 +
 dts/bindings/ieee802154/decawave,dw1000.yaml  |   37 +
 dts/bindings/ieee802154/nxp,mcr20a.yaml       |   27 +
 dts/bindings/ieee802154/telink,b91-zb.yaml    |   18 +
 dts/bindings/ieee802154/ti,cc1200.yaml        |   13 +
 dts/bindings/ieee802154/ti,cc2520.yaml        |   33 +
 dts/bindings/iio/adc/nuvoton,npcx-adc.yaml    |   23 +
 dts/bindings/iio/adc/nxp,lpc-lpadc.yaml       |   56 +
 .../interrupt-controller/arm,gic-v3-its.yaml  |   15 +
 .../interrupt-controller/arm,gic.yaml         |   21 +
 .../interrupt-controller/arm,v6m-nvic.yaml    |   21 +
 .../interrupt-controller/arm,v7m-nvic.yaml    |   21 +
 .../interrupt-controller/arm,v8.1m-nvic.yaml  |   21 +
 .../interrupt-controller/arm,v8m-nvic.yaml    |   21 +
 .../interrupt-controller/atmel,sam0-eic.yaml  |   15 +
 .../cdns,xtensa-core-intc.yaml                |   17 +
 .../cypress,psoc6-intmux-ch.yaml              |   26 +
 .../cypress,psoc6-intmux.yaml                 |   79 +
 .../espressif,esp32-intc.yaml                 |   14 +
 .../interrupt-controller/gaisler,irqmp.yaml   |   22 +
 .../interrupt-controller/intel,cavs-intc.yaml |   23 +
 .../interrupt-controller/intel,ioapic.yaml    |   17 +
 .../interrupt-controller/intel,vt-d.yaml      |   15 +
 .../interrupt-controller.yaml                 |   14 +
 .../ite,it8xxx2-intc.yaml                     |   15 +
 .../microchip,xec-ecia-girq.yaml              |   26 +
 .../microchip,xec-ecia.yaml                   |   22 +
 .../interrupt-controller/nuclei,eclic.yaml    |   19 +
 .../nuvoton,npcx-miwu-int-map.yaml            |   32 +
 .../nuvoton,npcx-miwu-wui-map.yaml            |   13 +
 .../nuvoton,npcx-miwu.yaml                    |   26 +
 .../openisa,rv32m1-event-unit.yaml            |   19 +
 .../openisa,rv32m1-intmux-ch.yaml             |   21 +
 .../openisa,rv32m1-intmux.yaml                |   15 +
 .../interrupt-controller/riscv,clint0.yaml    |   18 +
 .../interrupt-controller/riscv,cpu-intc.yaml  |   15 +
 .../interrupt-controller/riscv,plic0.yaml     |   22 +
 .../interrupt-controller/shared-irq.yaml      |   12 +
 .../sifive,plic-1.0.0.yaml                    |   14 +
 .../snps,archs-idu-intc.yaml                  |   15 +
 .../interrupt-controller/snps,arcv2-intc.yaml |   16 +
 .../snps,designware-intc.yaml                 |   25 +
 .../interrupt-controller/st,stm32-exti.yaml   |    9 +
 .../interrupt-controller/swerv,pic.yaml       |   20 +
 .../interrupt-controller/vexriscv-intc0.yaml  |   24 +
 .../ipc/zephyr,ipc-openamp-static-vrings.yaml |   30 +
 dts/bindings/ipm/intel,adsp-mailbox.yaml      |   15 +
 dts/bindings/ipm/intel,cavs-idc.yaml          |   15 +
 dts/bindings/ipm/nordic,nrf-ipc.yaml          |   15 +
 dts/bindings/ipm/nxp,lpc-mailbox.yaml         |   18 +
 dts/bindings/ipm/st,stm32-hsem-mailbox.yaml   |   15 +
 dts/bindings/ipm/st,stm32-ipcc-mailbox.yaml   |   12 +
 dts/bindings/ipm/zephyr,ipm-console.yaml      |   12 +
 dts/bindings/kscan/focaltech,ft5336.yaml      |   13 +
 .../kscan/holtek,ht16k33-keyscan.yaml         |   11 +
 dts/bindings/kscan/ite,it8xxx2-kscan.yaml     |   25 +
 dts/bindings/kscan/kscan.yaml                 |   12 +
 dts/bindings/kscan/microchip,xec-kscan.yaml   |   21 +
 dts/bindings/led/holtek,ht16k33.yaml          |   15 +
 dts/bindings/led/led-controller.yaml          |   39 +
 dts/bindings/led/nxp,pca9633.yaml             |    5 +
 dts/bindings/led/pwm-leds.yaml                |   33 +
 dts/bindings/led/ti,lp3943.yaml               |    5 +
 dts/bindings/led/ti,lp503x.yaml               |   30 +
 dts/bindings/led/ti,lp5562.yaml               |    5 +
 dts/bindings/led/ti,tlc59108.yaml             |    5 +
 dts/bindings/led_strip/apa,apa102.yaml        |    5 +
 dts/bindings/led_strip/greeled,lpd8803.yaml   |    8 +
 dts/bindings/led_strip/greeled,lpd8806.yaml   |    8 +
 .../led_strip/worldsemi,ws2812-gpio.yaml      |   25 +
 .../led_strip/worldsemi,ws2812-spi.yaml       |   35 +
 dts/bindings/led_strip/ws2812.yaml            |   66 +
 dts/bindings/lora/semtech,sx1261.yaml         |   16 +
 dts/bindings/lora/semtech,sx1262.yaml         |   16 +
 dts/bindings/lora/semtech,sx126x-base.yaml    |   70 +
 dts/bindings/lora/semtech,sx1272.yaml         |    8 +
 dts/bindings/lora/semtech,sx1276.yaml         |    8 +
 dts/bindings/lora/semtech,sx127x-base.yaml    |   70 +
 .../lora/st,stm32wl-subghz-radio.yaml         |   14 +
 dts/bindings/mailbox/mailbox-controller.yaml  |   10 +
 dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml    |   25 +
 dts/bindings/mdio/atmel,sam-mdio.yaml         |   18 +
 dts/bindings/mdio/mdio-controller.yaml        |   27 +
 .../memory-controllers/ite,it8xxx2-bbram.yaml |   15 +
 .../nuvoton,npcx-bbram.yaml                   |   15 +
 .../memory-controllers/nxp,imx-semc.yaml      |   18 +
 .../st,stm32-backup-sram.yaml                 |   22 +
 .../st,stm32-fmc-sdram.yaml                   |  169 +
 .../memory-controllers/st,stm32-fmc.yaml      |   48 +
 .../memory-controllers/zephyr,bbram-emul.yaml |   17 +
 dts/bindings/mhu/arm,mhu.yaml                 |   18 +
 .../misc/nuvoton,npcx-booter-variant.yaml     |   14 +
 dts/bindings/misc/nuvoton,npcx-soc-id.yaml    |   27 +
 dts/bindings/misc/skyworks,sky13351.yaml      |   18 +
 dts/bindings/misc/zephyr,modbus-serial.yaml   |   27 +
 dts/bindings/mmc/mmc.yaml                     |    6 +
 dts/bindings/mmc/nxp,imx-usdhc.yaml           |   48 +
 dts/bindings/mmc/st,stm32-sdmmc.yaml          |   31 +
 dts/bindings/mmc/zephyr,mmc-spi-slot.yaml     |    8 +
 dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml      |   18 +
 dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml      |   14 +
 dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml    |   14 +
 dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml      |   14 +
 dts/bindings/modem/openisa,rv32m1-genfsk.yaml |   15 +
 dts/bindings/modem/quectel,bg9x.yaml          |   28 +
 dts/bindings/modem/simcom,sim7080.yaml        |   16 +
 dts/bindings/modem/swir,hl7800.yaml           |   51 +
 dts/bindings/modem/u-blox,sara-r4.yaml        |   24 +
 dts/bindings/modem/wnc,m14a2a.yaml            |   37 +
 dts/bindings/modem/zephyr,gsm-ppp.yaml        |    8 +
 dts/bindings/mtd/atmel,at24.yaml              |    9 +
 dts/bindings/mtd/atmel,at25.yaml              |    8 +
 dts/bindings/mtd/atmel,at2x-base.yaml         |   29 +
 dts/bindings/mtd/atmel,at45.yaml              |   80 +
 dts/bindings/mtd/eeprom-base.yaml             |   18 +
 dts/bindings/mtd/fixed-partitions.yaml        |   39 +
 dts/bindings/mtd/jedec,jesd216.yaml           |   75 +
 dts/bindings/mtd/jedec,spi-nor-common.yaml    |   97 +
 dts/bindings/mtd/jedec,spi-nor.yaml           |   26 +
 dts/bindings/mtd/nordic,qspi-nor.yaml         |  102 +
 dts/bindings/mtd/nxp,imx-flexspi-device.yaml  |  101 +
 .../mtd/nxp,imx-flexspi-hyperflash.yaml       |    8 +
 .../mtd/nxp,imx-flexspi-hyperram.yaml         |    8 +
 .../mtd/nxp,imx-flexspi-mx25um51345g.yaml     |    8 +
 dts/bindings/mtd/nxp,imx-flexspi-nor.yaml     |    8 +
 dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml     |    8 +
 dts/bindings/mtd/soc-nv-flash.yaml            |   19 +
 dts/bindings/mtd/st,stm32-eeprom.yaml         |   12 +
 dts/bindings/mtd/st,stm32-nv-flash.yaml       |   14 +
 dts/bindings/mtd/ti,tmp116-eeprom.yaml        |   10 +
 dts/bindings/mtd/zephyr,emu-eeprom.yaml       |   31 +
 dts/bindings/mtd/zephyr,sim-eeprom.yaml       |   12 +
 .../multi_heap_manager/shared-multi-heap.yaml |   20 +
 .../wireless/generic-fem-two-ctrl-pins.yaml   |   57 +
 .../net/wireless/nordic,nrf-radio.yaml        |  217 ++
 .../net/wireless/nordic,nrf21540-fem-spi.yaml |   10 +
 .../net/wireless/nordic,nrf21540-fem.yaml     |  137 +
 dts/bindings/neural_net/intel,gna.yaml        |   19 +
 .../pcie/endpoint/brcm,iproc-pcie-ep.yaml     |   19 +
 dts/bindings/pcie/host/intel,pcie.yaml        |    8 +
 .../pcie/host/pci-host-ecam-generic.yaml      |   23 +
 dts/bindings/pcie/host/pcie-controller.yaml   |   14 +
 dts/bindings/pcie/host/ptm-root.yaml          |   10 +
 dts/bindings/peci/microchip,xec-peci.yaml     |   15 +
 dts/bindings/peci/peci.yaml                   |   20 +
 dts/bindings/phy/phy-controller.yaml          |   14 +
 dts/bindings/phy/st,stm32-usbphyc.yaml        |   15 +
 dts/bindings/phy/usb-nop-xceiv.yaml           |   14 +
 dts/bindings/pinctrl/atmel,sam-pinctrl.yaml   |   33 +
 dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml  |   55 +
 dts/bindings/pinctrl/atmel,sam0-pinmux.yaml   |   13 +
 .../pinctrl/cypress,psoc6-pinctrl.yaml        |   36 +
 .../pinctrl/espressif,esp32-pinmux.yaml       |   12 +
 dts/bindings/pinctrl/gd,gd32-afio.yaml        |   30 +
 dts/bindings/pinctrl/gd,gd32-pinctrl-af.yaml  |  111 +
 .../pinctrl/gd,gd32-pinctrl-afio.yaml         |  137 +
 .../pinctrl/gd,gd32-pinctrl-common.yaml       |   26 +
 dts/bindings/pinctrl/intel,s1000-pinmux.yaml  |   14 +
 .../pinctrl/ite,it8xxx2-pinctrl-conf.yaml     |   13 +
 dts/bindings/pinctrl/ite,it8xxx2-pinmux.yaml  |   32 +
 .../pinctrl/microchip,xec-pinmux.yaml         |   21 +
 dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml  |  110 +
 .../pinctrl/nuvoton,npcx-lvolctrl-conf.yaml   |   17 +
 .../pinctrl/nuvoton,npcx-lvolctrl-def.yaml    |   14 +
 .../pinctrl/nuvoton,npcx-pinctrl-conf.yaml    |   16 +
 .../pinctrl/nuvoton,npcx-pinctrl-def.yaml     |   14 +
 .../pinctrl/nuvoton,npcx-pslctrl-conf.yaml    |   44 +
 .../pinctrl/nuvoton,npcx-pslctrl-def.yaml     |   17 +
 dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml   |   33 +
 dts/bindings/pinctrl/nxp,imx-pinmux.yaml      |   19 +
 dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml  |   39 +
 dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml   |   12 +
 dts/bindings/pinctrl/nxp,lpc-iocon.yaml       |   12 +
 dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml |   22 +
 .../pinctrl/openisa,rv32m1-pinmux.yaml        |   16 +
 dts/bindings/pinctrl/pincfg-node-group.yaml   |  165 +
 dts/bindings/pinctrl/pincfg-node.yaml         |  160 +
 dts/bindings/pinctrl/pinctrl-device.yaml      |   43 +
 dts/bindings/pinctrl/sifive,iof.yaml          |   19 +
 .../pinctrl/snps,creg-gpio-mux-hsdk.yaml      |   17 +
 dts/bindings/pinctrl/st,stm32-pinctrl.yaml    |   94 +
 dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml  |  105 +
 dts/bindings/pinctrl/telink,b91-pinmux.yaml   |   29 +
 .../pinctrl/ti,cc13xx-cc26xx-pinmux.yaml      |   12 +
 dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml     |   20 +
 dts/bindings/power/nordic,nrf-power.yaml      |   15 +
 dts/bindings/power/nordic,nrf-regulators.yaml |   12 +
 dts/bindings/power/nordic,nrf-vmc.yaml        |   12 +
 dts/bindings/power/telink,b91-power.yaml      |   27 +
 dts/bindings/power/zephyr,power-state.yaml    |   36 +
 dts/bindings/ps2/microchip,xec-ps2.yaml       |   25 +
 .../ps2/nuvoton,npcx-ps2-channel.yaml         |   19 +
 dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml   |   20 +
 dts/bindings/ps2/ps2.yaml                     |   20 +
 dts/bindings/pwm/atmel,sam-pwm.yaml           |   38 +
 dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml      |   62 +
 dts/bindings/pwm/espressif,esp32-ledc.yaml    |   17 +
 dts/bindings/pwm/fsl,imx27-pwm.yaml           |   38 +
 dts/bindings/pwm/ite,it8xxx2-pwm.yaml         |   63 +
 dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml      |   18 +
 dts/bindings/pwm/litex,pwm.yaml               |   15 +
 dts/bindings/pwm/microchip,xec-pwm.yaml       |   15 +
 dts/bindings/pwm/nordic,nrf-pwm.yaml          |   77 +
 dts/bindings/pwm/nordic,nrf-sw-pwm.yaml       |   36 +
 dts/bindings/pwm/nuvoton,npcx-pwm.yaml        |   38 +
 dts/bindings/pwm/nxp,flexpwm.yaml             |   15 +
 dts/bindings/pwm/nxp,imx-pwm.yaml             |   26 +
 dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml     |   22 +
 dts/bindings/pwm/nxp,kinetis-pwt.yaml         |   38 +
 dts/bindings/pwm/nxp,kinetis-tpm.yaml         |   28 +
 dts/bindings/pwm/nxp,sctimer-pwm.yaml         |   31 +
 dts/bindings/pwm/openisa,rv32m1-tpm.yaml      |   24 +
 dts/bindings/pwm/pwm-controller.yaml          |   13 +
 dts/bindings/pwm/sifive,pwm0.yaml             |   33 +
 dts/bindings/pwm/silabs,gecko-pwm.yaml        |   36 +
 dts/bindings/pwm/snps,designware-pwm.yaml     |   17 +
 dts/bindings/pwm/st,stm32-pwm.yaml            |   34 +
 dts/bindings/pwm/telink,b91-pwm.yaml          |   66 +
 .../pwm/xlnx,xps-timer-1.00.a-pwm.yaml        |   24 +
 dts/bindings/qspi/st,stm32-qspi.yaml          |   52 +
 dts/bindings/regulator/regulator-fixed.yaml   |   50 +
 dts/bindings/regulator/regulator-pmic.yaml    |   92 +
 dts/bindings/regulator/regulator.yaml         |   17 +
 .../reserved-memory/reserved-memory.yaml      |   23 +
 dts/bindings/riscv/openisa,rv32m1-pcc.yaml    |   21 +
 dts/bindings/riscv/riscv,cpus.yaml            |   31 +
 dts/bindings/riscv/riscv,sifive-e24.yaml      |    8 +
 dts/bindings/riscv/riscv,sifive.yaml          |   12 +
 dts/bindings/rng/atmel,sam-trng.yaml          |   23 +
 dts/bindings/rng/espressif,esp32-trng.yaml    |   22 +
 dts/bindings/rng/litex,prbs.yaml              |   12 +
 dts/bindings/rng/neorv32-trng.yaml            |   15 +
 dts/bindings/rng/nordic,nrf-rng.yaml          |   15 +
 dts/bindings/rng/nxp,kinetis-rnga.yaml        |   18 +
 dts/bindings/rng/nxp,kinetis-trng.yaml        |   18 +
 dts/bindings/rng/nxp,lpc-rng.yaml             |   18 +
 dts/bindings/rng/openisa,rv32m1-trng.yaml     |   18 +
 dts/bindings/rng/silabs,gecko-trng.yaml       |   21 +
 dts/bindings/rng/st,stm32-rng.yaml            |   32 +
 dts/bindings/rng/telink,b91-trng.yaml         |   15 +
 dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml   |   18 +
 dts/bindings/rng/zephyr,native-posix-rng.yaml |   12 +
 dts/bindings/rtc/atmel,sam0-rtc.yaml          |   17 +
 dts/bindings/rtc/maxim,ds3231.yaml            |   39 +
 dts/bindings/rtc/microchip,mcp7940n.yaml      |   24 +
 dts/bindings/rtc/microchip,xec-timer.yaml     |   54 +
 dts/bindings/rtc/nordic,nrf-rtc.yaml          |   37 +
 dts/bindings/rtc/nxp,imx-snvs-rtc.yaml        |   11 +
 dts/bindings/rtc/nxp,kinetis-lptmr.yaml       |   33 +
 dts/bindings/rtc/nxp,kinetis-pit.yaml         |   22 +
 dts/bindings/rtc/nxp,kinetis-rtc.yaml         |   12 +
 dts/bindings/rtc/rtc.yaml                     |   21 +
 dts/bindings/rtc/silabs,gecko-rtcc.yaml       |   12 +
 dts/bindings/rtc/st,stm32-rtc.yaml            |   12 +
 dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml    |   15 +
 dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml   |   71 +
 dts/bindings/sensor/adi,adt7420.yaml          |   16 +
 dts/bindings/sensor/adi,adxl345.yaml          |    8 +
 dts/bindings/sensor/adi,adxl362.yaml          |   17 +
 dts/bindings/sensor/adi,adxl372-i2c.yaml      |   17 +
 dts/bindings/sensor/adi,adxl372-spi.yaml      |   18 +
 dts/bindings/sensor/ams,ccs811.yaml           |   31 +
 dts/bindings/sensor/ams,ens210.yaml           |    9 +
 dts/bindings/sensor/ams,iaqcore.yaml          |    8 +
 dts/bindings/sensor/aosong,dht.yaml           |   32 +
 dts/bindings/sensor/asahi-kasei,ak8975.yaml   |   10 +
 dts/bindings/sensor/atmel,sam-tc-qdec.yaml    |   36 +
 dts/bindings/sensor/avago,apds9960.yaml       |   18 +
 dts/bindings/sensor/bosch,bma280.yaml         |   26 +
 dts/bindings/sensor/bosch,bmc150_magn.yaml    |   15 +
 dts/bindings/sensor/bosch,bme280-i2c.yaml     |    8 +
 dts/bindings/sensor/bosch,bme280-spi.yaml     |    8 +
 dts/bindings/sensor/bosch,bme680-i2c.yaml     |   10 +
 dts/bindings/sensor/bosch,bmg160.yaml         |   15 +
 dts/bindings/sensor/bosch,bmi160.yaml         |   17 +
 dts/bindings/sensor/bosch,bmi270-i2c.yaml     |   10 +
 dts/bindings/sensor/bosch,bmm150.yaml         |   10 +
 dts/bindings/sensor/bosch,bmp388-i2c.yaml     |    9 +
 dts/bindings/sensor/bosch,bmp388-spi.yaml     |    9 +
 dts/bindings/sensor/bosch,bmp388.yaml         |  109 +
 dts/bindings/sensor/honeywell,hmc5883l.yaml   |   18 +
 dts/bindings/sensor/honeywell,mpr.yaml        |    9 +
 dts/bindings/sensor/honeywell,sm351lt.yaml    |   18 +
 dts/bindings/sensor/hoperf,hp206c.yaml        |   11 +
 dts/bindings/sensor/hoperf,th02.yaml          |   10 +
 dts/bindings/sensor/infineon,dps310.yaml      |   11 +
 dts/bindings/sensor/invensense,icm42605.yaml  |   89 +
 dts/bindings/sensor/invensense,mpu6050.yaml   |   19 +
 dts/bindings/sensor/invensense,mpu9150.yaml   |   23 +
 dts/bindings/sensor/isil,isl29035.yaml        |   19 +
 dts/bindings/sensor/lm75.yaml                 |    8 +
 dts/bindings/sensor/lm77.yaml                 |   35 +
 dts/bindings/sensor/maxim,max17055.yaml       |   48 +
 dts/bindings/sensor/maxim,max17262.yaml       |   47 +
 dts/bindings/sensor/maxim,max30101.yaml       |    8 +
 dts/bindings/sensor/maxim,max44009.yaml       |   15 +
 dts/bindings/sensor/maxim,max6675.yaml        |    8 +
 dts/bindings/sensor/meas,ms5607-i2c.yaml      |   10 +
 dts/bindings/sensor/meas,ms5607-spi.yaml      |   10 +
 dts/bindings/sensor/meas,ms5837.yaml          |    8 +
 dts/bindings/sensor/microchip,mcp9808.yaml    |   33 +
 dts/bindings/sensor/nordic,nrf-qdec.yaml      |   65 +
 dts/bindings/sensor/nordic,nrf-temp.yaml      |   18 +
 dts/bindings/sensor/nxp,fxas21002.yaml        |   27 +
 dts/bindings/sensor/nxp,fxos8700.yaml         |  159 +
 dts/bindings/sensor/nxp,kinetis-acmp.yaml     |   68 +
 .../sensor/nxp,kinetis-temperature.yaml       |   45 +
 dts/bindings/sensor/panasonic,amg88xx.yaml    |   18 +
 dts/bindings/sensor/plantower,pms7003.yaml    |   12 +
 dts/bindings/sensor/sbs,sbs-gauge.yaml        |    5 +
 dts/bindings/sensor/seeed,grove-light.yaml    |   14 +
 .../sensor/seeed,grove-temperature.yaml       |   19 +
 dts/bindings/sensor/semtech,sx9500.yaml       |   18 +
 dts/bindings/sensor/sensirion,sgp40.yaml      |   17 +
 dts/bindings/sensor/sensirion,sht3xd.yaml     |   19 +
 dts/bindings/sensor/sensirion,sht4x.yaml      |   24 +
 dts/bindings/sensor/sensirion,shtcx.yaml      |   37 +
 dts/bindings/sensor/silabs,si7006.yaml        |    8 +
 dts/bindings/sensor/silabs,si7055.yaml        |    8 +
 dts/bindings/sensor/silabs,si7060.yaml        |    8 +
 dts/bindings/sensor/silabs,si7210.yaml        |    8 +
 dts/bindings/sensor/st,hts221-common.yaml     |   12 +
 dts/bindings/sensor/st,hts221-i2c.yaml        |    9 +
 dts/bindings/sensor/st,hts221-spi.yaml        |    9 +
 dts/bindings/sensor/st,i3g4250d.yaml          |    9 +
 dts/bindings/sensor/st,iis2dh-i2c.yaml        |   19 +
 dts/bindings/sensor/st,iis2dh-spi.yaml        |   19 +
 dts/bindings/sensor/st,iis2dlpc-common.yaml   |  116 +
 dts/bindings/sensor/st,iis2dlpc-i2c.yaml      |    9 +
 dts/bindings/sensor/st,iis2dlpc-spi.yaml      |    9 +
 dts/bindings/sensor/st,iis2iclx-common.yaml   |   57 +
 dts/bindings/sensor/st,iis2iclx-i2c.yaml      |   10 +
 dts/bindings/sensor/st,iis2iclx-spi.yaml      |   10 +
 dts/bindings/sensor/st,iis2mdc-i2c.yaml       |   19 +
 dts/bindings/sensor/st,iis2mdc-spi.yaml       |   19 +
 dts/bindings/sensor/st,iis3dhhc-spi.yaml      |   19 +
 dts/bindings/sensor/st,ism330dhcx-common.yaml |  136 +
 dts/bindings/sensor/st,ism330dhcx-i2c.yaml    |   10 +
 dts/bindings/sensor/st,ism330dhcx-spi.yaml    |   10 +
 dts/bindings/sensor/st,lis2dh-common.yaml     |   19 +
 dts/bindings/sensor/st,lis2dh-i2c.yaml        |    9 +
 dts/bindings/sensor/st,lis2dh-spi.yaml        |    9 +
 dts/bindings/sensor/st,lis2dh12-i2c.yaml      |    8 +
 dts/bindings/sensor/st,lis2ds12-common.yaml   |   60 +
 dts/bindings/sensor/st,lis2ds12-i2c.yaml      |    8 +
 dts/bindings/sensor/st,lis2ds12-spi.yaml      |    9 +
 dts/bindings/sensor/st,lis2dw12-common.yaml   |  140 +
 dts/bindings/sensor/st,lis2dw12-i2c.yaml      |    8 +
 dts/bindings/sensor/st,lis2dw12-spi.yaml      |    9 +
 dts/bindings/sensor/st,lis2mdl-common.yaml    |   32 +
 dts/bindings/sensor/st,lis2mdl-i2c.yaml       |    9 +
 dts/bindings/sensor/st,lis2mdl-spi.yaml       |    9 +
 dts/bindings/sensor/st,lis3dh-i2c.yaml        |    8 +
 dts/bindings/sensor/st,lis3mdl-magn.yaml      |   18 +
 dts/bindings/sensor/st,lps22hb-press.yaml     |    8 +
 dts/bindings/sensor/st,lps22hh-common.yaml    |   30 +
 dts/bindings/sensor/st,lps22hh-i2c.yaml       |   10 +
 dts/bindings/sensor/st,lps22hh-spi.yaml       |   10 +
 dts/bindings/sensor/st,lps25hb-press.yaml     |    8 +
 .../sensor/st,lsm303agr-accel-i2c.yaml        |    9 +
 .../sensor/st,lsm303agr-accel-spi.yaml        |    9 +
 dts/bindings/sensor/st,lsm303dlhc-accel.yaml  |    8 +
 dts/bindings/sensor/st,lsm303dlhc-magn.yaml   |    8 +
 dts/bindings/sensor/st,lsm6ds0.yaml           |    8 +
 dts/bindings/sensor/st,lsm6dsl-i2c.yaml       |   14 +
 dts/bindings/sensor/st,lsm6dsl-spi.yaml       |   16 +
 dts/bindings/sensor/st,lsm6dso-common.yaml    |  116 +
 dts/bindings/sensor/st,lsm6dso-i2c.yaml       |   10 +
 dts/bindings/sensor/st,lsm6dso-spi.yaml       |   10 +
 dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml  |   13 +
 dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml   |   13 +
 dts/bindings/sensor/st,stm32-temp.yaml        |   43 +
 dts/bindings/sensor/st,stts751-i2c.yaml       |   19 +
 dts/bindings/sensor/st,vl53l0x.yaml           |   13 +
 dts/bindings/sensor/ti,bq274xx.yaml           |   42 +
 dts/bindings/sensor/ti,fdc2x1x.yaml           |  259 ++
 dts/bindings/sensor/ti,hdc.yaml               |   18 +
 dts/bindings/sensor/ti,hdc2010.yaml           |    8 +
 dts/bindings/sensor/ti,hdc2021.yaml           |    8 +
 dts/bindings/sensor/ti,hdc2022.yaml           |    8 +
 dts/bindings/sensor/ti,hdc2080.yaml           |    8 +
 dts/bindings/sensor/ti,hdc20xx.yaml           |   18 +
 dts/bindings/sensor/ti,ina219.yaml            |  131 +
 dts/bindings/sensor/ti,ina230.yaml            |   36 +
 dts/bindings/sensor/ti,ina237.yaml            |   23 +
 dts/bindings/sensor/ti,ina23x-common.yaml     |   33 +
 dts/bindings/sensor/ti,opt3001.yaml           |    8 +
 dts/bindings/sensor/ti,tmp007.yaml            |   18 +
 dts/bindings/sensor/ti,tmp108.yaml            |   18 +
 dts/bindings/sensor/ti,tmp112.yaml            |   24 +
 dts/bindings/sensor/ti,tmp116.yaml            |   10 +
 dts/bindings/sensor/vishay,vcnl4040.yaml      |   88 +
 dts/bindings/sensor/we,wsen-itds.yaml         |   41 +
 dts/bindings/sensor/winsen,mhz19b.yaml        |   24 +
 dts/bindings/serial/altr,jtag-uart.yaml       |    9 +
 dts/bindings/serial/arm,cmsdk-uart.yaml       |   12 +
 dts/bindings/serial/arm,pl011.yaml            |   12 +
 dts/bindings/serial/arm,sbsa-uart.yaml        |   12 +
 dts/bindings/serial/atmel,sam-uart.yaml       |   30 +
 dts/bindings/serial/atmel,sam-usart.yaml      |   30 +
 dts/bindings/serial/atmel,sam0-uart.yaml      |   62 +
 dts/bindings/serial/cypress,psoc6-uart.yaml   |   34 +
 dts/bindings/serial/espressif,esp32-uart.yaml |   32 +
 dts/bindings/serial/gaisler,apbuart.yaml      |    9 +
 dts/bindings/serial/gd,gd32-usart.yaml        |   20 +
 .../serial/infineon,xmc4xxx-uart.yaml         |    9 +
 dts/bindings/serial/ite,it8xxx2-uart.yaml     |   26 +
 dts/bindings/serial/litex,uart0.yaml          |   15 +
 dts/bindings/serial/microchip,xec-uart.yaml   |   43 +
 dts/bindings/serial/microsemi,coreuart.yaml   |   12 +
 dts/bindings/serial/neorv32-uart.yaml         |   24 +
 .../serial/nordic,nrf-uart-common.yaml        |   99 +
 dts/bindings/serial/nordic,nrf-uart.yaml      |   10 +
 dts/bindings/serial/nordic,nrf-uarte.yaml     |    5 +
 dts/bindings/serial/ns16550.yaml              |   24 +
 dts/bindings/serial/nuvoton,npcx-uart.yaml    |   26 +
 dts/bindings/serial/nuvoton,numicro-uart.yaml |    9 +
 dts/bindings/serial/nxp,imx-iuart.yaml        |   16 +
 dts/bindings/serial/nxp,imx-uart.yaml         |   25 +
 dts/bindings/serial/nxp,kinetis-lpsci.yaml    |   16 +
 dts/bindings/serial/nxp,kinetis-lpuart.yaml   |   12 +
 dts/bindings/serial/nxp,kinetis-uart.yaml     |   19 +
 dts/bindings/serial/nxp,lpc-usart.yaml        |    8 +
 dts/bindings/serial/nxp,lpc11u6x-uart.yaml    |   25 +
 .../serial/openisa,rv32m1-lpuart.yaml         |   12 +
 dts/bindings/serial/renesas,rcar-scif.yaml    |   15 +
 dts/bindings/serial/segger,rtt-uart.yaml      |   27 +
 dts/bindings/serial/sifive,uart0.yaml         |   15 +
 dts/bindings/serial/silabs,gecko-leuart.yaml  |   30 +
 dts/bindings/serial/silabs,gecko-uart.yaml    |   30 +
 dts/bindings/serial/silabs,gecko-usart.yaml   |   40 +
 dts/bindings/serial/snps,nsim-uart.yaml       |   12 +
 dts/bindings/serial/st,stm32-lpuart.yaml      |   21 +
 dts/bindings/serial/st,stm32-uart.yaml        |   18 +
 dts/bindings/serial/st,stm32-usart.yaml       |   18 +
 dts/bindings/serial/telink,b91-uart.yaml      |   19 +
 .../serial/ti,cc13xx-cc26xx-uart.yaml         |   25 +
 dts/bindings/serial/ti,cc32xx-uart.yaml       |   12 +
 dts/bindings/serial/ti,msp432p4xx-uart.yaml   |   12 +
 dts/bindings/serial/ti,stellaris-uart.yaml    |   12 +
 dts/bindings/serial/uart-controller.yaml      |   31 +
 dts/bindings/serial/uart-device.yaml          |   12 +
 .../serial/xlnx,xps-uartlite-1.00.a.yaml      |    9 +
 dts/bindings/serial/xlnx,xuartps.yaml         |    9 +
 dts/bindings/serial/zephyr,cdc-acm-uart.yaml  |   10 +
 .../serial/zephyr,native-posix-uart.yaml      |    8 +
 dts/bindings/spi/atmel,sam-spi.yaml           |   33 +
 dts/bindings/spi/atmel,sam0-spi.yaml          |   45 +
 dts/bindings/spi/cypress,psoc6-spi.yaml       |   34 +
 dts/bindings/spi/espressif,esp32-spi.yaml     |   79 +
 dts/bindings/spi/ite,it8xxx2-sspi.yaml        |   15 +
 dts/bindings/spi/litex,spi.yaml               |   12 +
 .../spi/microchip,xec-qmspi-ldma.yaml         |  106 +
 dts/bindings/spi/microchip,xec-qmspi.yaml     |   57 +
 dts/bindings/spi/nordic,nrf-spi-common.yaml   |   43 +
 dts/bindings/spi/nordic,nrf-spi.yaml          |   19 +
 dts/bindings/spi/nordic,nrf-spim.yaml         |   27 +
 dts/bindings/spi/nordic,nrf-spis.yaml         |   23 +
 dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml    |   16 +
 dts/bindings/spi/nxp,imx-flexspi.yaml         |   74 +
 dts/bindings/spi/nxp,imx-lpspi.yaml           |   39 +
 dts/bindings/spi/nxp,kinetis-dspi.yaml        |   95 +
 dts/bindings/spi/nxp,lpc-spi.yaml             |   38 +
 dts/bindings/spi/opencores,spi-simple.yaml    |   12 +
 dts/bindings/spi/openisa,rv32m1-lpspi.yaml    |   15 +
 dts/bindings/spi/sifive,spi0.yaml             |   12 +
 dts/bindings/spi/silabs,gecko-spi-usart.yaml  |   35 +
 dts/bindings/spi/snps,designware-spi.yaml     |   15 +
 dts/bindings/spi/spi-controller.yaml          |   63 +
 dts/bindings/spi/spi-device.yaml              |   45 +
 dts/bindings/spi/st,stm32-spi-common.yaml     |   19 +
 dts/bindings/spi/st,stm32-spi-fifo.yaml       |    8 +
 dts/bindings/spi/st,stm32-spi-subghz.yaml     |   22 +
 dts/bindings/spi/st,stm32-spi.yaml            |    8 +
 dts/bindings/spi/telink,b91-spi.yaml          |   56 +
 dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml    |   32 +
 dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml     |   39 +
 dts/bindings/spi/zephyr,spi-bitbang.yaml      |   29 +
 .../spi/zephyr,spi-emul-controller.yaml       |   12 +
 dts/bindings/sram/mmio-sram.yaml              |   15 +
 dts/bindings/sram/sifive,dtim0.yaml           |   12 +
 dts/bindings/syscon/syscon.yaml               |   16 +
 dts/bindings/tach/ite,it8xxx2-tach.yaml       |   40 +
 dts/bindings/tach/microchip,xec-tach.yaml     |   21 +
 dts/bindings/tach/nuvoton,npcx-tach.yaml      |   32 +
 dts/bindings/tach/tach.yaml                   |   12 +
 dts/bindings/tcpc/st,stm32-ucpd.yaml          |   71 +
 dts/bindings/test/vnd,adc-temp-sensor.yaml    |   32 +
 dts/bindings/test/vnd,adc.yaml                |   15 +
 dts/bindings/test/vnd,array-holder.yaml       |   17 +
 dts/bindings/test/vnd,busy-sim.yaml           |   20 +
 dts/bindings/test/vnd,child-bindings.yaml     |   15 +
 dts/bindings/test/vnd,clock.yaml              |   16 +
 dts/bindings/test/vnd,disabled-compat.yaml    |    8 +
 dts/bindings/test/vnd,dma.yaml                |   22 +
 dts/bindings/test/vnd,enum-holder-inst.yaml   |    8 +
 dts/bindings/test/vnd,enum-holder.yaml        |   17 +
 .../vnd,enum-int-required-false-holder.yaml   |   18 +
 .../vnd,enum-required-false-holder-inst.yaml  |    8 +
 .../test/vnd,enum-required-false-holder.yaml  |   17 +
 .../test/vnd,gpio-expander-common.yaml        |   20 +
 dts/bindings/test/vnd,gpio-expander-i2c.yaml  |    8 +
 dts/bindings/test/vnd,gpio-expander-spi.yaml  |    8 +
 dts/bindings/test/vnd,gpio-one-cell.yaml      |   21 +
 dts/bindings/test/vnd,gpio.yaml               |   28 +
 .../test/vnd,great-grandchild-bindings.yaml   |   27 +
 dts/bindings/test/vnd,i2c-device.yaml         |    8 +
 dts/bindings/test/vnd,i2c-mux.yaml            |   18 +
 dts/bindings/test/vnd,i2c.yaml                |    8 +
 dts/bindings/test/vnd,intc.yaml               |   19 +
 dts/bindings/test/vnd,interrupt-holder.yaml   |   15 +
 dts/bindings/test/vnd,mbox-zero-cell.yaml     |   11 +
 dts/bindings/test/vnd,mbox.yaml               |   16 +
 dts/bindings/test/vnd,pcie.yaml               |   10 +
 dts/bindings/test/vnd,phandle-holder.yaml     |   23 +
 dts/bindings/test/vnd,pinctrl-device.yaml     |    8 +
 dts/bindings/test/vnd,pinctrl-test.yaml       |   59 +
 dts/bindings/test/vnd,pinctrl.yaml            |    8 +
 dts/bindings/test/vnd,pwm.yaml                |   20 +
 dts/bindings/test/vnd,reg-holder.yaml         |   18 +
 dts/bindings/test/vnd,serial.yaml             |   13 +
 dts/bindings/test/vnd,spi-device-2.yaml       |    8 +
 dts/bindings/test/vnd,spi-device.yaml         |    8 +
 dts/bindings/test/vnd,spi.yaml                |    8 +
 dts/bindings/timer/arm,armv8-timer.yaml       |   12 +
 dts/bindings/timer/arm,cmsdk-dtimer.yaml      |   15 +
 dts/bindings/timer/arm,cmsdk-timer.yaml       |   15 +
 dts/bindings/timer/atmel,sam-tc.yaml          |   68 +
 dts/bindings/timer/atmel,sam0-tc32.yaml       |   38 +
 .../timer/espressif,esp32-systimer.yaml       |   18 +
 dts/bindings/timer/gaisler,gptimer.yaml       |   12 +
 dts/bindings/timer/intel,hpet.yaml            |   15 +
 dts/bindings/timer/ite,it8xxx2-timer.yaml     |   18 +
 dts/bindings/timer/litex,timer0.yaml          |   15 +
 .../timer/microchip,xec-rtos-timer.yaml       |   31 +
 dts/bindings/timer/nordic,nrf-timer.yaml      |   28 +
 .../timer/nuvoton,npcx-itim-timer.yaml        |   18 +
 dts/bindings/timer/nxp,imx-gpt.yaml           |   23 +
 dts/bindings/timer/nxp,lpc-ctimer.yaml        |   38 +
 dts/bindings/timer/openisa,rv32m1-lptmr.yaml  |   15 +
 dts/bindings/timer/renesas,rcar-cmt.yaml      |   23 +
 dts/bindings/timer/riscv,machine-timer.yaml   |   39 +
 dts/bindings/timer/silabs,gecko-timer.yaml    |   15 +
 dts/bindings/timer/st,stm32-lptim.yaml        |   11 +
 dts/bindings/timer/st,stm32-timers.yaml       |   28 +
 dts/bindings/timer/xlnx,ttcps.yaml            |   17 +
 dts/bindings/usb/atmel,sam-usbc.yaml          |   34 +
 dts/bindings/usb/atmel,sam-usbhs.yaml         |   21 +
 dts/bindings/usb/atmel,sam0-usb.yaml          |   13 +
 dts/bindings/usb/nordic,nrf-usbd.yaml         |   26 +
 dts/bindings/usb/nxp,kinetis-usbd.yaml        |   16 +
 dts/bindings/usb/nxp,mcux-usbd.yaml           |   16 +
 dts/bindings/usb/snps,designware-usb.yaml     |   15 +
 dts/bindings/usb/st,stm32-otgfs.yaml          |   30 +
 dts/bindings/usb/st,stm32-otghs.yaml          |   30 +
 dts/bindings/usb/st,stm32-usb.yaml            |   45 +
 dts/bindings/usb/usb-audio-hp.yaml            |  121 +
 dts/bindings/usb/usb-audio-hs.yaml            |  243 ++
 dts/bindings/usb/usb-audio-mic.yaml           |  134 +
 dts/bindings/usb/usb-audio.yaml               |   13 +
 dts/bindings/usb/usb-controller.yaml          |   31 +
 dts/bindings/usb/usb-ep.yaml                  |   28 +
 dts/bindings/usb/zephyr,native-posix-udc.yaml |    8 +
 dts/bindings/vendor-prefixes.txt              |  691 ++++
 dts/bindings/video/aptina,mt9m114.yaml        |    8 +
 dts/bindings/video/nxp,imx-csi.yaml           |   23 +
 dts/bindings/video/ovti,ov2640.yaml           |   16 +
 dts/bindings/video/ovti,ov7725.yaml           |   16 +
 dts/bindings/virtualization/qemu,ivshmem.yaml |    8 +
 dts/bindings/watchdog/arm,cmsdk-watchdog.yaml |   12 +
 dts/bindings/watchdog/atmel,sam-watchdog.yaml |   23 +
 .../watchdog/atmel,sam0-watchdog.yaml         |   15 +
 .../watchdog/espressif,esp32-watchdog.yaml    |   20 +
 .../watchdog/ite,it8xxx2-watchdog.yaml        |   18 +
 .../watchdog/microchip,xec-watchdog.yaml      |   18 +
 .../watchdog/nordic,nrf-watchdog.yaml         |   18 +
 .../watchdog/nuvoton,npcx-watchdog.yaml       |   21 +
 dts/bindings/watchdog/nxp,imx-wdog.yaml       |   18 +
 dts/bindings/watchdog/nxp,kinetis-wdog.yaml   |   21 +
 dts/bindings/watchdog/nxp,kinetis-wdog32.yaml |   31 +
 dts/bindings/watchdog/nxp,lpc-wwdt.yaml       |   23 +
 dts/bindings/watchdog/sifive,wdt.yaml         |   18 +
 dts/bindings/watchdog/silabs,gecko-wdog.yaml  |   24 +
 dts/bindings/watchdog/st,stm32-watchdog.yaml  |   15 +
 .../watchdog/st,stm32-window-watchdog.yaml    |   18 +
 dts/bindings/watchdog/ti,cc32xx-watchdog.yaml |   15 +
 .../watchdog/zephyr,counter-watchdog.yaml     |   16 +
 dts/bindings/wifi/atmel,winc1500.yaml         |   21 +
 dts/bindings/wifi/espressif,esp-at.yaml       |   27 +
 dts/bindings/wifi/inventek,eswifi-uart.yaml   |   18 +
 dts/bindings/wifi/inventek,eswifi.yaml        |   25 +
 dts/common/freq.h                             |   13 +
 dts/common/mem.h                              |   18 +
 dts/common/skeleton.dtsi                      |   14 +
 platforms/nuttx/cmake/px4_impl_os.cmake       |    2 +
 platforms/nuttx/src/px4/stm/CMakeLists.txt    |    1 +
 platforms/nuttx/src/px4/stm/hal_stm32         |    1 +
 src/include/devicetree.h                      | 3059 +++++++++++++++++
 src/include/devicetree/clocks.h               |  359 ++
 src/include/devicetree/dma.h                  |  376 ++
 src/include/devicetree/fixed-partitions.h     |   90 +
 src/include/devicetree/gpio.h                 |  305 ++
 src/include/devicetree/io-channels.h          |  363 ++
 src/include/devicetree/ordinals.h             |  101 +
 src/include/devicetree/pinctrl.h              |  455 +++
 src/include/devicetree/pwms.h                 |  601 ++++
 src/include/devicetree/spi.h                  |  349 ++
 src/include/devicetree/zephyr.h               |   63 +
 src/include/dt-bindings/adc/adc.h             |   32 +
 src/include/dt-bindings/clock/imx_ccm.h       |   27 +
 src/include/dt-bindings/clock/imx_ccm_rev2.h  |   82 +
 src/include/dt-bindings/clock/kinetis_mcg.h   |   13 +
 src/include/dt-bindings/clock/kinetis_pcc.h   |   17 +
 src/include/dt-bindings/clock/kinetis_scg.h   |   33 +
 src/include/dt-bindings/clock/kinetis_sim.h   |   28 +
 src/include/dt-bindings/clock/stm32_clock.h   |   26 +
 src/include/dt-bindings/dt-util.h             |   21 +
 src/include/dt-bindings/gpio/gpio.h           |  109 +
 src/include/dt-bindings/i2c/i2c.h             |   15 +
 src/include/dt-bindings/led/led.h             |   20 +
 .../memory-controller/stm32-fmc-sdram.h       |   49 +
 .../pinctrl/stm32-pinctrl-common.h            |   39 +
 .../dt-bindings/pinctrl/stm32-pinctrl.h       |  110 +
 .../dt-bindings/pinctrl/stm32f1-afio.h        |  212 ++
 .../dt-bindings/pinctrl/stm32f1-pinctrl.h     |  111 +
 src/include/dt-bindings/pwm/pwm.h             |   27 +
 src/include/dt-bindings/spi/spi.h             |   47 +
 src/include/dt-bindings/usb/usb.h             |   22 +
 src/include/sys/util.h                        |  393 +++
 src/include/sys/util_internal.h               |  146 +
 src/include/sys/util_loops.h                  | 2108 ++++++++++++
 src/include/sys/util_macro.h                  |  601 ++++
 src/include/zephyr/types.h                    |   39 +
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 create mode 100644 dts/bindings/serial/silabs,gecko-usart.yaml
 create mode 100644 dts/bindings/serial/snps,nsim-uart.yaml
 create mode 100644 dts/bindings/serial/st,stm32-lpuart.yaml
 create mode 100644 dts/bindings/serial/st,stm32-uart.yaml
 create mode 100644 dts/bindings/serial/st,stm32-usart.yaml
 create mode 100644 dts/bindings/serial/telink,b91-uart.yaml
 create mode 100644 dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml
 create mode 100644 dts/bindings/serial/ti,cc32xx-uart.yaml
 create mode 100644 dts/bindings/serial/ti,msp432p4xx-uart.yaml
 create mode 100644 dts/bindings/serial/ti,stellaris-uart.yaml
 create mode 100644 dts/bindings/serial/uart-controller.yaml
 create mode 100644 dts/bindings/serial/uart-device.yaml
 create mode 100644 dts/bindings/serial/xlnx,xps-uartlite-1.00.a.yaml
 create mode 100644 dts/bindings/serial/xlnx,xuartps.yaml
 create mode 100644 dts/bindings/serial/zephyr,cdc-acm-uart.yaml
 create mode 100644 dts/bindings/serial/zephyr,native-posix-uart.yaml
 create mode 100644 dts/bindings/spi/atmel,sam-spi.yaml
 create mode 100644 dts/bindings/spi/atmel,sam0-spi.yaml
 create mode 100644 dts/bindings/spi/cypress,psoc6-spi.yaml
 create mode 100644 dts/bindings/spi/espressif,esp32-spi.yaml
 create mode 100644 dts/bindings/spi/ite,it8xxx2-sspi.yaml
 create mode 100644 dts/bindings/spi/litex,spi.yaml
 create mode 100644 dts/bindings/spi/microchip,xec-qmspi-ldma.yaml
 create mode 100644 dts/bindings/spi/microchip,xec-qmspi.yaml
 create mode 100644 dts/bindings/spi/nordic,nrf-spi-common.yaml
 create mode 100644 dts/bindings/spi/nordic,nrf-spi.yaml
 create mode 100644 dts/bindings/spi/nordic,nrf-spim.yaml
 create mode 100644 dts/bindings/spi/nordic,nrf-spis.yaml
 create mode 100644 dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml
 create mode 100644 dts/bindings/spi/nxp,imx-flexspi.yaml
 create mode 100644 dts/bindings/spi/nxp,imx-lpspi.yaml
 create mode 100644 dts/bindings/spi/nxp,kinetis-dspi.yaml
 create mode 100644 dts/bindings/spi/nxp,lpc-spi.yaml
 create mode 100644 dts/bindings/spi/opencores,spi-simple.yaml
 create mode 100644 dts/bindings/spi/openisa,rv32m1-lpspi.yaml
 create mode 100644 dts/bindings/spi/sifive,spi0.yaml
 create mode 100644 dts/bindings/spi/silabs,gecko-spi-usart.yaml
 create mode 100644 dts/bindings/spi/snps,designware-spi.yaml
 create mode 100644 dts/bindings/spi/spi-controller.yaml
 create mode 100644 dts/bindings/spi/spi-device.yaml
 create mode 100644 dts/bindings/spi/st,stm32-spi-common.yaml
 create mode 100644 dts/bindings/spi/st,stm32-spi-fifo.yaml
 create mode 100644 dts/bindings/spi/st,stm32-spi-subghz.yaml
 create mode 100644 dts/bindings/spi/st,stm32-spi.yaml
 create mode 100644 dts/bindings/spi/telink,b91-spi.yaml
 create mode 100644 dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml
 create mode 100644 dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml
 create mode 100644 dts/bindings/spi/zephyr,spi-bitbang.yaml
 create mode 100644 dts/bindings/spi/zephyr,spi-emul-controller.yaml
 create mode 100644 dts/bindings/sram/mmio-sram.yaml
 create mode 100644 dts/bindings/sram/sifive,dtim0.yaml
 create mode 100644 dts/bindings/syscon/syscon.yaml
 create mode 100644 dts/bindings/tach/ite,it8xxx2-tach.yaml
 create mode 100644 dts/bindings/tach/microchip,xec-tach.yaml
 create mode 100644 dts/bindings/tach/nuvoton,npcx-tach.yaml
 create mode 100644 dts/bindings/tach/tach.yaml
 create mode 100644 dts/bindings/tcpc/st,stm32-ucpd.yaml
 create mode 100644 dts/bindings/test/vnd,adc-temp-sensor.yaml
 create mode 100644 dts/bindings/test/vnd,adc.yaml
 create mode 100644 dts/bindings/test/vnd,array-holder.yaml
 create mode 100644 dts/bindings/test/vnd,busy-sim.yaml
 create mode 100644 dts/bindings/test/vnd,child-bindings.yaml
 create mode 100644 dts/bindings/test/vnd,clock.yaml
 create mode 100644 dts/bindings/test/vnd,disabled-compat.yaml
 create mode 100644 dts/bindings/test/vnd,dma.yaml
 create mode 100644 dts/bindings/test/vnd,enum-holder-inst.yaml
 create mode 100644 dts/bindings/test/vnd,enum-holder.yaml
 create mode 100644 dts/bindings/test/vnd,enum-int-required-false-holder.yaml
 create mode 100644 dts/bindings/test/vnd,enum-required-false-holder-inst.yaml
 create mode 100644 dts/bindings/test/vnd,enum-required-false-holder.yaml
 create mode 100644 dts/bindings/test/vnd,gpio-expander-common.yaml
 create mode 100644 dts/bindings/test/vnd,gpio-expander-i2c.yaml
 create mode 100644 dts/bindings/test/vnd,gpio-expander-spi.yaml
 create mode 100644 dts/bindings/test/vnd,gpio-one-cell.yaml
 create mode 100644 dts/bindings/test/vnd,gpio.yaml
 create mode 100644 dts/bindings/test/vnd,great-grandchild-bindings.yaml
 create mode 100644 dts/bindings/test/vnd,i2c-device.yaml
 create mode 100644 dts/bindings/test/vnd,i2c-mux.yaml
 create mode 100644 dts/bindings/test/vnd,i2c.yaml
 create mode 100644 dts/bindings/test/vnd,intc.yaml
 create mode 100644 dts/bindings/test/vnd,interrupt-holder.yaml
 create mode 100644 dts/bindings/test/vnd,mbox-zero-cell.yaml
 create mode 100644 dts/bindings/test/vnd,mbox.yaml
 create mode 100644 dts/bindings/test/vnd,pcie.yaml
 create mode 100644 dts/bindings/test/vnd,phandle-holder.yaml
 create mode 100644 dts/bindings/test/vnd,pinctrl-device.yaml
 create mode 100644 dts/bindings/test/vnd,pinctrl-test.yaml
 create mode 100644 dts/bindings/test/vnd,pinctrl.yaml
 create mode 100644 dts/bindings/test/vnd,pwm.yaml
 create mode 100644 dts/bindings/test/vnd,reg-holder.yaml
 create mode 100644 dts/bindings/test/vnd,serial.yaml
 create mode 100644 dts/bindings/test/vnd,spi-device-2.yaml
 create mode 100644 dts/bindings/test/vnd,spi-device.yaml
 create mode 100644 dts/bindings/test/vnd,spi.yaml
 create mode 100644 dts/bindings/timer/arm,armv8-timer.yaml
 create mode 100644 dts/bindings/timer/arm,cmsdk-dtimer.yaml
 create mode 100644 dts/bindings/timer/arm,cmsdk-timer.yaml
 create mode 100644 dts/bindings/timer/atmel,sam-tc.yaml
 create mode 100644 dts/bindings/timer/atmel,sam0-tc32.yaml
 create mode 100644 dts/bindings/timer/espressif,esp32-systimer.yaml
 create mode 100644 dts/bindings/timer/gaisler,gptimer.yaml
 create mode 100644 dts/bindings/timer/intel,hpet.yaml
 create mode 100644 dts/bindings/timer/ite,it8xxx2-timer.yaml
 create mode 100644 dts/bindings/timer/litex,timer0.yaml
 create mode 100644 dts/bindings/timer/microchip,xec-rtos-timer.yaml
 create mode 100644 dts/bindings/timer/nordic,nrf-timer.yaml
 create mode 100644 dts/bindings/timer/nuvoton,npcx-itim-timer.yaml
 create mode 100644 dts/bindings/timer/nxp,imx-gpt.yaml
 create mode 100644 dts/bindings/timer/nxp,lpc-ctimer.yaml
 create mode 100644 dts/bindings/timer/openisa,rv32m1-lptmr.yaml
 create mode 100644 dts/bindings/timer/renesas,rcar-cmt.yaml
 create mode 100644 dts/bindings/timer/riscv,machine-timer.yaml
 create mode 100644 dts/bindings/timer/silabs,gecko-timer.yaml
 create mode 100644 dts/bindings/timer/st,stm32-lptim.yaml
 create mode 100644 dts/bindings/timer/st,stm32-timers.yaml
 create mode 100644 dts/bindings/timer/xlnx,ttcps.yaml
 create mode 100644 dts/bindings/usb/atmel,sam-usbc.yaml
 create mode 100644 dts/bindings/usb/atmel,sam-usbhs.yaml
 create mode 100644 dts/bindings/usb/atmel,sam0-usb.yaml
 create mode 100644 dts/bindings/usb/nordic,nrf-usbd.yaml
 create mode 100644 dts/bindings/usb/nxp,kinetis-usbd.yaml
 create mode 100644 dts/bindings/usb/nxp,mcux-usbd.yaml
 create mode 100644 dts/bindings/usb/snps,designware-usb.yaml
 create mode 100644 dts/bindings/usb/st,stm32-otgfs.yaml
 create mode 100644 dts/bindings/usb/st,stm32-otghs.yaml
 create mode 100644 dts/bindings/usb/st,stm32-usb.yaml
 create mode 100644 dts/bindings/usb/usb-audio-hp.yaml
 create mode 100644 dts/bindings/usb/usb-audio-hs.yaml
 create mode 100644 dts/bindings/usb/usb-audio-mic.yaml
 create mode 100644 dts/bindings/usb/usb-audio.yaml
 create mode 100644 dts/bindings/usb/usb-controller.yaml
 create mode 100644 dts/bindings/usb/usb-ep.yaml
 create mode 100644 dts/bindings/usb/zephyr,native-posix-udc.yaml
 create mode 100644 dts/bindings/vendor-prefixes.txt
 create mode 100644 dts/bindings/video/aptina,mt9m114.yaml
 create mode 100644 dts/bindings/video/nxp,imx-csi.yaml
 create mode 100644 dts/bindings/video/ovti,ov2640.yaml
 create mode 100644 dts/bindings/video/ovti,ov7725.yaml
 create mode 100644 dts/bindings/virtualization/qemu,ivshmem.yaml
 create mode 100644 dts/bindings/watchdog/arm,cmsdk-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/atmel,sam-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/atmel,sam0-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/espressif,esp32-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/ite,it8xxx2-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/microchip,xec-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/nordic,nrf-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/nxp,imx-wdog.yaml
 create mode 100644 dts/bindings/watchdog/nxp,kinetis-wdog.yaml
 create mode 100644 dts/bindings/watchdog/nxp,kinetis-wdog32.yaml
 create mode 100644 dts/bindings/watchdog/nxp,lpc-wwdt.yaml
 create mode 100644 dts/bindings/watchdog/sifive,wdt.yaml
 create mode 100644 dts/bindings/watchdog/silabs,gecko-wdog.yaml
 create mode 100644 dts/bindings/watchdog/st,stm32-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/st,stm32-window-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/ti,cc32xx-watchdog.yaml
 create mode 100644 dts/bindings/watchdog/zephyr,counter-watchdog.yaml
 create mode 100644 dts/bindings/wifi/atmel,winc1500.yaml
 create mode 100644 dts/bindings/wifi/espressif,esp-at.yaml
 create mode 100644 dts/bindings/wifi/inventek,eswifi-uart.yaml
 create mode 100644 dts/bindings/wifi/inventek,eswifi.yaml
 create mode 100644 dts/common/freq.h
 create mode 100644 dts/common/mem.h
 create mode 100644 dts/common/skeleton.dtsi
 create mode 160000 platforms/nuttx/src/px4/stm/hal_stm32
 create mode 100644 src/include/devicetree.h
 create mode 100644 src/include/devicetree/clocks.h
 create mode 100644 src/include/devicetree/dma.h
 create mode 100644 src/include/devicetree/fixed-partitions.h
 create mode 100644 src/include/devicetree/gpio.h
 create mode 100644 src/include/devicetree/io-channels.h
 create mode 100644 src/include/devicetree/ordinals.h
 create mode 100644 src/include/devicetree/pinctrl.h
 create mode 100644 src/include/devicetree/pwms.h
 create mode 100644 src/include/devicetree/spi.h
 create mode 100644 src/include/devicetree/zephyr.h
 create mode 100644 src/include/dt-bindings/adc/adc.h
 create mode 100644 src/include/dt-bindings/clock/imx_ccm.h
 create mode 100644 src/include/dt-bindings/clock/imx_ccm_rev2.h
 create mode 100644 src/include/dt-bindings/clock/kinetis_mcg.h
 create mode 100644 src/include/dt-bindings/clock/kinetis_pcc.h
 create mode 100644 src/include/dt-bindings/clock/kinetis_scg.h
 create mode 100644 src/include/dt-bindings/clock/kinetis_sim.h
 create mode 100644 src/include/dt-bindings/clock/stm32_clock.h
 create mode 100644 src/include/dt-bindings/dt-util.h
 create mode 100644 src/include/dt-bindings/gpio/gpio.h
 create mode 100644 src/include/dt-bindings/i2c/i2c.h
 create mode 100644 src/include/dt-bindings/led/led.h
 create mode 100644 src/include/dt-bindings/memory-controller/stm32-fmc-sdram.h
 create mode 100644 src/include/dt-bindings/pinctrl/stm32-pinctrl-common.h
 create mode 100644 src/include/dt-bindings/pinctrl/stm32-pinctrl.h
 create mode 100644 src/include/dt-bindings/pinctrl/stm32f1-afio.h
 create mode 100644 src/include/dt-bindings/pinctrl/stm32f1-pinctrl.h
 create mode 100644 src/include/dt-bindings/pwm/pwm.h
 create mode 100644 src/include/dt-bindings/spi/spi.h
 create mode 100644 src/include/dt-bindings/usb/usb.h
 create mode 100644 src/include/sys/util.h
 create mode 100644 src/include/sys/util_internal.h
 create mode 100644 src/include/sys/util_loops.h
 create mode 100644 src/include/sys/util_macro.h
 create mode 100644 src/include/zephyr/types.h

diff --git a/.gitmodules b/.gitmodules
index f23a7a3e78..f7387686e5 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -64,3 +64,6 @@
 	path = src/lib/crypto/libtommath
 	url = https://github.com/PX4/libtommath.git
 	branch = px4
+[submodule "platforms/nuttx/src/px4/stm/hal_stm32"]
+	path = platforms/nuttx/src/px4/stm/hal_stm32
+	url = git@github.com:zephyrproject-rtos/hal_stm32.git
diff --git a/CMakeLists.txt b/CMakeLists.txt
index bca9b38eaa..81c8610c31 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -413,6 +413,8 @@ add_subdirectory(src/lib EXCLUDE_FROM_ALL)
 add_subdirectory(platforms/${PX4_PLATFORM}/src/px4)
 add_subdirectory(platforms EXCLUDE_FROM_ALL)
 
+include(dts)
+
 if(EXISTS "${PX4_BOARD_DIR}/CMakeLists.txt")
 	add_subdirectory(${PX4_BOARD_DIR})
 endif()
diff --git a/Tools/astyle/files_to_check_code_style.sh b/Tools/astyle/files_to_check_code_style.sh
index 963c8a51cf..b71ff94869 100755
--- a/Tools/astyle/files_to_check_code_style.sh
+++ b/Tools/astyle/files_to_check_code_style.sh
@@ -10,6 +10,7 @@ fi
 exec find boards msg src platforms test \
     -path msg/templates/urtps -prune -o \
     -path platforms/nuttx/NuttX -prune -o \
+    -path platforms/nuttx/src/px4/stm/hal_stm32 -prune -o \
     -path platforms/qurt/dspal -prune -o \
     -path src/drivers/uavcan/libuavcan -prune -o \
     -path src/drivers/uavcan/uavcan_drivers/kinetis/driver/include/uavcan_kinetis -prune -o \
diff --git a/Tools/dts/README.txt b/Tools/dts/README.txt
new file mode 100644
index 0000000000..f6705bcf78
--- /dev/null
+++ b/Tools/dts/README.txt
@@ -0,0 +1,32 @@
+This directory used to contain the edtlib.py and dtlib.py libraries
+and tests, alongside the gen_defines.py script that uses them for
+converting DTS to the C macros used by Zephyr.
+
+The libraries and tests have now been moved to the 'python-devicetree'
+subdirectory.
+
+We are now in the process of extracting edtlib and dtlib into a
+standalone source code library that we intend to share with other
+projects.
+
+Links related to the work making this standalone:
+
+    https://pypi.org/project/devicetree/
+    https://python-devicetree.readthedocs.io/en/latest/
+    https://github.com/zephyrproject-rtos/python-devicetree
+
+The 'python-devicetree' subdirectory you find here next to this
+README.txt matches the standalone python-devicetree repository linked
+above.
+
+For now, the 'main' copy will continue to be hosted here in the zephyr
+repository. We will mirror changes into the standalone repository as
+needed; you can just ignore it for now.
+
+Code in the zephyr repository which needs these libraries will import
+devicetree.edtlib from now on, but the code will continue to be found
+by manipulating sys.path for now.
+
+Eventually, as APIs stabilize, the python-devicetree code in this
+repository will disappear, and a standalone repository will be the
+'main' one.
diff --git a/Tools/dts/gen_defines.py b/Tools/dts/gen_defines.py
new file mode 100755
index 0000000000..7cff885edf
--- /dev/null
+++ b/Tools/dts/gen_defines.py
@@ -0,0 +1,1032 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
+# Copyright (c) 2019 Linaro Limited
+# SPDX-License-Identifier: BSD-3-Clause
+
+# This script uses edtlib to generate a header file from a devicetree
+# (.dts) file. Information from binding files in YAML format is used
+# as well.
+#
+# Bindings are files that describe devicetree nodes. Devicetree nodes are
+# usually mapped to bindings via their 'compatible = "..."' property.
+#
+# See Zephyr's Devicetree user guide for details.
+#
+# Note: Do not access private (_-prefixed) identifiers from edtlib here (and
+# also note that edtlib is not meant to expose the dtlib API directly).
+# Instead, think of what API you need, and add it as a public documented API in
+# edtlib. This will keep this script simple.
+
+import argparse
+from collections import defaultdict
+import logging
+import os
+import pathlib
+import pickle
+import re
+import sys
+
+sys.path.append(os.path.join(os.path.dirname(__file__), 'python-devicetree',
+                             'src'))
+
+from devicetree import edtlib
+
+# The set of binding types whose values can be iterated over with
+# DT_FOREACH_PROP_ELEM(). If you change this, make sure to update the
+# doxygen string for that macro.
+FOREACH_PROP_ELEM_TYPES = set(['string', 'array', 'uint8-array', 'string-array',
+                               'phandles', 'phandle-array'])
+
+class LogFormatter(logging.Formatter):
+    '''A log formatter that prints the level name in lower case,
+    for compatibility with earlier versions of edtlib.'''
+
+    def __init__(self):
+        super().__init__(fmt='%(levelnamelower)s: %(message)s')
+
+    def format(self, record):
+        record.levelnamelower = record.levelname.lower()
+        return super().format(record)
+
+def main():
+    global header_file
+    global flash_area_num
+
+    args = parse_args()
+
+    setup_edtlib_logging()
+
+    vendor_prefixes = {}
+    for prefixes_file in args.vendor_prefixes:
+        vendor_prefixes.update(edtlib.load_vendor_prefixes_txt(prefixes_file))
+
+    try:
+        edt = edtlib.EDT(args.dts, args.bindings_dirs,
+                         # Suppress this warning if it's suppressed in dtc
+                         warn_reg_unit_address_mismatch=
+                             "-Wno-simple_bus_reg" not in args.dtc_flags,
+                         default_prop_types=True,
+                         infer_binding_for_paths=["/zephyr,user"],
+                         werror=args.edtlib_Werror,
+                         vendor_prefixes=vendor_prefixes)
+    except edtlib.EDTError as e:
+        sys.exit(f"devicetree error: {e}")
+
+    flash_area_num = 0
+
+    # Save merged DTS source, as a debugging aid
+    with open(args.dts_out, "w", encoding="utf-8") as f:
+        print(edt.dts_source, file=f)
+
+    # The raw index into edt.compat2nodes[compat] is used for node
+    # instance numbering within a compatible.
+    #
+    # As a way to satisfy people's intuitions about instance numbers,
+    # though, we sort this list so enabled instances come first.
+    #
+    # This might look like a hack, but it keeps drivers and
+    # applications which don't use instance numbers carefully working
+    # as expected, since e.g. instance number 0 is always the
+    # singleton instance if there's just one enabled node of a
+    # particular compatible.
+    #
+    # This doesn't violate any devicetree.h API guarantees about
+    # instance ordering, since we make no promises that instance
+    # numbers are stable across builds.
+    for compat, nodes in edt.compat2nodes.items():
+        edt.compat2nodes[compat] = sorted(
+            nodes, key=lambda node: 0 if node.status == "okay" else 1)
+
+    # Create the generated header.
+    with open(args.header_out, "w", encoding="utf-8") as header_file:
+        write_top_comment(edt)
+
+        # populate all z_path_id first so any children references will
+        # work correctly.
+        for node in sorted(edt.nodes, key=lambda node: node.dep_ordinal):
+            node.z_path_id = node_z_path_id(node)
+
+        # Check to see if we have duplicate "zephyr,memory-region" property values.
+        regions = dict()
+        for node in sorted(edt.nodes, key=lambda node: node.dep_ordinal):
+            if 'zephyr,memory-region' in node.props:
+                region = node.props['zephyr,memory-region'].val
+                if region in regions:
+                    sys.exit(f"ERROR: Duplicate 'zephyr,memory-region' ({region}) properties "
+                             f"between {regions[region].path} and {node.path}")
+                regions[region] = node
+
+        for node in sorted(edt.nodes, key=lambda node: node.dep_ordinal):
+            write_node_comment(node)
+
+            out_comment("Node's full path:")
+            out_dt_define(f"{node.z_path_id}_PATH", f'"{escape(node.path)}"')
+
+            out_comment("Node's name with unit-address:")
+            out_dt_define(f"{node.z_path_id}_FULL_NAME",
+                          f'"{escape(node.name)}"')
+
+            if node.parent is not None:
+                out_comment(f"Node parent ({node.parent.path}) identifier:")
+                out_dt_define(f"{node.z_path_id}_PARENT",
+                              f"DT_{node.parent.z_path_id}")
+
+            write_child_functions(node)
+            write_child_functions_status_okay(node)
+            write_dep_info(node)
+            write_idents_and_existence(node)
+            write_bus(node)
+            write_special_props(node)
+            write_vanilla_props(node)
+
+        write_chosen(edt)
+        write_global_compat_info(edt)
+
+        write_device_extern_header(args.device_header_out, edt)
+
+    if args.edt_pickle_out:
+        write_pickled_edt(edt, args.edt_pickle_out)
+
+
+def write_device_extern_header(device_header_out, edt):
+    # Generate header that will extern devicetree struct device's
+
+    with open(device_header_out, "w", encoding="utf-8") as dev_header_file:
+        print("#ifndef DEVICE_EXTERN_GEN_H", file=dev_header_file)
+        print("#define DEVICE_EXTERN_GEN_H", file=dev_header_file)
+        print("", file=dev_header_file)
+        print("#ifdef __cplusplus", file=dev_header_file)
+        print('extern "C" {', file=dev_header_file)
+        print("#endif", file=dev_header_file)
+        print("", file=dev_header_file)
+
+        for node in sorted(edt.nodes, key=lambda node: node.dep_ordinal):
+            print(f"extern const struct device DEVICE_DT_NAME_GET(DT_{node.z_path_id}); /* dts_ord_{node.dep_ordinal} */",
+                  file=dev_header_file)
+
+        print("", file=dev_header_file)
+        print("#ifdef __cplusplus", file=dev_header_file)
+        print("}", file=dev_header_file)
+        print("#endif", file=dev_header_file)
+        print("", file=dev_header_file)
+        print("#endif /* DEVICE_EXTERN_GEN_H */", file=dev_header_file)
+
+
+def setup_edtlib_logging():
+    # The edtlib module emits logs using the standard 'logging' module.
+    # Configure it so that warnings and above are printed to stderr,
+    # using the LogFormatter class defined above to format each message.
+
+    handler = logging.StreamHandler(sys.stderr)
+    handler.setFormatter(LogFormatter())
+
+    logger = logging.getLogger('edtlib')
+    logger.setLevel(logging.WARNING)
+    logger.addHandler(handler)
+
+def node_z_path_id(node):
+    # Return the node specific bit of the node's path identifier:
+    #
+    # - the root node's path "/" has path identifier "N"
+    # - "/foo" has "N_S_foo"
+    # - "/foo/bar" has "N_S_foo_S_bar"
+    # - "/foo/bar@123" has "N_S_foo_S_bar_123"
+    #
+    # This is used throughout this file to generate macros related to
+    # the node.
+
+    components = ["N"]
+    if node.parent is not None:
+        components.extend(f"S_{str2ident(component)}" for component in
+                          node.path.split("/")[1:])
+
+    return "_".join(components)
+
+def parse_args():
+    # Returns parsed command-line arguments
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--dts", required=True, help="DTS file")
+    parser.add_argument("--dtc-flags",
+                        help="'dtc' devicetree compiler flags, some of which "
+                             "might be respected here")
+    parser.add_argument("--bindings-dirs", nargs='+', required=True,
+                        help="directory with bindings in YAML format, "
+                        "we allow multiple")
+    parser.add_argument("--header-out", required=True,
+                        help="path to write header to")
+    parser.add_argument("--dts-out", required=True,
+                        help="path to write merged DTS source code to (e.g. "
+                             "as a debugging aid)")
+    parser.add_argument("--device-header-out", required=True,
+                        help="path to write device struct extern header to")
+    parser.add_argument("--edt-pickle-out",
+                        help="path to write pickled edtlib.EDT object to")
+    parser.add_argument("--vendor-prefixes", action='append', default=[],
+                        help="vendor-prefixes.txt path; used for validation; "
+                             "may be given multiple times")
+    parser.add_argument("--edtlib-Werror", action="store_true",
+                        help="if set, edtlib-specific warnings become errors. "
+                             "(this does not apply to warnings shared "
+                             "with dtc.)")
+
+    return parser.parse_args()
+
+
+def write_top_comment(edt):
+    # Writes an overview comment with misc. info at the top of the header and
+    # configuration file
+
+    s = f"""\
+Generated by gen_defines.py
+
+DTS input file:
+  {edt.dts_path}
+
+Directories with bindings:
+  {", ".join(map(relativize, edt.bindings_dirs))}
+
+Node dependency ordering (ordinal and path):
+"""
+
+    for scc in edt.scc_order:
+        if len(scc) > 1:
+            err("cycle in devicetree involving "
+                + ", ".join(node.path for node in scc))
+        s += f"  {scc[0].dep_ordinal:<3} {scc[0].path}\n"
+
+    s += """
+Definitions derived from these nodes in dependency order are next,
+followed by /chosen nodes.
+"""
+
+    out_comment(s, blank_before=False)
+
+
+def write_node_comment(node):
+    # Writes a comment describing 'node' to the header and configuration file
+
+    s = f"""\
+Devicetree node: {node.path}
+
+Node identifier: DT_{node.z_path_id}
+"""
+
+    if node.matching_compat:
+        if node.binding_path:
+            s += f"""
+Binding (compatible = {node.matching_compat}):
+  {relativize(node.binding_path)}
+"""
+        else:
+            s += f"""
+Binding (compatible = {node.matching_compat}):
+  No yaml (bindings inferred from properties)
+"""
+
+    if node.description:
+        # We used to put descriptions in the generated file, but
+        # devicetree bindings now have pages in the HTML
+        # documentation. Let users who are accustomed to digging
+        # around in the generated file where to find the descriptions
+        # now.
+        #
+        # Keeping them here would mean that the descriptions
+        # themselves couldn't contain C multi-line comments, which is
+        # inconvenient when we want to do things like quote snippets
+        # of .dtsi files within the descriptions, or otherwise
+        # include the string "*/".
+        s += ("\n(Descriptions have moved to the Devicetree Bindings Index\n"
+              "in the documentation.)\n")
+
+    out_comment(s)
+
+
+def relativize(path):
+    # If 'path' is within $ZEPHYR_BASE, returns it relative to $ZEPHYR_BASE,
+    # with a "$ZEPHYR_BASE/..." hint at the start of the string. Otherwise,
+    # returns 'path' unchanged.
+
+    zbase = os.getenv("ZEPHYR_BASE")
+    if zbase is None:
+        return path
+
+    try:
+        return str("$ZEPHYR_BASE" / pathlib.Path(path).relative_to(zbase))
+    except ValueError:
+        # Not within ZEPHYR_BASE
+        return path
+
+
+def write_idents_and_existence(node):
+    # Writes macros related to the node's aliases, labels, etc.,
+    # as well as existence flags.
+
+    # Aliases
+    idents = [f"N_ALIAS_{str2ident(alias)}" for alias in node.aliases]
+    # Instances
+    for compat in node.compats:
+        instance_no = node.edt.compat2nodes[compat].index(node)
+        idents.append(f"N_INST_{instance_no}_{str2ident(compat)}")
+    # Node labels
+    idents.extend(f"N_NODELABEL_{str2ident(label)}" for label in node.labels)
+
+    out_comment("Existence and alternate IDs:")
+    out_dt_define(node.z_path_id + "_EXISTS", 1)
+
+    # Only determine maxlen if we have any idents
+    if idents:
+        maxlen = max(len("DT_" + ident) for ident in idents)
+    for ident in idents:
+        out_dt_define(ident, "DT_" + node.z_path_id, width=maxlen)
+
+
+def write_bus(node):
+    # Macros about the node's bus controller, if there is one
+
+    bus = node.bus_node
+    if not bus:
+        return
+
+    if not bus.label:
+        err(f"missing 'label' property on bus node {bus!r}")
+
+    out_comment(f"Bus info (controller: '{bus.path}', type: '{node.on_bus}')")
+    out_dt_define(f"{node.z_path_id}_BUS_{str2ident(node.on_bus)}", 1)
+    out_dt_define(f"{node.z_path_id}_BUS", f"DT_{bus.z_path_id}")
+
+
+def write_special_props(node):
+    # Writes required macros for special case properties, when the
+    # data cannot otherwise be obtained from write_vanilla_props()
+    # results
+
+    # Macros that are special to the devicetree specification
+    out_comment("Macros for properties that are special in the specification:")
+    write_regs(node)
+    write_ranges(node)
+    write_interrupts(node)
+    write_compatibles(node)
+    write_status(node)
+
+    # Macros that are special to bindings inherited from Linux, which
+    # we can't capture with the current bindings language.
+    write_pinctrls(node)
+    write_fixed_partitions(node)
+
+def write_ranges(node):
+    # ranges property: edtlib knows the right #address-cells and
+    # #size-cells of parent and child, and can therefore pack the
+    # child & parent addresses and sizes correctly
+
+    idx_vals = []
+    path_id = node.z_path_id
+
+    if node.ranges is not None:
+        idx_vals.append((f"{path_id}_RANGES_NUM", len(node.ranges)))
+
+    for i,range in enumerate(node.ranges):
+        idx_vals.append((f"{path_id}_RANGES_IDX_{i}_EXISTS", 1))
+
+        if node.bus == "pcie":
+            idx_vals.append((f"{path_id}_RANGES_IDX_{i}_VAL_CHILD_BUS_FLAGS_EXISTS", 1))
+            idx_macro = f"{path_id}_RANGES_IDX_{i}_VAL_CHILD_BUS_FLAGS"
+            idx_value = range.child_bus_addr >> ((range.child_bus_cells - 1) * 32)
+            idx_vals.append((idx_macro,
+                             f"{idx_value} /* {hex(idx_value)} */"))
+        if range.child_bus_addr is not None:
+            idx_macro = f"{path_id}_RANGES_IDX_{i}_VAL_CHILD_BUS_ADDRESS"
+            if node.bus == "pcie":
+                idx_value = range.child_bus_addr & ((1 << (range.child_bus_cells - 1) * 32) - 1)
+            else:
+                idx_value = range.child_bus_addr
+            idx_vals.append((idx_macro,
+                             f"{idx_value} /* {hex(idx_value)} */"))
+        if range.parent_bus_addr is not None:
+            idx_macro = f"{path_id}_RANGES_IDX_{i}_VAL_PARENT_BUS_ADDRESS"
+            idx_vals.append((idx_macro,
+                             f"{range.parent_bus_addr} /* {hex(range.parent_bus_addr)} */"))
+        if range.length is not None:
+            idx_macro = f"{path_id}_RANGES_IDX_{i}_VAL_LENGTH"
+            idx_vals.append((idx_macro,
+                             f"{range.length} /* {hex(range.length)} */"))
+
+    for macro, val in idx_vals:
+        out_dt_define(macro, val)
+
+    out_dt_define(f"{path_id}_FOREACH_RANGE(fn)",
+            " ".join(f"fn(DT_{path_id}, {i})" for i,range in enumerate(node.ranges)))
+
+def write_regs(node):
+    # reg property: edtlib knows the right #address-cells and
+    # #size-cells, and can therefore pack the register base addresses
+    # and sizes correctly
+
+    idx_vals = []
+    name_vals = []
+    path_id = node.z_path_id
+
+    if node.regs is not None:
+        idx_vals.append((f"{path_id}_REG_NUM", len(node.regs)))
+
+    for i, reg in enumerate(node.regs):
+        idx_vals.append((f"{path_id}_REG_IDX_{i}_EXISTS", 1))
+        if reg.addr is not None:
+            idx_macro = f"{path_id}_REG_IDX_{i}_VAL_ADDRESS"
+            idx_vals.append((idx_macro,
+                             f"{reg.addr} /* {hex(reg.addr)} */"))
+            if reg.name:
+                name_macro = f"{path_id}_REG_NAME_{reg.name}_VAL_ADDRESS"
+                name_vals.append((name_macro, f"DT_{idx_macro}"))
+
+        if reg.size is not None:
+            idx_macro = f"{path_id}_REG_IDX_{i}_VAL_SIZE"
+            idx_vals.append((idx_macro,
+                             f"{reg.size} /* {hex(reg.size)} */"))
+            if reg.name:
+                name_macro = f"{path_id}_REG_NAME_{reg.name}_VAL_SIZE"
+                name_vals.append((name_macro, f"DT_{idx_macro}"))
+
+    for macro, val in idx_vals:
+        out_dt_define(macro, val)
+    for macro, val in name_vals:
+        out_dt_define(macro, val)
+
+def write_interrupts(node):
+    # interrupts property: we have some hard-coded logic for interrupt
+    # mapping here.
+    #
+    # TODO: can we push map_arm_gic_irq_type() and
+    # encode_zephyr_multi_level_irq() out of Python and into C with
+    # macro magic in devicetree.h?
+
+    def map_arm_gic_irq_type(irq, irq_num):
+        # Maps ARM GIC IRQ (type)+(index) combo to linear IRQ number
+        if "type" not in irq.data:
+            err(f"Expected binding for {irq.controller!r} to have 'type' in "
+                "interrupt-cells")
+        irq_type = irq.data["type"]
+
+        if irq_type == 0:  # GIC_SPI
+            return irq_num + 32
+        if irq_type == 1:  # GIC_PPI
+            return irq_num + 16
+        err(f"Invalid interrupt type specified for {irq!r}")
+
+    def encode_zephyr_multi_level_irq(irq, irq_num):
+        # See doc/reference/kernel/other/interrupts.rst for details
+        # on how this encoding works
+
+        irq_ctrl = irq.controller
+        # Look for interrupt controller parent until we have none
+        while irq_ctrl.interrupts:
+            irq_num = (irq_num + 1) << 8
+            if "irq" not in irq_ctrl.interrupts[0].data:
+                err(f"Expected binding for {irq_ctrl!r} to have 'irq' in "
+                    "interrupt-cells")
+            irq_num |= irq_ctrl.interrupts[0].data["irq"]
+            irq_ctrl = irq_ctrl.interrupts[0].controller
+        return irq_num
+
+    idx_vals = []
+    name_vals = []
+    path_id = node.z_path_id
+
+    if node.interrupts is not None:
+        idx_vals.append((f"{path_id}_IRQ_NUM", len(node.interrupts)))
+
+    for i, irq in enumerate(node.interrupts):
+        for cell_name, cell_value in irq.data.items():
+            name = str2ident(cell_name)
+
+            if cell_name == "irq":
+                if "arm,gic" in irq.controller.compats:
+                    cell_value = map_arm_gic_irq_type(irq, cell_value)
+                cell_value = encode_zephyr_multi_level_irq(irq, cell_value)
+
+            idx_vals.append((f"{path_id}_IRQ_IDX_{i}_EXISTS", 1))
+            idx_macro = f"{path_id}_IRQ_IDX_{i}_VAL_{name}"
+            idx_vals.append((idx_macro, cell_value))
+            idx_vals.append((idx_macro + "_EXISTS", 1))
+            if irq.name:
+                name_macro = \
+                    f"{path_id}_IRQ_NAME_{str2ident(irq.name)}_VAL_{name}"
+                name_vals.append((name_macro, f"DT_{idx_macro}"))
+                name_vals.append((name_macro + "_EXISTS", 1))
+
+    for macro, val in idx_vals:
+        out_dt_define(macro, val)
+    for macro, val in name_vals:
+        out_dt_define(macro, val)
+
+
+def write_compatibles(node):
+    # Writes a macro for each of the node's compatibles. We don't care
+    # about whether edtlib / Zephyr's binding language recognizes
+    # them. The compatibles the node provides are what is important.
+
+    for compat in node.compats:
+        out_dt_define(
+            f"{node.z_path_id}_COMPAT_MATCHES_{str2ident(compat)}", 1)
+
+
+def write_child_functions(node):
+    # Writes macro that are helpers that will call a macro/function
+    # for each child node.
+
+    out_dt_define(f"{node.z_path_id}_FOREACH_CHILD(fn)",
+            " ".join(f"fn(DT_{child.z_path_id})" for child in
+                node.children.values()))
+
+    out_dt_define(f"{node.z_path_id}_FOREACH_CHILD_VARGS(fn, ...)",
+            " ".join(f"fn(DT_{child.z_path_id}, __VA_ARGS__)" for child in
+                node.children.values()))
+
+def write_child_functions_status_okay(node):
+    # Writes macros that are helpers that will call a macro/function
+    # for each child node with status "okay".
+
+    functions = ''
+    functions_args = ''
+    for child in node.children.values():
+        if child.status == "okay":
+            functions = functions + f"fn(DT_{child.z_path_id}) "
+            functions_args = functions_args + f"fn(DT_{child.z_path_id}, " \
+                                                            "__VA_ARGS__) "
+
+    out_dt_define(f"{node.z_path_id}_FOREACH_CHILD_STATUS_OKAY(fn)", functions)
+    out_dt_define(f"{node.z_path_id}_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)",
+                                                                functions_args)
+
+
+def write_status(node):
+    out_dt_define(f"{node.z_path_id}_STATUS_{str2ident(node.status)}", 1)
+
+
+def write_pinctrls(node):
+    # Write special macros for pinctrl-<index> and pinctrl-names properties.
+
+    out_comment("Pin control (pinctrl-<i>, pinctrl-names) properties:")
+
+    out_dt_define(f"{node.z_path_id}_PINCTRL_NUM", len(node.pinctrls))
+
+    if not node.pinctrls:
+        return
+
+    for pc_idx, pinctrl in enumerate(node.pinctrls):
+        out_dt_define(f"{node.z_path_id}_PINCTRL_IDX_{pc_idx}_EXISTS", 1)
+
+        if not pinctrl.name:
+            continue
+
+        name = pinctrl.name_as_token
+
+        # Below we rely on the fact that edtlib ensures the
+        # pinctrl-<pc_idx> properties are contiguous, start from 0,
+        # and contain only phandles.
+        out_dt_define(f"{node.z_path_id}_PINCTRL_IDX_{pc_idx}_TOKEN", name)
+        out_dt_define(f"{node.z_path_id}_PINCTRL_IDX_{pc_idx}_UPPER_TOKEN", name.upper())
+        out_dt_define(f"{node.z_path_id}_PINCTRL_NAME_{name}_EXISTS", 1)
+        out_dt_define(f"{node.z_path_id}_PINCTRL_NAME_{name}_IDX", pc_idx)
+        for idx, ph in enumerate(pinctrl.conf_nodes):
+            out_dt_define(f"{node.z_path_id}_PINCTRL_NAME_{name}_IDX_{idx}_PH",
+                          f"DT_{ph.z_path_id}")
+
+
+def write_fixed_partitions(node):
+    # Macros for child nodes of each fixed-partitions node.
+
+    if not (node.parent and "fixed-partitions" in node.parent.compats):
+        return
+
+    global flash_area_num
+    out_comment("fixed-partitions identifier:")
+    out_dt_define(f"{node.z_path_id}_PARTITION_ID", flash_area_num)
+    flash_area_num += 1
+
+
+def write_vanilla_props(node):
+    # Writes macros for any and all properties defined in the
+    # "properties" section of the binding for the node.
+    #
+    # This does generate macros for special properties as well, like
+    # regs, etc. Just let that be rather than bothering to add
+    # never-ending amounts of special case code here to skip special
+    # properties. This function's macros can't conflict with
+    # write_special_props() macros, because they're in different
+    # namespaces. Special cases aren't special enough to break the rules.
+
+    macro2val = {}
+    for prop_name, prop in node.props.items():
+        prop_id = str2ident(prop_name)
+        macro = f"{node.z_path_id}_P_{prop_id}"
+        val = prop2value(prop)
+        if val is not None:
+            # DT_N_<node-id>_P_<prop-id>
+            macro2val[macro] = val
+
+        if prop.spec.type == 'string':
+            macro2val[macro + "_STRING_TOKEN"] = prop.val_as_token
+            macro2val[macro + "_STRING_UPPER_TOKEN"] = prop.val_as_token.upper()
+
+        if prop.enum_index is not None:
+            # DT_N_<node-id>_P_<prop-id>_ENUM_IDX
+            macro2val[macro + "_ENUM_IDX"] = prop.enum_index
+            spec = prop.spec
+
+            if spec.enum_tokenizable:
+                as_token = prop.val_as_token
+
+                # DT_N_<node-id>_P_<prop-id>_ENUM_TOKEN
+                macro2val[macro + "_ENUM_TOKEN"] = as_token
+
+                if spec.enum_upper_tokenizable:
+                    # DT_N_<node-id>_P_<prop-id>_ENUM_UPPER_TOKEN
+                    macro2val[macro + "_ENUM_UPPER_TOKEN"] = as_token.upper()
+
+        if "phandle" in prop.type:
+            macro2val.update(phandle_macros(prop, macro))
+        elif "array" in prop.type:
+            # DT_N_<node-id>_P_<prop-id>_IDX_<i>
+            # DT_N_<node-id>_P_<prop-id>_IDX_<i>_EXISTS
+            for i, subval in enumerate(prop.val):
+                if isinstance(subval, str):
+                    macro2val[macro + f"_IDX_{i}"] = quote_str(subval)
+                else:
+                    macro2val[macro + f"_IDX_{i}"] = subval
+                macro2val[macro + f"_IDX_{i}_EXISTS"] = 1
+
+        if prop.type in FOREACH_PROP_ELEM_TYPES:
+            # DT_N_<node-id>_P_<prop-id>_FOREACH_PROP_ELEM
+            macro2val[f"{macro}_FOREACH_PROP_ELEM(fn)"] = \
+                ' \\\n\t'.join(f'fn(DT_{node.z_path_id}, {prop_id}, {i})'
+                              for i in range(len(prop.val)))
+
+            macro2val[f"{macro}_FOREACH_PROP_ELEM_VARGS(fn, ...)"] = \
+                ' \\\n\t'.join(f'fn(DT_{node.z_path_id}, {prop_id}, {i},'
+                                ' __VA_ARGS__)'
+                              for i in range(len(prop.val)))
+
+        plen = prop_len(prop)
+        if plen is not None:
+            # DT_N_<node-id>_P_<prop-id>_LEN
+            macro2val[macro + "_LEN"] = plen
+
+        macro2val[f"{macro}_EXISTS"] = 1
+
+    if macro2val:
+        out_comment("Generic property macros:")
+        for macro, val in macro2val.items():
+            out_dt_define(macro, val)
+    else:
+        out_comment("(No generic property macros)")
+
+
+def write_dep_info(node):
+    # Write dependency-related information about the node.
+
+    def fmt_dep_list(dep_list):
+        if dep_list:
+            # Sort the list by dependency ordinal for predictability.
+            sorted_list = sorted(dep_list, key=lambda node: node.dep_ordinal)
+            return "\\\n\t" + \
+                " \\\n\t".join(f"{n.dep_ordinal}, /* {n.path} */"
+                               for n in sorted_list)
+        else:
+            return "/* nothing */"
+
+    out_comment("Node's dependency ordinal:")
+    out_dt_define(f"{node.z_path_id}_ORD", node.dep_ordinal)
+
+    out_comment("Ordinals for what this node depends on directly:")
+    out_dt_define(f"{node.z_path_id}_REQUIRES_ORDS",
+                  fmt_dep_list(node.depends_on))
+
+    out_comment("Ordinals for what depends directly on this node:")
+    out_dt_define(f"{node.z_path_id}_SUPPORTS_ORDS",
+                  fmt_dep_list(node.required_by))
+
+
+def prop2value(prop):
+    # Gets the macro value for property 'prop', if there is
+    # a single well-defined C rvalue that it can be represented as.
+    # Returns None if there isn't one.
+
+    if prop.type == "string":
+        return quote_str(prop.val)
+
+    if prop.type == "int":
+        return prop.val
+
+    if prop.type == "boolean":
+        return 1 if prop.val else 0
+
+    if prop.type in ["array", "uint8-array"]:
+        return list2init(f"{val} /* {hex(val)} */" for val in prop.val)
+
+    if prop.type == "string-array":
+        return list2init(quote_str(val) for val in prop.val)
+
+    # phandle, phandles, phandle-array, path, compound: nothing
+    return None
+
+
+def prop_len(prop):
+    # Returns the property's length if and only if we should generate
+    # a _LEN macro for the property. Otherwise, returns None.
+    #
+    # This deliberately excludes ranges, dma-ranges, reg and interrupts.
+    # While they have array type, their lengths as arrays are
+    # basically nonsense semantically due to #address-cells and
+    # #size-cells for "reg", #interrupt-cells for "interrupts"
+    # and #address-cells, #size-cells and the #address-cells from the
+    # parent node for "ranges" and "dma-ranges".
+    #
+    # We have special purpose macros for the number of register blocks
+    # / interrupt specifiers. Excluding them from this list means
+    # DT_PROP_LEN(node_id, ...) fails fast at the devicetree.h layer
+    # with a build error. This forces users to switch to the right
+    # macros.
+
+    if prop.type == "phandle":
+        return 1
+
+    if (prop.type in ["array", "uint8-array", "string-array",
+                      "phandles", "phandle-array"] and
+                prop.name not in ["ranges", "dma-ranges", "reg", "interrupts"]):
+        return len(prop.val)
+
+    return None
+
+
+def phandle_macros(prop, macro):
+    # Returns a dict of macros for phandle or phandles property 'prop'.
+    #
+    # The 'macro' argument is the N_<node-id>_P_<prop-id> bit.
+    #
+    # These are currently special because we can't serialize their
+    # values without using label properties, which we're trying to get
+    # away from needing in Zephyr. (Label properties are great for
+    # humans, but have drawbacks for code size and boot time.)
+    #
+    # The names look a bit weird to make it easier for devicetree.h
+    # to use the same macros for phandle, phandles, and phandle-array.
+
+    ret = {}
+
+    if prop.type == "phandle":
+        # A phandle is treated as a phandles with fixed length 1.
+        ret[f"{macro}"] = f"DT_{prop.val.z_path_id}"
+        ret[f"{macro}_IDX_0"] = f"DT_{prop.val.z_path_id}"
+        ret[f"{macro}_IDX_0_PH"] = f"DT_{prop.val.z_path_id}"
+        ret[f"{macro}_IDX_0_EXISTS"] = 1
+    elif prop.type == "phandles":
+        for i, node in enumerate(prop.val):
+            ret[f"{macro}_IDX_{i}"] = f"DT_{node.z_path_id}"
+            ret[f"{macro}_IDX_{i}_PH"] = f"DT_{node.z_path_id}"
+            ret[f"{macro}_IDX_{i}_EXISTS"] = 1
+    elif prop.type == "phandle-array":
+        for i, entry in enumerate(prop.val):
+            if entry is None:
+                # Unspecified element. The phandle-array at this index
+                # does not point at a ControllerAndData value, but
+                # subsequent indices in the array may.
+                ret[f"{macro}_IDX_{i}_EXISTS"] = 0
+                continue
+
+            ret.update(controller_and_data_macros(entry, i, macro))
+
+    return ret
+
+
+def controller_and_data_macros(entry, i, macro):
+    # Helper procedure used by phandle_macros().
+    #
+    # Its purpose is to write the "controller" (i.e. label property of
+    # the phandle's node) and associated data macros for a
+    # ControllerAndData.
+
+    ret = {}
+    data = entry.data
+
+    # DT_N_<node-id>_P_<prop-id>_IDX_<i>_EXISTS
+    ret[f"{macro}_IDX_{i}_EXISTS"] = 1
+    # DT_N_<node-id>_P_<prop-id>_IDX_<i>_PH
+    ret[f"{macro}_IDX_{i}_PH"] = f"DT_{entry.controller.z_path_id}"
+    # DT_N_<node-id>_P_<prop-id>_IDX_<i>_VAL_<VAL>
+    for cell, val in data.items():
+        ret[f"{macro}_IDX_{i}_VAL_{str2ident(cell)}"] = val
+        ret[f"{macro}_IDX_{i}_VAL_{str2ident(cell)}_EXISTS"] = 1
+
+    if not entry.name:
+        return ret
+
+    name = str2ident(entry.name)
+    # DT_N_<node-id>_P_<prop-id>_IDX_<i>_EXISTS
+    ret[f"{macro}_IDX_{i}_EXISTS"] = 1
+    # DT_N_<node-id>_P_<prop-id>_IDX_<i>_NAME
+    ret[f"{macro}_IDX_{i}_NAME"] = quote_str(entry.name)
+    # DT_N_<node-id>_P_<prop-id>_NAME_<NAME>_PH
+    ret[f"{macro}_NAME_{name}_PH"] = f"DT_{entry.controller.z_path_id}"
+    # DT_N_<node-id>_P_<prop-id>_NAME_<NAME>_EXISTS
+    ret[f"{macro}_NAME_{name}_EXISTS"] = 1
+    # DT_N_<node-id>_P_<prop-id>_NAME_<NAME>_VAL_<VAL>
+    for cell, val in data.items():
+        cell_ident = str2ident(cell)
+        ret[f"{macro}_NAME_{name}_VAL_{cell_ident}"] = \
+            f"DT_{macro}_IDX_{i}_VAL_{cell_ident}"
+        ret[f"{macro}_NAME_{name}_VAL_{cell_ident}_EXISTS"] = 1
+
+    return ret
+
+
+def write_chosen(edt):
+    # Tree-wide information such as chosen nodes is printed here.
+
+    out_comment("Chosen nodes\n")
+    chosen = {}
+    for name, node in edt.chosen_nodes.items():
+        chosen[f"DT_CHOSEN_{str2ident(name)}"] = f"DT_{node.z_path_id}"
+        chosen[f"DT_CHOSEN_{str2ident(name)}_EXISTS"] = 1
+    max_len = max(map(len, chosen), default=0)
+    for macro, value in chosen.items():
+        out_define(macro, value, width=max_len)
+
+
+def write_global_compat_info(edt):
+    # Tree-wide information related to each compatible, such as number
+    # of instances with status "okay", is printed here.
+
+    n_okay_macros = {}
+    for_each_macros = {}
+    compat2buses = defaultdict(list)  # just for "okay" nodes
+    for compat, okay_nodes in edt.compat2okay.items():
+        for node in okay_nodes:
+            bus = node.on_bus
+            if bus is not None and bus not in compat2buses[compat]:
+                compat2buses[compat].append(bus)
+
+        ident = str2ident(compat)
+        n_okay_macros[f"DT_N_INST_{ident}_NUM_OKAY"] = len(okay_nodes)
+
+        # Helpers for non-INST for-each macros that take node
+        # identifiers as arguments.
+        for_each_macros[f"DT_FOREACH_OKAY_{ident}(fn)"] = \
+            " ".join(f"fn(DT_{node.z_path_id})"
+                     for node in okay_nodes)
+        for_each_macros[f"DT_FOREACH_OKAY_VARGS_{ident}(fn, ...)"] = \
+            " ".join(f"fn(DT_{node.z_path_id}, __VA_ARGS__)"
+                     for node in okay_nodes)
+
+        # Helpers for INST versions of for-each macros, which take
+        # instance numbers. We emit separate helpers for these because
+        # avoiding an intermediate node_id --> instance number
+        # conversion in the preprocessor helps to keep the macro
+        # expansions simpler. That hopefully eases debugging.
+        for_each_macros[f"DT_FOREACH_OKAY_INST_{ident}(fn)"] = \
+            " ".join(f"fn({edt.compat2nodes[compat].index(node)})"
+                     for node in okay_nodes)
+        for_each_macros[f"DT_FOREACH_OKAY_INST_VARGS_{ident}(fn, ...)"] = \
+            " ".join(f"fn({edt.compat2nodes[compat].index(node)}, __VA_ARGS__)"
+                     for node in okay_nodes)
+
+    for compat, nodes in edt.compat2nodes.items():
+        for node in nodes:
+            if compat == "fixed-partitions":
+                for child in node.children.values():
+                    if "label" in child.props:
+                        label = child.props["label"].val
+                        macro = f"COMPAT_{str2ident(compat)}_LABEL_{str2ident(label)}"
+                        val = f"DT_{child.z_path_id}"
+
+                        out_dt_define(macro, val)
+                        out_dt_define(macro + "_EXISTS", 1)
+
+    out_comment('Macros for compatibles with status "okay" nodes\n')
+    for compat, okay_nodes in edt.compat2okay.items():
+        if okay_nodes:
+            out_define(f"DT_COMPAT_HAS_OKAY_{str2ident(compat)}", 1)
+
+    out_comment('Macros for status "okay" instances of each compatible\n')
+    for macro, value in n_okay_macros.items():
+        out_define(macro, value)
+    for macro, value in for_each_macros.items():
+        out_define(macro, value)
+
+    out_comment('Bus information for status "okay" nodes of each compatible\n')
+    for compat, buses in compat2buses.items():
+        for bus in buses:
+            out_define(
+                f"DT_COMPAT_{str2ident(compat)}_BUS_{str2ident(bus)}", 1)
+
+def str2ident(s):
+    # Converts 's' to a form suitable for (part of) an identifier
+
+    return re.sub('[-,.@/+]', '_', s.lower())
+
+
+def list2init(l):
+    # Converts 'l', a Python list (or iterable), to a C array initializer
+
+    return "{" + ", ".join(l) + "}"
+
+
+def out_dt_define(macro, val, width=None, deprecation_msg=None):
+    # Writes "#define DT_<macro> <val>" to the header file
+    #
+    # The macro will be left-justified to 'width' characters if that
+    # is specified, and the value will follow immediately after in
+    # that case. Otherwise, this function decides how to add
+    # whitespace between 'macro' and 'val'.
+    #
+    # If a 'deprecation_msg' string is passed, the generated identifiers will
+    # generate a warning if used, via __WARN(<deprecation_msg>)).
+    #
+    # Returns the full generated macro for 'macro', with leading "DT_".
+    ret = "DT_" + macro
+    out_define(ret, val, width=width, deprecation_msg=deprecation_msg)
+    return ret
+
+
+def out_define(macro, val, width=None, deprecation_msg=None):
+    # Helper for out_dt_define(). Outputs "#define <macro> <val>",
+    # adds a deprecation message if given, and allocates whitespace
+    # unless told not to.
+
+    warn = fr' __WARN("{deprecation_msg}")' if deprecation_msg else ""
+
+    if width:
+        s = f"#define {macro.ljust(width)}{warn} {val}"
+    else:
+        s = f"#define {macro}{warn} {val}"
+
+    print(s, file=header_file)
+
+
+def out_comment(s, blank_before=True):
+    # Writes 's' as a comment to the header and configuration file. 's' is
+    # allowed to have multiple lines. blank_before=True adds a blank line
+    # before the comment.
+
+    if blank_before:
+        print(file=header_file)
+
+    if "\n" in s:
+        # Format multi-line comments like
+        #
+        #   /*
+        #    * first line
+        #    * second line
+        #    *
+        #    * empty line before this line
+        #    */
+        res = ["/*"]
+        for line in s.splitlines():
+            # Avoid an extra space after '*' for empty lines. They turn red in
+            # Vim if space error checking is on, which is annoying.
+            res.append(" *" if not line.strip() else " * " + line)
+        res.append(" */")
+        print("\n".join(res), file=header_file)
+    else:
+        # Format single-line comments like
+        #
+        #   /* foo bar */
+        print("/* " + s + " */", file=header_file)
+
+
+def escape(s):
+    # Backslash-escapes any double quotes and backslashes in 's'
+
+    # \ must be escaped before " to avoid double escaping
+    return s.replace("\\", "\\\\").replace('"', '\\"')
+
+
+def quote_str(s):
+    # Puts quotes around 's' and escapes any double quotes and
+    # backslashes within it
+
+    return f'"{escape(s)}"'
+
+
+def write_pickled_edt(edt, out_file):
+    # Writes the edt object in pickle format to out_file.
+
+    with open(out_file, 'wb') as f:
+        # Pickle protocol version 4 is the default as of Python 3.8
+        # and was introduced in 3.4, so it is both available and
+        # recommended on all versions of Python that Zephyr supports
+        # (at time of writing, Python 3.6 was Zephyr's minimum
+        # version, and 3.8 the most recent CPython release).
+        #
+        # Using a common protocol version here will hopefully avoid
+        # reproducibility issues in different Python installations.
+        pickle.dump(edt, f, protocol=4)
+
+
+def err(s):
+    raise Exception(s)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/Tools/dts/gen_dts_cmake.py b/Tools/dts/gen_dts_cmake.py
new file mode 100755
index 0000000000..f86d2a875e
--- /dev/null
+++ b/Tools/dts/gen_dts_cmake.py
@@ -0,0 +1,151 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+'''
+This script uses edtlib and the devicetree data in the build directory
+to generate a CMake file which contains devicetree data.
+
+That data can then be used in the rest of the build system.
+
+The generated CMake file looks like this:
+
+  add_custom_target(devicetree_target)
+  set_target_properties(devicetree_target PROPERTIES
+                        "DT_PROP|/soc|compatible" "vnd,soc;")
+  ...
+
+It defines a special CMake target, and saves various values in the
+devicetree as CMake target properties.
+
+Be careful:
+
+  "Property" here can refer to a CMake target property or a
+  DTS property. DTS property values are stored inside
+  CMake target properties, along with other devicetree data.
+
+The build system includes this generated file early on, so
+devicetree values can be used at CMake processing time.
+
+Accss is not done directly, but with Zephyr CMake extension APIs,
+like this:
+
+  # sets 'compat' to "vnd,soc" in CMake
+  dt_prop(compat PATH "/soc" PROPERTY compatible INDEX 0)
+
+This is analogous to how DTS values are encoded as C macros,
+which can be read in source code using C APIs like
+DT_PROP(node_id, foo) from devicetree.h.
+'''
+
+import argparse
+import os
+import pickle
+import sys
+
+sys.path.append(os.path.join(os.path.dirname(__file__), 'python-devicetree',
+                             'src'))
+
+
+def parse_args():
+    # Returns parsed command-line arguments
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--cmake-out", required=True,
+                        help="path to write the CMake property file")
+    parser.add_argument("--edt-pickle", required=True,
+                        help="path to read the pickled edtlib.EDT object from")
+
+    return parser.parse_args()
+
+
+def main():
+    args = parse_args()
+
+    with open(args.edt_pickle, 'rb') as f:
+        edt = pickle.load(f)
+
+    # In what looks like an undocumented implementation detail, CMake
+    # target properties are stored in a C++ standard library map whose
+    # keys and values are each arbitrary strings, so we can use
+    # whatever we want as target property names.
+    #
+    # We therefore use '|' as a field separator character below within
+    # because it's not a valid character in DTS node paths or property
+    # names. This lets us store the "real" paths and property names
+    # without conversion to lowercase-and-underscores like we have to
+    # do in C.
+    #
+    # If CMake adds restrictions on target property names later, we
+    # can just tweak the generated file to use a more restrictive
+    # property encoding, perhaps reusing the same style documented in
+    # macros.bnf for C macros.
+
+    cmake_props = []
+    chosen_nodes = edt.chosen_nodes
+    for node in chosen_nodes:
+        path = chosen_nodes[node].path
+        cmake_props.append(f'"DT_CHOSEN|{node}" "{path}"')
+
+    # The separate loop over edt.nodes here is meant to keep
+    # all of the alias-related properties in one place.
+    for node in edt.nodes:
+        path = node.path
+        for alias in node.aliases:
+            cmake_props.append(f'"DT_ALIAS|{alias}" "{path}"')
+
+    for node in edt.nodes:
+        cmake_props.append(f'"DT_NODE|{node.path}" TRUE')
+
+        for label in node.labels:
+            cmake_props.append(f'"DT_NODELABEL|{label}" "{node.path}"')
+
+        for item in node.props:
+            # We currently do not support phandles for edt -> cmake conversion.
+            if "phandle" not in node.props[item].type:
+                if "array" in node.props[item].type:
+                    # Convert array to CMake list
+                    cmake_value = ''
+                    for val in node.props[item].val:
+                        cmake_value = f'{cmake_value}{val};'
+                else:
+                    cmake_value = node.props[item].val
+
+                # Encode node's property 'item' as a CMake target property
+                # with a name like 'DT_PROP|<path>|<property>'.
+                cmake_prop = f'DT_PROP|{node.path}|{item}'
+                cmake_props.append(f'"{cmake_prop}" "{cmake_value}"')
+
+        if node.regs is not None:
+            cmake_props.append(f'"DT_REG|{node.path}|NUM" "{len(node.regs)}"')
+            cmake_addr = ''
+            cmake_size = ''
+
+            for reg in node.regs:
+                if reg.addr is None:
+                    cmake_addr = f'{cmake_addr}NONE;'
+                else:
+                    cmake_addr = f'{cmake_addr}{hex(reg.addr)};'
+
+                if reg.size is None:
+                    cmake_size = f'{cmake_size}NONE;'
+                else:
+                    cmake_size = f'{cmake_size}{hex(reg.size)};'
+
+            cmake_props.append(f'"DT_REG|{node.path}|ADDR" "{cmake_addr}"')
+            cmake_props.append(f'"DT_REG|{node.path}|SIZE" "{cmake_size}"')
+
+    with open(args.cmake_out, "w", encoding="utf-8") as cmake_file:
+        print('add_custom_target(devicetree_target)', file=cmake_file)
+        print(file=cmake_file)
+
+        for prop in cmake_props:
+            print(
+                f'set_target_properties(devicetree_target PROPERTIES {prop})',
+                file=cmake_file
+            )
+
+
+if __name__ == "__main__":
+    main()
diff --git a/Tools/dts/python-devicetree/.gitignore b/Tools/dts/python-devicetree/.gitignore
new file mode 100644
index 0000000000..20574a3456
--- /dev/null
+++ b/Tools/dts/python-devicetree/.gitignore
@@ -0,0 +1,7 @@
+dist/
+src/devicetree.egg-info/
+build/
+devicetree.egg-info/
+__pycache__/
+.tox/
+doc/build/
diff --git a/Tools/dts/python-devicetree/requirements.txt b/Tools/dts/python-devicetree/requirements.txt
new file mode 100644
index 0000000000..f827ad8d1d
--- /dev/null
+++ b/Tools/dts/python-devicetree/requirements.txt
@@ -0,0 +1 @@
+sphinx_rtd_theme                # docs
diff --git a/Tools/dts/python-devicetree/setup.py b/Tools/dts/python-devicetree/setup.py
new file mode 100644
index 0000000000..590ba31510
--- /dev/null
+++ b/Tools/dts/python-devicetree/setup.py
@@ -0,0 +1,42 @@
+# Copyright (c) 2021, Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import setuptools
+
+long_description = '''
+Placeholder
+===========
+
+This is just a placeholder for moving Zephyr's devicetree libraries
+to PyPI.
+'''
+
+version = '0.0.1'
+
+setuptools.setup(
+    # TBD, just use these for now.
+    author='Zephyr Project',
+    author_email='devel@lists.zephyrproject.org',
+
+    name='devicetree',
+    version=version,
+    description='Python libraries for devicetree',
+    long_description=long_description,
+    # http://docutils.sourceforge.net/FAQ.html#what-s-the-official-mime-type-for-restructuredtext-data
+    long_description_content_type="text/x-rst",
+    url='https://github.com/zephyrproject-rtos/python-devicetree',
+    packages=setuptools.find_packages(where='src'),
+    package_dir={'': 'src'},
+    classifiers=[
+        'Programming Language :: Python :: 3 :: Only',
+        'License :: OSI Approved :: Apache Software License',
+        'Operating System :: POSIX :: Linux',
+        'Operating System :: MacOS :: MacOS X',
+        'Operating System :: Microsoft :: Windows',
+    ],
+    install_requires=[
+        'PyYAML>=5.1',
+    ],
+    python_requires='>=3.6',
+)
diff --git a/Tools/dts/python-devicetree/src/devicetree/__init__.py b/Tools/dts/python-devicetree/src/devicetree/__init__.py
new file mode 100644
index 0000000000..e9a568330b
--- /dev/null
+++ b/Tools/dts/python-devicetree/src/devicetree/__init__.py
@@ -0,0 +1,4 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+__all__ = ['edtlib', 'dtlib']
diff --git a/Tools/dts/python-devicetree/src/devicetree/dtlib.py b/Tools/dts/python-devicetree/src/devicetree/dtlib.py
new file mode 100644
index 0000000000..dc337a671f
--- /dev/null
+++ b/Tools/dts/python-devicetree/src/devicetree/dtlib.py
@@ -0,0 +1,2022 @@
+# Copyright (c) 2019, Nordic Semiconductor
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Tip: You can view just the documentation with 'pydoc3 devicetree.dtlib'
+
+"""
+A library for extracting information from .dts (devicetree) files. See the
+documentation for the DT and Node classes for more information.
+
+The top-level entry point of the library is the DT class. DT.__init__() takes a
+.dts file to parse and a list of directories to search for any /include/d
+files.
+"""
+
+import collections
+import enum
+import errno
+import os
+import re
+import string
+import sys
+import textwrap
+from typing import Any, Dict, Iterable, List, \
+    NamedTuple, NoReturn, Optional, Tuple, Union
+
+# NOTE: tests/test_dtlib.py is the test suite for this library.
+
+class DTError(Exception):
+    "Exception raised for devicetree-related errors"
+
+class Node:
+    r"""
+    Represents a node in the devicetree ('node-name { ... };').
+
+    These attributes are available on Node instances:
+
+    name:
+      The name of the node (a string).
+
+    unit_addr:
+      The portion after the '@' in the node's name, or the empty string if the
+      name has no '@' in it.
+
+      Note that this is a string. Run int(node.unit_addr, 16) to get an
+      integer.
+
+    props:
+      A collections.OrderedDict that maps the properties defined on the node to
+      their values. 'props' is indexed by property name (a string), and values
+      are Property objects.
+
+      To convert property values to Python numbers or strings, use
+      dtlib.to_num(), dtlib.to_nums(), or dtlib.to_string().
+
+      Property values are represented as 'bytes' arrays to support the full
+      generality of DTS, which allows assignments like
+
+        x = "foo", < 0x12345678 >, [ 9A ];
+
+      This gives x the value b"foo\0\x12\x34\x56\x78\x9A". Numbers in DTS are
+      stored in big-endian format.
+
+    nodes:
+      A collections.OrderedDict containing the subnodes of the node, indexed by
+      name.
+
+    labels:
+      A list with all labels pointing to the node, in the same order as the
+      labels appear, but with duplicates removed.
+
+      'label_1: label_2: node { ... };' gives 'labels' the value
+      ["label_1", "label_2"].
+
+    parent:
+      The parent Node of the node. 'None' for the root node.
+
+    path:
+      The path to the node as a string, e.g. "/foo/bar".
+
+    dt:
+      The DT instance this node belongs to.
+    """
+
+    #
+    # Public interface
+    #
+
+    def __init__(self, name: str, parent: Optional['Node'], dt: 'DT'):
+        """
+        Node constructor. Not meant to be called directly by clients.
+        """
+        self.name = name
+        self.parent = parent
+        self.dt = dt
+
+        if name.count("@") > 1:
+            dt._parse_error("multiple '@' in node name")
+        if not name == "/":
+            for char in name:
+                if char not in _nodename_chars:
+                    dt._parse_error(f"{self.path}: bad character '{char}' "
+                                    "in node name")
+
+        self.props: Dict[str, 'Property'] = collections.OrderedDict()
+        self.nodes: Dict[str, 'Node'] = collections.OrderedDict()
+        self.labels: List[str] = []
+        self._omit_if_no_ref = False
+        self._is_referenced = False
+
+    @property
+    def unit_addr(self) -> str:
+        """
+        See the class documentation.
+        """
+        return self.name.partition("@")[2]
+
+    @property
+    def path(self) -> str:
+        """
+        See the class documentation.
+        """
+        node_names = []
+
+        cur = self
+        while cur.parent:
+            node_names.append(cur.name)
+            cur = cur.parent
+
+        return "/" + "/".join(reversed(node_names))
+
+    def node_iter(self) -> Iterable['Node']:
+        """
+        Returns a generator for iterating over the node and its children,
+        recursively.
+
+        For example, this will iterate over all nodes in the tree (like
+        dt.node_iter()).
+
+          for node in dt.root.node_iter():
+              ...
+        """
+        yield self
+        for node in self.nodes.values():
+            yield from node.node_iter()
+
+    def _get_prop(self, name: str) -> 'Property':
+        # Returns the property named 'name' on the node, creating it if it
+        # doesn't already exist
+
+        prop = self.props.get(name)
+        if not prop:
+            prop = Property(self, name)
+            self.props[name] = prop
+        return prop
+
+    def _del(self) -> None:
+        # Removes the node from the tree
+        self.parent.nodes.pop(self.name)  # type: ignore
+
+    def __str__(self):
+        """
+        Returns a DTS representation of the node. Called automatically if the
+        node is print()ed.
+        """
+        s = "".join(label + ": " for label in self.labels)
+
+        s += f"{self.name} {{\n"
+
+        for prop in self.props.values():
+            s += "\t" + str(prop) + "\n"
+
+        for child in self.nodes.values():
+            s += textwrap.indent(child.__str__(), "\t") + "\n"
+
+        s += "};"
+
+        return s
+
+    def __repr__(self):
+        """
+        Returns some information about the Node instance. Called automatically
+        if the Node instance is evaluated.
+        """
+        return f"<Node {self.path} in '{self.dt.filename}'>"
+
+# See Property.type
+class Type(enum.IntEnum):
+    EMPTY = 0
+    BYTES = 1
+    NUM = 2
+    NUMS = 3
+    STRING = 4
+    STRINGS = 5
+    PATH = 6
+    PHANDLE = 7
+    PHANDLES = 8
+    PHANDLES_AND_NUMS = 9
+    COMPOUND = 10
+
+class _MarkerType(enum.IntEnum):
+    # Types of markers in property values
+
+    # References
+    PATH = 0     # &foo
+    PHANDLE = 1  # <&foo>
+    LABEL = 2    # foo: <1 2 3>
+
+    # Start of data blocks of specific type
+    UINT8 = 3   # [00 01 02] (and also used for /incbin/)
+    UINT16 = 4  # /bits/ 16 <1 2 3>
+    UINT32 = 5  # <1 2 3>
+    UINT64 = 6  # /bits/ 64 <1 2 3>
+    STRING = 7  # "foo"
+
+class Property:
+    """
+    Represents a property ('x = ...').
+
+    These attributes are available on Property instances:
+
+    name:
+      The name of the property (a string).
+
+    value:
+      The value of the property, as a 'bytes' string. Numbers are stored in
+      big-endian format, and strings are null-terminated. Putting multiple
+      comma-separated values in an assignment (e.g., 'x = < 1 >, "foo"') will
+      concatenate the values.
+
+      See the to_*() methods for converting the value to other types.
+
+    type:
+      The type of the property, inferred from the syntax used in the
+      assignment. This is one of the following constants (with example
+      assignments):
+
+        Assignment                  | Property.type
+        ----------------------------+------------------------
+        foo;                        | dtlib.Type.EMPTY
+        foo = [];                   | dtlib.Type.BYTES
+        foo = [01 02];              | dtlib.Type.BYTES
+        foo = /bits/ 8 <1>;         | dtlib.Type.BYTES
+        foo = <1>;                  | dtlib.Type.NUM
+        foo = <>;                   | dtlib.Type.NUMS
+        foo = <1 2 3>;              | dtlib.Type.NUMS
+        foo = <1 2>, <3>;           | dtlib.Type.NUMS
+        foo = "foo";                | dtlib.Type.STRING
+        foo = "foo", "bar";         | dtlib.Type.STRINGS
+        foo = <&l>;                 | dtlib.Type.PHANDLE
+        foo = <&l1 &l2 &l3>;        | dtlib.Type.PHANDLES
+        foo = <&l1 &l2>, <&l3>;     | dtlib.Type.PHANDLES
+        foo = <&l1 1 2 &l2 3 4>;    | dtlib.Type.PHANDLES_AND_NUMS
+        foo = <&l1 1 2>, <&l2 3 4>; | dtlib.Type.PHANDLES_AND_NUMS
+        foo = &l;                   | dtlib.Type.PATH
+        *Anything else*             | dtlib.Type.COMPOUND
+
+      *Anything else* includes properties mixing phandle (<&label>) and node
+      path (&label) references with other data.
+
+      Data labels in the property value do not influence the type.
+
+    labels:
+      A list with all labels pointing to the property, in the same order as the
+      labels appear, but with duplicates removed.
+
+      'label_1: label2: x = ...' gives 'labels' the value
+      {"label_1", "label_2"}.
+
+    offset_labels:
+      A dictionary that maps any labels within the property's value to their
+      offset, in bytes. For example, 'x = < 0 label_1: 1 label_2: >' gives
+      'offset_labels' the value {"label_1": 4, "label_2": 8}.
+
+      Iteration order will match the order of the labels on Python versions
+      that preserve dict insertion order.
+
+    node:
+      The Node the property is on.
+    """
+
+    #
+    # Public interface
+    #
+
+    def __init__(self, node: Node, name: str):
+        if "@" in name:
+            node.dt._parse_error("'@' is only allowed in node names")
+
+        self.name = name
+        self.node = node
+        self.value = b""
+        self.labels: List[str] = []
+        self._label_offset_lst: List[Tuple[str, int]] = []
+        # We have to wait to set this until later, when we've got
+        # the entire tree.
+        self.offset_labels: Dict[str, int] = {}
+
+        # A list of [offset, label, type] lists (sorted by offset),
+        # giving the locations of references within the value. 'type'
+        # is either _MarkerType.PATH, for a node path reference,
+        # _MarkerType.PHANDLE, for a phandle reference, or
+        # _MarkerType.LABEL, for a label on/within data. Node paths
+        # and phandles need to be patched in after parsing.
+        self._markers: List[List] = []
+
+    def to_num(self, signed=False) -> int:
+        """
+        Returns the value of the property as a number.
+
+        Raises DTError if the property was not assigned with this syntax (has
+        Property.type Type.NUM):
+
+            foo = < 1 >;
+
+        signed (default: False):
+          If True, the value will be interpreted as signed rather than
+          unsigned.
+        """
+        if self.type is not Type.NUM:
+            _err("expected property '{0}' on {1} in {2} to be assigned with "
+                 "'{0} = < (number) >;', not '{3}'"
+                 .format(self.name, self.node.path, self.node.dt.filename,
+                         self))
+
+        return int.from_bytes(self.value, "big", signed=signed)
+
+    def to_nums(self, signed=False) -> List[int]:
+        """
+        Returns the value of the property as a list of numbers.
+
+        Raises DTError if the property was not assigned with this syntax (has
+        Property.type Type.NUM or Type.NUMS):
+
+            foo = < 1 2 ... >;
+
+        signed (default: False):
+          If True, the values will be interpreted as signed rather than
+          unsigned.
+        """
+        if self.type not in (Type.NUM, Type.NUMS):
+            _err("expected property '{0}' on {1} in {2} to be assigned with "
+                 "'{0} = < (number) (number) ... >;', not '{3}'"
+                 .format(self.name, self.node.path, self.node.dt.filename,
+                         self))
+
+        return [int.from_bytes(self.value[i:i + 4], "big", signed=signed)
+                for i in range(0, len(self.value), 4)]
+
+    def to_bytes(self) -> bytes:
+        """
+        Returns the value of the property as a raw 'bytes', like
+        Property.value, except with added type checking.
+
+        Raises DTError if the property was not assigned with this syntax (has
+        Property.type Type.BYTES):
+
+            foo = [ 01 ... ];
+        """
+        if self.type is not Type.BYTES:
+            _err("expected property '{0}' on {1} in {2} to be assigned with "
+                 "'{0} = [ (byte) (byte) ... ];', not '{3}'"
+                 .format(self.name, self.node.path, self.node.dt.filename,
+                         self))
+
+        return self.value
+
+    def to_string(self) -> str:
+        """
+        Returns the value of the property as a string.
+
+        Raises DTError if the property was not assigned with this syntax (has
+        Property.type Type.STRING):
+
+            foo = "string";
+
+        This function might also raise UnicodeDecodeError if the string is
+        not valid UTF-8.
+        """
+        if self.type is not Type.STRING:
+            _err("expected property '{0}' on {1} in {2} to be assigned with "
+                 "'{0} = \"string\";', not '{3}'"
+                 .format(self.name, self.node.path, self.node.dt.filename,
+                         self))
+
+        try:
+            ret = self.value.decode("utf-8")[:-1]  # Strip null
+        except UnicodeDecodeError:
+            _err(f"value of property '{self.name}' ({self.value!r}) "
+                 f"on {self.node.path} in {self.node.dt.filename} "
+                 "is not valid UTF-8")
+
+        return ret  # The separate 'return' appeases the type checker.
+
+    def to_strings(self) -> List[str]:
+        """
+        Returns the value of the property as a list of strings.
+
+        Raises DTError if the property was not assigned with this syntax (has
+        Property.type Type.STRING or Type.STRINGS):
+
+            foo = "string", "string", ... ;
+
+        Also raises DTError if any of the strings are not valid UTF-8.
+        """
+        if self.type not in (Type.STRING, Type.STRINGS):
+            _err("expected property '{0}' on {1} in {2} to be assigned with "
+                 "'{0} = \"string\", \"string\", ... ;', not '{3}'"
+                 .format(self.name, self.node.path, self.node.dt.filename,
+                         self))
+
+        try:
+            ret = self.value.decode("utf-8").split("\0")[:-1]
+        except UnicodeDecodeError:
+            _err(f"value of property '{self.name}' ({self.value!r}) "
+                 f"on {self.node.path} in {self.node.dt.filename} "
+                 "is not valid UTF-8")
+
+        return ret  # The separate 'return' appeases the type checker.
+
+    def to_node(self) -> Node:
+        """
+        Returns the Node the phandle in the property points to.
+
+        Raises DTError if the property was not assigned with this syntax (has
+        Property.type Type.PHANDLE).
+
+            foo = < &bar >;
+        """
+        if self.type is not Type.PHANDLE:
+            _err("expected property '{0}' on {1} in {2} to be assigned with "
+                 "'{0} = < &foo >;', not '{3}'"
+                 .format(self.name, self.node.path, self.node.dt.filename,
+                         self))
+
+        return self.node.dt.phandle2node[int.from_bytes(self.value, "big")]
+
+    def to_nodes(self) -> List[Node]:
+        """
+        Returns a list with the Nodes the phandles in the property point to.
+
+        Raises DTError if the property value contains anything other than
+        phandles. All of the following are accepted:
+
+            foo = < >
+            foo = < &bar >;
+            foo = < &bar &baz ... >;
+            foo = < &bar ... >, < &baz ... >;
+        """
+        def type_ok():
+            if self.type in (Type.PHANDLE, Type.PHANDLES):
+                return True
+            # Also accept 'foo = < >;'
+            return self.type is Type.NUMS and not self.value
+
+        if not type_ok():
+            _err("expected property '{0}' on {1} in {2} to be assigned with "
+                 "'{0} = < &foo &bar ... >;', not '{3}'"
+                 .format(self.name, self.node.path,
+                         self.node.dt.filename, self))
+
+        return [self.node.dt.phandle2node[int.from_bytes(self.value[i:i + 4],
+                                                         "big")]
+                for i in range(0, len(self.value), 4)]
+
+    def to_path(self) -> Node:
+        """
+        Returns the Node referenced by the path stored in the property.
+
+        Raises DTError if the property was not assigned with either of these
+        syntaxes (has Property.type Type.PATH or Type.STRING):
+
+            foo = &bar;
+            foo = "/bar";
+
+        For the second case, DTError is raised if the path does not exist.
+        """
+        if self.type not in (Type.PATH, Type.STRING):
+            _err("expected property '{0}' on {1} in {2} to be assigned with "
+                 "either '{0} = &foo' or '{0} = \"/path/to/node\"', not '{3}'"
+                 .format(self.name, self.node.path, self.node.dt.filename,
+                         self))
+
+        try:
+            path = self.value.decode("utf-8")[:-1]
+        except UnicodeDecodeError:
+            _err(f"value of property '{self.name}' ({self.value!r}) "
+                 f"on {self.node.path} in {self.node.dt.filename} "
+                 "is not valid UTF-8")
+
+        try:
+            ret = self.node.dt.get_node(path)
+        except DTError:
+            _err(f"property '{self.name}' on {self.node.path} in "
+                 f"{self.node.dt.filename} points to the non-existent node "
+                 f'"{path}"')
+
+        return ret  # The separate 'return' appeases the type checker.
+
+    @property
+    def type(self) -> int:
+        """
+        See the class docstring.
+        """
+        # Data labels (e.g. 'foo = label: <3>') are irrelevant, so filter them
+        # out
+        types = [marker[1] for marker in self._markers
+                 if marker[1] != _MarkerType.LABEL]
+
+        if not types:
+            return Type.EMPTY
+
+        if types == [_MarkerType.UINT8]:
+            return Type.BYTES
+
+        if types == [_MarkerType.UINT32]:
+            return Type.NUM if len(self.value) == 4 else Type.NUMS
+
+        # Treat 'foo = <1 2 3>, <4 5>, ...' as Type.NUMS too
+        if set(types) == {_MarkerType.UINT32}:
+            return Type.NUMS
+
+        if set(types) == {_MarkerType.STRING}:
+            return Type.STRING if len(types) == 1 else Type.STRINGS
+
+        if types == [_MarkerType.PATH]:
+            return Type.PATH
+
+        if types == [_MarkerType.UINT32, _MarkerType.PHANDLE] and \
+                len(self.value) == 4:
+            return Type.PHANDLE
+
+        if set(types) == {_MarkerType.UINT32, _MarkerType.PHANDLE}:
+            if len(self.value) == 4*types.count(_MarkerType.PHANDLE):
+                # Array with just phandles in it
+                return Type.PHANDLES
+            # Array with both phandles and numbers
+            return Type.PHANDLES_AND_NUMS
+
+        return Type.COMPOUND
+
+    def __str__(self):
+        s = "".join(label + ": " for label in self.labels) + self.name
+        if not self.value:
+            return s + ";"
+
+        s += " ="
+
+        for i, (pos, marker_type, ref) in enumerate(self._markers):
+            if i < len(self._markers) - 1:
+                next_marker = self._markers[i + 1]
+            else:
+                next_marker = None
+
+            # End of current marker
+            end = next_marker[0] if next_marker else len(self.value)
+
+            if marker_type is _MarkerType.STRING:
+                # end - 1 to strip off the null terminator
+                s += f' "{_decode_and_escape(self.value[pos:end - 1])}"'
+                if end != len(self.value):
+                    s += ","
+            elif marker_type is _MarkerType.PATH:
+                s += " &" + ref
+                if end != len(self.value):
+                    s += ","
+            else:
+                # <> or []
+
+                if marker_type is _MarkerType.LABEL:
+                    s += f" {ref}:"
+                elif marker_type is _MarkerType.PHANDLE:
+                    s += " &" + ref
+                    pos += 4
+                    # Subtle: There might be more data between the phandle and
+                    # the next marker, so we can't 'continue' here
+                else:  # marker_type is _MarkerType.UINT*
+                    elm_size = _TYPE_TO_N_BYTES[marker_type]
+                    s += _N_BYTES_TO_START_STR[elm_size]
+
+                while pos != end:
+                    num = int.from_bytes(self.value[pos:pos + elm_size],
+                                         "big")
+                    if elm_size == 1:
+                        s += f" {num:02X}"
+                    else:
+                        s += f" {hex(num)}"
+
+                    pos += elm_size
+
+                if pos != 0 and \
+                   (not next_marker or
+                    next_marker[1] not in (_MarkerType.PHANDLE, _MarkerType.LABEL)):
+
+                    s += _N_BYTES_TO_END_STR[elm_size]
+                    if pos != len(self.value):
+                        s += ","
+
+        return s + ";"
+
+
+    def __repr__(self):
+        return f"<Property '{self.name}' at '{self.node.path}' in " \
+            f"'{self.node.dt.filename}'>"
+
+    #
+    # Internal functions
+    #
+
+    def _add_marker(self, marker_type: _MarkerType, data: Any = None):
+        # Helper for registering markers in the value that are processed after
+        # parsing. See _fixup_props(). 'marker_type' identifies the type of
+        # marker, and 'data' has any optional data associated with the marker.
+
+        # len(self.value) gives the current offset. This function is called
+        # while the value is built. We use a list instead of a tuple to be able
+        # to fix up offsets later (they might increase if the value includes
+        # path references, e.g. 'foo = &bar, <3>;', which are expanded later).
+        self._markers.append([len(self.value), marker_type, data])
+
+        # For phandle references, add a dummy value with the same length as a
+        # phandle. This is handy for the length check in _register_phandles().
+        if marker_type is _MarkerType.PHANDLE:
+            self.value += b"\0\0\0\0"
+
+class _T(enum.IntEnum):
+    # Token IDs used by the DT lexer.
+
+    # These values must be contiguous and start from 1.
+    INCLUDE = 1
+    LINE = 2
+    STRING = 3
+    DTS_V1 = 4
+    PLUGIN = 5
+    MEMRESERVE = 6
+    BITS = 7
+    DEL_PROP = 8
+    DEL_NODE = 9
+    OMIT_IF_NO_REF = 10
+    LABEL = 11
+    CHAR_LITERAL = 12
+    REF = 13
+    INCBIN = 14
+    SKIP = 15
+    EOF = 16
+
+    # These values must be larger than the above contiguous range.
+    NUM = 17
+    PROPNODENAME = 18
+    MISC = 19
+    BYTE = 20
+    BAD = 21
+
+class _FileStackElt(NamedTuple):
+    # Used for maintaining the /include/ stack.
+
+    filename: str
+    lineno: int
+    contents: str
+    pos: int
+
+_TokVal = Union[int, str]
+
+class _Token(NamedTuple):
+    id: int
+    val: _TokVal
+
+    def __repr__(self):
+        id_repr = _T(self.id).name
+        return f'Token(id=_T.{id_repr}, val={repr(self.val)})'
+
+class DT:
+    """
+    Represents a devicetree parsed from a .dts file (or from many files, if the
+    .dts file /include/s other files). Creating many instances of this class is
+    fine. The library has no global state.
+
+    These attributes are available on DT instances:
+
+    root:
+      A Node instance representing the root (/) node.
+
+    alias2node:
+      A dictionary that maps maps alias strings (from /aliases) to Node
+      instances
+
+    label2node:
+      A dictionary that maps each node label (a string) to the Node instance
+      for the node.
+
+    label2prop:
+      A dictionary that maps each property label (a string) to a Property
+      instance.
+
+    label2prop_offset:
+      A dictionary that maps each label (a string) within a property value
+      (e.g., 'x = label_1: < 1 label2: 2 >;') to a (prop, offset) tuple, where
+      'prop' is a Property instance and 'offset' the byte offset (0 for label_1
+      and 4 for label_2 in the example).
+
+    phandle2node:
+      A dictionary that maps each phandle (a number) to a Node instance.
+
+    memreserves:
+      A list of (labels, address, length) tuples for the /memreserve/s in the
+      .dts file, in the same order as they appear in the file.
+
+      'labels' is a possibly empty set with all labels preceding the memreserve
+      (e.g., 'label1: label2: /memreserve/ ...'). 'address' and 'length' are
+      numbers.
+
+    filename:
+      The filename passed to the DT constructor.
+    """
+
+    #
+    # Public interface
+    #
+
+    def __init__(self, filename: str, include_path: Iterable[str] = (),
+                 force: bool = False):
+        """
+        Parses a DTS file to create a DT instance. Raises OSError if 'filename'
+        can't be opened, and DTError for any parse errors.
+
+        filename:
+          Path to the .dts file to parse.
+
+        include_path:
+          An iterable (e.g. list or tuple) containing paths to search for
+          /include/d and /incbin/'d files. By default, files are only looked up
+          relative to the .dts file that contains the /include/ or /incbin/.
+
+        force:
+          Try not to raise DTError even if the input tree has errors.
+          For experimental use; results not guaranteed.
+        """
+        self.filename = filename
+        self._include_path = list(include_path)
+        self._force = force
+
+        with open(filename, encoding="utf-8") as f:
+            self._file_contents = f.read()
+
+        self._tok_i = self._tok_end_i = 0
+        self._filestack: List[_FileStackElt] = []
+
+        self.alias2node: Dict[str, Node] = {}
+
+        self._lexer_state: int = _DEFAULT
+        self._saved_token: Optional[_Token] = None
+
+        self._lineno: int = 1
+
+        self._root: Optional[Node] = None
+
+        self._parse_dt()
+
+        self._register_phandles()
+        self._fixup_props()
+        self._register_aliases()
+        self._remove_unreferenced()
+        self._register_labels()
+
+    @property
+    def root(self) -> Node:
+        """
+        See the class documentation.
+        """
+        # This is necessary because mypy can't tell that we never
+        # treat self._root as a non-None value until it's initialized
+        # properly in _parse_dt().
+        return self._root       # type: ignore
+
+    def get_node(self, path: str) -> Node:
+        """
+        Returns the Node instance for the node with path or alias 'path' (a
+        string). Raises DTError if the path or alias doesn't exist.
+
+        For example, both dt.get_node("/foo/bar") and dt.get_node("bar-alias")
+        will return the 'bar' node below:
+
+          /dts-v1/;
+
+          / {
+                  foo {
+                          bar_label: bar {
+                                  baz {
+                                  };
+                          };
+                  };
+
+                  aliases {
+                          bar-alias = &bar-label;
+                  };
+          };
+
+        Fetching subnodes via aliases is supported:
+        dt.get_node("bar-alias/baz") returns the 'baz' node.
+        """
+        if path.startswith("/"):
+            return _root_and_path_to_node(self.root, path, path)
+
+        # Path does not start with '/'. First component must be an alias.
+        alias, _, rest = path.partition("/")
+        if alias not in self.alias2node:
+            _err(f"no alias '{alias}' found -- did you forget the leading "
+                 "'/' in the node path?")
+
+        return _root_and_path_to_node(self.alias2node[alias], rest, path)
+
+    def has_node(self, path: str) -> bool:
+        """
+        Returns True if the path or alias 'path' exists. See Node.get_node().
+        """
+        try:
+            self.get_node(path)
+            return True
+        except DTError:
+            return False
+
+    def node_iter(self) -> Iterable[Node]:
+        """
+        Returns a generator for iterating over all nodes in the devicetree.
+
+        For example, this will print the name of each node that has a property
+        called 'foo':
+
+          for node in dt.node_iter():
+              if "foo" in node.props:
+                  print(node.name)
+        """
+        yield from self.root.node_iter()
+
+    def __str__(self):
+        """
+        Returns a DTS representation of the devicetree. Called automatically if
+        the DT instance is print()ed.
+        """
+        s = "/dts-v1/;\n\n"
+
+        if self.memreserves:
+            for labels, address, offset in self.memreserves:
+                # List the labels in a consistent order to help with testing
+                for label in labels:
+                    s += f"{label}: "
+                s += f"/memreserve/ {address:#018x} {offset:#018x};\n"
+            s += "\n"
+
+        return s + str(self.root)
+
+    def __repr__(self):
+        """
+        Returns some information about the DT instance. Called automatically if
+        the DT instance is evaluated.
+        """
+        return f"DT(filename='{self.filename}', " \
+            f"include_path={self._include_path})"
+
+    #
+    # Parsing
+    #
+
+    def _parse_dt(self):
+        # Top-level parsing loop
+
+        self._parse_header()
+        self._parse_memreserves()
+
+        while True:
+            tok = self._next_token()
+
+            if tok.val == "/":
+                # '/ { ... };', the root node
+                if not self._root:
+                    self._root = Node(name="/", parent=None, dt=self)
+                self._parse_node(self.root)
+
+            elif tok.id in (_T.LABEL, _T.REF):
+                # '&foo { ... };' or 'label: &foo { ... };'. The C tools only
+                # support a single label here too.
+
+                if tok.id == _T.LABEL:
+                    label = tok.val
+                    tok = self._next_token()
+                    if tok.id != _T.REF:
+                        self._parse_error("expected label reference (&foo)")
+                else:
+                    label = None
+
+                try:
+                    node = self._ref2node(tok.val)
+                except DTError as e:
+                    self._parse_error(e)
+                node = self._parse_node(node)
+
+                if label:
+                    _append_no_dup(node.labels, label)
+
+            elif tok.id == _T.DEL_NODE:
+                self._next_ref2node()._del()
+                self._expect_token(";")
+
+            elif tok.id == _T.OMIT_IF_NO_REF:
+                self._next_ref2node()._omit_if_no_ref = True
+                self._expect_token(";")
+
+            elif tok.id == _T.EOF:
+                if not self._root:
+                    self._parse_error("no root node defined")
+                return
+
+            else:
+                self._parse_error("expected '/' or label reference (&foo)")
+
+    def _parse_header(self):
+        # Parses /dts-v1/ (expected) and /plugin/ (unsupported) at the start of
+        # files. There may be multiple /dts-v1/ at the start of a file.
+
+        has_dts_v1 = False
+
+        while self._peek_token().id == _T.DTS_V1:
+            has_dts_v1 = True
+            self._next_token()
+            self._expect_token(";")
+            # /plugin/ always comes after /dts-v1/
+            if self._peek_token().id == _T.PLUGIN:
+                self._parse_error("/plugin/ is not supported")
+
+        if not has_dts_v1:
+            self._parse_error("expected '/dts-v1/;' at start of file")
+
+    def _parse_memreserves(self):
+        # Parses /memreserve/, which appears after /dts-v1/
+
+        self.memreserves = []
+        while True:
+            # Labels before /memreserve/
+            labels = []
+            while self._peek_token().id == _T.LABEL:
+                _append_no_dup(labels, self._next_token().val)
+
+            if self._peek_token().id == _T.MEMRESERVE:
+                self._next_token()
+                self.memreserves.append(
+                    (labels, self._eval_prim(), self._eval_prim()))
+                self._expect_token(";")
+            elif labels:
+                self._parse_error("expected /memreserve/ after labels at "
+                                  "beginning of file")
+            else:
+                return
+
+    def _parse_node(self, node):
+        # Parses the '{ ... };' part of 'node-name { ... };'. Returns the new
+        # Node.
+
+        self._expect_token("{")
+        while True:
+            labels, omit_if_no_ref = self._parse_propnode_labels()
+            tok = self._next_token()
+
+            if tok.id == _T.PROPNODENAME:
+                if self._peek_token().val == "{":
+                    # '<tok> { ...', expect node
+
+                    # Fetch the existing node if it already exists. This
+                    # happens when overriding nodes.
+                    child = node.nodes.get(tok.val) or \
+                        Node(name=tok.val, parent=node, dt=self)
+
+                    for label in labels:
+                        _append_no_dup(child.labels, label)
+
+                    if omit_if_no_ref:
+                        child._omit_if_no_ref = True
+
+                    node.nodes[child.name] = child
+                    self._parse_node(child)
+
+                else:
+                    # Not '<tok> { ...', expect property assignment
+
+                    if omit_if_no_ref:
+                        self._parse_error(
+                            "/omit-if-no-ref/ can only be used on nodes")
+
+                    prop = node._get_prop(tok.val)
+
+                    if self._check_token("="):
+                        self._parse_assignment(prop)
+                    elif not self._check_token(";"):
+                        # ';' is for an empty property, like 'foo;'
+                        self._parse_error("expected '{', '=', or ';'")
+
+                    for label in labels:
+                        _append_no_dup(prop.labels, label)
+
+            elif tok.id == _T.DEL_NODE:
+                tok2 = self._next_token()
+                if tok2.id != _T.PROPNODENAME:
+                    self._parse_error("expected node name")
+                if tok2.val in node.nodes:
+                    node.nodes[tok2.val]._del()
+                self._expect_token(";")
+
+            elif tok.id == _T.DEL_PROP:
+                tok2 = self._next_token()
+                if tok2.id != _T.PROPNODENAME:
+                    self._parse_error("expected property name")
+                node.props.pop(tok2.val, None)
+                self._expect_token(";")
+
+            elif tok.val == "}":
+                self._expect_token(";")
+                return node
+
+            else:
+                self._parse_error("expected node name, property name, or '}'")
+
+    def _parse_propnode_labels(self):
+        # _parse_node() helpers for parsing labels and /omit-if-no-ref/s before
+        # nodes and properties. Returns a (<label list>, <omit-if-no-ref bool>)
+        # tuple.
+
+        labels = []
+        omit_if_no_ref = False
+        while True:
+            tok = self._peek_token()
+            if tok.id == _T.LABEL:
+                _append_no_dup(labels, tok.val)
+            elif tok.id == _T.OMIT_IF_NO_REF:
+                omit_if_no_ref = True
+            elif (labels or omit_if_no_ref) and tok.id != _T.PROPNODENAME:
+                # Got something like 'foo: bar: }'
+                self._parse_error("expected node or property name")
+            else:
+                return labels, omit_if_no_ref
+
+            self._next_token()
+
+    def _parse_assignment(self, prop):
+        # Parses the right-hand side of property assignment
+        #
+        # prop:
+        #   'Property' instance being assigned
+
+        # Remove any old value, path/phandle references, and in-value labels,
+        # in case the property value is being overridden
+        prop.value = b""
+        prop._markers = []
+
+        while True:
+            # Parse labels before the value (e.g., '..., label: < 0 >')
+            self._parse_value_labels(prop)
+
+            tok = self._next_token()
+
+            if tok.val == "<":
+                self._parse_cells(prop, 4)
+
+            elif tok.id == _T.BITS:
+                n_bits = self._expect_num()
+                if n_bits not in {8, 16, 32, 64}:
+                    self._parse_error("expected 8, 16, 32, or 64")
+                self._expect_token("<")
+                self._parse_cells(prop, n_bits//8)
+
+            elif tok.val == "[":
+                self._parse_bytes(prop)
+
+            elif tok.id == _T.STRING:
+                prop._add_marker(_MarkerType.STRING)
+                prop.value += self._unescape(tok.val.encode("utf-8")) + b"\0"
+
+            elif tok.id == _T.REF:
+                prop._add_marker(_MarkerType.PATH, tok.val)
+
+            elif tok.id == _T.INCBIN:
+                self._parse_incbin(prop)
+
+            else:
+                self._parse_error("malformed value")
+
+            # Parse labels after the value (e.g., '< 0 > label:, ...')
+            self._parse_value_labels(prop)
+
+            tok = self._next_token()
+            if tok.val == ";":
+                return
+            if tok.val == ",":
+                continue
+            self._parse_error("expected ';' or ','")
+
+    def _parse_cells(self, prop, n_bytes):
+        # Parses '<...>'
+
+        prop._add_marker(_N_BYTES_TO_TYPE[n_bytes])
+
+        while True:
+            tok = self._peek_token()
+            if tok.id == _T.REF:
+                self._next_token()
+                if n_bytes != 4:
+                    self._parse_error("phandle references are only allowed in "
+                                      "arrays with 32-bit elements")
+                prop._add_marker(_MarkerType.PHANDLE, tok.val)
+
+            elif tok.id == _T.LABEL:
+                prop._add_marker(_MarkerType.LABEL, tok.val)
+                self._next_token()
+
+            elif self._check_token(">"):
+                return
+
+            else:
+                # Literal value
+                num = self._eval_prim()
+                try:
+                    prop.value += num.to_bytes(n_bytes, "big")
+                except OverflowError:
+                    try:
+                        # Try again as a signed number, in case it's negative
+                        prop.value += num.to_bytes(n_bytes, "big", signed=True)
+                    except OverflowError:
+                        self._parse_error(
+                            f"{num} does not fit in {8*n_bytes} bits")
+
+    def _parse_bytes(self, prop):
+        # Parses '[ ... ]'
+
+        prop._add_marker(_MarkerType.UINT8)
+
+        while True:
+            tok = self._next_token()
+            if tok.id == _T.BYTE:
+                prop.value += tok.val.to_bytes(1, "big")
+
+            elif tok.id == _T.LABEL:
+                prop._add_marker(_MarkerType.LABEL, tok.val)
+
+            elif tok.val == "]":
+                return
+
+            else:
+                self._parse_error("expected two-digit byte or ']'")
+
+    def _parse_incbin(self, prop):
+        # Parses
+        #
+        #   /incbin/ ("filename")
+        #
+        # and
+        #
+        #   /incbin/ ("filename", <offset>, <size>)
+
+        prop._add_marker(_MarkerType.UINT8)
+
+        self._expect_token("(")
+
+        tok = self._next_token()
+        if tok.id != _T.STRING:
+            self._parse_error("expected quoted filename")
+        filename = tok.val
+
+        tok = self._next_token()
+        if tok.val == ",":
+            offset = self._eval_prim()
+            self._expect_token(",")
+            size = self._eval_prim()
+            self._expect_token(")")
+        else:
+            if tok.val != ")":
+                self._parse_error("expected ',' or ')'")
+            offset = None
+
+        try:
+            with self._open(filename, "rb") as f:
+                if offset is None:
+                    prop.value += f.read()
+                else:
+                    f.seek(offset)
+                    prop.value += f.read(size)
+        except OSError as e:
+            self._parse_error(f"could not read '{filename}': {e}")
+
+    def _parse_value_labels(self, prop):
+        # _parse_assignment() helper for parsing labels before/after each
+        # comma-separated value
+
+        while True:
+            tok = self._peek_token()
+            if tok.id != _T.LABEL:
+                return
+            prop._add_marker(_MarkerType.LABEL, tok.val)
+            self._next_token()
+
+    def _node_phandle(self, node):
+        # Returns the phandle for Node 'node', creating a new phandle if the
+        # node has no phandle, and fixing up the value for existing
+        # self-referential phandles (which get set to b'\0\0\0\0' initially).
+        # Self-referential phandles must be rewritten instead of recreated, so
+        # that labels are preserved.
+
+        if "phandle" in node.props:
+            phandle_prop = node.props["phandle"]
+        else:
+            phandle_prop = Property(node, "phandle")
+            phandle_prop._add_marker(_MarkerType.UINT32)  # For displaying
+            phandle_prop.value = b'\0\0\0\0'
+
+        if phandle_prop.value == b'\0\0\0\0':
+            phandle_i = 1
+            while phandle_i in self.phandle2node:
+                phandle_i += 1
+            self.phandle2node[phandle_i] = node
+
+            phandle_prop.value = phandle_i.to_bytes(4, "big")
+            node.props["phandle"] = phandle_prop
+
+        return phandle_prop.value
+
+    # Expression evaluation
+
+    def _eval_prim(self):
+        tok = self._peek_token()
+        if tok.id in (_T.NUM, _T.CHAR_LITERAL):
+            return self._next_token().val
+
+        tok = self._next_token()
+        if tok.val != "(":
+            self._parse_error("expected number or parenthesized expression")
+        val = self._eval_ternary()
+        self._expect_token(")")
+        return val
+
+    def _eval_ternary(self):
+        val = self._eval_or()
+        if self._check_token("?"):
+            if_val = self._eval_ternary()
+            self._expect_token(":")
+            else_val = self._eval_ternary()
+            return if_val if val else else_val
+        return val
+
+    def _eval_or(self):
+        val = self._eval_and()
+        while self._check_token("||"):
+            val = 1 if self._eval_and() or val else 0
+        return val
+
+    def _eval_and(self):
+        val = self._eval_bitor()
+        while self._check_token("&&"):
+            val = 1 if self._eval_bitor() and val else 0
+        return val
+
+    def _eval_bitor(self):
+        val = self._eval_bitxor()
+        while self._check_token("|"):
+            val |= self._eval_bitxor()
+        return val
+
+    def _eval_bitxor(self):
+        val = self._eval_bitand()
+        while self._check_token("^"):
+            val ^= self._eval_bitand()
+        return val
+
+    def _eval_bitand(self):
+        val = self._eval_eq()
+        while self._check_token("&"):
+            val &= self._eval_eq()
+        return val
+
+    def _eval_eq(self):
+        val = self._eval_rela()
+        while True:
+            if self._check_token("=="):
+                val = 1 if val == self._eval_rela() else 0
+            elif self._check_token("!="):
+                val = 1 if val != self._eval_rela() else 0
+            else:
+                return val
+
+    def _eval_rela(self):
+        val = self._eval_shift()
+        while True:
+            if self._check_token("<"):
+                val = 1 if val < self._eval_shift() else 0
+            elif self._check_token(">"):
+                val = 1 if val > self._eval_shift() else 0
+            elif self._check_token("<="):
+                val = 1 if val <= self._eval_shift() else 0
+            elif self._check_token(">="):
+                val = 1 if val >= self._eval_shift() else 0
+            else:
+                return val
+
+    def _eval_shift(self):
+        val = self._eval_add()
+        while True:
+            if self._check_token("<<"):
+                val <<= self._eval_add()
+            elif self._check_token(">>"):
+                val >>= self._eval_add()
+            else:
+                return val
+
+    def _eval_add(self):
+        val = self._eval_mul()
+        while True:
+            if self._check_token("+"):
+                val += self._eval_mul()
+            elif self._check_token("-"):
+                val -= self._eval_mul()
+            else:
+                return val
+
+    def _eval_mul(self):
+        val = self._eval_unary()
+        while True:
+            if self._check_token("*"):
+                val *= self._eval_unary()
+            elif self._check_token("/"):
+                denom = self._eval_unary()
+                if not denom:
+                    self._parse_error("division by zero")
+                val //= denom
+            elif self._check_token("%"):
+                denom = self._eval_unary()
+                if not denom:
+                    self._parse_error("division by zero")
+                val %= denom
+            else:
+                return val
+
+    def _eval_unary(self):
+        if self._check_token("-"):
+            return -self._eval_unary()
+        if self._check_token("~"):
+            return ~self._eval_unary()
+        if self._check_token("!"):
+            return 0 if self._eval_unary() else 1
+        return self._eval_prim()
+
+    #
+    # Lexing
+    #
+
+    def _check_token(self, val):
+        if self._peek_token().val == val:
+            self._next_token()
+            return True
+        return False
+
+    def _peek_token(self):
+        if not self._saved_token:
+            self._saved_token = self._next_token()
+        return self._saved_token
+
+    def _next_token(self):
+        if self._saved_token:
+            tmp = self._saved_token
+            self._saved_token = None
+            return tmp
+
+        while True:
+            tok_id = None
+
+            match = _token_re.match(self._file_contents, self._tok_end_i)
+            if match:
+                tok_id = match.lastindex
+                if tok_id == _T.CHAR_LITERAL:
+                    val = self._unescape(match.group(tok_id).encode("utf-8"))
+                    if len(val) != 1:
+                        self._parse_error("character literals must be length 1")
+                    tok_val = ord(val)
+                else:
+                    tok_val = match.group(tok_id)
+
+            elif self._lexer_state is _DEFAULT:
+                match = _num_re.match(self._file_contents, self._tok_end_i)
+                if match:
+                    tok_id = _T.NUM
+                    num_s = match.group(1)
+                    tok_val = int(num_s,
+                                  16 if num_s.startswith(("0x", "0X")) else
+                                  8 if num_s[0] == "0" else
+                                  10)
+
+            elif self._lexer_state is _EXPECT_PROPNODENAME:
+                match = _propnodename_re.match(self._file_contents,
+                                               self._tok_end_i)
+                if match:
+                    tok_id = _T.PROPNODENAME
+                    tok_val = match.group(1)
+                    self._lexer_state = _DEFAULT
+
+            else:  # self._lexer_state is _EXPECT_BYTE
+                match = _byte_re.match(self._file_contents, self._tok_end_i)
+                if match:
+                    tok_id = _T.BYTE
+                    tok_val = int(match.group(), 16)
+
+            if not tok_id:
+                match = _misc_re.match(self._file_contents, self._tok_end_i)
+                if match:
+                    tok_id = _T.MISC
+                    tok_val = match.group()
+                else:
+                    self._tok_i = self._tok_end_i
+                    # Could get here due to a node/property naming appearing in
+                    # an unexpected context as well as for bad characters in
+                    # files. Generate a token for it so that the error can
+                    # trickle up to some context where we can give a more
+                    # helpful error message.
+                    return _Token(_T.BAD, "<unknown token>")
+
+            self._tok_i = match.start()
+            self._tok_end_i = match.end()
+
+            if tok_id == _T.SKIP:
+                self._lineno += tok_val.count("\n")
+                continue
+
+            # /include/ is handled in the lexer in the C tools as well, and can
+            # appear anywhere
+            if tok_id == _T.INCLUDE:
+                # Can have newlines between /include/ and the filename
+                self._lineno += tok_val.count("\n")
+                # Do this manual extraction instead of doing it in the regex so
+                # that we can properly count newlines
+                filename = tok_val[tok_val.find('"') + 1:-1]
+                self._enter_file(filename)
+                continue
+
+            if tok_id == _T.LINE:
+                # #line directive
+                self._lineno = int(tok_val.split()[0]) - 1
+                self.filename = tok_val[tok_val.find('"') + 1:-1]
+                continue
+
+            if tok_id == _T.EOF:
+                if self._filestack:
+                    self._leave_file()
+                    continue
+                return _Token(_T.EOF, "<EOF>")
+
+            # State handling
+
+            if tok_id in (_T.DEL_PROP, _T.DEL_NODE, _T.OMIT_IF_NO_REF) or \
+               tok_val in ("{", ";"):
+
+                self._lexer_state = _EXPECT_PROPNODENAME
+
+            elif tok_val == "[":
+                self._lexer_state = _EXPECT_BYTE
+
+            elif tok_id in (_T.MEMRESERVE, _T.BITS) or tok_val == "]":
+                self._lexer_state = _DEFAULT
+
+            return _Token(tok_id, tok_val)
+
+    def _expect_token(self, tok_val):
+        # Raises an error if the next token does not have the string value
+        # 'tok_val'. Returns the token.
+
+        tok = self._next_token()
+        if tok.val != tok_val:
+            self._parse_error(f"expected '{tok_val}', not '{tok.val}'")
+
+        return tok
+
+    def _expect_num(self):
+        # Raises an error if the next token is not a number. Returns the token.
+
+        tok = self._next_token()
+        if tok.id != _T.NUM:
+            self._parse_error("expected number")
+        return tok.val
+
+    def _parse_error(self, s):
+        # This works out for the first line of the file too, where rfind()
+        # returns -1
+        column = self._tok_i - self._file_contents.rfind("\n", 0,
+                                                         self._tok_i + 1)
+        _err(f"{self.filename}:{self._lineno} (column {column}): "
+             f"parse error: {s}")
+
+    def _enter_file(self, filename):
+        # Enters the /include/d file 'filename', remembering the position in
+        # the /include/ing file for later
+
+        self._filestack.append(
+            _FileStackElt(self.filename, self._lineno,
+                          self._file_contents, self._tok_end_i))
+
+        # Handle escapes in filenames, just for completeness
+        filename = self._unescape(filename.encode("utf-8"))
+        try:
+            filename = filename.decode("utf-8")
+        except UnicodeDecodeError:
+            self._parse_error("filename is not valid UTF-8")
+
+        with self._open(filename, encoding="utf-8") as f:
+            try:
+                self._file_contents = f.read()
+            except OSError as e:
+                self._parse_error(e)
+
+        # Check for recursive /include/
+        for i, parent in enumerate(self._filestack):
+            if filename == parent[0]:
+                self._parse_error("recursive /include/:\n" + " ->\n".join(
+                    [f"{parent[0]}:{parent[1]}"
+                     for parent in self._filestack[i:]] +
+                    [filename]))
+
+        self.filename = f.name
+        self._lineno = 1
+        self._tok_end_i = 0
+
+    def _leave_file(self):
+        # Leaves an /include/d file, returning to the file that /include/d it
+
+        self.filename, self._lineno, self._file_contents, self._tok_end_i = \
+            self._filestack.pop()
+
+    def _next_ref2node(self):
+        # Checks that the next token is a label/path reference and returns the
+        # Node it points to. Only used during parsing, so uses _parse_error()
+        # on errors to save some code in callers.
+
+        label = self._next_token()
+        if label.id != _T.REF:
+            self._parse_error(
+                "expected label (&foo) or path (&{/foo/bar}) reference")
+        try:
+            return self._ref2node(label.val)
+        except DTError as e:
+            self._parse_error(e)
+
+    def _ref2node(self, s):
+        # Returns the Node the label/path reference 's' points to
+
+        if s[0] == "{":
+            # Path reference (&{/foo/bar})
+            path = s[1:-1]
+            if not path.startswith("/"):
+                _err(f"node path '{path}' does not start with '/'")
+            # Will raise DTError if the path doesn't exist
+            return _root_and_path_to_node(self.root, path, path)
+
+        # Label reference (&foo).
+
+        # label2node hasn't been filled in yet, and using it would get messy
+        # when nodes are deleted
+        for node in self.node_iter():
+            if s in node.labels:
+                return node
+
+        _err(f"undefined node label '{s}'")
+
+    #
+    # Post-processing
+    #
+
+    def _register_phandles(self):
+        # Registers any manually-inserted phandle properties in
+        # self.phandle2node, so that we can avoid allocating any phandles from
+        # that set. Also checks the format of the phandles and does misc.
+        # sanity checking.
+
+        self.phandle2node = {}
+        for node in self.node_iter():
+            phandle = node.props.get("phandle")
+            if phandle:
+                if len(phandle.value) != 4:
+                    _err(f"{node.path}: bad phandle length "
+                         f"({len(phandle.value)}), expected 4 bytes")
+
+                is_self_referential = False
+                for marker in phandle._markers:
+                    _, marker_type, ref = marker
+                    if marker_type is _MarkerType.PHANDLE:
+                        # The phandle's value is itself a phandle reference
+                        if self._ref2node(ref) is node:
+                            # Alright to set a node's phandle equal to its own
+                            # phandle. It'll force a new phandle to be
+                            # allocated even if the node is otherwise
+                            # unreferenced.
+                            is_self_referential = True
+                            break
+
+                        _err(f"{node.path}: {phandle.name} "
+                             "refers to another node")
+
+                # Could put on else on the 'for' above too, but keep it
+                # somewhat readable
+                if not is_self_referential:
+                    phandle_val = int.from_bytes(phandle.value, "big")
+
+                    if phandle_val in {0, 0xFFFFFFFF}:
+                        _err(f"{node.path}: bad value {phandle_val:#010x} "
+                             f"for {phandle.name}")
+
+                    if phandle_val in self.phandle2node:
+                        _err(f"{node.path}: duplicated phandle {phandle_val:#x} "
+                             "(seen before at "
+                             f"{self.phandle2node[phandle_val].path})")
+
+                    self.phandle2node[phandle_val] = node
+
+    def _fixup_props(self):
+        # Fills in node path and phandle references in property values, and
+        # registers labels within values. This must be done after parsing,
+        # since forwards references are allowed and nodes and properties might
+        # be deleted.
+
+        for node in self.node_iter():
+            # The tuple() avoids a 'dictionary changed size during iteration'
+            # error
+            for prop in tuple(node.props.values()):
+                # 'prev_pos' and 'pos' are indices in the unpatched
+                # property value. The result is built up in 'res'.
+                prev_pos = 0
+                res = b""
+
+                for marker in prop._markers:
+                    pos, marker_type, ref = marker
+
+                    # Add data before the marker, reading from the unpatched
+                    # property value
+                    res += prop.value[prev_pos:pos]
+
+                    # Fix the marker offset so that it's correct for the
+                    # patched property value, for later (not used in this
+                    # function). The offset might change due to path
+                    # references, which expand to something like "/foo/bar".
+                    marker[0] = len(res)
+
+                    if marker_type is _MarkerType.LABEL:
+                        # This is a temporary format so that we can catch
+                        # duplicate references. prop._label_offset_lst is changed
+                        # to a dictionary that maps labels to offsets in
+                        # _register_labels().
+                        _append_no_dup(prop._label_offset_lst, (ref, len(res)))
+                    elif marker_type in (_MarkerType.PATH, _MarkerType.PHANDLE):
+                        # Path or phandle reference
+                        try:
+                            ref_node = self._ref2node(ref)
+                        except DTError as e:
+                            _err(f"{prop.node.path}: {e}")
+
+                        # For /omit-if-no-ref/
+                        ref_node._is_referenced = True
+
+                        if marker_type is _MarkerType.PATH:
+                            res += ref_node.path.encode("utf-8") + b'\0'
+                        else:  # marker_type is PHANDLE
+                            res += self._node_phandle(ref_node)
+                            # Skip over the dummy phandle placeholder
+                            pos += 4
+
+                    prev_pos = pos
+
+                # Store the final fixed-up value. Add the data after the last
+                # marker.
+                prop.value = res + prop.value[prev_pos:]
+
+    def _register_aliases(self):
+        # Registers aliases from the /aliases node in self.alias2node. Also
+        # checks the format of the alias properties.
+
+        # We copy this to self.alias2node at the end to avoid get_node()
+        # looking up paths via other aliases while verifying aliases
+        alias2node = {}
+
+        alias_re = re.compile("[0-9a-z-]+$")
+
+        aliases = self.root.nodes.get("aliases")
+        if aliases:
+            for prop in aliases.props.values():
+                if not alias_re.match(prop.name):
+                    _err(f"/aliases: alias property name '{prop.name}' "
+                         "should include only characters from [0-9a-z-]")
+
+                # Property.to_path() checks that the node exists, has
+                # the right type, etc. Swallow errors for invalid
+                # aliases with self._force.
+                try:
+                    alias2node[prop.name] = prop.to_path()
+                except DTError:
+                    if self._force:
+                        continue
+                    raise
+
+        self.alias2node = alias2node
+
+    def _remove_unreferenced(self):
+        # Removes any unreferenced nodes marked with /omit-if-no-ref/ from the
+        # tree
+
+        # tuple() is to avoid 'RuntimeError: dictionary changed size during
+        # iteration' errors
+        for node in tuple(self.node_iter()):
+            if node._omit_if_no_ref and not node._is_referenced:
+                node._del()
+
+    def _register_labels(self):
+        # Checks for duplicate labels and registers labels in label2node,
+        # label2prop, and label2prop_offset
+
+        label2things = collections.defaultdict(set)
+
+        self.label2node = {}
+        self.label2prop = {}
+        self.label2prop_offset = {}
+
+        # Register all labels and the nodes/props they point to in label2things
+        for node in self.node_iter():
+            for label in node.labels:
+                label2things[label].add(node)
+                self.label2node[label] = node
+
+            for prop in node.props.values():
+                for label in prop.labels:
+                    label2things[label].add(prop)
+                    self.label2prop[label] = prop
+
+                for label, offset in prop._label_offset_lst:
+                    label2things[label].add((prop, offset))
+                    self.label2prop_offset[label] = (prop, offset)
+
+                # See _fixup_props()
+                prop.offset_labels = dict(prop._label_offset_lst)
+
+        for label, things in label2things.items():
+            if len(things) > 1:
+                strings = []
+                for thing in things:
+                    if isinstance(thing, Node):
+                        strings.append(f"on {thing.path}")
+                    elif isinstance(thing, Property):
+                        strings.append(f"on property '{thing.name}' "
+                                       f"of node {thing.node.path}")
+                    else:
+                        # Label within property value
+                        strings.append("in the value of property "
+                                       f"'{thing[0].name}' of node "
+                                       f"{thing[0].node.path}")
+
+                # Give consistent error messages to help with testing
+                strings.sort()
+
+                _err(f"Label '{label}' appears " + " and ".join(strings))
+
+
+    #
+    # Misc.
+    #
+
+    def _unescape(self, b):
+        # Replaces backslash escapes in the 'bytes' array 'b'. We can't do this at
+        # the string level, because the result might not be valid UTF-8 when
+        # octal/hex escapes are involved.
+
+        def sub(match):
+            esc = match.group(1)
+            if esc == b"a": return b"\a"
+            if esc == b"b": return b"\b"
+            if esc == b"t": return b"\t"
+            if esc == b"n": return b"\n"
+            if esc == b"v": return b"\v"
+            if esc == b"f": return b"\f"
+            if esc == b"r": return b"\r"
+
+            if esc[0] in b"01234567":
+                # Octal escape
+                try:
+                    return int(esc, 8).to_bytes(1, "big")
+                except OverflowError:
+                    self._parse_error("octal escape out of range (> 255)")
+
+            if esc[0] == ord("x") and len(esc) > 1:
+                # Hex escape
+                return int(esc[1:], 16).to_bytes(1, "big")
+
+            # Return <char> as-is for other \<char>
+            return esc[0].to_bytes(1, "big")
+
+        return _unescape_re.sub(sub, b)
+
+    def _open(self, filename, mode="r", **kwargs):
+        # Wrapper around standard Python open(), accepting the same params.
+        # But searches for a 'filename' file in the directory of the current
+        # file and the include path.
+
+        # The C tools support specifying stdin with '-' too
+        if filename == "-":
+            return sys.stdin.buffer if "b" in mode else sys.stdin
+
+        # Try the directory of the current file first
+        dirname = os.path.dirname(self.filename)
+        try:
+            return open(os.path.join(dirname, filename), mode, **kwargs)
+        except OSError as e:
+            if e.errno != errno.ENOENT:
+                self._parse_error(e)
+
+            # Try each directory from the include path
+            for path in self._include_path:
+                try:
+                    return open(os.path.join(path, filename), mode, **kwargs)
+                except OSError as e:
+                    if e.errno != errno.ENOENT:
+                        self._parse_error(e)
+                    continue
+
+            self._parse_error(f"'{filename}' could not be found")
+
+#
+# Public functions
+#
+
+def to_num(data: bytes, length: Optional[int] = None,
+           signed: bool = False) -> int:
+    """
+    Converts the 'bytes' array 'data' to a number. The value is expected to be
+    in big-endian format, which is standard in devicetree.
+
+    length (default: None):
+      The expected length of the value in bytes, as a simple type check. If
+      None, the length check is skipped.
+
+    signed (default: False):
+      If True, the value will be interpreted as signed rather than unsigned.
+    """
+    _check_is_bytes(data)
+    if length is not None:
+        _check_length_positive(length)
+        if len(data) != length:
+            _err(f"{data!r} is {len(data)} bytes long, expected {length}")
+
+    return int.from_bytes(data, "big", signed=signed)
+
+def to_nums(data: bytes, length: int = 4, signed: bool = False) -> List[int]:
+    """
+    Like Property.to_nums(), but takes an arbitrary 'bytes' array. The values
+    are assumed to be in big-endian format, which is standard in devicetree.
+    """
+    _check_is_bytes(data)
+    _check_length_positive(length)
+
+    if len(data) % length:
+        _err(f"{data!r} is {len(data)} bytes long, "
+             f"expected a length that's a a multiple of {length}")
+
+    return [int.from_bytes(data[i:i + length], "big", signed=signed)
+            for i in range(0, len(data), length)]
+
+#
+# Public constants
+#
+
+def _check_is_bytes(data):
+    if not isinstance(data, bytes):
+        _err(f"'{data}' has type '{type(data).__name__}', expected 'bytes'")
+
+def _check_length_positive(length):
+    if length < 1:
+        _err("'length' must be greater than zero, was " + str(length))
+
+def _append_no_dup(lst, elm):
+    # Appends 'elm' to 'lst', but only if it isn't already in 'lst'. Lets us
+    # preserve order, which a set() doesn't.
+
+    if elm not in lst:
+        lst.append(elm)
+
+def _decode_and_escape(b):
+    # Decodes the 'bytes' array 'b' as UTF-8 and backslash-escapes special
+    # characters
+
+    # Hacky but robust way to avoid double-escaping any '\' spit out by
+    # 'backslashreplace' bytes.translate() can't map to more than a single
+    # byte, but str.translate() can map to more than one character, so it's
+    # nice here. There's probably a nicer way to do this.
+    return b.decode("utf-8", "surrogateescape") \
+            .translate(_escape_table) \
+            .encode("utf-8", "surrogateescape") \
+            .decode("utf-8", "backslashreplace")
+
+def _root_and_path_to_node(cur, path, fullpath):
+    # Returns the node pointed at by 'path', relative to the Node 'cur'. For
+    # example, if 'cur' has path /foo/bar, and 'path' is "baz/qaz", then the
+    # node with path /foo/bar/baz/qaz is returned. 'fullpath' is the path as
+    # given in the .dts file, for error messages.
+
+    for component in path.split("/"):
+        # Collapse multiple / in a row, and allow a / at the end
+        if not component:
+            continue
+
+        if component not in cur.nodes:
+            _err(f"component '{component}' in path '{fullpath}' "
+                 "does not exist")
+
+        cur = cur.nodes[component]
+
+    return cur
+
+def _err(msg) -> NoReturn:
+    raise DTError(msg)
+
+_escape_table = str.maketrans({
+    "\\": "\\\\",
+    '"': '\\"',
+    "\a": "\\a",
+    "\b": "\\b",
+    "\t": "\\t",
+    "\n": "\\n",
+    "\v": "\\v",
+    "\f": "\\f",
+    "\r": "\\r"})
+
+# Lexer states
+_DEFAULT = 0
+_EXPECT_PROPNODENAME = 1
+_EXPECT_BYTE = 2
+
+_num_re = re.compile(r"(0[xX][0-9a-fA-F]+|[0-9]+)(?:ULL|UL|LL|U|L)?")
+
+# A leading \ is allowed property and node names, probably to allow weird node
+# names that would clash with other stuff
+_propnodename_re = re.compile(r"\\?([a-zA-Z0-9,._+*#?@-]+)")
+
+# Node names are more restrictive than property names.
+_nodename_chars = set(string.ascii_letters + string.digits + ',._+-@')
+
+# Misc. tokens that are tried after a property/node name. This is important, as
+# there's overlap with the allowed characters in names.
+_misc_re = re.compile(
+    "|".join(re.escape(pat) for pat in (
+        "==", "!=", "!", "=", ",", ";", "+", "-", "*", "/", "%", "~", "?", ":",
+        "^", "(", ")", "{", "}", "[", "]", "<<", "<=", "<", ">>", ">=", ">",
+        "||", "|", "&&", "&")))
+
+_byte_re = re.compile(r"[0-9a-fA-F]{2}")
+
+# Matches a backslash escape within a 'bytes' array. Captures the 'c' part of
+# '\c', where c might be a single character or an octal/hex escape.
+_unescape_re = re.compile(br'\\([0-7]{1,3}|x[0-9A-Fa-f]{1,2}|.)')
+
+def _init_tokens():
+    # Builds a (<token 1>)|(<token 2>)|... regex and returns it. The
+    # way this is constructed makes the token's value as an int appear
+    # in match.lastindex after a match.
+
+    # Each pattern must have exactly one capturing group, which can capture any
+    # part of the pattern. This makes match.lastindex match the token type.
+    # _Token.val is based on the captured string.
+    token_spec = {
+        _T.INCLUDE: r'(/include/\s*"(?:[^\\"]|\\.)*")',
+        # #line directive or GCC linemarker
+        _T.LINE:
+        r'^#(?:line)?[ \t]+([0-9]+[ \t]+"(?:[^\\"]|\\.)*")(?:[ \t]+[0-9]+){0,4}',
+
+        _T.STRING: r'"((?:[^\\"]|\\.)*)"',
+        _T.DTS_V1: r"(/dts-v1/)",
+        _T.PLUGIN: r"(/plugin/)",
+        _T.MEMRESERVE: r"(/memreserve/)",
+        _T.BITS: r"(/bits/)",
+        _T.DEL_PROP: r"(/delete-property/)",
+        _T.DEL_NODE: r"(/delete-node/)",
+        _T.OMIT_IF_NO_REF: r"(/omit-if-no-ref/)",
+        _T.LABEL: r"([a-zA-Z_][a-zA-Z0-9_]*):",
+        _T.CHAR_LITERAL: r"'((?:[^\\']|\\.)*)'",
+        _T.REF: r"&([a-zA-Z_][a-zA-Z0-9_]*|{[a-zA-Z0-9,._+*#?@/-]*})",
+        _T.INCBIN: r"(/incbin/)",
+        # Whitespace, C comments, and C++ comments
+        _T.SKIP: r"(\s+|(?:/\*(?:.|\n)*?\*/)|//.*$)",
+        # Return a token for end-of-file so that the parsing code can
+        # always assume that there are more tokens when looking
+        # ahead. This simplifies things.
+        _T.EOF: r"(\Z)",
+    }
+
+    # MULTILINE is needed for C++ comments and #line directives
+    return re.compile("|".join(token_spec[tok_id] for tok_id in
+                               range(1, _T.EOF + 1)),
+                      re.MULTILINE | re.ASCII)
+
+_token_re = _init_tokens()
+
+_TYPE_TO_N_BYTES = {
+    _MarkerType.UINT8: 1,
+    _MarkerType.UINT16: 2,
+    _MarkerType.UINT32: 4,
+    _MarkerType.UINT64: 8,
+}
+
+_N_BYTES_TO_TYPE = {
+    1: _MarkerType.UINT8,
+    2: _MarkerType.UINT16,
+    4: _MarkerType.UINT32,
+    8: _MarkerType.UINT64,
+}
+
+_N_BYTES_TO_START_STR = {
+    1: " [",
+    2: " /bits/ 16 <",
+    4: " <",
+    8: " /bits/ 64 <",
+}
+
+_N_BYTES_TO_END_STR = {
+    1: " ]",
+    2: " >",
+    4: " >",
+    8: " >",
+}
diff --git a/Tools/dts/python-devicetree/src/devicetree/edtlib.py b/Tools/dts/python-devicetree/src/devicetree/edtlib.py
new file mode 100644
index 0000000000..8fa3679278
--- /dev/null
+++ b/Tools/dts/python-devicetree/src/devicetree/edtlib.py
@@ -0,0 +1,2996 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# Copyright (c) 2019 Linaro Limited
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Tip: You can view just the documentation with 'pydoc3 devicetree.edtlib'
+
+"""
+Library for working with devicetrees at a higher level compared to dtlib. Like
+dtlib, this library presents a tree of devicetree nodes, but the nodes are
+augmented with information from bindings and include some interpretation of
+properties. Some of this interpretation is based on conventions established
+by the Linux kernel, so the Documentation/devicetree/bindings in the Linux
+source code is sometimes good reference material.
+
+Bindings are YAML files that describe devicetree nodes. Devicetree
+nodes are usually mapped to bindings via their 'compatible = "..."' property,
+but a binding can also come from a 'child-binding:' key in the binding for the
+parent devicetree node.
+
+Each devicetree node (dtlib.Node) gets a corresponding edtlib.Node instance,
+which has all the information related to the node.
+
+The top-level entry points for the library are the EDT and Binding classes.
+See their constructor docstrings for details. There is also a
+bindings_from_paths() helper function.
+"""
+
+# NOTE: tests/test_edtlib.py is the test suite for this library.
+
+# Implementation notes
+# --------------------
+#
+# A '_' prefix on an identifier in Python is a convention for marking it private.
+# Please do not access private things. Instead, think of what API you need, and
+# add it.
+#
+# This module is not meant to have any global state. It should be possible to
+# create several EDT objects with independent binding paths and flags. If you
+# need to add a configuration parameter or the like, store it in the EDT
+# instance, and initialize it e.g. with a constructor argument.
+#
+# This library is layered on top of dtlib, and is not meant to expose it to
+# clients. This keeps the header generation script simple.
+#
+# General biased advice:
+#
+# - Consider using @property for APIs that don't need parameters. It makes
+#   functions look like attributes, which is less awkward in clients, and makes
+#   it easy to switch back and forth between variables and functions.
+#
+# - Think about the data type of the thing you're exposing. Exposing something
+#   as e.g. a list or a dictionary is often nicer and more flexible than adding
+#   a function.
+#
+# - Avoid get_*() prefixes on functions. Name them after the thing they return
+#   instead. This often makes the code read more naturally in callers.
+#
+#   Also, consider using @property instead of get_*().
+#
+# - Don't expose dtlib stuff directly.
+#
+# - Add documentation for any new APIs you add.
+#
+#   The convention here is that docstrings (quoted strings) are used for public
+#   APIs, and "doc comments" for internal functions.
+#
+#   @properties are documented in the class docstring, as if they were
+#   variables. See the existing @properties for a template.
+
+from collections import OrderedDict, defaultdict
+from copy import deepcopy
+import logging
+import os
+import re
+from typing import Set
+
+import yaml
+try:
+    # Use the C LibYAML parser if available, rather than the Python parser.
+    # This makes e.g. gen_defines.py more than twice as fast.
+    from yaml import CLoader as Loader
+except ImportError:
+    from yaml import Loader     # type: ignore
+
+from devicetree.dtlib import DT, DTError, to_num, to_nums, Type
+from devicetree.grutils import Graph
+
+
+#
+# Public classes
+#
+
+
+class EDT:
+    """
+    Represents a devicetree augmented with information from bindings.
+
+    These attributes are available on EDT objects:
+
+    nodes:
+      A list of Node objects for the nodes that appear in the devicetree
+
+    compat2nodes:
+      A collections.defaultdict that maps each 'compatible' string that appears
+      on some Node to a list of Nodes with that compatible.
+
+    compat2okay:
+      Like compat2nodes, but just for nodes with status 'okay'.
+
+    label2node:
+      A collections.OrderedDict that maps a node label to the node with
+      that label.
+
+    dep_ord2node:
+      A collections.OrderedDict that maps an ordinal to the node with
+      that dependency ordinal.
+
+    chosen_nodes:
+      A collections.OrderedDict that maps the properties defined on the
+      devicetree's /chosen node to their values. 'chosen' is indexed by
+      property name (a string), and values are converted to Node objects.
+      Note that properties of the /chosen node which can't be converted
+      to a Node are not included in the value.
+
+    dts_path:
+      The .dts path passed to __init__()
+
+    dts_source:
+      The final DTS source code of the loaded devicetree after merging nodes
+      and processing /delete-node/ and /delete-property/, as a string
+
+    bindings_dirs:
+      The bindings directory paths passed to __init__()
+
+    scc_order:
+      A list of lists of Nodes. All elements of each list
+      depend on each other, and the Nodes in any list do not depend
+      on any Node in a subsequent list. Each list defines a Strongly
+      Connected Component (SCC) of the graph.
+
+      For an acyclic graph each list will be a singleton. Cycles
+      will be represented by lists with multiple nodes. Cycles are
+      not expected to be present in devicetree graphs.
+
+    The standard library's pickle module can be used to marshal and
+    unmarshal EDT objects.
+    """
+    def __init__(self, dts, bindings_dirs,
+                 warn_reg_unit_address_mismatch=True,
+                 default_prop_types=True,
+                 support_fixed_partitions_on_any_bus=True,
+                 infer_binding_for_paths=None,
+                 vendor_prefixes=None,
+                 werror=False):
+        """EDT constructor.
+
+        dts:
+          Path to devicetree .dts file
+
+        bindings_dirs:
+          List of paths to directories containing bindings, in YAML format.
+          These directories are recursively searched for .yaml files.
+
+        warn_reg_unit_address_mismatch (default: True):
+          If True, a warning is logged if a node has a 'reg' property where
+          the address of the first entry does not match the unit address of the
+          node
+
+        default_prop_types (default: True):
+          If True, default property types will be used when a node has no
+          bindings.
+
+        support_fixed_partitions_on_any_bus (default True):
+          If True, set the Node.bus for 'fixed-partitions' compatible nodes
+          to None.  This allows 'fixed-partitions' binding to match regardless
+          of the bus the 'fixed-partition' is under.
+
+        infer_binding_for_paths (default: None):
+          An iterable of devicetree paths identifying nodes for which bindings
+          should be inferred from the node content.  (Child nodes are not
+          processed.)  Pass none if no nodes should support inferred bindings.
+
+        vendor_prefixes (default: None):
+          A dict mapping vendor prefixes in compatible properties to their
+          descriptions. If given, compatibles in the form "manufacturer,device"
+          for which "manufacturer" is neither a key in the dict nor a specially
+          exempt set of grandfathered-in cases will cause warnings.
+
+        werror (default: False):
+          If True, some edtlib specific warnings become errors. This currently
+          errors out if 'dts' has any deprecated properties set, or an unknown
+          vendor prefix is used.
+        """
+        self._warn_reg_unit_address_mismatch = warn_reg_unit_address_mismatch
+        self._default_prop_types = default_prop_types
+        self._fixed_partitions_no_bus = support_fixed_partitions_on_any_bus
+        self._infer_binding_for_paths = set(infer_binding_for_paths or [])
+        self._werror = bool(werror)
+        self._vendor_prefixes = vendor_prefixes or {}
+
+        self.dts_path = dts
+        self.bindings_dirs = bindings_dirs
+
+        try:
+            self._dt = DT(dts)
+        except DTError as e:
+            raise EDTError(e) from e
+        _check_dt(self._dt)
+
+        self._init_compat2binding()
+        self._init_nodes()
+        self._init_graph()
+        self._init_luts()
+
+        self._check()
+
+    def get_node(self, path):
+        """
+        Returns the Node at the DT path or alias 'path'. Raises EDTError if the
+        path or alias doesn't exist.
+        """
+        try:
+            return self._node2enode[self._dt.get_node(path)]
+        except DTError as e:
+            _err(e)
+
+    @property
+    def chosen_nodes(self):
+        ret = OrderedDict()
+
+        try:
+            chosen = self._dt.get_node("/chosen")
+        except DTError:
+            return ret
+
+        for name, prop in chosen.props.items():
+            try:
+                node = prop.to_path()
+            except DTError:
+                # DTS value is not phandle or string, or path doesn't exist
+                continue
+
+            ret[name] = self._node2enode[node]
+
+        return ret
+
+    def chosen_node(self, name):
+        """
+        Returns the Node pointed at by the property named 'name' in /chosen, or
+        None if the property is missing
+        """
+        return self.chosen_nodes.get(name)
+
+    @property
+    def dts_source(self):
+        return f"{self._dt}"
+
+    def __repr__(self):
+        return f"<EDT for '{self.dts_path}', binding directories " \
+            f"'{self.bindings_dirs}'>"
+
+    @property
+    def scc_order(self):
+        try:
+            return self._graph.scc_order()
+        except Exception as e:
+            raise EDTError(e)
+
+    def _init_graph(self):
+        # Constructs a graph of dependencies between Node instances,
+        # which is usable for computing a partial order over the dependencies.
+        # The algorithm supports detecting dependency loops.
+        #
+        # Actually computing the SCC order is lazily deferred to the
+        # first time the scc_order property is read.
+
+        self._graph = Graph()
+
+        for node in self.nodes:
+            # A Node always depends on its parent.
+            for child in node.children.values():
+                self._graph.add_edge(child, node)
+
+            # A Node depends on any Nodes present in 'phandle',
+            # 'phandles', or 'phandle-array' property values.
+            for prop in node.props.values():
+                if prop.type == 'phandle':
+                    self._graph.add_edge(node, prop.val)
+                elif prop.type == 'phandles':
+                    for phandle_node in prop.val:
+                        self._graph.add_edge(node, phandle_node)
+                elif prop.type == 'phandle-array':
+                    for cd in prop.val:
+                        if cd is None:
+                            continue
+                        self._graph.add_edge(node, cd.controller)
+
+            # A Node depends on whatever supports the interrupts it
+            # generates.
+            for intr in node.interrupts:
+                self._graph.add_edge(node, intr.controller)
+
+    def _init_compat2binding(self):
+        # Creates self._compat2binding, a dictionary that maps
+        # (<compatible>, <bus>) tuples (both strings) to Binding objects.
+        #
+        # The Binding objects are created from YAML files discovered
+        # in self.bindings_dirs as needed.
+        #
+        # For example, self._compat2binding["company,dev", "can"]
+        # contains the Binding for the 'company,dev' device, when it
+        # appears on the CAN bus.
+        #
+        # For bindings that don't specify a bus, <bus> is None, so that e.g.
+        # self._compat2binding["company,notonbus", None] is the Binding.
+        #
+        # Only bindings for 'compatible' strings that appear in the devicetree
+        # are loaded.
+
+        dt_compats = _dt_compats(self._dt)
+        # Searches for any 'compatible' string mentioned in the devicetree
+        # files, with a regex
+        dt_compats_search = re.compile(
+            "|".join(re.escape(compat) for compat in dt_compats)
+        ).search
+
+        self._binding_paths = _binding_paths(self.bindings_dirs)
+        self._binding_fname2path = {os.path.basename(path): path
+                                    for path in self._binding_paths}
+
+        self._compat2binding = {}
+        for binding_path in self._binding_paths:
+            with open(binding_path, encoding="utf-8") as f:
+                contents = f.read()
+
+            # As an optimization, skip parsing files that don't contain any of
+            # the .dts 'compatible' strings, which should be reasonably safe
+            if not dt_compats_search(contents):
+                continue
+
+            # Load the binding and check that it actually matches one of the
+            # compatibles. Might get false positives above due to comments and
+            # stuff.
+
+            try:
+                # Parsed PyYAML output (Python lists/dictionaries/strings/etc.,
+                # representing the file)
+                raw = yaml.load(contents, Loader=_BindingLoader)
+            except yaml.YAMLError as e:
+                _err(
+                        f"'{binding_path}' appears in binding directories "
+                        f"but isn't valid YAML: {e}")
+                continue
+
+            # Convert the raw data to a Binding object, erroring out
+            # if necessary.
+            binding = self._binding(raw, binding_path, dt_compats)
+
+            # Register the binding in self._compat2binding, along with
+            # any child bindings that have their own compatibles.
+            while binding is not None:
+                if binding.compatible:
+                    self._register_binding(binding)
+                binding = binding.child_binding
+
+    def _binding(self, raw, binding_path, dt_compats):
+        # Convert a 'raw' binding from YAML to a Binding object and return it.
+        #
+        # Error out if the raw data looks like an invalid binding.
+        #
+        # Return None if the file doesn't contain a binding or the
+        # binding's compatible isn't in dt_compats.
+
+        # Get the 'compatible:' string.
+        if raw is None or "compatible" not in raw:
+            # Empty file, binding fragment, spurious file, etc.
+            return None
+
+        compatible = raw["compatible"]
+
+        if compatible not in dt_compats:
+            # Not a compatible we care about.
+            return None
+
+        # Initialize and return the Binding object.
+        return Binding(binding_path, self._binding_fname2path, raw=raw)
+
+    def _register_binding(self, binding):
+        # Do not allow two different bindings to have the same
+        # 'compatible:'/'on-bus:' combo
+        old_binding = self._compat2binding.get((binding.compatible,
+                                                binding.on_bus))
+        if old_binding:
+            msg = (f"both {old_binding.path} and {binding.path} have "
+                   f"'compatible: {binding.compatible}'")
+            if binding.on_bus is not None:
+                msg += f" and 'on-bus: {binding.on_bus}'"
+            _err(msg)
+
+        # Register the binding.
+        self._compat2binding[binding.compatible, binding.on_bus] = binding
+
+    def _init_nodes(self):
+        # Creates a list of edtlib.Node objects from the dtlib.Node objects, in
+        # self.nodes
+
+        # Maps each dtlib.Node to its corresponding edtlib.Node
+        self._node2enode = {}
+
+        self.nodes = []
+
+        for dt_node in self._dt.node_iter():
+            # Warning: We depend on parent Nodes being created before their
+            # children. This is guaranteed by node_iter().
+            node = Node()
+            node.edt = self
+            node._node = dt_node
+            if "compatible" in node._node.props:
+                node.compats = node._node.props["compatible"].to_strings()
+            else:
+                node.compats = []
+            node.bus_node = node._bus_node(self._fixed_partitions_no_bus)
+            node._init_binding()
+            node._init_regs()
+            node._init_ranges()
+
+            self.nodes.append(node)
+            self._node2enode[dt_node] = node
+
+        for node in self.nodes:
+            # These depend on all Node objects having been created, because
+            # they (either always or sometimes) reference other nodes, so we
+            # run them separately
+            node._init_props(default_prop_types=self._default_prop_types,
+                             err_on_deprecated=self._werror)
+            node._init_interrupts()
+            node._init_pinctrls()
+
+        if self._warn_reg_unit_address_mismatch:
+            # This warning matches the simple_bus_reg warning in dtc
+            for node in self.nodes:
+                if node.regs and node.regs[0].addr != node.unit_addr:
+                    _LOG.warning("unit address and first address in 'reg' "
+                                 f"(0x{node.regs[0].addr:x}) don't match for "
+                                 f"{node.path}")
+
+    def _init_luts(self):
+        # Initialize node lookup tables (LUTs).
+
+        self.label2node = OrderedDict()
+        self.dep_ord2node = OrderedDict()
+        self.compat2nodes = defaultdict(list)
+        self.compat2okay = defaultdict(list)
+
+        for node in self.nodes:
+            for label in node.labels:
+                self.label2node[label] = node
+
+            for compat in node.compats:
+                self.compat2nodes[compat].append(node)
+
+                if node.status == "okay":
+                    self.compat2okay[compat].append(node)
+
+        for nodeset in self.scc_order:
+            node = nodeset[0]
+            self.dep_ord2node[node.dep_ordinal] = node
+
+    def _check(self):
+        # Tree-wide checks and warnings.
+
+        for binding in self._compat2binding.values():
+            for spec in binding.prop2specs.values():
+                if not spec.enum or spec.type != 'string':
+                    continue
+
+                if not spec.enum_tokenizable:
+                    _LOG.warning(
+                        f"compatible '{binding.compatible}' "
+                        f"in binding '{binding.path}' has non-tokenizable enum "
+                        f"for property '{spec.name}': " +
+                        ', '.join(repr(x) for x in spec.enum))
+                elif not spec.enum_upper_tokenizable:
+                    _LOG.warning(
+                        f"compatible '{binding.compatible}' "
+                        f"in binding '{binding.path}' has enum for property "
+                        f"'{spec.name}' that is only tokenizable "
+                        'in lowercase: ' +
+                        ', '.join(repr(x) for x in spec.enum))
+
+        # Validate the contents of compatible properties.
+        self._checked_compatibles: Set[str] = set()
+        for node in self.nodes:
+            if 'compatible' not in node.props:
+                continue
+
+            compatibles = node.props['compatible'].val
+
+            # _check() runs after _init_compat2binding() has called
+            # _dt_compats(), which already converted every compatible
+            # property to a list of strings. So we know 'compatibles'
+            # is a list, but add an assert for future-proofing.
+            assert isinstance(compatibles, list)
+
+            for compat in compatibles:
+                # This is also just for future-proofing.
+                assert isinstance(compat, str)
+
+                self._check_compatible(node, compat)
+        del self._checked_compatibles  # We have no need for this anymore.
+
+    def _check_compatible(self, node, compat):
+        if compat in self._checked_compatibles:
+            return
+
+        # The regular expression comes from dt-schema.
+        compat_re = r'^[a-zA-Z][a-zA-Z0-9,+\-._]+$'
+        if not re.match(compat_re, compat):
+            _err(f"node '{node.path}' compatible '{compat}' "
+                 'must match this regular expression: '
+                 f"'{compat_re}'")
+
+        if ',' in compat and self._vendor_prefixes:
+            vendor = compat.split(',', 1)[0]
+            # As an exception, the root node can have whatever
+            # compatibles it wants. Other nodes get checked.
+            if node.path != '/' and \
+                   vendor not in self._vendor_prefixes and \
+                   vendor not in _VENDOR_PREFIX_ALLOWED:
+                if self._werror:
+                    handler_fn = _err
+                else:
+                    handler_fn = _LOG.warning
+                handler_fn(
+                    f"node '{node.path}' compatible '{compat}' "
+                    f"has unknown vendor prefix '{vendor}'")
+
+        self._checked_compatibles.add(compat)
+
+class Node:
+    """
+    Represents a devicetree node, augmented with information from bindings, and
+    with some interpretation of devicetree properties. There's a one-to-one
+    correspondence between devicetree nodes and Nodes.
+
+    These attributes are available on Node objects:
+
+    edt:
+      The EDT instance this node is from
+
+    name:
+      The name of the node
+
+    unit_addr:
+      An integer with the ...@<unit-address> portion of the node name,
+      translated through any 'ranges' properties on parent nodes, or None if
+      the node name has no unit-address portion
+
+    description:
+      The description string from the binding for the node, or None if the node
+      has no binding. Leading and trailing whitespace (including newlines) is
+      removed.
+
+    path:
+      The devicetree path of the node
+
+    label:
+      The text from the 'label' property on the node, or None if the node has
+      no 'label'
+
+    labels:
+      A list of all of the devicetree labels for the node, in the same order
+      as the labels appear, but with duplicates removed.
+
+      This corresponds to the actual devicetree source labels, unlike the
+      "label" attribute, which is the value of a devicetree property named
+      "label".
+
+    parent:
+      The Node instance for the devicetree parent of the Node, or None if the
+      node is the root node
+
+    children:
+      A dictionary with the Node instances for the devicetree children of the
+      node, indexed by name
+
+    dep_ordinal:
+      A non-negative integer value such that the value for a Node is
+      less than the value for all Nodes that depend on it.
+
+      The ordinal is defined for all Nodes, and is unique among nodes in its
+      EDT 'nodes' list.
+
+    required_by:
+      A list with the nodes that directly depend on the node
+
+    depends_on:
+      A list with the nodes that the node directly depends on
+
+    status:
+      The node's status property value, as a string, or "okay" if the node
+      has no status property set. If the node's status property is "ok",
+      it is converted to "okay" for consistency.
+
+    read_only:
+      True if the node has a 'read-only' property, and False otherwise
+
+    matching_compat:
+      The 'compatible' string for the binding that matched the node, or None if
+      the node has no binding
+
+    binding_path:
+      The path to the binding file for the node, or None if the node has no
+      binding
+
+    compats:
+      A list of 'compatible' strings for the node, in the same order that
+      they're listed in the .dts file
+
+    ranges:
+      A list if Range objects extracted from the node's ranges property.
+      The list is empty if the node does not have a range property.
+
+    regs:
+      A list of Register objects for the node's registers
+
+    props:
+      A collections.OrderedDict that maps property names to Property objects.
+      Property objects are created for all devicetree properties on the node
+      that are mentioned in 'properties:' in the binding.
+
+    aliases:
+      A list of aliases for the node. This is fetched from the /aliases node.
+
+    interrupts:
+      A list of ControllerAndData objects for the interrupts generated by the
+      node. The list is empty if the node does not generate interrupts.
+
+    pinctrls:
+      A list of PinCtrl objects for the pinctrl-<index> properties on the
+      node, sorted by index. The list is empty if the node does not have any
+      pinctrl-<index> properties.
+
+    bus:
+      If the node is a bus node (has a 'bus:' key in its binding), then this
+      attribute holds the bus type, e.g. "i2c" or "spi". If the node is not a
+      bus node, then this attribute is None.
+
+    on_bus:
+      The bus the node appears on, e.g. "i2c" or "spi". The bus is determined
+      by searching upwards for a parent node whose binding has a 'bus:' key,
+      returning the value of the first 'bus:' key found. If none of the node's
+      parents has a 'bus:' key, this attribute is None.
+
+    bus_node:
+      Like on_bus, but contains the Node for the bus controller, or None if the
+      node is not on a bus.
+
+    flash_controller:
+      The flash controller for the node. Only meaningful for nodes representing
+      flash partitions.
+
+    spi_cs_gpio:
+      The device's SPI GPIO chip select as a ControllerAndData instance, if it
+      exists, and None otherwise. See
+      Documentation/devicetree/bindings/spi/spi-controller.yaml in the Linux kernel.
+    """
+    @property
+    def name(self):
+        "See the class docstring"
+        return self._node.name
+
+    @property
+    def unit_addr(self):
+        "See the class docstring"
+
+        # TODO: Return a plain string here later, like dtlib.Node.unit_addr?
+
+        if "@" not in self.name:
+            return None
+
+        try:
+            addr = int(self.name.split("@", 1)[1], 16)
+        except ValueError:
+            _err(f"{self!r} has non-hex unit address")
+
+        return _translate(addr, self._node)
+
+    @property
+    def description(self):
+        "See the class docstring."
+        if self._binding:
+            return self._binding.description
+        return None
+
+    @property
+    def path(self):
+        "See the class docstring"
+        return self._node.path
+
+    @property
+    def label(self):
+        "See the class docstring"
+        if "label" in self._node.props:
+            return self._node.props["label"].to_string()
+        return None
+
+    @property
+    def labels(self):
+        "See the class docstring"
+        return self._node.labels
+
+    @property
+    def parent(self):
+        "See the class docstring"
+        return self.edt._node2enode.get(self._node.parent)
+
+    @property
+    def children(self):
+        "See the class docstring"
+        # Could be initialized statically too to preserve identity, but not
+        # sure if needed. Parent nodes being initialized before their children
+        # would need to be kept in mind.
+        return OrderedDict((name, self.edt._node2enode[node])
+                           for name, node in self._node.nodes.items())
+
+    @property
+    def required_by(self):
+        "See the class docstring"
+        return self.edt._graph.required_by(self)
+
+    @property
+    def depends_on(self):
+        "See the class docstring"
+        return self.edt._graph.depends_on(self)
+
+    @property
+    def status(self):
+        "See the class docstring"
+        status = self._node.props.get("status")
+
+        if status is None:
+            as_string = "okay"
+        else:
+            as_string = status.to_string()
+
+        if as_string == "ok":
+            as_string = "okay"
+
+        return as_string
+
+    @property
+    def read_only(self):
+        "See the class docstring"
+        return "read-only" in self._node.props
+
+    @property
+    def aliases(self):
+        "See the class docstring"
+        return [alias for alias, node in self._node.dt.alias2node.items()
+                if node is self._node]
+
+    @property
+    def bus(self):
+        "See the class docstring"
+        if self._binding:
+            return self._binding.bus
+        return None
+
+    @property
+    def on_bus(self):
+        "See the class docstring"
+        bus_node = self.bus_node
+        return bus_node.bus if bus_node else None
+
+    @property
+    def flash_controller(self):
+        "See the class docstring"
+
+        # The node path might be something like
+        # /flash-controller@4001E000/flash@0/partitions/partition@fc000. We go
+        # up two levels to get the flash and check its compat. The flash
+        # controller might be the flash itself (for cases like NOR flashes).
+        # For the case of 'soc-nv-flash', we assume the controller is the
+        # parent of the flash node.
+
+        if not self.parent or not self.parent.parent:
+            _err(f"flash partition {self!r} lacks parent or grandparent node")
+
+        controller = self.parent.parent
+        if controller.matching_compat == "soc-nv-flash":
+            return controller.parent
+        return controller
+
+    @property
+    def spi_cs_gpio(self):
+        "See the class docstring"
+
+        if not (self.on_bus == "spi" and "cs-gpios" in self.bus_node.props):
+            return None
+
+        if not self.regs:
+            _err(f"{self!r} needs a 'reg' property, to look up the "
+                 "chip select index for SPI")
+
+        parent_cs_lst = self.bus_node.props["cs-gpios"].val
+
+        # cs-gpios is indexed by the unit address
+        cs_index = self.regs[0].addr
+        if cs_index >= len(parent_cs_lst):
+            _err(f"index from 'regs' in {self!r} ({cs_index}) "
+                 "is >= number of cs-gpios in "
+                 f"{self.bus_node!r} ({len(parent_cs_lst)})")
+
+        return parent_cs_lst[cs_index]
+
+    def __repr__(self):
+        if self.binding_path:
+            binding = "binding " + self.binding_path
+        else:
+            binding = "no binding"
+        return f"<Node {self.path} in '{self.edt.dts_path}', {binding}>"
+
+    def _init_binding(self):
+        # Initializes Node.matching_compat, Node._binding, and
+        # Node.binding_path.
+        #
+        # Node._binding holds the data from the node's binding file, in the
+        # format returned by PyYAML (plain Python lists, dicts, etc.), or None
+        # if the node has no binding.
+
+        # This relies on the parent of the node having already been
+        # initialized, which is guaranteed by going through the nodes in
+        # node_iter() order.
+
+        if self.path in self.edt._infer_binding_for_paths:
+            self._binding_from_properties()
+            return
+
+        if self.compats:
+            on_bus = self.on_bus
+
+            for compat in self.compats:
+                # When matching, respect the order of the 'compatible' entries,
+                # and for each one first try to match against an explicitly
+                # specified bus (if any) and then against any bus. This is so
+                # that matching against bindings which do not specify a bus
+                # works the same way in Zephyr as it does elsewhere.
+                if (compat, on_bus) in self.edt._compat2binding:
+                    binding = self.edt._compat2binding[compat, on_bus]
+                elif (compat, None) in self.edt._compat2binding:
+                    binding = self.edt._compat2binding[compat, None]
+                else:
+                    continue
+
+                self.binding_path = binding.path
+                self.matching_compat = compat
+                self._binding = binding
+                return
+        else:
+            # No 'compatible' property. See if the parent binding has
+            # a compatible. This can come from one or more levels of
+            # nesting with 'child-binding:'.
+
+            binding_from_parent = self._binding_from_parent()
+            if binding_from_parent:
+                self._binding = binding_from_parent
+                self.binding_path = self._binding.path
+                self.matching_compat = self._binding.compatible
+
+                return
+
+        # No binding found
+        self._binding = self.binding_path = self.matching_compat = None
+
+    def _binding_from_properties(self):
+        # Sets up a Binding object synthesized from the properties in the node.
+
+        if self.compats:
+            _err(f"compatible in node with inferred binding: {self.path}")
+
+        # Synthesize a 'raw' binding as if it had been parsed from YAML.
+        raw = {
+            'description': 'Inferred binding from properties, via edtlib.',
+            'properties': {},
+        }
+        for name, prop in self._node.props.items():
+            pp = OrderedDict()
+            if prop.type == Type.EMPTY:
+                pp["type"] = "boolean"
+            elif prop.type == Type.BYTES:
+                pp["type"] = "uint8-array"
+            elif prop.type == Type.NUM:
+                pp["type"] = "int"
+            elif prop.type == Type.NUMS:
+                pp["type"] = "array"
+            elif prop.type == Type.STRING:
+                pp["type"] = "string"
+            elif prop.type == Type.STRINGS:
+                pp["type"] = "string-array"
+            elif prop.type == Type.PHANDLE:
+                pp["type"] = "phandle"
+            elif prop.type == Type.PHANDLES:
+                pp["type"] = "phandles"
+            elif prop.type == Type.PHANDLES_AND_NUMS:
+                pp["type"] = "phandle-array"
+            elif prop.type == Type.PATH:
+                pp["type"] = "path"
+            else:
+                _err(f"cannot infer binding from property: {prop} "
+                     f"with type {prop.type!r}")
+            raw['properties'][name] = pp
+
+        # Set up Node state.
+        self.binding_path = None
+        self.matching_compat = None
+        self.compats = []
+        self._binding = Binding(None, {}, raw=raw, require_compatible=False)
+
+    def _binding_from_parent(self):
+        # Returns the binding from 'child-binding:' in the parent node's
+        # binding.
+
+        if not self.parent:
+            return None
+
+        pbinding = self.parent._binding
+        if not pbinding:
+            return None
+
+        if pbinding.child_binding:
+            return pbinding.child_binding
+
+        return None
+
+    def _bus_node(self, support_fixed_partitions_on_any_bus = True):
+        # Returns the value for self.bus_node. Relies on parent nodes being
+        # initialized before their children.
+
+        if not self.parent:
+            # This is the root node
+            return None
+
+        # Treat 'fixed-partitions' as if they are not on any bus.  The reason is
+        # that flash nodes might be on a SPI or controller or SoC bus.  Having
+        # bus be None means we'll always match the binding for fixed-partitions
+        # also this means want processing the fixed-partitions node we wouldn't
+        # try to do anything bus specific with it.
+        if support_fixed_partitions_on_any_bus and "fixed-partitions" in self.compats:
+            return None
+
+        if self.parent.bus:
+            # The parent node is a bus node
+            return self.parent
+
+        # Same bus node as parent (possibly None)
+        return self.parent.bus_node
+
+    def _init_props(self, default_prop_types=False, err_on_deprecated=False):
+        # Creates self.props. See the class docstring. Also checks that all
+        # properties on the node are declared in its binding.
+
+        self.props = OrderedDict()
+
+        node = self._node
+        if self._binding:
+            prop2specs = self._binding.prop2specs
+        else:
+            prop2specs = None
+
+        # Initialize self.props
+        if prop2specs:
+            for prop_spec in prop2specs.values():
+                self._init_prop(prop_spec, err_on_deprecated)
+            self._check_undeclared_props()
+        elif default_prop_types:
+            for name in node.props:
+                if name not in _DEFAULT_PROP_SPECS:
+                    continue
+                prop_spec = _DEFAULT_PROP_SPECS[name]
+                val = self._prop_val(name, prop_spec.type, False, False, None,
+                                     None, err_on_deprecated)
+                self.props[name] = Property(prop_spec, val, self)
+
+    def _init_prop(self, prop_spec, err_on_deprecated):
+        # _init_props() helper for initializing a single property.
+        # 'prop_spec' is a PropertySpec object from the node's binding.
+
+        name = prop_spec.name
+        prop_type = prop_spec.type
+        if not prop_type:
+            _err(f"'{name}' in {self.binding_path} lacks 'type'")
+
+        val = self._prop_val(name, prop_type, prop_spec.deprecated,
+                             prop_spec.required, prop_spec.default,
+                             prop_spec.specifier_space, err_on_deprecated)
+
+        if val is None:
+            # 'required: false' property that wasn't there, or a property type
+            # for which we store no data.
+            return
+
+        enum = prop_spec.enum
+        if enum and val not in enum:
+            _err(f"value of property '{name}' on {self.path} in "
+                 f"{self.edt.dts_path} ({val!r}) is not in 'enum' list in "
+                 f"{self.binding_path} ({enum!r})")
+
+        const = prop_spec.const
+        if const is not None and val != const:
+            _err(f"value of property '{name}' on {self.path} in "
+                 f"{self.edt.dts_path} ({val!r}) "
+                 "is different from the 'const' value specified in "
+                 f"{self.binding_path} ({const!r})")
+
+        # Skip properties that start with '#', like '#size-cells', and mapping
+        # properties like 'gpio-map'/'interrupt-map'
+        if name[0] == "#" or name.endswith("-map"):
+            return
+
+        self.props[name] = Property(prop_spec, val, self)
+
+    def _prop_val(self, name, prop_type, deprecated, required, default,
+                  specifier_space, err_on_deprecated):
+        # _init_prop() helper for getting the property's value
+        #
+        # name:
+        #   Property name from binding
+        #
+        # prop_type:
+        #   Property type from binding (a string like "int")
+        #
+        # deprecated:
+        #   True if the property is deprecated
+        #
+        # required:
+        #   True if the property is required to exist
+        #
+        # default:
+        #   Default value to use when the property doesn't exist, or None if
+        #   the binding doesn't give a default value
+        #
+        # specifier_space:
+        #   Property specifier-space from binding (if prop_type is "phandle-array")
+        #
+        # err_on_deprecated:
+        #   If True, a deprecated property is an error instead of warning.
+
+        node = self._node
+        prop = node.props.get(name)
+
+        if prop and deprecated:
+            msg = (f"'{name}' is marked as deprecated in 'properties:' "
+                   f"in {self.binding_path} for node {node.path}.")
+            if err_on_deprecated:
+                _err(msg)
+            else:
+                _LOG.warning(msg)
+
+        if not prop:
+            if required and self.status == "okay":
+                _err(f"'{name}' is marked as required in 'properties:' in "
+                     f"{self.binding_path}, but does not appear in {node!r}")
+
+            if default is not None:
+                # YAML doesn't have a native format for byte arrays. We need to
+                # convert those from an array like [0x12, 0x34, ...]. The
+                # format has already been checked in
+                # _check_prop_type_and_default().
+                if prop_type == "uint8-array":
+                    return bytes(default)
+                return default
+
+            return False if prop_type == "boolean" else None
+
+        if prop_type == "boolean":
+            if prop.type != Type.EMPTY:
+                _err("'{0}' in {1!r} is defined with 'type: boolean' in {2}, "
+                     "but is assigned a value ('{3}') instead of being empty "
+                     "('{0};')".format(name, node, self.binding_path, prop))
+            return True
+
+        if prop_type == "int":
+            return prop.to_num()
+
+        if prop_type == "array":
+            return prop.to_nums()
+
+        if prop_type == "uint8-array":
+            return prop.to_bytes()
+
+        if prop_type == "string":
+            return prop.to_string()
+
+        if prop_type == "string-array":
+            return prop.to_strings()
+
+        if prop_type == "phandle":
+            return self.edt._node2enode[prop.to_node()]
+
+        if prop_type == "phandles":
+            return [self.edt._node2enode[node] for node in prop.to_nodes()]
+
+        if prop_type == "phandle-array":
+            # This type is a bit high-level for dtlib as it involves
+            # information from bindings and *-names properties, so there's no
+            # to_phandle_array() in dtlib. Do the type check ourselves.
+            if prop.type not in (Type.PHANDLE, Type.PHANDLES, Type.PHANDLES_AND_NUMS):
+                _err(f"expected property '{name}' in {node.path} in "
+                     f"{node.dt.filename} to be assigned "
+                     f"with '{name} = < &foo ... &bar 1 ... &baz 2 3 >' "
+                     f"(a mix of phandles and numbers), not '{prop}'")
+
+            return self._standard_phandle_val_list(prop, specifier_space)
+
+        if prop_type == "path":
+            return self.edt._node2enode[prop.to_path()]
+
+        # prop_type == "compound". Checking that the 'type:'
+        # value is valid is done in _check_prop_type_and_default().
+        #
+        # 'compound' is a dummy type for properties that don't fit any of the
+        # patterns above, so that we can require all entries in 'properties:'
+        # to have a 'type: ...'. No Property object is created for it.
+        return None
+
+    def _check_undeclared_props(self):
+        # Checks that all properties are declared in the binding
+
+        for prop_name in self._node.props:
+            # Allow a few special properties to not be declared in the binding
+            if prop_name.endswith("-controller") or \
+               prop_name.startswith("#") or \
+               prop_name.startswith("pinctrl-") or \
+               prop_name in {
+                   "compatible", "status", "ranges", "phandle",
+                   "interrupt-parent", "interrupts-extended", "device_type"}:
+                continue
+
+            if prop_name not in self._binding.prop2specs:
+                _err(f"'{prop_name}' appears in {self._node.path} in "
+                     f"{self.edt.dts_path}, but is not declared in "
+                     f"'properties:' in {self.binding_path}")
+
+    def _init_ranges(self):
+        # Initializes self.ranges
+        node = self._node
+
+        self.ranges = []
+
+        if "ranges" not in node.props:
+            return
+
+        child_address_cells = node.props.get("#address-cells")
+        parent_address_cells = _address_cells(node)
+        if child_address_cells is None:
+            child_address_cells = 2 # Default value per DT spec.
+        else:
+            child_address_cells = child_address_cells.to_num()
+        child_size_cells = node.props.get("#size-cells")
+        if child_size_cells is None:
+            child_size_cells = 1 # Default value per DT spec.
+        else:
+            child_size_cells = child_size_cells.to_num()
+
+        # Number of cells for one translation 3-tuple in 'ranges'
+        entry_cells = child_address_cells + parent_address_cells + child_size_cells
+
+        if entry_cells == 0:
+            if len(node.props["ranges"].value) == 0:
+                return
+            else:
+                _err(f"'ranges' should be empty in {self._node.path} since "
+                     f"<#address-cells> = {child_address_cells}, "
+                     f"<#address-cells for parent> = {parent_address_cells} and "
+                     f"<#size-cells> = {child_size_cells}")
+
+        for raw_range in _slice(node, "ranges", 4*entry_cells,
+                                f"4*(<#address-cells> (= {child_address_cells}) + "
+                                "<#address-cells for parent> "
+                                f"(= {parent_address_cells}) + "
+                                f"<#size-cells> (= {child_size_cells}))"):
+
+            range = Range()
+            range.node = self
+            range.child_bus_cells = child_address_cells
+            if child_address_cells == 0:
+                range.child_bus_addr = None
+            else:
+                range.child_bus_addr = to_num(raw_range[:4*child_address_cells])
+            range.parent_bus_cells = parent_address_cells
+            if parent_address_cells == 0:
+                range.parent_bus_addr = None
+            else:
+                range.parent_bus_addr = to_num(raw_range[(4*child_address_cells):\
+                                            (4*child_address_cells + 4*parent_address_cells)])
+            range.length_cells = child_size_cells
+            if child_size_cells == 0:
+                range.length = None
+            else:
+                range.length = to_num(raw_range[(4*child_address_cells + \
+                                                    4*parent_address_cells):])
+
+            self.ranges.append(range)
+
+    def _init_regs(self):
+        # Initializes self.regs
+
+        node = self._node
+
+        self.regs = []
+
+        if "reg" not in node.props:
+            return
+
+        address_cells = _address_cells(node)
+        size_cells = _size_cells(node)
+
+        for raw_reg in _slice(node, "reg", 4*(address_cells + size_cells),
+                              f"4*(<#address-cells> (= {address_cells}) + "
+                              f"<#size-cells> (= {size_cells}))"):
+            reg = Register()
+            reg.node = self
+            if address_cells == 0:
+                reg.addr = None
+            else:
+                reg.addr = _translate(to_num(raw_reg[:4*address_cells]), node)
+            if size_cells == 0:
+                reg.size = None
+            else:
+                reg.size = to_num(raw_reg[4*address_cells:])
+            if size_cells != 0 and reg.size == 0:
+                _err(f"zero-sized 'reg' in {self._node!r} seems meaningless "
+                     "(maybe you want a size of one or #size-cells = 0 "
+                     "instead)")
+
+            self.regs.append(reg)
+
+        _add_names(node, "reg", self.regs)
+
+    def _init_pinctrls(self):
+        # Initializes self.pinctrls from any pinctrl-<index> properties
+
+        node = self._node
+
+        # pinctrl-<index> properties
+        pinctrl_props = [prop for name, prop in node.props.items()
+                         if re.match("pinctrl-[0-9]+", name)]
+        # Sort by index
+        pinctrl_props.sort(key=lambda prop: prop.name)
+
+        # Check indices
+        for i, prop in enumerate(pinctrl_props):
+            if prop.name != "pinctrl-" + str(i):
+                _err(f"missing 'pinctrl-{i}' property on {node!r} "
+                     "- indices should be contiguous and start from zero")
+
+        self.pinctrls = []
+        for prop in pinctrl_props:
+            pinctrl = PinCtrl()
+            pinctrl.node = self
+            pinctrl.conf_nodes = [
+                self.edt._node2enode[node] for node in prop.to_nodes()
+            ]
+            self.pinctrls.append(pinctrl)
+
+        _add_names(node, "pinctrl", self.pinctrls)
+
+    def _init_interrupts(self):
+        # Initializes self.interrupts
+
+        node = self._node
+
+        self.interrupts = []
+
+        for controller_node, data in _interrupts(node):
+            interrupt = ControllerAndData()
+            interrupt.node = self
+            interrupt.controller = self.edt._node2enode[controller_node]
+            interrupt.data = self._named_cells(interrupt.controller, data,
+                                               "interrupt")
+
+            self.interrupts.append(interrupt)
+
+        _add_names(node, "interrupt", self.interrupts)
+
+    def _standard_phandle_val_list(self, prop, specifier_space):
+        # Parses a property like
+        #
+        #     <prop.name> = <phandle cell phandle cell ...>;
+        #
+        # where each phandle points to a controller node that has a
+        #
+        #     #<specifier_space>-cells = <size>;
+        #
+        # property that gives the number of cells in the value after the
+        # controller's phandle in the property.
+        #
+        # E.g. with a property like
+        #
+        #     pwms = <&foo 1 2 &bar 3>;
+        #
+        # If 'specifier_space' is "pwm", then we should have this elsewhere
+        # in the tree:
+        #
+        #     foo: ... {
+        #             #pwm-cells = <2>;
+        #     };
+        #
+        #     bar: ... {
+        #             #pwm-cells = <1>;
+        #     };
+        #
+        # These values can be given names using the <specifier_space>-names:
+        # list in the binding for the phandle nodes.
+        #
+        # Also parses any
+        #
+        #     <specifier_space>-names = "...", "...", ...
+        #
+        # Returns a list of Optional[ControllerAndData] instances.
+        #
+        # An index is None if the underlying phandle-array element is
+        # unspecified.
+
+        if not specifier_space:
+            if prop.name.endswith("gpios"):
+                # There's some slight special-casing for *-gpios properties in that
+                # e.g. foo-gpios still maps to #gpio-cells rather than
+                # #foo-gpio-cells
+                specifier_space = "gpio"
+            else:
+                # Strip -s. We've already checked that property names end in -s
+                # if there is no specifier space in _check_prop_type_and_default().
+                specifier_space = prop.name[:-1]
+
+        res = []
+
+        for item in _phandle_val_list(prop, specifier_space):
+            if item is None:
+                res.append(None)
+                continue
+
+            controller_node, data = item
+            mapped_controller, mapped_data = \
+                _map_phandle_array_entry(prop.node, controller_node, data,
+                                         specifier_space)
+
+            entry = ControllerAndData()
+            entry.node = self
+            entry.controller = self.edt._node2enode[mapped_controller]
+            entry.basename = specifier_space
+            entry.data = self._named_cells(entry.controller, mapped_data,
+                                           specifier_space)
+
+            res.append(entry)
+
+        _add_names(self._node, specifier_space, res)
+
+        return res
+
+    def _named_cells(self, controller, data, basename):
+        # Returns a dictionary that maps <basename>-cells names given in the
+        # binding for 'controller' to cell values. 'data' is the raw data, as a
+        # byte array.
+
+        if not controller._binding:
+            _err(f"{basename} controller {controller._node!r} "
+                 f"for {self._node!r} lacks binding")
+
+        if basename in controller._binding.specifier2cells:
+            cell_names = controller._binding.specifier2cells[basename]
+        else:
+            # Treat no *-cells in the binding the same as an empty *-cells, so
+            # that bindings don't have to have e.g. an empty 'clock-cells:' for
+            # '#clock-cells = <0>'.
+            cell_names = []
+
+        data_list = to_nums(data)
+        if len(data_list) != len(cell_names):
+            _err(f"unexpected '{basename}-cells:' length in binding for "
+                 f"{controller._node!r} - {len(cell_names)} "
+                 f"instead of {len(data_list)}")
+
+        return OrderedDict(zip(cell_names, data_list))
+
+
+class Range:
+    """
+    Represents a translation range on a node as described by the 'ranges' property.
+
+    These attributes are available on Range objects:
+
+    node:
+      The Node instance this range is from
+
+    child_bus_cells:
+      Is the number of cells (4-bytes wide words) describing the child bus address.
+
+    child_bus_addr:
+      Is a physical address within the child bus address space, or None if the
+      child address-cells is equal 0.
+
+    parent_bus_cells:
+      Is the number of cells (4-bytes wide words) describing the parent bus address.
+
+    parent_bus_addr:
+      Is a physical address within the parent bus address space, or None if the
+      parent address-cells is equal 0.
+
+    length_cells:
+      Is the number of cells (4-bytes wide words) describing the size of range in
+      the child address space.
+
+    length:
+      Specifies the size of the range in the child address space, or None if the
+      child size-cells is equal 0.
+    """
+    def __repr__(self):
+        fields = []
+
+        if self.child_bus_cells is not None:
+            fields.append("child-bus-cells: " + hex(self.child_bus_cells))
+        if self.child_bus_addr is not None:
+            fields.append("child-bus-addr: " + hex(self.child_bus_addr))
+        if self.parent_bus_cells is not None:
+            fields.append("parent-bus-cells: " + hex(self.parent_bus_cells))
+        if self.parent_bus_addr is not None:
+            fields.append("parent-bus-addr: " + hex(self.parent_bus_addr))
+        if self.length_cells is not None:
+            fields.append("length-cells " + hex(self.length_cells))
+        if self.length is not None:
+            fields.append("length " + hex(self.length))
+
+        return "<Range, {}>".format(", ".join(fields))
+
+class Register:
+    """
+    Represents a register on a node.
+
+    These attributes are available on Register objects:
+
+    node:
+      The Node instance this register is from
+
+    name:
+      The name of the register as given in the 'reg-names' property, or None if
+      there is no 'reg-names' property
+
+    addr:
+      The starting address of the register, in the parent address space, or None
+      if #address-cells is zero. Any 'ranges' properties are taken into account.
+
+    size:
+      The length of the register in bytes
+    """
+    def __repr__(self):
+        fields = []
+
+        if self.name is not None:
+            fields.append("name: " + self.name)
+        if self.addr is not None:
+            fields.append("addr: " + hex(self.addr))
+        if self.size is not None:
+            fields.append("size: " + hex(self.size))
+
+        return "<Register, {}>".format(", ".join(fields))
+
+
+class ControllerAndData:
+    """
+    Represents an entry in an 'interrupts' or 'type: phandle-array' property
+    value, e.g. <&ctrl-1 4 0> in
+
+        cs-gpios = <&ctrl-1 4 0 &ctrl-2 3 4>;
+
+    These attributes are available on ControllerAndData objects:
+
+    node:
+      The Node instance the property appears on
+
+    controller:
+      The Node instance for the controller (e.g. the controller the interrupt
+      gets sent to for interrupts)
+
+    data:
+      A dictionary that maps names from the *-cells key in the binding for the
+      controller to data values, e.g. {"pin": 4, "flags": 0} for the example
+      above.
+
+      'interrupts = <1 2>' might give {"irq": 1, "level": 2}.
+
+    name:
+      The name of the entry as given in
+      'interrupt-names'/'gpio-names'/'pwm-names'/etc., or None if there is no
+      *-names property
+
+    basename:
+      Basename for the controller when supporting named cells
+    """
+    def __repr__(self):
+        fields = []
+
+        if self.name is not None:
+            fields.append("name: " + self.name)
+
+        fields.append(f"controller: {self.controller}")
+        fields.append(f"data: {self.data}")
+
+        return "<ControllerAndData, {}>".format(", ".join(fields))
+
+
+class PinCtrl:
+    """
+    Represents a pin control configuration for a set of pins on a device,
+    e.g. pinctrl-0 or pinctrl-1.
+
+    These attributes are available on PinCtrl objects:
+
+    node:
+      The Node instance the pinctrl-* property is on
+
+    name:
+      The name of the configuration, as given in pinctrl-names, or None if
+      there is no pinctrl-names property
+
+    name_as_token:
+      Like 'name', but with non-alphanumeric characters converted to underscores.
+
+    conf_nodes:
+      A list of Node instances for the pin configuration nodes, e.g.
+      the nodes pointed at by &state_1 and &state_2 in
+
+          pinctrl-0 = <&state_1 &state_2>;
+    """
+
+    @property
+    def name_as_token(self):
+        "See the class docstring"
+        return _val_as_token(self.name) if self.name is not None else None
+
+    def __repr__(self):
+        fields = []
+
+        if self.name is not None:
+            fields.append("name: " + self.name)
+
+        fields.append("configuration nodes: " + str(self.conf_nodes))
+
+        return "<PinCtrl, {}>".format(", ".join(fields))
+
+
+class Property:
+    """
+    Represents a property on a Node, as set in its DT node and with
+    additional info from the 'properties:' section of the binding.
+
+    Only properties mentioned in 'properties:' get created. Properties of type
+    'compound' currently do not get Property instances, as it's not clear
+    what to generate for them.
+
+    These attributes are available on Property objects. Several are
+    just convenience accessors for attributes on the PropertySpec object
+    accessible via the 'spec' attribute.
+
+    These attributes are available on Property objects:
+
+    node:
+      The Node instance the property is on
+
+    spec:
+      The PropertySpec object which specifies this property.
+
+    name:
+      Convenience for spec.name.
+
+    description:
+      Convenience for spec.name with leading and trailing whitespace
+      (including newlines) removed.
+
+    type:
+      Convenience for spec.type.
+
+    val:
+      The value of the property, with the format determined by spec.type,
+      which comes from the 'type:' string in the binding.
+
+        - For 'type: int/array/string/string-array', 'val' is what you'd expect
+          (a Python integer or string, or a list of them)
+
+        - For 'type: phandle' and 'type: path', 'val' is the pointed-to Node
+          instance
+
+        - For 'type: phandles', 'val' is a list of the pointed-to Node
+          instances
+
+        - For 'type: phandle-array', 'val' is a list of ControllerAndData
+          instances. See the documentation for that class.
+
+    val_as_token:
+      The value of the property as a token, i.e. with non-alphanumeric
+      characters replaced with underscores. This is only safe to access
+      if self.enum_tokenizable returns True.
+
+    enum_index:
+      The index of 'val' in 'spec.enum' (which comes from the 'enum:' list
+      in the binding), or None if spec.enum is None.
+    """
+
+    def __init__(self, spec, val, node):
+        self.val = val
+        self.spec = spec
+        self.node = node
+
+    @property
+    def name(self):
+        "See the class docstring"
+        return self.spec.name
+
+    @property
+    def description(self):
+        "See the class docstring"
+        return self.spec.description.strip()
+
+    @property
+    def type(self):
+        "See the class docstring"
+        return self.spec.type
+
+    @property
+    def val_as_token(self):
+        "See the class docstring"
+        return _val_as_token(self.val)
+
+    @property
+    def enum_index(self):
+        "See the class docstring"
+        enum = self.spec.enum
+        return enum.index(self.val) if enum else None
+
+    def __repr__(self):
+        fields = ["name: " + self.name,
+                  # repr() to deal with lists
+                  "type: " + self.type,
+                  "value: " + repr(self.val)]
+
+        if self.enum_index is not None:
+            fields.append(f"enum index: {self.enum_index}")
+
+        return "<Property, {}>".format(", ".join(fields))
+
+
+class Binding:
+    """
+    Represents a parsed binding.
+
+    These attributes are available on Binding objects:
+
+    path:
+      The absolute path to the file defining the binding.
+
+    description:
+      The free-form description of the binding.
+
+    compatible:
+      The compatible string the binding matches.
+
+      This may be None. For example, it's None when the Binding is inferred
+      from node properties. It can also be None for Binding objects created
+      using 'child-binding:' with no compatible.
+
+    prop2specs:
+      A collections.OrderedDict mapping property names to PropertySpec objects
+      describing those properties' values.
+
+    specifier2cells:
+      A collections.OrderedDict that maps specifier space names (like "gpio",
+      "clock", "pwm", etc.) to lists of cell names.
+
+      For example, if the binding YAML contains 'pin' and 'flags' cell names
+      for the 'gpio' specifier space, like this:
+
+          gpio-cells:
+          - pin
+          - flags
+
+      Then the Binding object will have a 'specifier2cells' attribute mapping
+      "gpio" to ["pin", "flags"]. A missing key should be interpreted as zero
+      cells.
+
+    raw:
+      The binding as an object parsed from YAML.
+
+    bus:
+      If nodes with this binding's 'compatible' describe a bus, a string
+      describing the bus type (like "i2c"). None otherwise.
+
+    on_bus:
+      If nodes with this binding's 'compatible' appear on a bus, a string
+      describing the bus type (like "i2c"). None otherwise.
+
+    child_binding:
+      If this binding describes the properties of child nodes, then
+      this is a Binding object for those children; it is None otherwise.
+      A Binding object's 'child_binding.child_binding' is not None if there
+      are multiple levels of 'child-binding' descriptions in the binding.
+    """
+
+    def __init__(self, path, fname2path, raw=None,
+                 require_compatible=True, require_description=True):
+        """
+        Binding constructor.
+
+        path:
+          Path to binding YAML file. May be None.
+
+        fname2path:
+          Map from include files to their absolute paths. Must
+          not be None, but may be empty.
+
+        raw:
+          Optional raw content in the binding.
+          This does not have to have any "include:" lines resolved.
+          May be left out, in which case 'path' is opened and read.
+          This can be used to resolve child bindings, for example.
+
+        require_compatible:
+          If True, it is an error if the binding does not contain a
+          "compatible:" line. If False, a missing "compatible:" is
+          not an error. Either way, "compatible:" must be a string
+          if it is present in the binding.
+
+        require_description:
+          If True, it is an error if the binding does not contain a
+          "description:" line. If False, a missing "description:" is
+          not an error. Either way, "description:" must be a string
+          if it is present in the binding.
+        """
+        self.path = path
+        self._fname2path = fname2path
+
+        if raw is None:
+            with open(path, encoding="utf-8") as f:
+                raw = yaml.load(f, Loader=_BindingLoader)
+
+        # Merge any included files into self.raw. This also pulls in
+        # inherited child binding definitions, so it has to be done
+        # before initializing those.
+        self.raw = self._merge_includes(raw, self.path)
+
+        # Recursively initialize any child bindings. These don't
+        # require a 'compatible' or 'description' to be well defined,
+        # but they must be dicts.
+        if "child-binding" in raw:
+            if not isinstance(raw["child-binding"], dict):
+                _err(f"malformed 'child-binding:' in {self.path}, "
+                     "expected a binding (dictionary with keys/values)")
+            self.child_binding = Binding(path, fname2path,
+                                         raw=raw["child-binding"],
+                                         require_compatible=False,
+                                         require_description=False)
+        else:
+            self.child_binding = None
+
+        # Make sure this is a well defined object.
+        self._check(require_compatible, require_description)
+
+        # Initialize look up tables.
+        self.prop2specs = OrderedDict()
+        for prop_name in self.raw.get("properties", {}).keys():
+            self.prop2specs[prop_name] = PropertySpec(prop_name, self)
+        self.specifier2cells = OrderedDict()
+        for key, val in self.raw.items():
+            if key.endswith("-cells"):
+                self.specifier2cells[key[:-len("-cells")]] = val
+
+    def __repr__(self):
+        if self.compatible:
+            compat = f" for compatible '{self.compatible}'"
+        else:
+            compat = ""
+        return f"<Binding {os.path.basename(self.path)}" + compat + ">"
+
+    @property
+    def description(self):
+        "See the class docstring"
+        return self.raw['description']
+
+    @property
+    def compatible(self):
+        "See the class docstring"
+        return self.raw.get('compatible')
+
+    @property
+    def bus(self):
+        "See the class docstring"
+        return self.raw.get('bus')
+
+    @property
+    def on_bus(self):
+        "See the class docstring"
+        return self.raw.get('on-bus')
+
+    def _merge_includes(self, raw, binding_path):
+        # Constructor helper. Merges included files in
+        # 'raw["include"]' into 'raw' using 'self._include_paths' as a
+        # source of include files, removing the "include" key while
+        # doing so.
+        #
+        # This treats 'binding_path' as the binding file being built up
+        # and uses it for error messages.
+
+        if "include" not in raw:
+            return raw
+
+        include = raw.pop("include")
+
+        # First, merge the included files together. If more than one included
+        # file has a 'required:' for a particular property, OR the values
+        # together, so that 'required: true' wins.
+
+        merged = {}
+
+        if isinstance(include, str):
+            # Simple scalar string case
+            _merge_props(merged, self._load_raw(include), None, binding_path,
+                         False)
+        elif isinstance(include, list):
+            # List of strings and maps. These types may be intermixed.
+            for elem in include:
+                if isinstance(elem, str):
+                    _merge_props(merged, self._load_raw(elem), None,
+                                 binding_path, False)
+                elif isinstance(elem, dict):
+                    name = elem.pop('name', None)
+                    allowlist = elem.pop('property-allowlist', None)
+                    blocklist = elem.pop('property-blocklist', None)
+                    child_filter = elem.pop('child-binding', None)
+
+                    if elem:
+                        # We've popped out all the valid keys.
+                        _err(f"'include:' in {binding_path} should not have "
+                             f"these unexpected contents: {elem}")
+
+                    _check_include_dict(name, allowlist, blocklist,
+                                        child_filter, binding_path)
+
+                    contents = self._load_raw(name)
+
+                    _filter_properties(contents, allowlist, blocklist,
+                                       child_filter, binding_path)
+                    _merge_props(merged, contents, None, binding_path, False)
+                else:
+                    _err(f"all elements in 'include:' in {binding_path} "
+                         "should be either strings or maps with a 'name' key "
+                         "and optional 'property-allowlist' or "
+                         f"'property-blocklist' keys, but got: {elem}")
+        else:
+            # Invalid item.
+            _err(f"'include:' in {binding_path} "
+                 f"should be a string or list, but has type {type(include)}")
+
+        # Next, merge the merged included files into 'raw'. Error out if
+        # 'raw' has 'required: false' while the merged included files have
+        # 'required: true'.
+
+        _merge_props(raw, merged, None, binding_path, check_required=True)
+
+        return raw
+
+    def _load_raw(self, fname):
+        # Returns the contents of the binding given by 'fname' after merging
+        # any bindings it lists in 'include:' into it. 'fname' is just the
+        # basename of the file, so we check that there aren't multiple
+        # candidates.
+
+        path = self._fname2path.get(fname)
+
+        if not path:
+            _err(f"'{fname}' not found")
+
+        with open(path, encoding="utf-8") as f:
+            contents = yaml.load(f, Loader=_BindingLoader)
+
+        return self._merge_includes(contents, path)
+
+    def _check(self, require_compatible, require_description):
+        # Does sanity checking on the binding.
+
+        raw = self.raw
+
+        if "compatible" in raw:
+            compatible = raw["compatible"]
+            if not isinstance(compatible, str):
+                _err(f"malformed 'compatible: {compatible}' "
+                     f"field in {self.path} - "
+                     f"should be a string, not {type(compatible).__name__}")
+        elif require_compatible:
+            _err(f"missing 'compatible' in {self.path}")
+
+        if "description" in raw:
+            description = raw["description"]
+            if not isinstance(description, str) or not description:
+                _err(f"malformed or empty 'description' in {self.path}")
+        elif require_description:
+            _err(f"missing 'description' in {self.path}")
+
+        # Allowed top-level keys. The 'include' key should have been
+        # removed by _load_raw() already.
+        ok_top = {"description", "compatible", "bus", "on-bus",
+                  "properties", "child-binding"}
+
+        # Descriptive errors for legacy bindings.
+        legacy_errors = {
+            "#cells": "expected *-cells syntax",
+            "child": "use 'bus: <bus>' instead",
+            "child-bus": "use 'bus: <bus>' instead",
+            "parent": "use 'on-bus: <bus>' instead",
+            "parent-bus": "use 'on-bus: <bus>' instead",
+            "sub-node": "use 'child-binding' instead",
+            "title": "use 'description' instead",
+        }
+
+        for key in raw:
+            if key in legacy_errors:
+                _err(f"legacy '{key}:' in {self.path}, {legacy_errors[key]}")
+
+            if key not in ok_top and not key.endswith("-cells"):
+                _err(f"unknown key '{key}' in {self.path}, "
+                     "expected one of {', '.join(ok_top)}, or *-cells")
+
+        for bus_key in "bus", "on-bus":
+            if bus_key in raw and \
+               not isinstance(raw[bus_key], str):
+                _err(f"malformed '{bus_key}:' value in {self.path}, "
+                     "expected string")
+
+        self._check_properties()
+
+        for key, val in raw.items():
+            if key.endswith("-cells"):
+                if not isinstance(val, list) or \
+                   not all(isinstance(elem, str) for elem in val):
+                    _err(f"malformed '{key}:' in {self.path}, "
+                         "expected a list of strings")
+
+    def _check_properties(self):
+        # _check() helper for checking the contents of 'properties:'.
+
+        raw = self.raw
+
+        if "properties" not in raw:
+            return
+
+        ok_prop_keys = {"description", "type", "required",
+                        "enum", "const", "default", "deprecated",
+                        "specifier-space"}
+
+        for prop_name, options in raw["properties"].items():
+            for key in options:
+                if key not in ok_prop_keys:
+                    _err(f"unknown setting '{key}' in "
+                         f"'properties: {prop_name}: ...' in {self.path}, "
+                         f"expected one of {', '.join(ok_prop_keys)}")
+
+            _check_prop_type_and_default(
+                prop_name, options, self.path)
+
+            for true_false_opt in ["required", "deprecated"]:
+                if true_false_opt in options:
+                    option = options[true_false_opt]
+                    if not isinstance(option, bool):
+                        _err(f"malformed '{true_false_opt}:' setting '{option}' "
+                             f"for '{prop_name}' in 'properties' in {self.path}, "
+                             "expected true/false")
+
+            if options.get("deprecated") and options.get("required"):
+                _err(f"'{prop_name}' in 'properties' in {self.path} should not "
+                      "have both 'deprecated' and 'required' set")
+
+            if "description" in options and \
+               not isinstance(options["description"], str):
+                _err("missing, malformed, or empty 'description' for "
+                     f"'{prop_name}' in 'properties' in {self.path}")
+
+            if "enum" in options and not isinstance(options["enum"], list):
+                _err(f"enum in {self.path} for property '{prop_name}' "
+                     "is not a list")
+
+            if "const" in options and not isinstance(options["const"],
+                                                     (int, str)):
+                _err(f"const in {self.path} for property '{prop_name}' "
+                     "is not a scalar")
+
+
+def bindings_from_paths(yaml_paths, ignore_errors=False):
+    """
+    Get a list of Binding objects from the yaml files 'yaml_paths'.
+
+    If 'ignore_errors' is True, YAML files that cause an EDTError when
+    loaded are ignored. (No other exception types are silenced.)
+    """
+
+    ret = []
+    fname2path = {os.path.basename(path): path for path in yaml_paths}
+    for path in yaml_paths:
+        try:
+            ret.append(Binding(path, fname2path))
+        except EDTError:
+            if ignore_errors:
+                continue
+            raise
+
+    return ret
+
+class PropertySpec:
+    """
+    Represents a "property specification", i.e. the description of a
+    property provided by a binding file, like its type and description.
+
+    These attributes are available on PropertySpec objects:
+
+    binding:
+      The Binding object which defined this property.
+
+    name:
+      The property's name.
+
+    path:
+      The file where this property was defined. In case a binding includes
+      other bindings, this is the file where the property was last modified.
+
+    type:
+      The type of the property as a string, as given in the binding.
+
+    description:
+      The free-form description of the property as a string, or None.
+
+    enum:
+      A list of values the property may take as given in the binding, or None.
+
+    enum_tokenizable:
+      True if enum is not None and all the values in it are tokenizable;
+      False otherwise.
+
+      A property must have string type and an "enum:" in its binding to be
+      tokenizable. Additionally, the "enum:" values must be unique after
+      converting all non-alphanumeric characters to underscores (so "foo bar"
+      and "foo_bar" in the same "enum:" would not be tokenizable).
+
+    enum_upper_tokenizable:
+      Like 'enum_tokenizable', with the additional restriction that the
+      "enum:" values must be unique after uppercasing and converting
+      non-alphanumeric characters to underscores.
+
+    const:
+      The property's constant value as given in the binding, or None.
+
+    default:
+      The property's default value as given in the binding, or None.
+
+    deprecated:
+      True if the property is deprecated; False otherwise.
+
+    required:
+      True if the property is marked required; False otherwise.
+
+    specifier_space:
+      The specifier space for the property as given in the binding, or None.
+    """
+
+    def __init__(self, name, binding):
+        self.binding = binding
+        self.name = name
+        self._raw = self.binding.raw["properties"][name]
+
+    def __repr__(self):
+        return f"<PropertySpec {self.name} type '{self.type}'>"
+
+    @property
+    def path(self):
+        "See the class docstring"
+        return self.binding.path
+
+    @property
+    def type(self):
+        "See the class docstring"
+        return self._raw["type"]
+
+    @property
+    def description(self):
+        "See the class docstring"
+        return self._raw.get("description")
+
+    @property
+    def enum(self):
+        "See the class docstring"
+        return self._raw.get("enum")
+
+    @property
+    def enum_tokenizable(self):
+        "See the class docstring"
+        if not hasattr(self, '_enum_tokenizable'):
+            if self.type != 'string' or self.enum is None:
+                self._enum_tokenizable = False
+            else:
+                # Saving _as_tokens here lets us reuse it in
+                # enum_upper_tokenizable.
+                self._as_tokens = [re.sub(_NOT_ALPHANUM_OR_UNDERSCORE,
+                                          '_', value)
+                                   for value in self.enum]
+                self._enum_tokenizable = (len(self._as_tokens) ==
+                                          len(set(self._as_tokens)))
+
+        return self._enum_tokenizable
+
+    @property
+    def enum_upper_tokenizable(self):
+        "See the class docstring"
+        if not hasattr(self, '_enum_upper_tokenizable'):
+            if not self.enum_tokenizable:
+                self._enum_upper_tokenizable = False
+            else:
+                self._enum_upper_tokenizable = \
+                    (len(self._as_tokens) ==
+                     len(set(x.upper() for x in self._as_tokens)))
+        return self._enum_upper_tokenizable
+
+    @property
+    def const(self):
+        "See the class docstring"
+        return self._raw.get("const")
+
+    @property
+    def default(self):
+        "See the class docstring"
+        return self._raw.get("default")
+
+    @property
+    def required(self):
+        "See the class docstring"
+        return self._raw.get("required", False)
+
+    @property
+    def deprecated(self):
+        "See the class docstring"
+        return self._raw.get("deprecated", False)
+
+    @property
+    def specifier_space(self):
+        "See the class docstring"
+        return self._raw.get("specifier-space")
+
+
+class EDTError(Exception):
+    "Exception raised for devicetree- and binding-related errors"
+
+#
+# Public global functions
+#
+
+
+def load_vendor_prefixes_txt(vendor_prefixes):
+    """Load a vendor-prefixes.txt file and return a dict
+    representation mapping a vendor prefix to the vendor name.
+    """
+    vnd2vendor = {}
+    with open(vendor_prefixes, 'r', encoding='utf-8') as f:
+        for line in f:
+            line = line.strip()
+
+            if not line or line.startswith('#'):
+                # Comment or empty line.
+                continue
+
+            # Other lines should be in this form:
+            #
+            # <vnd><TAB><vendor>
+            vnd_vendor = line.split('\t', 1)
+            assert len(vnd_vendor) == 2, line
+            vnd2vendor[vnd_vendor[0]] = vnd_vendor[1]
+    return vnd2vendor
+
+#
+# Private global functions
+#
+
+
+def _dt_compats(dt):
+    # Returns a set() with all 'compatible' strings in the devicetree
+    # represented by dt (a dtlib.DT instance)
+
+    return {compat
+            for node in dt.node_iter()
+                if "compatible" in node.props
+                    for compat in node.props["compatible"].to_strings()}
+
+
+def _binding_paths(bindings_dirs):
+    # Returns a list with the paths to all bindings (.yaml files) in
+    # 'bindings_dirs'
+
+    binding_paths = []
+
+    for bindings_dir in bindings_dirs:
+        for root, _, filenames in os.walk(bindings_dir):
+            for filename in filenames:
+                if filename.endswith(".yaml") or filename.endswith(".yml"):
+                    binding_paths.append(os.path.join(root, filename))
+
+    return binding_paths
+
+
+def _binding_inc_error(msg):
+    # Helper for reporting errors in the !include implementation
+
+    raise yaml.constructor.ConstructorError(None, None, "error: " + msg)
+
+
+def _check_include_dict(name, allowlist, blocklist, child_filter,
+                        binding_path):
+    # Check that an 'include:' named 'name' with property-allowlist
+    # 'allowlist', property-blocklist 'blocklist', and
+    # child-binding filter 'child_filter' has valid structure.
+
+    if name is None:
+        _err(f"'include:' element in {binding_path} "
+             "should have a 'name' key")
+
+    if allowlist is not None and blocklist is not None:
+        _err(f"'include:' of file '{name}' in {binding_path} "
+             "should not specify both 'property-allowlist:' "
+             "and 'property-blocklist:'")
+
+    while child_filter is not None:
+        child_copy = deepcopy(child_filter)
+        child_allowlist = child_copy.pop('property-allowlist', None)
+        child_blocklist = child_copy.pop('property-blocklist', None)
+        next_child_filter = child_copy.pop('child-binding', None)
+
+        if child_copy:
+            # We've popped out all the valid keys.
+            _err(f"'include:' of file '{name}' in {binding_path} "
+                 "should not have these unexpected contents in a "
+                 f"'child-binding': {child_copy}")
+
+        if child_allowlist is not None and child_blocklist is not None:
+            _err(f"'include:' of file '{name}' in {binding_path} "
+                 "should not specify both 'property-allowlist:' and "
+                 "'property-blocklist:' in a 'child-binding:'")
+
+        child_filter = next_child_filter
+
+
+def _filter_properties(raw, allowlist, blocklist, child_filter,
+                       binding_path):
+    # Destructively modifies 'raw["properties"]' and
+    # 'raw["child-binding"]', if they exist, according to
+    # 'allowlist', 'blocklist', and 'child_filter'.
+
+    props = raw.get('properties')
+    _filter_properties_helper(props, allowlist, blocklist, binding_path)
+
+    child_binding = raw.get('child-binding')
+    while child_filter is not None and child_binding is not None:
+        _filter_properties_helper(child_binding.get('properties'),
+                                  child_filter.get('property-allowlist'),
+                                  child_filter.get('property-blocklist'),
+                                  binding_path)
+        child_filter = child_filter.get('child-binding')
+        child_binding = child_binding.get('child-binding')
+
+
+def _filter_properties_helper(props, allowlist, blocklist, binding_path):
+    if props is None or (allowlist is None and blocklist is None):
+        return
+
+    _check_prop_filter('property-allowlist', allowlist, binding_path)
+    _check_prop_filter('property-blocklist', blocklist, binding_path)
+
+    if allowlist is not None:
+        allowset = set(allowlist)
+        to_del = [prop for prop in props if prop not in allowset]
+    else:
+        blockset = set(blocklist)
+        to_del = [prop for prop in props if prop in blockset]
+
+    for prop in to_del:
+        del props[prop]
+
+
+def _check_prop_filter(name, value, binding_path):
+    # Ensure an include: ... property-allowlist or property-blocklist
+    # is a list.
+
+    if value is None:
+        return
+
+    if not isinstance(value, list):
+        _err(f"'{name}' value {value} in {binding_path} should be a list")
+
+
+def _merge_props(to_dict, from_dict, parent, binding_path, check_required):
+    # Recursively merges 'from_dict' into 'to_dict', to implement 'include:'.
+    #
+    # If 'from_dict' and 'to_dict' contain a 'required:' key for the same
+    # property, then the values are ORed together.
+    #
+    # If 'check_required' is True, then an error is raised if 'from_dict' has
+    # 'required: true' while 'to_dict' has 'required: false'. This prevents
+    # bindings from "downgrading" requirements from bindings they include,
+    # which might help keep bindings well-organized.
+    #
+    # It's an error for most other keys to appear in both 'from_dict' and
+    # 'to_dict'. When it's not an error, the value in 'to_dict' takes
+    # precedence.
+    #
+    # 'parent' is the name of the parent key containing 'to_dict' and
+    # 'from_dict', and 'binding_path' is the path to the top-level binding.
+    # These are used to generate errors for sketchy property overwrites.
+
+    for prop in from_dict:
+        if isinstance(to_dict.get(prop), dict) and \
+           isinstance(from_dict[prop], dict):
+            _merge_props(to_dict[prop], from_dict[prop], prop, binding_path,
+                         check_required)
+        elif prop not in to_dict:
+            to_dict[prop] = from_dict[prop]
+        elif _bad_overwrite(to_dict, from_dict, prop, check_required):
+            _err(f"{binding_path} (in '{parent}'): '{prop}' "
+                 f"from included file overwritten ('{from_dict[prop]}' "
+                 f"replaced with '{to_dict[prop]}')")
+        elif prop == "required":
+            # Need a separate check here, because this code runs before
+            # Binding._check()
+            if not (isinstance(from_dict["required"], bool) and
+                    isinstance(to_dict["required"], bool)):
+                _err(f"malformed 'required:' setting for '{parent}' in "
+                     f"'properties' in {binding_path}, expected true/false")
+
+            # 'required: true' takes precedence
+            to_dict["required"] = to_dict["required"] or from_dict["required"]
+
+
+def _bad_overwrite(to_dict, from_dict, prop, check_required):
+    # _merge_props() helper. Returns True in cases where it's bad that
+    # to_dict[prop] takes precedence over from_dict[prop].
+
+    if to_dict[prop] == from_dict[prop]:
+        return False
+
+    # These are overridden deliberately
+    if prop in {"title", "description", "compatible"}:
+        return False
+
+    if prop == "required":
+        if not check_required:
+            return False
+        return from_dict[prop] and not to_dict[prop]
+
+    return True
+
+
+def _binding_include(loader, node):
+    # Implements !include, for backwards compatibility. '!include [foo, bar]'
+    # just becomes [foo, bar].
+
+    if isinstance(node, yaml.ScalarNode):
+        # !include foo.yaml
+        return [loader.construct_scalar(node)]
+
+    if isinstance(node, yaml.SequenceNode):
+        # !include [foo.yaml, bar.yaml]
+        return loader.construct_sequence(node)
+
+    _binding_inc_error("unrecognised node type in !include statement")
+
+
+def _check_prop_type_and_default(prop_name, options, binding_path):
+    # Binding._check_properties() helper. Checks 'type:', 'default:' and
+    # 'specifier-space:' for the property named 'prop_name'
+
+    prop_type = options.get("type")
+    default = options.get("default")
+
+    if prop_type is None:
+        _err(f"missing 'type:' for '{prop_name}' in 'properties' in "
+             f"{binding_path}")
+
+    ok_types = {"boolean", "int", "array", "uint8-array", "string",
+                "string-array", "phandle", "phandles", "phandle-array",
+                "path", "compound"}
+
+    if prop_type not in ok_types:
+        _err(f"'{prop_name}' in 'properties:' in {binding_path} "
+             f"has unknown type '{prop_type}', expected one of " +
+             ", ".join(ok_types))
+
+    if "specifier-space" in options and prop_type != "phandle-array":
+        _err(f"'specifier-space' in 'properties: {prop_name}' "
+             f"has type '{prop_type}', expected 'phandle-array'")
+
+    if prop_type == "phandle-array":
+        if not prop_name.endswith("s") and not "specifier-space" in options:
+            _err(f"'{prop_name}' in 'properties:' in {binding_path} "
+                 f"has type 'phandle-array' and its name does not end in 's', "
+                 f"but no 'specifier-space' was provided.")
+    # Check default
+
+    if default is None:
+        return
+
+    if prop_type in {"boolean", "compound", "phandle", "phandles",
+                     "phandle-array", "path"}:
+        _err("'default:' can't be combined with "
+             f"'type: {prop_type}' for '{prop_name}' in "
+             f"'properties:' in {binding_path}")
+
+    def ok_default():
+        # Returns True if 'default' is an okay default for the property's type
+
+        if prop_type == "int" and isinstance(default, int) or \
+           prop_type == "string" and isinstance(default, str):
+            return True
+
+        # array, uint8-array, or string-array
+
+        if not isinstance(default, list):
+            return False
+
+        if prop_type == "array" and \
+           all(isinstance(val, int) for val in default):
+            return True
+
+        if prop_type == "uint8-array" and \
+           all(isinstance(val, int) and 0 <= val <= 255 for val in default):
+            return True
+
+        # string-array
+        return all(isinstance(val, str) for val in default)
+
+    if not ok_default():
+        _err(f"'default: {default}' is invalid for '{prop_name}' "
+             f"in 'properties:' in {binding_path}, "
+             f"which has type {prop_type}")
+
+
+def _translate(addr, node):
+    # Recursively translates 'addr' on 'node' to the address space(s) of its
+    # parent(s), by looking at 'ranges' properties. Returns the translated
+    # address.
+    #
+    # node:
+    #   dtlib.Node instance
+
+    if not node.parent or "ranges" not in node.parent.props:
+        # No translation
+        return addr
+
+    if not node.parent.props["ranges"].value:
+        # DT spec.: "If the property is defined with an <empty> value, it
+        # specifies that the parent and child address space is identical, and
+        # no address translation is required."
+        #
+        # Treat this the same as a 'range' that explicitly does a one-to-one
+        # mapping, as opposed to there not being any translation.
+        return _translate(addr, node.parent)
+
+    # Gives the size of each component in a translation 3-tuple in 'ranges'
+    child_address_cells = _address_cells(node)
+    parent_address_cells = _address_cells(node.parent)
+    child_size_cells = _size_cells(node)
+
+    # Number of cells for one translation 3-tuple in 'ranges'
+    entry_cells = child_address_cells + parent_address_cells + child_size_cells
+
+    for raw_range in _slice(node.parent, "ranges", 4*entry_cells,
+                            f"4*(<#address-cells> (= {child_address_cells}) + "
+                            "<#address-cells for parent> "
+                            f"(= {parent_address_cells}) + "
+                            f"<#size-cells> (= {child_size_cells}))"):
+        child_addr = to_num(raw_range[:4*child_address_cells])
+        raw_range = raw_range[4*child_address_cells:]
+
+        parent_addr = to_num(raw_range[:4*parent_address_cells])
+        raw_range = raw_range[4*parent_address_cells:]
+
+        child_len = to_num(raw_range)
+
+        if child_addr <= addr < child_addr + child_len:
+            # 'addr' is within range of a translation in 'ranges'. Recursively
+            # translate it and return the result.
+            return _translate(parent_addr + addr - child_addr, node.parent)
+
+    # 'addr' is not within range of any translation in 'ranges'
+    return addr
+
+
+def _add_names(node, names_ident, objs):
+    # Helper for registering names from <foo>-names properties.
+    #
+    # node:
+    #   edtlib.Node instance
+    #
+    # names-ident:
+    #   The <foo> part of <foo>-names, e.g. "reg" for "reg-names"
+    #
+    # objs:
+    #   list of objects whose .name field should be set
+
+    full_names_ident = names_ident + "-names"
+
+    if full_names_ident in node.props:
+        names = node.props[full_names_ident].to_strings()
+        if len(names) != len(objs):
+            _err(f"{full_names_ident} property in {node.path} "
+                 f"in {node.dt.filename} has {len(names)} strings, "
+                 f"expected {len(objs)} strings")
+
+        for obj, name in zip(objs, names):
+            if obj is None:
+                continue
+            obj.name = name
+    else:
+        for obj in objs:
+            if obj is not None:
+                obj.name = None
+
+
+def _interrupt_parent(node):
+    # Returns the node pointed at by the closest 'interrupt-parent', searching
+    # the parents of 'node'. As of writing, this behavior isn't specified in
+    # the DT spec., but seems to match what some .dts files except.
+
+    while node:
+        if "interrupt-parent" in node.props:
+            return node.props["interrupt-parent"].to_node()
+        node = node.parent
+
+    _err(f"{node!r} has an 'interrupts' property, but neither the node "
+         f"nor any of its parents has an 'interrupt-parent' property")
+
+
+def _interrupts(node):
+    # Returns a list of (<controller>, <data>) tuples, with one tuple per
+    # interrupt generated by 'node'. <controller> is the destination of the
+    # interrupt (possibly after mapping through an 'interrupt-map'), and <data>
+    # the data associated with the interrupt (as a 'bytes' object).
+
+    # Takes precedence over 'interrupts' if both are present
+    if "interrupts-extended" in node.props:
+        prop = node.props["interrupts-extended"]
+        return [_map_interrupt(node, iparent, spec)
+                for iparent, spec in _phandle_val_list(prop, "interrupt")]
+
+    if "interrupts" in node.props:
+        # Treat 'interrupts' as a special case of 'interrupts-extended', with
+        # the same interrupt parent for all interrupts
+
+        iparent = _interrupt_parent(node)
+        interrupt_cells = _interrupt_cells(iparent)
+
+        return [_map_interrupt(node, iparent, raw)
+                for raw in _slice(node, "interrupts", 4*interrupt_cells,
+                                  "4*<#interrupt-cells>")]
+
+    return []
+
+
+def _map_interrupt(child, parent, child_spec):
+    # Translates an interrupt headed from 'child' to 'parent' with data
+    # 'child_spec' through any 'interrupt-map' properties. Returns a
+    # (<controller>, <data>) tuple with the final destination after mapping.
+
+    if "interrupt-controller" in parent.props:
+        return (parent, child_spec)
+
+    def own_address_cells(node):
+        # Used for parents pointed at by 'interrupt-map'. We can't use
+        # _address_cells(), because it's the #address-cells property on 'node'
+        # itself that matters.
+
+        address_cells = node.props.get("#address-cells")
+        if not address_cells:
+            _err(f"missing #address-cells on {node!r} "
+                 "(while handling interrupt-map)")
+        return address_cells.to_num()
+
+    def spec_len_fn(node):
+        # Can't use _address_cells() here, because it's the #address-cells
+        # property on 'node' itself that matters
+        return own_address_cells(node) + _interrupt_cells(node)
+
+    parent, raw_spec = _map(
+        "interrupt", child, parent, _raw_unit_addr(child) + child_spec,
+        spec_len_fn, require_controller=True)
+
+    # Strip the parent unit address part, if any
+    return (parent, raw_spec[4*own_address_cells(parent):])
+
+
+def _map_phandle_array_entry(child, parent, child_spec, basename):
+    # Returns a (<controller>, <data>) tuple with the final destination after
+    # mapping through any '<basename>-map' (e.g. gpio-map) properties. See
+    # _map_interrupt().
+
+    def spec_len_fn(node):
+        prop_name = f"#{basename}-cells"
+        if prop_name not in node.props:
+            _err(f"expected '{prop_name}' property on {node!r} "
+                 f"(referenced by {child!r})")
+        return node.props[prop_name].to_num()
+
+    # Do not require <prefix>-controller for anything but interrupts for now
+    return _map(basename, child, parent, child_spec, spec_len_fn,
+                require_controller=False)
+
+
+def _map(prefix, child, parent, child_spec, spec_len_fn, require_controller):
+    # Common code for mapping through <prefix>-map properties, e.g.
+    # interrupt-map and gpio-map.
+    #
+    # prefix:
+    #   The prefix, e.g. "interrupt" or "gpio"
+    #
+    # child:
+    #   The "sender", e.g. the node with 'interrupts = <...>'
+    #
+    # parent:
+    #   The "receiver", e.g. a node with 'interrupt-map = <...>' or
+    #   'interrupt-controller' (no mapping)
+    #
+    # child_spec:
+    #   The data associated with the interrupt/GPIO/etc., as a 'bytes' object,
+    #   e.g. <1 2> for 'foo-gpios = <&gpio1 1 2>'.
+    #
+    # spec_len_fn:
+    #   Function called on a parent specified in a *-map property to get the
+    #   length of the parent specifier (data after phandle in *-map), in cells
+    #
+    # require_controller:
+    #   If True, the final controller node after mapping is required to have
+    #   to have a <prefix>-controller property.
+
+    map_prop = parent.props.get(prefix + "-map")
+    if not map_prop:
+        if require_controller and prefix + "-controller" not in parent.props:
+            _err(f"expected '{prefix}-controller' property on {parent!r} "
+                 f"(referenced by {child!r})")
+
+        # No mapping
+        return (parent, child_spec)
+
+    masked_child_spec = _mask(prefix, child, parent, child_spec)
+
+    raw = map_prop.value
+    while raw:
+        if len(raw) < len(child_spec):
+            _err(f"bad value for {map_prop!r}, missing/truncated child data")
+        child_spec_entry = raw[:len(child_spec)]
+        raw = raw[len(child_spec):]
+
+        if len(raw) < 4:
+            _err(f"bad value for {map_prop!r}, missing/truncated phandle")
+        phandle = to_num(raw[:4])
+        raw = raw[4:]
+
+        # Parent specified in *-map
+        map_parent = parent.dt.phandle2node.get(phandle)
+        if not map_parent:
+            _err(f"bad phandle ({phandle}) in {map_prop!r}")
+
+        map_parent_spec_len = 4*spec_len_fn(map_parent)
+        if len(raw) < map_parent_spec_len:
+            _err(f"bad value for {map_prop!r}, missing/truncated parent data")
+        parent_spec = raw[:map_parent_spec_len]
+        raw = raw[map_parent_spec_len:]
+
+        # Got one *-map row. Check if it matches the child data.
+        if child_spec_entry == masked_child_spec:
+            # Handle *-map-pass-thru
+            parent_spec = _pass_thru(
+                prefix, child, parent, child_spec, parent_spec)
+
+            # Found match. Recursively map and return it.
+            return _map(prefix, parent, map_parent, parent_spec, spec_len_fn,
+                        require_controller)
+
+    _err(f"child specifier for {child!r} ({child_spec}) "
+         f"does not appear in {map_prop!r}")
+
+
+def _mask(prefix, child, parent, child_spec):
+    # Common code for handling <prefix>-mask properties, e.g. interrupt-mask.
+    # See _map() for the parameters.
+
+    mask_prop = parent.props.get(prefix + "-map-mask")
+    if not mask_prop:
+        # No mask
+        return child_spec
+
+    mask = mask_prop.value
+    if len(mask) != len(child_spec):
+        _err(f"{child!r}: expected '{prefix}-mask' in {parent!r} "
+             f"to be {len(child_spec)} bytes, is {len(mask)} bytes")
+
+    return _and(child_spec, mask)
+
+
+def _pass_thru(prefix, child, parent, child_spec, parent_spec):
+    # Common code for handling <prefix>-map-thru properties, e.g.
+    # interrupt-pass-thru.
+    #
+    # parent_spec:
+    #   The parent data from the matched entry in the <prefix>-map property
+    #
+    # See _map() for the other parameters.
+
+    pass_thru_prop = parent.props.get(prefix + "-map-pass-thru")
+    if not pass_thru_prop:
+        # No pass-thru
+        return parent_spec
+
+    pass_thru = pass_thru_prop.value
+    if len(pass_thru) != len(child_spec):
+        _err(f"{child!r}: expected '{prefix}-map-pass-thru' in {parent!r} "
+             f"to be {len(child_spec)} bytes, is {len(pass_thru)} bytes")
+
+    res = _or(_and(child_spec, pass_thru),
+              _and(parent_spec, _not(pass_thru)))
+
+    # Truncate to length of parent spec.
+    return res[-len(parent_spec):]
+
+
+def _raw_unit_addr(node):
+    # _map_interrupt() helper. Returns the unit address (derived from 'reg' and
+    # #address-cells) as a raw 'bytes'
+
+    if 'reg' not in node.props:
+        _err(f"{node!r} lacks 'reg' property "
+             "(needed for 'interrupt-map' unit address lookup)")
+
+    addr_len = 4*_address_cells(node)
+
+    if len(node.props['reg'].value) < addr_len:
+        _err(f"{node!r} has too short 'reg' property "
+             "(while doing 'interrupt-map' unit address lookup)")
+
+    return node.props['reg'].value[:addr_len]
+
+
+def _and(b1, b2):
+    # Returns the bitwise AND of the two 'bytes' objects b1 and b2. Pads
+    # with ones on the left if the lengths are not equal.
+
+    # Pad on the left, to equal length
+    maxlen = max(len(b1), len(b2))
+    return bytes(x & y for x, y in zip(b1.rjust(maxlen, b'\xff'),
+                                       b2.rjust(maxlen, b'\xff')))
+
+
+def _or(b1, b2):
+    # Returns the bitwise OR of the two 'bytes' objects b1 and b2. Pads with
+    # zeros on the left if the lengths are not equal.
+
+    # Pad on the left, to equal length
+    maxlen = max(len(b1), len(b2))
+    return bytes(x | y for x, y in zip(b1.rjust(maxlen, b'\x00'),
+                                       b2.rjust(maxlen, b'\x00')))
+
+
+def _not(b):
+    # Returns the bitwise not of the 'bytes' object 'b'
+
+    # ANDing with 0xFF avoids negative numbers
+    return bytes(~x & 0xFF for x in b)
+
+
+def _phandle_val_list(prop, n_cells_name):
+    # Parses a '<phandle> <value> <phandle> <value> ...' value. The number of
+    # cells that make up each <value> is derived from the node pointed at by
+    # the preceding <phandle>.
+    #
+    # prop:
+    #   dtlib.Property with value to parse
+    #
+    # n_cells_name:
+    #   The <name> part of the #<name>-cells property to look for on the nodes
+    #   the phandles point to, e.g. "gpio" for #gpio-cells.
+    #
+    # Returns a list[Optional[tuple]].
+    #
+    # Each tuple in the list is a (<node>, <value>) pair, where <node>
+    # is the node pointed at by <phandle>. If <phandle> does not refer
+    # to a node, the entire list element is None.
+
+    full_n_cells_name = f"#{n_cells_name}-cells"
+
+    res = []
+
+    raw = prop.value
+    while raw:
+        if len(raw) < 4:
+            # Not enough room for phandle
+            _err("bad value for " + repr(prop))
+        phandle = to_num(raw[:4])
+        raw = raw[4:]
+
+        node = prop.node.dt.phandle2node.get(phandle)
+        if not node:
+            # Unspecified phandle-array element. This is valid; a 0
+            # phandle value followed by no cells is an empty element.
+            res.append(None)
+            continue
+
+        if full_n_cells_name not in node.props:
+            _err(f"{node!r} lacks {full_n_cells_name}")
+
+        n_cells = node.props[full_n_cells_name].to_num()
+        if len(raw) < 4*n_cells:
+            _err("missing data after phandle in " + repr(prop))
+
+        res.append((node, raw[:4*n_cells]))
+        raw = raw[4*n_cells:]
+
+    return res
+
+
+def _address_cells(node):
+    # Returns the #address-cells setting for 'node', giving the number of <u32>
+    # cells used to encode the address in the 'reg' property
+
+    if "#address-cells" in node.parent.props:
+        return node.parent.props["#address-cells"].to_num()
+    return 2  # Default value per DT spec.
+
+
+def _size_cells(node):
+    # Returns the #size-cells setting for 'node', giving the number of <u32>
+    # cells used to encode the size in the 'reg' property
+
+    if "#size-cells" in node.parent.props:
+        return node.parent.props["#size-cells"].to_num()
+    return 1  # Default value per DT spec.
+
+
+def _interrupt_cells(node):
+    # Returns the #interrupt-cells property value on 'node', erroring out if
+    # 'node' has no #interrupt-cells property
+
+    if "#interrupt-cells" not in node.props:
+        _err(f"{node!r} lacks #interrupt-cells")
+    return node.props["#interrupt-cells"].to_num()
+
+
+def _slice(node, prop_name, size, size_hint):
+    # Splits node.props[prop_name].value into 'size'-sized chunks, returning a
+    # list of chunks. Raises EDTError if the length of the property is not
+    # evenly divisible by 'size'. 'size_hint' is a string shown on errors that
+    # gives a hint on how 'size' was calculated.
+
+    raw = node.props[prop_name].value
+    if len(raw) % size:
+        _err(f"'{prop_name}' property in {node!r} has length {len(raw)}, "
+             f"which is not evenly divisible by {size} (= {size_hint}). "
+             "Note that #*-cells properties come either from the parent node or "
+             "from the controller (in the case of 'interrupts').")
+
+    return [raw[i:i + size] for i in range(0, len(raw), size)]
+
+
+def _check_dt(dt):
+    # Does devicetree sanity checks. dtlib is meant to be general and
+    # anything-goes except for very special properties like phandle, but in
+    # edtlib we can be pickier.
+
+    # Check that 'status' has one of the values given in the devicetree spec.
+
+    # Accept "ok" for backwards compatibility
+    ok_status = {"ok", "okay", "disabled", "reserved", "fail", "fail-sss"}
+
+    for node in dt.node_iter():
+        if "status" in node.props:
+            try:
+                status_val = node.props["status"].to_string()
+            except DTError as e:
+                # The error message gives the path
+                _err(str(e))
+
+            if status_val not in ok_status:
+                _err(f"unknown 'status' value \"{status_val}\" in {node.path} "
+                     f"in {node.dt.filename}, expected one of " +
+                     ", ".join(ok_status) +
+                     " (see the devicetree specification)")
+
+        ranges_prop = node.props.get("ranges")
+        if ranges_prop:
+            if ranges_prop.type not in (Type.EMPTY, Type.NUMS):
+                _err(f"expected 'ranges = < ... >;' in {node.path} in "
+                     f"{node.dt.filename}, not '{ranges_prop}' "
+                     "(see the devicetree specification)")
+
+
+def _err(msg):
+    raise EDTError(msg)
+
+# Logging object
+_LOG = logging.getLogger(__name__)
+
+# Regular expression for non-alphanumeric-or-underscore characters.
+_NOT_ALPHANUM_OR_UNDERSCORE = re.compile(r'\W', re.ASCII)
+
+
+def _val_as_token(val):
+    return re.sub(_NOT_ALPHANUM_OR_UNDERSCORE, '_', val)
+
+
+# Custom PyYAML binding loader class to avoid modifying yaml.Loader directly,
+# which could interfere with YAML loading in clients
+class _BindingLoader(Loader):
+    pass
+
+
+# Add legacy '!include foo.yaml' handling
+_BindingLoader.add_constructor("!include", _binding_include)
+
+# Use OrderedDict instead of plain dict for YAML mappings, to preserve
+# insertion order on Python 3.5 and earlier (plain dicts only preserve
+# insertion order on Python 3.6+). This makes testing easier and avoids
+# surprises.
+#
+# Adapted from
+# https://stackoverflow.com/questions/5121931/in-python-how-can-you-load-yaml-mappings-as-ordereddicts.
+# Hopefully this API stays stable.
+_BindingLoader.add_constructor(
+    yaml.resolver.BaseResolver.DEFAULT_MAPPING_TAG,
+    lambda loader, node: OrderedDict(loader.construct_pairs(node)))
+
+#
+# "Default" binding for properties which are defined by the spec.
+#
+# Zephyr: do not change the _DEFAULT_PROP_TYPES keys without
+# updating the documentation for the DT_PROP() macro in
+# include/devicetree.h.
+#
+
+_DEFAULT_PROP_TYPES = {
+    "compatible": "string-array",
+    "status": "string",
+    "reg": "array",
+    "reg-names": "string-array",
+    "label": "string",
+    "interrupts": "array",
+    "interrupts-extended": "compound",
+    "interrupt-names": "string-array",
+    "interrupt-controller": "boolean",
+}
+
+_STATUS_ENUM = "ok okay disabled reserved fail fail-sss".split()
+
+def _raw_default_property_for(name):
+    ret = {
+        'type': _DEFAULT_PROP_TYPES[name],
+        'required': False,
+    }
+    if name == 'status':
+        ret['enum'] = _STATUS_ENUM
+    return ret
+
+_DEFAULT_PROP_BINDING = Binding(
+    None, {},
+    raw={
+        'properties': {
+            name: _raw_default_property_for(name)
+            for name in _DEFAULT_PROP_TYPES
+        },
+    },
+    require_compatible=False, require_description=False,
+)
+
+_DEFAULT_PROP_SPECS = {
+    name: PropertySpec(name, _DEFAULT_PROP_BINDING)
+    for name in _DEFAULT_PROP_TYPES
+}
+
+# A set of vendor prefixes which are grandfathered in by Linux,
+# and therefore by us as well.
+_VENDOR_PREFIX_ALLOWED = set([
+    "at25", "bm", "devbus", "dmacap", "dsa",
+    "exynos", "fsia", "fsib", "gpio-fan", "gpio-key", "gpio", "gpmc",
+    "hdmi", "i2c-gpio", "keypad", "m25p", "max8952", "max8997",
+    "max8998", "mpmc", "pinctrl-single", "#pinctrl-single", "PowerPC",
+    "pl022", "pxa-mmc", "rcar_sound", "rotary-encoder", "s5m8767",
+    "sdhci", "simple-audio-card", "st-plgpio", "st-spics", "ts",
+])
diff --git a/Tools/dts/python-devicetree/src/devicetree/grutils.py b/Tools/dts/python-devicetree/src/devicetree/grutils.py
new file mode 100644
index 0000000000..c3ce825b20
--- /dev/null
+++ b/Tools/dts/python-devicetree/src/devicetree/grutils.py
@@ -0,0 +1,161 @@
+# Copyright 2009-2013, 2019 Peter A. Bigot
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# This implementation is derived from the one in
+# [PyXB](https://github.com/pabigot/pyxb), stripped down and modified
+# specifically to manage edtlib Node instances.
+
+import collections
+
+class Graph:
+    """
+    Represent a directed graph with edtlib Node objects as nodes.
+
+    This is used to determine order dependencies among nodes in a
+    devicetree.  An edge from C{source} to C{target} indicates that
+    some aspect of C{source} requires that some aspect of C{target}
+    already be available.
+    """
+
+    def __init__(self, root=None):
+        self.__roots = None
+        if root is not None:
+            self.__roots = {root}
+        self.__edge_map = collections.defaultdict(set)
+        self.__reverse_map = collections.defaultdict(set)
+        self.__nodes = set()
+
+    def add_edge(self, source, target):
+        """
+        Add a directed edge from the C{source} to the C{target}.
+
+        The nodes are added to the graph if necessary.
+        """
+        self.__edge_map[source].add(target)
+        if source != target:
+            self.__reverse_map[target].add(source)
+        self.__nodes.add(source)
+        self.__nodes.add(target)
+
+    def roots(self):
+        """
+        Return the set of nodes calculated to be roots (i.e., those
+        that have no incoming edges).
+
+        This caches the roots calculated in a previous invocation.
+
+        @rtype: C{set}
+        """
+        if not self.__roots:
+            self.__roots = set()
+            for n in self.__nodes:
+                if n not in self.__reverse_map:
+                    self.__roots.add(n)
+        return self.__roots
+
+    def _tarjan(self):
+        # Execute Tarjan's algorithm on the graph.
+        #
+        # Tarjan's algorithm
+        # (http://en.wikipedia.org/wiki/Tarjan%27s_strongly_connected_components_algorithm)
+        # computes the strongly-connected components
+        # (http://en.wikipedia.org/wiki/Strongly_connected_component)
+        # of the graph: i.e., the sets of nodes that form a minimal
+        # closed set under edge transition.  In essence, the loops.
+        # We use this to detect groups of components that have a
+        # dependency cycle, and to impose a total order on components
+        # based on dependencies.
+
+        self.__stack = []
+        self.__scc_order = []
+        self.__index = 0
+        self.__tarjan_index = {}
+        self.__tarjan_low_link = {}
+        for v in self.__nodes:
+            self.__tarjan_index[v] = None
+        roots = sorted(self.roots(), key=node_key)
+        if self.__nodes and not roots:
+            raise Exception('TARJAN: No roots found in graph with {} nodes'.format(len(self.__nodes)))
+
+        for r in roots:
+            self._tarjan_root(r)
+
+        # Assign ordinals for edtlib
+        ordinal = 0
+        for scc in self.__scc_order:
+            # Zephyr customization: devicetree Node graphs should have
+            # no loops, so all SCCs should be singletons.  That may
+            # change in the future, but for now we only give an
+            # ordinal to singletons.
+            if len(scc) == 1:
+                scc[0].dep_ordinal = ordinal
+                ordinal += 1
+
+    def _tarjan_root(self, v):
+        # Do the work of Tarjan's algorithm for a given root node.
+
+        if self.__tarjan_index.get(v) is not None:
+            # "Root" was already reached.
+            return
+        self.__tarjan_index[v] = self.__tarjan_low_link[v] = self.__index
+        self.__index += 1
+        self.__stack.append(v)
+        source = v
+        for target in sorted(self.__edge_map[source], key=node_key):
+            if self.__tarjan_index[target] is None:
+                self._tarjan_root(target)
+                self.__tarjan_low_link[v] = min(self.__tarjan_low_link[v], self.__tarjan_low_link[target])
+            elif target in self.__stack:
+                self.__tarjan_low_link[v] = min(self.__tarjan_low_link[v], self.__tarjan_low_link[target])
+
+        if self.__tarjan_low_link[v] == self.__tarjan_index[v]:
+            scc = []
+            while True:
+                scc.append(self.__stack.pop())
+                if v == scc[-1]:
+                    break
+            self.__scc_order.append(scc)
+
+    def scc_order(self):
+        """Return the strongly-connected components in order.
+
+        The data structure is a list, in dependency order, of strongly
+        connected components (which can be single nodes).  Appearance
+        of a node in a set earlier in the list indicates that it has
+        no dependencies on any node that appears in a subsequent set.
+        This order is preferred over a depth-first-search order for
+        code generation, since it detects loops.
+        """
+        if not self.__scc_order:
+            self._tarjan()
+        return self.__scc_order
+    __scc_order = None
+
+    def depends_on(self, node):
+        """Get the nodes that 'node' directly depends on."""
+        return sorted(self.__edge_map[node], key=node_key)
+
+    def required_by(self, node):
+        """Get the nodes that directly depend on 'node'."""
+        return sorted(self.__reverse_map[node], key=node_key)
+
+def node_key(node):
+    # This sort key ensures that sibling nodes with the same name will
+    # use unit addresses as tiebreakers. That in turn ensures ordinals
+    # for otherwise indistinguishable siblings are in increasing order
+    # by unit address, which is convenient for displaying output.
+
+    if node.parent:
+        parent_path = node.parent.path
+    else:
+        parent_path = '/'
+
+    if node.unit_addr is not None:
+        name = node.name.rsplit('@', 1)[0]
+        unit_addr = node.unit_addr
+    else:
+        name = node.name
+        unit_addr = -1
+
+    return (parent_path, name, unit_addr)
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-2/multidir.yaml b/Tools/dts/python-devicetree/tests/test-bindings-2/multidir.yaml
new file mode 100644
index 0000000000..19721b2ae2
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-2/multidir.yaml
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Binding in test-bindings-2/
+
+compatible: "in-dir-2"
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/README.rst b/Tools/dts/python-devicetree/tests/test-bindings-include/README.rst
new file mode 100644
index 0000000000..c8ab889bcb
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/README.rst
@@ -0,0 +1 @@
+This directory contains bindings used to test the 'include:' feature.
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/allow-and-blocklist-child.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/allow-and-blocklist-child.yaml
new file mode 100644
index 0000000000..17711202b4
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/allow-and-blocklist-child.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  An include must not give both an allowlist and a blocklist in a
+  child binding. This binding should cause an error.
+compatible: allow-and-blocklist-child
+include:
+  - name: include.yaml
+    child-binding:
+      property-blocklist: [x]
+      property-allowlist: [y]
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/allow-and-blocklist.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/allow-and-blocklist.yaml
new file mode 100644
index 0000000000..80af46561f
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/allow-and-blocklist.yaml
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  An include must not give both an allowlist and a blocklist.
+  This binding should cause an error.
+compatible: allow-and-blocklist
+include:
+  - name: include.yaml
+    property-blocklist: [x]
+    property-allowlist: [y]
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/allow-not-list.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/allow-not-list.yaml
new file mode 100644
index 0000000000..4ec3d87fb5
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/allow-not-list.yaml
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  A property-allowlist, if given, must be a list. This binding should
+  cause an error.
+compatible: allow-not-list
+include:
+  - name: include.yaml
+    property-allowlist:
+      foo:
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/allowlist.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/allowlist.yaml
new file mode 100644
index 0000000000..4cd2c52494
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/allowlist.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Valid property-allowlist.
+compatible: allowlist
+include:
+  - name: include.yaml
+    property-allowlist: [x]
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/block-not-list.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/block-not-list.yaml
new file mode 100644
index 0000000000..bf58da5a77
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/block-not-list.yaml
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  A property-blocklist, if given, must be a list. This binding should
+  cause an error.
+compatible: block-not-list
+include:
+  - name: include.yaml
+    property-blocklist:
+      foo:
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/blocklist.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/blocklist.yaml
new file mode 100644
index 0000000000..a56db024bd
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/blocklist.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Valid property-blocklist.
+compatible: blocklist
+include:
+  - name: include.yaml
+    property-blocklist: [x]
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/empty-allowlist.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/empty-allowlist.yaml
new file mode 100644
index 0000000000..c217d068bb
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/empty-allowlist.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: An empty property-allowlist is valid.
+compatible: empty-allowlist
+include:
+  - name: include.yaml
+    property-allowlist: []
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/empty-blocklist.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/empty-blocklist.yaml
new file mode 100644
index 0000000000..76bed12f50
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/empty-blocklist.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: An empty property-blocklist is valid.
+compatible: empty-blocklist
+include:
+  - name: include.yaml
+    property-blocklist: []
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/filter-child-bindings.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/filter-child-bindings.yaml
new file mode 100644
index 0000000000..1547e3687e
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/filter-child-bindings.yaml
@@ -0,0 +1,11 @@
+description: Test binding for filtering 'child-binding' properties
+
+include:
+  - name: include.yaml
+    property-allowlist: [x]
+    child-binding:
+      property-blocklist: [child-prop-1]
+      child-binding:
+        property-allowlist: [grandchild-prop-1]
+
+compatible: filter-child-bindings
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/include-2.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/include-2.yaml
new file mode 100644
index 0000000000..6fe5822467
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/include-2.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Second file for testing "intermixed" includes.
+compatible: include-2
+properties:
+  a:
+    type: int
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/include-invalid-keys.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/include-invalid-keys.yaml
new file mode 100644
index 0000000000..1b75430360
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/include-invalid-keys.yaml
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  Invalid include element: invalid keys are present.
+compatible: include-invalid-keys
+include:
+  - name: include.yaml
+    property-allowlist: [x]
+    bad-key-1: 3
+    bad-key-2: 3
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/include-invalid-type.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/include-invalid-type.yaml
new file mode 100644
index 0000000000..a11085dc24
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/include-invalid-type.yaml
@@ -0,0 +1,5 @@
+description: |
+  Invalid include: wrong top level type.
+compatible: include-invalid-type
+include:
+  a-map-is-not-allowed-here: 3
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/include-no-list.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/include-no-list.yaml
new file mode 100644
index 0000000000..940e824985
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/include-no-list.yaml
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: A map element with just a name is valid, and has no filters.
+compatible: include-no-list
+include:
+  - name: include.yaml
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/include-no-name.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/include-no-name.yaml
new file mode 100644
index 0000000000..3202879aa4
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/include-no-name.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: |
+  Invalid include element: no name key is present.
+compatible: include-no-name
+include:
+  - property-allowlist: [x]
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/include.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/include.yaml
new file mode 100644
index 0000000000..455992009e
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/include.yaml
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Test file for including other bindings
+compatible: include
+properties:
+  x:
+    type: int
+  y:
+    type: int
+  z:
+    type: int
+child-binding:
+  properties:
+    child-prop-1:
+      type: int
+    child-prop-2:
+      type: int
+
+  child-binding:
+    properties:
+      grandchild-prop-1:
+        type: int
+      grandchild-prop-2:
+        type: int
diff --git a/Tools/dts/python-devicetree/tests/test-bindings-include/intermixed.yaml b/Tools/dts/python-devicetree/tests/test-bindings-include/intermixed.yaml
new file mode 100644
index 0000000000..2837a3ec89
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings-include/intermixed.yaml
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Including intermixed file names and maps is valid.
+compatible: intermixed
+include:
+  - name: include.yaml
+    property-allowlist: [x]
+  - include-2.yaml
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/bar-bus.yaml b/Tools/dts/python-devicetree/tests/test-bindings/bar-bus.yaml
new file mode 100644
index 0000000000..e429e3010d
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/bar-bus.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Bar bus controller
+
+compatible: "bar-bus"
+
+bus: "bar"
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/child-binding-with-compat.yaml b/Tools/dts/python-devicetree/tests/test-bindings/child-binding-with-compat.yaml
new file mode 100644
index 0000000000..1744ad2fe7
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/child-binding-with-compat.yaml
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: child-binding with separate compatible than the parent
+
+compatible: "top-binding-with-compat"
+
+child-binding:
+    compatible: child-compat
+    description: child node
+    properties:
+        child-prop:
+            type: int
+            required: true
+
+    child-binding:
+        description: grandchild node
+        properties:
+            grandchild-prop:
+                type: int
+                required: true
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/child-binding.yaml b/Tools/dts/python-devicetree/tests/test-bindings/child-binding.yaml
new file mode 100644
index 0000000000..5319dea8ac
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/child-binding.yaml
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: child-binding test
+
+compatible: "top-binding"
+
+child-binding:
+    description: child node
+    properties:
+        child-prop:
+            type: int
+            required: true
+
+    child-binding:
+        description: grandchild node
+        properties:
+            grandchild-prop:
+                type: int
+                required: true
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/child.yaml b/Tools/dts/python-devicetree/tests/test-bindings/child.yaml
new file mode 100644
index 0000000000..091c659433
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/child.yaml
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+include: [grandchild-1.yaml, grandchild-2.yaml, grandchild-3.yaml]
+
+properties:
+    bar:
+        required: true
+        type: int
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/defaults.yaml b/Tools/dts/python-devicetree/tests/test-bindings/defaults.yaml
new file mode 100644
index 0000000000..706067c59d
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/defaults.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Property default value test
+
+compatible: "defaults"
+
+properties:
+    int:
+        type: int
+        required: false
+        default: 123
+
+    array:
+        type: array
+        required: false
+        default: [1, 2, 3]
+
+    uint8-array:
+        type: uint8-array
+        required: false
+        default: [0x89, 0xAB, 0xCD]
+
+    string:
+        type: string
+        required: false
+        default: "hello"
+
+    string-array:
+        type: string-array
+        required: false
+        default: ["hello", "there"]
+
+    default-not-used:
+        type: int
+        required: false
+        default: 123
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/deprecated.yaml b/Tools/dts/python-devicetree/tests/test-bindings/deprecated.yaml
new file mode 100644
index 0000000000..d8c72e5c05
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/deprecated.yaml
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Property deprecated value test
+
+compatible: "test-deprecated"
+
+properties:
+    oldprop:
+        type: int
+        deprecated: true
+        required: false
+
+    curprop:
+        type: int
+        required: false
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/device-on-any-bus.yaml b/Tools/dts/python-devicetree/tests/test-bindings/device-on-any-bus.yaml
new file mode 100644
index 0000000000..06c29e4ae0
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/device-on-any-bus.yaml
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device on any bus
+
+compatible: "on-any-bus"
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/device-on-bar-bus.yaml b/Tools/dts/python-devicetree/tests/test-bindings/device-on-bar-bus.yaml
new file mode 100644
index 0000000000..d2c72bb5a9
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/device-on-bar-bus.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device on bar bus
+
+compatible: "on-bus"
+
+on-bus: "bar"
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/device-on-foo-bus.yaml b/Tools/dts/python-devicetree/tests/test-bindings/device-on-foo-bus.yaml
new file mode 100644
index 0000000000..3ed4a75255
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/device-on-foo-bus.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device on foo bus
+
+compatible: "on-bus"
+
+on-bus: "foo"
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/enums.yaml b/Tools/dts/python-devicetree/tests/test-bindings/enums.yaml
new file mode 100644
index 0000000000..f36b89b26e
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/enums.yaml
@@ -0,0 +1,36 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Property enum test
+
+compatible: "enums"
+
+properties:
+  int-enum:
+    type: int
+    enum:
+      - 1
+      - 2
+      - 3
+
+  string-enum:                  # not tokenizable
+    type: string
+    enum:
+      - foo bar
+      - foo_bar
+
+  tokenizable-lower-enum:       # tokenizable in lowercase only
+    type: string
+    enum:
+      - bar
+      - BAR
+
+  tokenizable-enum:             # tokenizable in lower and uppercase
+    type: string
+    enum:
+      - bar
+      - whitespace is ok
+      - 123 is ok
+
+  no-enum:
+    type: string
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/false-positive.yaml b/Tools/dts/python-devicetree/tests/test-bindings/false-positive.yaml
new file mode 100644
index 0000000000..30de8fbb16
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/false-positive.yaml
@@ -0,0 +1,4 @@
+# A file that mentions a 'compatible' string without actually implementing it.
+# Used to check for issues with how we optimize binding loading.
+
+# props
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/foo-bus.yaml b/Tools/dts/python-devicetree/tests/test-bindings/foo-bus.yaml
new file mode 100644
index 0000000000..a3a98d330b
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/foo-bus.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Foo bus controller
+
+compatible: "foo-bus"
+
+bus: "foo"
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/foo-optional.yaml b/Tools/dts/python-devicetree/tests/test-bindings/foo-optional.yaml
new file mode 100644
index 0000000000..5383ade22e
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/foo-optional.yaml
@@ -0,0 +1,4 @@
+properties:
+    foo:
+        type: int
+        required: false
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/foo-required.yaml b/Tools/dts/python-devicetree/tests/test-bindings/foo-required.yaml
new file mode 100644
index 0000000000..1544e1cd40
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/foo-required.yaml
@@ -0,0 +1,4 @@
+properties:
+    foo:
+        type: int
+        required: true
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/gpio-dst.yaml b/Tools/dts/python-devicetree/tests/test-bindings/gpio-dst.yaml
new file mode 100644
index 0000000000..19db316144
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/gpio-dst.yaml
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: GPIO destination for mapping test
+
+compatible: "gpio-dst"
+
+gpio-cells:
+    - val
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/gpio-src.yaml b/Tools/dts/python-devicetree/tests/test-bindings/gpio-src.yaml
new file mode 100644
index 0000000000..b7e5c33571
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/gpio-src.yaml
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: GPIO source for mapping test
+
+compatible: "gpio-src"
+
+properties:
+    foo-gpios:
+        type: phandle-array
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/grandchild-1.yaml b/Tools/dts/python-devicetree/tests/test-bindings/grandchild-1.yaml
new file mode 100644
index 0000000000..249158f523
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/grandchild-1.yaml
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+properties:
+    foo:
+        required: false
+        type: int
+
+    baz:
+        required: true
+        type: int
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/grandchild-2.yaml b/Tools/dts/python-devicetree/tests/test-bindings/grandchild-2.yaml
new file mode 100644
index 0000000000..d7d0b5c373
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/grandchild-2.yaml
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+properties:
+    baz:
+        required: true
+        type: int
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/grandchild-3.yaml b/Tools/dts/python-devicetree/tests/test-bindings/grandchild-3.yaml
new file mode 100644
index 0000000000..c1ba6b8e80
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/grandchild-3.yaml
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+properties:
+    qaz:
+        required: true
+        type: int
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/interrupt-1-cell.yaml b/Tools/dts/python-devicetree/tests/test-bindings/interrupt-1-cell.yaml
new file mode 100644
index 0000000000..ab2db66790
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/interrupt-1-cell.yaml
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Interrupt controller with one cell
+
+compatible: "interrupt-one-cell"
+
+interrupt-cells:
+    - one
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/interrupt-2-cell.yaml b/Tools/dts/python-devicetree/tests/test-bindings/interrupt-2-cell.yaml
new file mode 100644
index 0000000000..2c3144d68f
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/interrupt-2-cell.yaml
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Interrupt controller with two cells
+
+compatible: "interrupt-two-cell"
+
+interrupt-cells:
+    - one
+    - two
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/interrupt-3-cell.yaml b/Tools/dts/python-devicetree/tests/test-bindings/interrupt-3-cell.yaml
new file mode 100644
index 0000000000..846dee07a6
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/interrupt-3-cell.yaml
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Interrupt controller with three cells
+
+compatible: "interrupt-three-cell"
+
+interrupt-cells:
+    - one
+    - two
+    - three
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/multidir.yaml b/Tools/dts/python-devicetree/tests/test-bindings/multidir.yaml
new file mode 100644
index 0000000000..8504475397
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/multidir.yaml
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Binding in test-bindings/
+
+compatible: "in-dir-1"
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/order-1.yaml b/Tools/dts/python-devicetree/tests/test-bindings/order-1.yaml
new file mode 100644
index 0000000000..e6024a8bdb
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/order-1.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Include ordering test
+
+compatible: "order-1"
+
+include: ["foo-required.yaml", "foo-optional.yaml"]
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/order-2.yaml b/Tools/dts/python-devicetree/tests/test-bindings/order-2.yaml
new file mode 100644
index 0000000000..cad1f9b440
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/order-2.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Include ordering test
+
+compatible: "order-2"
+
+include: ["foo-optional.yaml", "foo-required.yaml"]
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/parent.yaml b/Tools/dts/python-devicetree/tests/test-bindings/parent.yaml
new file mode 100644
index 0000000000..8a0e0f4593
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/parent.yaml
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Parent binding
+
+compatible: "binding-include-test"
+
+include: child.yaml
+
+properties:
+    foo:
+        # Changed from not being required in grandchild-1.yaml
+        required: true
+        # Type set in grandchild
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-0.yaml b/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-0.yaml
new file mode 100644
index 0000000000..3b2430c419
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-0.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Controller with zero data values
+
+compatible: "phandle-array-controller-0"
+
+phandle-array-foo-cells: []
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-1.yaml b/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-1.yaml
new file mode 100644
index 0000000000..9d5c6c5cd6
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-1.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Controller with one data value
+
+compatible: "phandle-array-controller-1"
+
+phandle-array-foo-cells:
+    - one
+
+gpio-cells:
+    - gpio-one
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-2.yaml b/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-2.yaml
new file mode 100644
index 0000000000..e7a3cab664
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/phandle-array-controller-2.yaml
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Controller with two data values
+
+compatible: "phandle-array-controller-2"
+
+phandle-array-foo-cells:
+    - one
+    - two
diff --git a/Tools/dts/python-devicetree/tests/test-bindings/props.yaml b/Tools/dts/python-devicetree/tests/test-bindings/props.yaml
new file mode 100644
index 0000000000..40b4cb9bd0
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-bindings/props.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device.props test
+
+compatible: "props"
+
+properties:
+    nonexistent-boolean:
+        type: boolean
+
+    existent-boolean:
+        type: boolean
+
+    int:
+        type: int
+        const: 1
+
+    array:
+        type: array
+
+    uint8-array:
+        type: uint8-array
+
+    string:
+        type: string
+        const: "foo"
+
+    string-array:
+        type: string-array
+
+    phandle-ref:
+        type: phandle
+
+    phandle-refs:
+        type: phandles
+
+    phandle-array-foos:
+        type: phandle-array
+
+    phandle-array-foo-names:
+        type: string-array
+
+    # There's some slight special-casing for GPIOs in that 'foo-gpios = ...'
+    # gets resolved to #gpio-cells rather than #foo-gpio-cells, so test that
+    # too
+    foo-gpios:
+        type: phandle-array
+
+    path:
+        type: path
diff --git a/Tools/dts/python-devicetree/tests/test-multidir.dts b/Tools/dts/python-devicetree/tests/test-multidir.dts
new file mode 100644
index 0000000000..4bd046317d
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-multidir.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// Used by testedtlib.py. Dedicated file for testing having multiple binding
+// directories.
+
+/dts-v1/;
+
+/ {
+	in-dir-1 {
+		compatible = "in-dir-1";
+	};
+	in-dir-2 {
+		compatible = "in-dir-2";
+	};
+};
diff --git a/Tools/dts/python-devicetree/tests/test-wrong-bindings/wrong-phandle-array-name.yaml b/Tools/dts/python-devicetree/tests/test-wrong-bindings/wrong-phandle-array-name.yaml
new file mode 100644
index 0000000000..b66b36c6e8
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-wrong-bindings/wrong-phandle-array-name.yaml
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device.wrong_phandle_array_name test
+
+compatible: "wrong_phandle_array_name"
+
+properties:
+    wrong-phandle-array-name:
+        type: phandle-array
diff --git a/Tools/dts/python-devicetree/tests/test-wrong-bindings/wrong-specifier-space-type.yaml b/Tools/dts/python-devicetree/tests/test-wrong-bindings/wrong-specifier-space-type.yaml
new file mode 100644
index 0000000000..d6aa7ae866
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test-wrong-bindings/wrong-specifier-space-type.yaml
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+description: Device.wrong_specifier_space_type test
+
+compatible: "wrong_specifier_space_type"
+
+properties:
+    wrong-type-for-specifier-space:
+        type: phandle
+        specifier-space: foobar
diff --git a/Tools/dts/python-devicetree/tests/test.dts b/Tools/dts/python-devicetree/tests/test.dts
new file mode 100644
index 0000000000..c8f6b8c20a
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test.dts
@@ -0,0 +1,534 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// Used by testedtlib.py
+
+/dts-v1/;
+
+/ {
+	//
+	// Interrupts
+	//
+
+	interrupt-parent-test {
+		controller {
+			compatible = "interrupt-three-cell";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+		node {
+			interrupts = <1 2 3 4 5 6>;
+			interrupt-names = "foo", "bar";
+			interrupt-parent = <&{/interrupt-parent-test/controller}>;
+		};
+	};
+	interrupts-extended-test {
+		controller-0 {
+			compatible = "interrupt-one-cell";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+		controller-1 {
+			compatible = "interrupt-two-cell";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+		controller-2 {
+			compatible = "interrupt-three-cell";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+		node {
+			interrupts-extended = <
+				&{/interrupts-extended-test/controller-0} 1
+				&{/interrupts-extended-test/controller-1} 2 3
+				&{/interrupts-extended-test/controller-2} 4 5 6>;
+		};
+	};
+	interrupt-map-test {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		controller-0 {
+			compatible = "interrupt-one-cell";
+			#address-cells = <1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+		controller-1 {
+			compatible = "interrupt-two-cell";
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+		controller-2 {
+			compatible = "interrupt-three-cell";
+			#address-cells = <3>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+		nexus {
+			#interrupt-cells = <2>;
+			interrupt-map = <
+				0 0  0 0  &{/interrupt-map-test/controller-0}  0      0
+				0 0  0 1  &{/interrupt-map-test/controller-1}  0 0    0 1
+				0 0  0 2  &{/interrupt-map-test/controller-2}  0 0 0  0 0 2
+				0 1  0 0  &{/interrupt-map-test/controller-0}  0      3
+				0 1  0 1  &{/interrupt-map-test/controller-1}  0 0    0 4
+				0 1  0 2  &{/interrupt-map-test/controller-2}  0 0 0  0 0 5>;
+		};
+		node@0 {
+			reg = <0 0>;
+			interrupts = <0 0 0 1 0 2>;
+			interrupt-parent = <&{/interrupt-map-test/nexus}>;
+		};
+		node@1 {
+			reg = <0 1>;
+			interrupts-extended = <
+			    &{/interrupt-map-test/nexus} 0 0
+			    &{/interrupt-map-test/nexus} 0 1
+			    &{/interrupt-map-test/nexus} 0 2>;
+		};
+	};
+	interrupt-map-bitops-test {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		controller {
+			compatible = "interrupt-two-cell";
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+		nexus {
+			#interrupt-cells = <2>;
+			interrupt-map = <
+			    6 6  6 6  &{/interrupt-map-bitops-test/controller}  2 1
+			>;
+			interrupt-map-mask = <0xE 0x7 0xE 0x7>;
+			// Not specified in the DT spec., but shows up due to
+			// common code with GPIO. Might as well test it here.
+			interrupt-map-pass-thru = <1 2 3 3>;
+		};
+		// Child unit specifier: 00000007 0000000E 00000007 0000000E
+		// Mask:                 0000000E 00000007 0000000E 00000007
+		// Pass-thru:            00000001 00000002 00000003 00000003
+		node@70000000E {
+			reg = <0x7 0xE>;
+			interrupt-parent = <&{/interrupt-map-bitops-test/nexus}>;
+			interrupts = <0x7 0xE>;
+		};
+	};
+
+	//
+	// 'ranges'
+	//
+
+	ranges-zero-cells {
+		#address-cells = <0>;
+
+		node {
+			#address-cells = <0>;
+			#size-cells = <0>;
+
+			ranges;
+		};
+	};
+
+	ranges-zero-parent-cells {
+		#address-cells = <0>;
+
+		node {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ranges = <0xA>,
+				 <0x1A>,
+				 <0x2A>;
+		};
+	};
+
+	ranges-one-address-cells {
+		#address-cells = <0>;
+
+		node {
+			reg = <1>;
+			#address-cells = <1>;
+
+			ranges = <0xA 0xB>,
+				 <0x1A 0x1B>,
+				 <0x2A 0x2B>;
+		};
+	};
+
+	ranges-one-address-two-size-cells {
+		#address-cells = <0>;
+
+		node {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <2>;
+
+			ranges = <0xA 0xB 0xC>,
+				 <0x1A 0x1B 0x1C>,
+				 <0x2A 0x2B 0x2C>;
+		};
+	};
+
+	ranges-two-address-cells {
+		#address-cells = <1>;
+
+		node@1 {
+			reg = <1 2>;
+
+			ranges = <0xA 0xB 0xC 0xD>,
+				 <0x1A 0x1B 0x1C 0x1D>,
+				 <0x2A 0x2B 0x2C 0x2D>;
+		};
+	};
+
+	ranges-two-address-two-size-cells {
+		#address-cells = <1>;
+
+		node@1 {
+			reg = <1 2>;
+			#size-cells = <2>;
+
+			ranges = <0xA 0xB 0xC 0xD 0xE>,
+				 <0x1A 0x1B 0x1C 0x1D 0x1E>,
+				 <0x2A 0x2B 0x2C 0x2D 0x1D>;
+		};
+	};
+
+	ranges-three-address-cells {
+		node@1 {
+			reg = <0 1 2>;
+			#address-cells = <3>;
+
+			ranges = <0xA 0xB 0xC 0xD 0xE 0xF>,
+				 <0x1A 0x1B 0x1C 0x1D 0x1E 0x1F>,
+				 <0x2A 0x2B 0x2C 0x2D 0x2E 0x2F>;
+		};
+	};
+
+	ranges-three-address-two-size-cells {
+		node@1 {
+			reg = <0 1 2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0xA 0xB 0xC 0xD 0xE 0xF 0x10>,
+				 <0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x110>,
+				 <0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x210>;
+		};
+	};
+
+
+	//
+	// 'reg'
+	//
+
+	reg-zero-address-cells {
+		#address-cells = <0>;
+		#size-cells = <1>;
+
+		node {
+			reg = <1 2>;
+		};
+	};
+	reg-zero-size-cells {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		node {
+			reg = <1 2>;
+		};
+	};
+	// Use implied #size-cells = <1>
+	reg-ranges {
+		#address-cells = <2>;
+
+		parent {
+			#address-cells = <1>;
+			ranges = <1  0xA 0xB  1 /* 1    -> 0xA 0xB */
+				  2  0xC 0xD  2 /* 2..3 -> 0xC 0xD */
+				  4  0xE 0xF  1 /* 4    -> 0xE 0xF */
+				 >;
+
+			node {
+				reg = <5 1 /* Matches no range */
+				       4 1 /* Matches third range */
+				       3 1 /* Matches second range */
+				       2 1 /* Matches second range */
+				       1 1 /* Matches first range */
+				       0 1 /* Matches no range */
+				       >;
+			};
+		};
+	};
+	// Build up <3 2 1> address with nested 'ranges'
+	reg-nested-ranges {
+		#address-cells = <3>;
+
+		grandparent {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0  3 0 0  2 2>;
+
+			parent {
+				#address-cells = <1>;
+				ranges = <0  2 0  2>;
+
+				node {
+					reg = <1 1>;
+				};
+			};
+		};
+	};
+
+	//
+	// 'pinctrl-<index>'
+	//
+
+	pinctrl {
+		dev {
+			pinctrl-0 = <>;
+			pinctrl-1 = <&{/pinctrl/pincontroller/state-1}>;
+			pinctrl-2 = <&{/pinctrl/pincontroller/state-1}
+				     &{/pinctrl/pincontroller/state-2}>;
+			pinctrl-names = "zero", "one", "two";
+		};
+		pincontroller {
+			state-1 {
+			};
+			state-2 {
+			};
+		};
+	};
+
+	//
+	// For testing Node.parent and Node.children
+	//
+
+	parent {
+		child-1 {
+		};
+		child-2 {
+			grandchild {
+			};
+		};
+	};
+
+	//
+	// For testing 'include:'
+	//
+
+	binding-include {
+		compatible = "binding-include-test";
+		foo = <0>;
+		bar = <1>;
+		baz = <2>;
+		qaz = <3>;
+	};
+
+	//
+	// For testing Node.props (derived from 'properties:' in the binding)
+	//
+
+	props {
+		compatible = "props";
+		existent-boolean;
+		int = <1>;
+		array = <1 2 3>;
+		uint8-array = [ 12 34 ];
+		string = "foo";
+		string-array = "foo", "bar", "baz";
+		phandle-ref = < &{/ctrl-1} >;
+		phandle-refs = < &{/ctrl-1} &{/ctrl-2} >;
+		phandle-array-foos = < &{/ctrl-1} 1 &{/ctrl-2} 2 3 >;
+		foo-gpios = < &{/ctrl-1} 1 >;
+		path = &{/ctrl-1};
+	};
+
+	ctrl-1 {
+		compatible = "phandle-array-controller-1";
+		#phandle-array-foo-cells = <1>;
+		#gpio-cells = <1>;
+	};
+
+	ctrl-2 {
+		compatible = "phandle-array-controller-2";
+		#phandle-array-foo-cells = <2>;
+	};
+
+	props-2 {
+		compatible = "props";
+		phandle-array-foos = < &{/ctrl-0-1} 0 &{/ctrl-0-2} >;
+		phandle-array-foo-names = "a", "missing", "b";
+	};
+
+	ctrl-0-1 {
+		compatible = "phandle-array-controller-0";
+		#phandle-array-foo-cells = <0>;
+	};
+
+	ctrl-0-2 {
+		compatible = "phandle-array-controller-0";
+		#phandle-array-foo-cells = <0>;
+	};
+
+	//
+	// Test <prefix>-map, via gpio-map
+	//
+
+	gpio-map {
+		source {
+			compatible = "gpio-src";
+			foo-gpios = <&{/gpio-map/connector} 3 4
+				     &{/gpio-map/connector} 1 2>;
+		};
+		connector {
+			#gpio-cells = <2>;
+			// Use different data lengths for source and
+			// destination to make it a bit trickier
+			gpio-map = <1 2 &{/gpio-map/destination} 5
+				    3 4 &{/gpio-map/destination} 6>;
+		};
+		destination {
+			compatible = "gpio-dst";
+			gpio-controller;
+			#gpio-cells = <1>;
+		};
+	};
+
+	//
+	// For testing Node.props with 'default:' values in binding
+	//
+
+	defaults {
+		compatible = "defaults";
+		// Should override the 'default:' in the binding
+		default-not-used = <234>;
+	};
+
+	//
+	// For testing 'enum:'
+	//
+
+	enums {
+		compatible = "enums";
+		int-enum = <1>;
+		string-enum = "foo_bar";
+		tokenizable-enum = "123 is ok";
+		tokenizable-lower-enum = "bar";
+		no-enum = "baz";
+	};
+
+	//
+	// For testing 'bus:' and 'on-bus:'
+	//
+
+	buses {
+		// The 'node' nodes below will map to different bindings since
+		// they appear on different buses
+		foo-bus {
+			compatible = "foo-bus";
+			node1 {
+				compatible = "on-bus", "on-any-bus";
+				nested {
+					compatible = "on-bus";
+				};
+			};
+			node2 {
+				compatible = "on-any-bus", "on-bus";
+			};
+		};
+		bar-bus {
+			compatible = "bar-bus";
+			node {
+				compatible = "on-bus";
+			};
+		};
+		no-bus-node {
+			compatible = "on-any-bus";
+		};
+	};
+
+	//
+	// Node with 'child-binding:' in binding (along with a recursive
+	// 'child-binding:')
+	//
+
+	child-binding {
+		compatible = "top-binding";
+		child-1 {
+			child-prop = <1>;
+			grandchild {
+				grandchild-prop = <2>;
+			};
+		};
+		child-2 {
+			child-prop = <3>;
+		};
+	};
+
+	//
+	// zephyr,user binding inference
+	//
+
+	zephyr,user {
+		boolean;
+		bytes = [81 82 83];
+		number = <23>;
+		numbers = <1>, <2>, <3>;
+		string = "text";
+		strings = "a", "b", "c";
+		handle = <&{/ctrl-1}>;
+		phandles = <&{/ctrl-1}>, <&{/ctrl-2}>;
+		phandle-array-foos = <&{/ctrl-2} 1 2>;
+	};
+
+	//
+	// For testing that neither 'include: [foo.yaml, bar.yaml]' nor
+	// 'include: [bar.yaml, foo.yaml]' causes errors when one of the files
+	// has 'required: true' and the other 'required: false'
+	//
+
+	include-order {
+		node-1 {
+			compatible = "order-1";
+			foo = <1>;
+		};
+		node-2 {
+			compatible = "order-2";
+			foo = <2>;
+		};
+	};
+
+	//
+	// For testing deprecated property
+	//
+	test-deprecated {
+		compatible = "test-deprecated";
+		oldprop = <4>;	/* deprecated property */
+		curprop = <5>;
+	};
+
+
+	//
+	// For testing deprecated features
+	//
+
+	deprecated {
+		compatible = "deprecated";
+		required = <1>;
+		required-2 = <2>;
+		#foo-cells = <2>;
+		sub-node {
+			foos = <&{/deprecated} 1 2>;
+		};
+	};
+};
diff --git a/Tools/dts/python-devicetree/tests/test_dtlib.py b/Tools/dts/python-devicetree/tests/test_dtlib.py
new file mode 100644
index 0000000000..60717bb8aa
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test_dtlib.py
@@ -0,0 +1,2272 @@
+# Copyright (c) 2019, Nordic Semiconductor
+# SPDX-License-Identifier: BSD-3-Clause
+
+import contextlib
+import os
+import re
+import tempfile
+
+import pytest
+
+from devicetree import dtlib
+
+# Test suite for dtlib.py.
+#
+# Run it using pytest (https://docs.pytest.org/en/stable/usage.html):
+#
+#   $ pytest tests/test_dtlib.py
+#
+# Extra options you can pass to pytest for debugging:
+#
+#   - to stop on the first failure with shorter traceback output,
+#     use '-x --tb=native'
+#   - to drop into a debugger on failure, use '--pdb'
+#   - to run a particular test function or functions, use
+#     '-k test_function_pattern_goes_here'
+
+def parse(dts, include_path=(), **kwargs):
+    '''Parse a DTS string 'dts', using the given include path.
+
+    Any kwargs are passed on to DT().'''
+
+    fd, path = tempfile.mkstemp(prefix='pytest-', suffix='.dts')
+    try:
+        os.write(fd, dts.encode('utf-8'))
+        return dtlib.DT(path, include_path, **kwargs)
+    finally:
+        os.close(fd)
+        os.unlink(path)
+
+def verify_parse(dts, expected, include_path=()):
+    '''Like parse(), but also verifies that the parsed DT object's string
+    representation is expected[1:-1].
+
+    The [1:] is so that the first line can be put on a separate line
+    after triple quotes, as is done below.'''
+
+    dt = parse(dts[1:], include_path)
+
+    actual = str(dt)
+    expected = expected[1:-1]
+    assert actual == expected, f'unexpected round-trip on {dts}'
+
+    return dt
+
+def verify_error(dts, expected_msg):
+    '''Verify that parsing 'dts' results in a DTError with the
+    given error message 'msg'. The message must match exactly.'''
+
+    with pytest.raises(dtlib.DTError) as e:
+        parse(dts[1:])
+    actual_msg = str(e.value)
+    assert actual_msg == expected_msg, f'wrong error from {dts}'
+
+def verify_error_endswith(dts, expected_msg):
+    '''
+    Like verify_error(), but checks the message ends with
+    'expected_msg' instead of checking for strict equality.
+    '''
+
+    with pytest.raises(dtlib.DTError) as e:
+        parse(dts[1:])
+    actual_msg = str(e.value)
+    assert actual_msg.endswith(expected_msg), f'wrong error from {dts}'
+
+def verify_error_matches(dts, expected_re):
+    '''
+    Like verify_error(), but checks the message fully matches regular
+    expression 'expected_re' instead of checking for strict equality.
+    '''
+
+    with pytest.raises(dtlib.DTError) as e:
+        parse(dts[1:])
+    actual_msg = str(e.value)
+    assert re.fullmatch(expected_re, actual_msg), \
+        f'wrong error from {dts}' \
+        f'actual message:\n{actual_msg!r}\n' \
+        f'does not match:\n{expected_re!r}'
+
+@contextlib.contextmanager
+def temporary_chdir(dirname):
+    '''A context manager that changes directory to 'dirname'.
+
+    The current working directory is unconditionally returned to its
+    present location after the context manager exits.
+    '''
+    here = os.getcwd()
+    try:
+        os.chdir(dirname)
+        yield
+    finally:
+        os.chdir(here)
+
+def test_invalid_nodenames():
+    # Regression test that verifies node names are not matched against
+    # the more permissive set of rules used for property names.
+
+    verify_error_endswith("""
+/dts-v1/;
+/ { node? {}; };
+""",
+                          "/node?: bad character '?' in node name")
+
+def test_cell_parsing():
+    '''Miscellaneous properties containing zero or more cells'''
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	a;
+	b = < >;
+	c = [ ];
+	d = < 10 20 >;
+	e = < 0U 1L 2UL 3LL 4ULL >;
+	f = < 0x10 0x20 >;
+	g = < 010 020 >;
+	h = /bits/ 8 < 0x10 0x20 (-1) >;
+	i = /bits/ 16 < 0x10 0x20 (-1) >;
+	j = /bits/ 32 < 0x10 0x20 (-1) >;
+	k = /bits/ 64 < 0x10 0x20 (-1) >;
+	l = < 'a' 'b' 'c' >;
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	a;
+	b;
+	c;
+	d = < 0xa 0x14 >;
+	e = < 0x0 0x1 0x2 0x3 0x4 >;
+	f = < 0x10 0x20 >;
+	g = < 0x8 0x10 >;
+	h = [ 10 20 FF ];
+	i = /bits/ 16 < 0x10 0x20 0xffff >;
+	j = < 0x10 0x20 0xffffffff >;
+	k = /bits/ 64 < 0x10 0x20 0xffffffffffffffff >;
+	l = < 0x61 0x62 0x63 >;
+};
+""")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a = /bits/ 16 < 0x10000 >;
+};
+""",
+":4 (column 18): parse error: 65536 does not fit in 16 bits")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a = < 0x100000000 >;
+};
+""",
+":4 (column 8): parse error: 4294967296 does not fit in 32 bits")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a = /bits/ 128 < 0 >;
+};
+""",
+":4 (column 13): parse error: expected 8, 16, 32, or 64")
+
+def test_bytes_parsing():
+    '''Properties with byte array values'''
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	a = [ ];
+	b = [ 12 34 ];
+	c = [ 1234 ];
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	a;
+	b = [ 12 34 ];
+	c = [ 12 34 ];
+};
+""")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a = [ 123 ];
+};
+""",
+":4 (column 10): parse error: expected two-digit byte or ']'")
+
+def test_string_parsing():
+    '''Properties with string values'''
+
+    verify_parse(r"""
+/dts-v1/;
+
+/ {
+	a = "";
+	b = "ABC";
+	c = "\\\"\xab\377\a\b\t\n\v\f\r";
+};
+""",
+r"""
+/dts-v1/;
+
+/ {
+	a = "";
+	b = "ABC";
+	c = "\\\"\xab\xff\a\b\t\n\v\f\r";
+};
+""")
+
+    verify_error_endswith(r"""
+/dts-v1/;
+
+/ {
+	a = "\400";
+};
+""",
+":4 (column 6): parse error: octal escape out of range (> 255)")
+
+def test_char_literal_parsing():
+    '''Properties with character literal values'''
+
+    verify_parse(r"""
+/dts-v1/;
+
+/ {
+	a = < '\'' >;
+	b = < '\x12' >;
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	a = < 0x27 >;
+	b = < 0x12 >;
+};
+""")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	// Character literals are not allowed at the top level
+	a = 'x';
+};
+""",
+":5 (column 6): parse error: malformed value")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a = < '' >;
+};
+""",
+":4 (column 7): parse error: character literals must be length 1")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a = < '12' >;
+};
+""",
+":4 (column 7): parse error: character literals must be length 1")
+
+def test_incbin(tmp_path):
+    '''Test /incbin/, an undocumented feature that allows for
+    binary file inclusion.
+
+    https://github.com/dgibson/dtc/commit/e37ec7d5889fa04047daaa7a4ff55150ed7954d4'''
+
+    open(tmp_path / "tmp_bin", "wb").write(b"\00\01\02\03")
+
+    verify_parse(f"""
+/dts-v1/;
+
+/ {{
+	a = /incbin/ ("{tmp_path}/tmp_bin");
+	b = /incbin/ ("{tmp_path}/tmp_bin", 1, 1);
+	c = /incbin/ ("{tmp_path}/tmp_bin", 1, 2);
+}};
+""",
+"""
+/dts-v1/;
+
+/ {
+	a = [ 00 01 02 03 ];
+	b = [ 01 ];
+	c = [ 01 02 ];
+};
+""")
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	a = /incbin/ ("tmp_bin");
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	a = [ 00 01 02 03 ];
+};
+""",
+                 include_path=(tmp_path,))
+
+    verify_error_endswith(r"""
+/dts-v1/;
+
+/ {
+	a = /incbin/ ("missing");
+};
+""",
+":4 (column 25): parse error: 'missing' could not be found")
+
+def test_node_merging():
+    '''
+    Labels and properties specified for the same node in different
+    statements should be merged.
+    '''
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	l1: l2: l1: foo {
+		foo1 = [ 01 ];
+		l4: l5: bar {
+			bar1 = [ 01 ];
+		};
+	};
+};
+
+l3: &l1 {
+	foo2 = [ 02 ];
+	l6: l7: bar {
+		bar2 = [ 02 ];
+	};
+};
+
+&l3 {
+	foo3 = [ 03 ];
+};
+
+&{/foo} {
+	foo4 = [ 04 ];
+};
+
+&{/foo/bar} {
+	bar3 = [ 03 ];
+	l8: baz {};
+};
+
+/ {
+};
+
+/ {
+	top = [ 01 ];
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	top = [ 01 ];
+	l1: l2: l3: foo {
+		foo1 = [ 01 ];
+		foo2 = [ 02 ];
+		foo3 = [ 03 ];
+		foo4 = [ 04 ];
+		l4: l5: l6: l7: bar {
+			bar1 = [ 01 ];
+			bar2 = [ 02 ];
+			bar3 = [ 03 ];
+			l8: baz {
+			};
+		};
+	};
+};
+""")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+};
+
+&missing {
+};
+""",
+":6 (column 1): parse error: undefined node label 'missing'")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+};
+
+&{foo} {
+};
+""",
+":6 (column 1): parse error: node path 'foo' does not start with '/'")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+};
+
+&{/foo} {
+};
+""",
+":6 (column 1): parse error: component 'foo' in path '/foo' does not exist")
+
+def test_property_labels():
+    '''Like nodes, properties can have labels too.'''
+
+    def verify_label2prop(label, expected):
+        actual = dt.label2prop[label].name
+        assert actual == expected, f"label '{label}' mapped to wrong property"
+
+    dt = verify_parse("""
+/dts-v1/;
+
+/ {
+	a;
+	b;
+	l2: c;
+	l4: l5: l5: l4: d = < 0 >;
+};
+
+/ {
+	l1: b;
+	l3: c;
+	l6: d;
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	a;
+	l1: b;
+	l2: l3: c;
+	l4: l5: l6: d = < 0x0 >;
+};
+""")
+
+    verify_label2prop("l1", "b")
+    verify_label2prop("l2", "c")
+    verify_label2prop("l3", "c")
+    verify_label2prop("l4", "d")
+    verify_label2prop("l5", "d")
+    verify_label2prop("l6", "d")
+
+def test_property_offset_labels():
+    '''
+    It's possible to give labels to data at nonnegative byte offsets
+    within a property value.
+    '''
+
+    def verify_label2offset(label, expected_prop, expected_offset):
+        actual_prop, actual_offset = dt.label2prop_offset[label]
+        actual_prop = actual_prop.name
+        assert (actual_prop, actual_offset) == \
+            (expected_prop, expected_offset), \
+            f"label '{label}' maps to wrong offset or property"
+
+    dt = verify_parse("""
+/dts-v1/;
+
+/ {
+	a = l01: l02: < l03: &node l04: l05: 2 l06: >,
+            l07: l08: [ l09: 03 l10: l11: 04 l12: l13: ] l14:, "A";
+
+	b = < 0 > l23: l24:;
+
+	node: node {
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	a = l01: l02: < l03: &node l04: l05: 0x2 l06: l07: l08: >, [ l09: 03 l10: l11: 04 l12: l13: l14: ], "A";
+	b = < 0x0 l23: l24: >;
+	node: node {
+		phandle = < 0x1 >;
+	};
+};
+""")
+
+    verify_label2offset("l01", "a", 0)
+    verify_label2offset("l02", "a", 0)
+    verify_label2offset("l04", "a", 4)
+    verify_label2offset("l05", "a", 4)
+    verify_label2offset("l06", "a", 8)
+    verify_label2offset("l09", "a", 8)
+    verify_label2offset("l10", "a", 9)
+
+    verify_label2offset("l23", "b", 4)
+    verify_label2offset("l24", "b", 4)
+
+def test_unit_addr():
+    '''Node unit addresses must be correctly extracted from their names.'''
+
+    def verify_unit_addr(path, expected):
+        node = dt.get_node(path)
+        assert node.unit_addr == expected, \
+            f"{node!r} has unexpected unit address"
+
+    dt = verify_parse("""
+/dts-v1/;
+
+/ {
+	no-unit-addr {
+	};
+
+	unit-addr@ABC {
+	};
+
+	unit-addr-non-numeric@foo-bar {
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	no-unit-addr {
+	};
+	unit-addr@ABC {
+	};
+	unit-addr-non-numeric@foo-bar {
+	};
+};
+""")
+
+    verify_unit_addr("/no-unit-addr", "")
+    verify_unit_addr("/unit-addr@ABC", "ABC")
+    verify_unit_addr("/unit-addr-non-numeric@foo-bar", "foo-bar")
+
+def test_node_path_references():
+    '''Node phandles may be specified using a reference to the node's path.'''
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	a = &label;
+	b = [ 01 ], &label;
+	c = [ 01 ], &label, <2>;
+	d = &{/abc};
+	label: abc {
+		e = &label;
+		f = &{/abc};
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	a = &label;
+	b = [ 01 ], &label;
+	c = [ 01 ], &label, < 0x2 >;
+	d = &{/abc};
+	label: abc {
+		e = &label;
+		f = &{/abc};
+	};
+};
+""")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	sub {
+		x = &missing;
+	};
+};
+""",
+"/sub: undefined node label 'missing'")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	sub {
+		x = &{/sub/missing};
+	};
+};
+""",
+"/sub: component 'missing' in path '/sub/missing' does not exist")
+
+def test_phandles():
+    '''Various tests related to phandles.'''
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	x = < &a &{/b} &c >;
+
+	dummy1 {
+		phandle = < 1 >;
+	};
+
+	dummy2 {
+		phandle = < 3 >;
+	};
+
+	a: a {
+	};
+
+	b {
+	};
+
+	c: c {
+		phandle = < 0xFF >;
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	x = < &a &{/b} &c >;
+	dummy1 {
+		phandle = < 0x1 >;
+	};
+	dummy2 {
+		phandle = < 0x3 >;
+	};
+	a: a {
+		phandle = < 0x2 >;
+	};
+	b {
+		phandle = < 0x4 >;
+	};
+	c: c {
+		phandle = < 0xff >;
+	};
+};
+""")
+
+    # Check that a node can be assigned a phandle to itself. This just forces a
+    # phandle to be allocated on it. The C tools support this too.
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	dummy {
+		phandle = < 1 >;
+	};
+
+	a {
+                foo: phandle = < &{/a} >;
+	};
+
+	label: b {
+                bar: phandle = < &label >;
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	dummy {
+		phandle = < 0x1 >;
+	};
+	a {
+		foo: phandle = < &{/a} >;
+	};
+	label: b {
+		bar: phandle = < &label >;
+	};
+};
+""")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	sub {
+		x = < &missing >;
+	};
+};
+""",
+"/sub: undefined node label 'missing'")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a: sub {
+		x = /bits/ 16 < &a >;
+	};
+};
+""",
+":5 (column 19): parse error: phandle references are only allowed in arrays with 32-bit elements")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo {
+		phandle = [ 00 ];
+	};
+};
+""",
+"/foo: bad phandle length (1), expected 4 bytes")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo {
+		phandle = < 0 >;
+	};
+};
+""",
+"/foo: bad value 0x00000000 for phandle")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo {
+		phandle = < (-1) >;
+	};
+};
+""",
+"/foo: bad value 0xffffffff for phandle")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo {
+		phandle = < 17 >;
+	};
+
+	bar {
+		phandle = < 17 >;
+	};
+};
+""",
+"/bar: duplicated phandle 0x11 (seen before at /foo)")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo {
+		phandle = < &{/bar} >;
+	};
+
+	bar {
+	};
+};
+""",
+"/foo: phandle refers to another node")
+
+def test_phandle2node():
+    '''Test the phandle2node dict in a dt instance.'''
+
+    def verify_phandle2node(prop, offset, expected_name):
+        phandle = dtlib.to_num(dt.root.props[prop].value[offset:offset + 4])
+        actual_name = dt.phandle2node[phandle].name
+
+        assert actual_name == expected_name, \
+            f"'{prop}' is a phandle for the wrong thing"
+
+    dt = parse("""
+/dts-v1/;
+
+/ {
+	phandle_ = < &{/node1} 0 1 >;
+	phandles = < 0 &{/node2} 1 &{/node3} >;
+
+	node1 {
+		phandle = < 123 >;
+	};
+
+	node2 {
+	};
+
+	node3 {
+	};
+};
+""")
+
+    verify_phandle2node("phandle_", 0, "node1")
+    verify_phandle2node("phandles", 4, "node2")
+    verify_phandle2node("phandles", 12, "node3")
+
+def test_mixed_assign():
+    '''Test mixed value type assignments'''
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	x = /bits/ 8 < 0xFF 0xFF >,
+	    &abc,
+	    < 0xFF &abc 0xFF &abc >,
+	    &abc,
+	    [ FF FF ],
+	    "abc";
+
+	abc: abc {
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	x = [ FF FF ], &abc, < 0xff &abc 0xff &abc >, &abc, [ FF FF ], "abc";
+	abc: abc {
+		phandle = < 0x1 >;
+	};
+};
+""")
+
+def test_deletion():
+    '''Properties and nodes may be deleted from the tree.'''
+
+    # Test property deletion
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	keep = < 1 >;
+	delete = < &sub >, &sub;
+	/delete-property/ missing;
+	/delete-property/ delete;
+	sub: sub {
+		y = < &sub >, &sub;
+	};
+};
+
+&sub {
+	/delete-property/ y;
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	keep = < 0x1 >;
+	sub: sub {
+	};
+};
+""")
+
+    # Test node deletion
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	sub1 {
+		x = < 1 >;
+		sub2 {
+			x = < &sub >, &sub;
+		};
+		/delete-node/ sub2;
+	};
+
+	sub3: sub3 {
+		x = < &sub >, &sub;
+	};
+
+	sub4 {
+		x = < &sub >, &sub;
+	};
+};
+
+/delete-node/ &sub3;
+/delete-node/ &{/sub4};
+""",
+"""
+/dts-v1/;
+
+/ {
+	sub1 {
+		x = < 0x1 >;
+	};
+};
+""")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+};
+
+/delete-node/ &missing;
+""",
+":6 (column 15): parse error: undefined node label 'missing'")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/delete-node/ {
+""",
+":3 (column 15): parse error: expected label (&foo) or path (&{/foo/bar}) reference")
+
+def test_include_curdir(tmp_path):
+    '''Verify that /include/ (which is handled in the lexer) searches the
+    current directory'''
+
+    with temporary_chdir(tmp_path):
+        with open("same-dir-1", "w") as f:
+            f.write("""
+    x = [ 00 ];
+    /include/ "same-dir-2"
+""")
+        with open("same-dir-2", "w") as f:
+            f.write("""
+    y = [ 01 ];
+    /include/ "same-dir-3"
+""")
+        with open("same-dir-3", "w") as f:
+            f.write("""
+    z = [ 02 ];
+""")
+        with open("test.dts", "w") as f:
+            f.write("""
+/dts-v1/;
+
+/ {
+	/include/ "same-dir-1"
+};
+""")
+        dt = dtlib.DT("test.dts")
+        assert str(dt) == """
+/dts-v1/;
+
+/ {
+	x = [ 00 ];
+	y = [ 01 ];
+	z = [ 02 ];
+};
+"""[1:-1]
+
+def test_include_is_lexical(tmp_path):
+    '''/include/ is done in the lexer, which means that property
+    definitions can span multiple included files in different
+    directories.'''
+
+    with open(tmp_path / "tmp2.dts", "w") as f:
+        f.write("""
+/dts-v1/;
+/ {
+""")
+    with open(tmp_path / "tmp3.dts", "w") as f:
+        f.write("""
+    x = <1>;
+""")
+
+    subdir_1 = tmp_path / "subdir-1"
+    subdir_1.mkdir()
+    with open(subdir_1 / "via-include-path-1", "w") as f:
+        f.write("""
+      = /include/ "via-include-path-2"
+""")
+
+    subdir_2 = tmp_path / "subdir-2"
+    subdir_2.mkdir()
+    with open(subdir_2 / "via-include-path-2", "w") as f:
+        f.write("""
+        <2>;
+};
+""")
+
+    with open(tmp_path / "test.dts", "w") as test_dts:
+        test_dts.write("""
+/include/ "tmp2.dts"
+/include/ "tmp3.dts"
+y /include/ "via-include-path-1"
+""")
+
+    with temporary_chdir(tmp_path):
+        dt = dtlib.DT("test.dts", include_path=(subdir_1, subdir_2))
+    expected_dt = """
+/dts-v1/;
+
+/ {
+	x = < 0x1 >;
+	y = < 0x2 >;
+};
+"""[1:-1]
+    assert str(dt) == expected_dt
+
+def test_include_misc(tmp_path):
+    '''Miscellaneous /include/ tests.'''
+
+    # Missing includes should error out.
+
+    verify_error_endswith("""
+/include/ "missing"
+""",
+":1 (column 1): parse error: 'missing' could not be found")
+
+    # Verify that an error in an included file points to the right location
+
+    with temporary_chdir(tmp_path):
+        with open("tmp2.dts", "w") as f:
+            f.write("""\
+
+
+  x
+""")
+        with open("tmp.dts", "w") as f:
+            f.write("""
+
+
+/include/ "tmp2.dts"
+""")
+        with pytest.raises(dtlib.DTError) as e:
+            dtlib.DT("tmp.dts")
+
+        assert str(e.value) == \
+            "tmp2.dts:3 (column 3): parse error: expected '/dts-v1/;' at start of file"
+
+def test_include_recursion(tmp_path):
+    '''Test recursive /include/ detection'''
+
+    with temporary_chdir(tmp_path):
+        with open("tmp2.dts", "w") as f:
+            f.write('/include/ "tmp3.dts"\n')
+        with open("tmp3.dts", "w") as f:
+            f.write('/include/ "tmp.dts"\n')
+
+        with open("tmp.dts", "w") as f:
+            f.write('/include/ "tmp2.dts"\n')
+        with pytest.raises(dtlib.DTError) as e:
+            dtlib.DT("tmp.dts")
+
+        expected_err = """\
+tmp3.dts:1 (column 1): parse error: recursive /include/:
+tmp.dts:1 ->
+tmp2.dts:1 ->
+tmp3.dts:1 ->
+tmp.dts"""
+        assert str(e.value) == expected_err
+
+        with open("tmp.dts", "w") as f:
+            f.write('/include/ "tmp.dts"\n')
+        with pytest.raises(dtlib.DTError) as e:
+            dtlib.DT("tmp.dts")
+        expected_err = """\
+tmp.dts:1 (column 1): parse error: recursive /include/:
+tmp.dts:1 ->
+tmp.dts"""
+        assert str(e.value) == expected_err
+
+def test_omit_if_no_ref():
+    '''The /omit-if-no-ref/ marker is a bit of undocumented
+    dtc magic that removes a node from the tree if it isn't
+    referred to elsewhere.
+
+    https://elinux.org/Device_Tree_Source_Undocumented
+    '''
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	x = < &{/referenced} >, &referenced2;
+
+	/omit-if-no-ref/ referenced {
+	};
+
+	referenced2: referenced2 {
+	};
+
+	/omit-if-no-ref/ unreferenced {
+	};
+
+	l1: /omit-if-no-ref/ unreferenced2 {
+	};
+
+	/omit-if-no-ref/ l2: unreferenced3 {
+	};
+
+	unreferenced4: unreferenced4 {
+	};
+
+	unreferenced5 {
+	};
+};
+
+/omit-if-no-ref/ &referenced2;
+/omit-if-no-ref/ &unreferenced4;
+/omit-if-no-ref/ &{/unreferenced5};
+""",
+"""
+/dts-v1/;
+
+/ {
+	x = < &{/referenced} >, &referenced2;
+	referenced {
+		phandle = < 0x1 >;
+	};
+	referenced2: referenced2 {
+	};
+};
+""")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	/omit-if-no-ref/ x = "";
+};
+""",
+":4 (column 21): parse error: /omit-if-no-ref/ can only be used on nodes")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	/omit-if-no-ref/ x;
+};
+""",
+":4 (column 20): parse error: /omit-if-no-ref/ can only be used on nodes")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	/omit-if-no-ref/ {
+	};
+};
+""",
+":4 (column 19): parse error: expected node or property name")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	/omit-if-no-ref/ = < 0 >;
+};
+""",
+":4 (column 19): parse error: expected node or property name")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+};
+
+/omit-if-no-ref/ &missing;
+""",
+":6 (column 18): parse error: undefined node label 'missing'")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/omit-if-no-ref/ {
+""",
+":3 (column 18): parse error: expected label (&foo) or path (&{/foo/bar}) reference")
+
+def test_expr():
+    '''Property values may contain expressions.'''
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	ter1        = < (0 ? 1 : 0 ? 2 : 3) >;
+	ter2        = < (0 ? 1 : 1 ? 2 : 3) >;
+	ter3        = < (1 ? 1 : 0 ? 2 : 3) >;
+	ter4        = < (1 ? 1 : 1 ? 2 : 3) >;
+	or1         = < (0 || 0) >;
+	or2         = < (0 || 1) >;
+	or3         = < (1 || 0) >;
+	or4         = < (1 || 1) >;
+	and1        = < (0 && 0) >;
+	and2        = < (0 && 1) >;
+	and3        = < (1 && 0) >;
+	and4        = < (1 && 1) >;
+	bitor       = < (1 | 2) >;
+	bitxor      = < (7 ^ 2) >;
+	bitand      = < (3 & 6) >;
+	eq1         = < (1 == 0) >;
+	eq2         = < (1 == 1) >;
+	neq1        = < (1 != 0) >;
+	neq2        = < (1 != 1) >;
+	lt1         = < (1 < 2) >;
+	lt2         = < (2 < 2) >;
+	lt3         = < (3 < 2) >;
+	lteq1       = < (1 <= 2) >;
+	lteq2       = < (2 <= 2) >;
+	lteq3       = < (3 <= 2) >;
+	gt1         = < (1 > 2) >;
+	gt2         = < (2 > 2) >;
+	gt3         = < (3 > 2) >;
+	gteq1       = < (1 >= 2) >;
+	gteq2       = < (2 >= 2) >;
+	gteq3       = < (3 >= 2) >;
+	lshift      = < (2 << 3) >;
+	rshift      = < (16 >> 3) >;
+	add         = < (3 + 4) >;
+	sub         = < (7 - 4) >;
+	mul         = < (3 * 4) >;
+	div         = < (11 / 3) >;
+	mod         = < (11 % 3) >;
+	unary_minus = < (-3) >;
+	bitnot      = < (~1) >;
+	not0        = < (!-1) >;
+	not1        = < (!0) >;
+	not2        = < (!1) >;
+	not3        = < (!2) >;
+	nest        = < (((--3) + (-2)) * (--(-2))) >;
+	char_lits   = < ('a' + 'b') >;
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	ter1 = < 0x3 >;
+	ter2 = < 0x2 >;
+	ter3 = < 0x1 >;
+	ter4 = < 0x1 >;
+	or1 = < 0x0 >;
+	or2 = < 0x1 >;
+	or3 = < 0x1 >;
+	or4 = < 0x1 >;
+	and1 = < 0x0 >;
+	and2 = < 0x0 >;
+	and3 = < 0x0 >;
+	and4 = < 0x1 >;
+	bitor = < 0x3 >;
+	bitxor = < 0x5 >;
+	bitand = < 0x2 >;
+	eq1 = < 0x0 >;
+	eq2 = < 0x1 >;
+	neq1 = < 0x1 >;
+	neq2 = < 0x0 >;
+	lt1 = < 0x1 >;
+	lt2 = < 0x0 >;
+	lt3 = < 0x0 >;
+	lteq1 = < 0x1 >;
+	lteq2 = < 0x1 >;
+	lteq3 = < 0x0 >;
+	gt1 = < 0x0 >;
+	gt2 = < 0x0 >;
+	gt3 = < 0x1 >;
+	gteq1 = < 0x0 >;
+	gteq2 = < 0x1 >;
+	gteq3 = < 0x1 >;
+	lshift = < 0x10 >;
+	rshift = < 0x2 >;
+	add = < 0x7 >;
+	sub = < 0x3 >;
+	mul = < 0xc >;
+	div = < 0x3 >;
+	mod = < 0x2 >;
+	unary_minus = < 0xfffffffd >;
+	bitnot = < 0xfffffffe >;
+	not0 = < 0x0 >;
+	not1 = < 0x1 >;
+	not2 = < 0x0 >;
+	not3 = < 0x0 >;
+	nest = < 0xfffffffe >;
+	char_lits = < 0xc3 >;
+};
+""")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a = < (1/(-1 + 1)) >;
+};
+""",
+":4 (column 18): parse error: division by zero")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	a = < (1%0) >;
+};
+""",
+":4 (column 11): parse error: division by zero")
+
+def test_comment_removal():
+    '''Comments should be removed when round-tripped to a str.'''
+
+    verify_parse("""
+/**//dts-v1//**/;//
+//
+// foo
+/ /**/{// foo
+x/**/=/*
+foo
+*/</**/1/***/>/****/;/**/}/*/**/;
+""",
+"""
+/dts-v1/;
+
+/ {
+	x = < 0x1 >;
+};
+""")
+
+def verify_path_is(path, node_name, dt):
+    '''Verify 'node.name' matches 'node_name' in 'dt'.'''
+
+    try:
+        node = dt.get_node(path)
+        assert node.name == node_name, f'unexpected path {path}'
+    except dtlib.DTError:
+        assert False, f'no node found for path {path}'
+
+def verify_path_error(path, msg, dt):
+    '''Verify that an attempt to get node 'path' from 'dt' raises
+    a DTError whose str is 'msg'.'''
+
+    with pytest.raises(dtlib.DTError) as e:
+        dt.get_node(path)
+    assert str(e.value) == msg, f"'{path}' gives the wrong error"
+
+def test_get_node():
+    '''Test DT.get_node().'''
+
+    dt = parse("""
+/dts-v1/;
+
+/ {
+	foo {
+		bar {
+		};
+	};
+
+	baz {
+	};
+};
+""")
+
+    verify_path_is("/", "/", dt)
+    verify_path_is("//", "/", dt)
+    verify_path_is("///", "/", dt)
+    verify_path_is("/foo", "foo", dt)
+    verify_path_is("//foo", "foo", dt)
+    verify_path_is("///foo", "foo", dt)
+    verify_path_is("/foo/bar", "bar", dt)
+    verify_path_is("//foo//bar", "bar", dt)
+    verify_path_is("///foo///bar", "bar", dt)
+    verify_path_is("/baz", "baz", dt)
+
+    verify_path_error(
+        "",
+        "no alias '' found -- did you forget the leading '/' in the node path?",
+        dt)
+    verify_path_error(
+        "missing",
+        "no alias 'missing' found -- did you forget the leading '/' in the node path?",
+        dt)
+    verify_path_error(
+        "/missing",
+        "component 'missing' in path '/missing' does not exist",
+        dt)
+    verify_path_error(
+        "/foo/missing",
+        "component 'missing' in path '/foo/missing' does not exist",
+        dt)
+
+    def verify_path_exists(path):
+        assert dt.has_node(path), f"path '{path}' does not exist"
+
+    def verify_path_missing(path):
+        assert not dt.has_node(path), f"path '{path}' exists"
+
+    verify_path_exists("/")
+    verify_path_exists("/foo")
+    verify_path_exists("/foo/bar")
+
+    verify_path_missing("/missing")
+    verify_path_missing("/foo/missing")
+
+def test_aliases():
+    '''Test /aliases'''
+
+    dt = parse("""
+/dts-v1/;
+
+/ {
+	aliases {
+		alias1 = &l1;
+		alias2 = &l2;
+		alias3 = &{/sub/node3};
+		alias4 = &{/node4};
+	};
+
+	l1: node1 {
+	};
+
+	l2: node2 {
+	};
+
+	sub {
+		node3 {
+		};
+	};
+
+	node4 {
+		node5 {
+		};
+	};
+};
+""")
+
+    def verify_alias_target(alias, node_name):
+        verify_path_is(alias, node_name, dt)
+        assert alias in dt.alias2node
+        assert dt.alias2node[alias].name == node_name, f"bad result for {alias}"
+
+    verify_alias_target("alias1", "node1")
+    verify_alias_target("alias2", "node2")
+    verify_alias_target("alias3", "node3")
+    verify_path_is("alias4/node5", "node5", dt)
+
+    verify_path_error(
+        "alias4/node5/node6",
+        "component 'node6' in path 'alias4/node5/node6' does not exist",
+        dt)
+
+    verify_error_matches("""
+/dts-v1/;
+
+/ {
+	aliases {
+		a = [ 00 ];
+	};
+};
+""",
+"expected property 'a' on /aliases in .*" +
+re.escape("to be assigned with either 'a = &foo' or 'a = \"/path/to/node\"', not 'a = [ 00 ];'"))
+
+    verify_error_matches(r"""
+/dts-v1/;
+
+/ {
+	aliases {
+		a = "\xFF";
+	};
+};
+""",
+re.escape(r"value of property 'a' (b'\xff\x00') on /aliases in ") +
+".* is not valid UTF-8")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	aliases {
+		A = "/aliases";
+	};
+};
+""",
+"/aliases: alias property name 'A' should include only characters from [0-9a-z-]")
+
+    verify_error_matches(r"""
+/dts-v1/;
+
+/ {
+	aliases {
+		a = "/missing";
+	};
+};
+""",
+"property 'a' on /aliases in .* points to the non-existent node \"/missing\"")
+
+def test_prop_type():
+    '''Test Property.type'''
+
+    def verify_type(prop, expected):
+        actual = dt.root.props[prop].type
+        assert actual == expected, f'{prop} has wrong type'
+
+    dt = parse("""
+/dts-v1/;
+
+/ {
+	empty;
+	bytes1 = [ ];
+	bytes2 = [ 01 ];
+	bytes3 = [ 01 02 ];
+	bytes4 = foo: [ 01 bar: 02 ];
+	bytes5 = /bits/ 8 < 1 2 3 >;
+	num = < 1 >;
+	nums1 = < >;
+	nums2 = < >, < >;
+	nums3 = < 1 2 >;
+	nums4 = < 1 2 >, < 3 >, < 4 >;
+	string = "foo";
+	strings = "foo", "bar";
+	path1 = &node;
+	path2 = &{/node};
+	phandle1 = < &node >;
+	phandle2 = < &{/node} >;
+	phandles1 = < &node &node >;
+	phandles2 = < &node >, < &node >;
+	phandle-and-nums-1 = < &node 1 >;
+	phandle-and-nums-2 = < &node 1 2 &node 3 4 >;
+	phandle-and-nums-3 = < &node 1 2 >, < &node 3 4 >;
+	compound1 = < 1 >, [ 02 ];
+	compound2 = "foo", < >;
+
+	node: node {
+	};
+};
+""")
+
+    verify_type("empty", dtlib.Type.EMPTY)
+    verify_type("bytes1", dtlib.Type.BYTES)
+    verify_type("bytes2", dtlib.Type.BYTES)
+    verify_type("bytes3", dtlib.Type.BYTES)
+    verify_type("bytes4", dtlib.Type.BYTES)
+    verify_type("bytes5", dtlib.Type.BYTES)
+    verify_type("num", dtlib.Type.NUM)
+    verify_type("nums1", dtlib.Type.NUMS)
+    verify_type("nums2", dtlib.Type.NUMS)
+    verify_type("nums3", dtlib.Type.NUMS)
+    verify_type("nums4", dtlib.Type.NUMS)
+    verify_type("string", dtlib.Type.STRING)
+    verify_type("strings", dtlib.Type.STRINGS)
+    verify_type("phandle1", dtlib.Type.PHANDLE)
+    verify_type("phandle2", dtlib.Type.PHANDLE)
+    verify_type("phandles1", dtlib.Type.PHANDLES)
+    verify_type("phandles2", dtlib.Type.PHANDLES)
+    verify_type("phandle-and-nums-1", dtlib.Type.PHANDLES_AND_NUMS)
+    verify_type("phandle-and-nums-2", dtlib.Type.PHANDLES_AND_NUMS)
+    verify_type("phandle-and-nums-3", dtlib.Type.PHANDLES_AND_NUMS)
+    verify_type("path1", dtlib.Type.PATH)
+    verify_type("path2", dtlib.Type.PATH)
+    verify_type("compound1", dtlib.Type.COMPOUND)
+    verify_type("compound2", dtlib.Type.COMPOUND)
+
+def test_prop_type_casting():
+    '''Test Property.to_{num,nums,string,strings,node}()'''
+
+    dt = parse(r"""
+/dts-v1/;
+
+/ {
+	u = < 1 >;
+	s = < 0xFFFFFFFF >;
+	u8 = /bits/ 8 < 1 >;
+	u16 = /bits/ 16 < 1 2 >;
+	u64 = /bits/ 64 < 1 >;
+        bytes = [ 01 02 03 ];
+	empty;
+	zero = < >;
+	two_u = < 1 2 >;
+	two_s = < 0xFFFFFFFF 0xFFFFFFFE >;
+	three_u = < 1 2 3 >;
+	three_u_split = < 1 >, < 2 >, < 3 >;
+	empty_string = "";
+	string = "foo\tbar baz";
+	invalid_string = "\xff";
+	strings = "foo", "bar", "baz";
+	invalid_strings = "foo", "\xff", "bar";
+	ref = <&{/target}>;
+	refs = <&{/target} &{/target2}>;
+	refs2 = <&{/target}>, <&{/target2}>;
+	path = &{/target};
+	manualpath = "/target";
+	missingpath = "/missing";
+
+	target {
+		phandle = < 100 >;
+	};
+
+	target2 {
+	};
+};
+""")
+
+    # Test Property.to_num()
+
+    def verify_to_num(prop, signed, expected):
+        signed_str = "a signed" if signed else "an unsigned"
+        actual = dt.root.props[prop].to_num(signed)
+        assert actual == expected, \
+            f"{prop} has bad {signed_str} numeric value"
+
+    def verify_to_num_error_matches(prop, expected_re):
+        with pytest.raises(dtlib.DTError) as e:
+            dt.root.props[prop].to_num()
+        actual_msg = str(e.value)
+        assert re.fullmatch(expected_re, actual_msg), \
+            f"'{prop}' to_num gives the wrong error: " \
+            f"actual message:\n{actual_msg!r}\n" \
+            f"does not match:\n{expected_re!r}"
+
+    verify_to_num("u", False, 1)
+    verify_to_num("u", True, 1)
+    verify_to_num("s", False, 0xFFFFFFFF)
+    verify_to_num("s", True, -1)
+
+    verify_to_num_error_matches(
+        "two_u",
+        "expected property 'two_u' on / in .* to be assigned with " +
+        re.escape("'two_u = < (number) >;', not 'two_u = < 0x1 0x2 >;'"))
+    verify_to_num_error_matches(
+        "u8",
+        "expected property 'u8' on / in .* to be assigned with " +
+        re.escape("'u8 = < (number) >;', not 'u8 = [ 01 ];'"))
+    verify_to_num_error_matches(
+        "u16",
+        "expected property 'u16' on / in .* to be assigned with " +
+        re.escape("'u16 = < (number) >;', not 'u16 = /bits/ 16 < 0x1 0x2 >;'"))
+    verify_to_num_error_matches(
+        "u64",
+        "expected property 'u64' on / in .* to be assigned with " +
+        re.escape("'u64 = < (number) >;', not 'u64 = /bits/ 64 < 0x1 >;'"))
+    verify_to_num_error_matches(
+        "string",
+        "expected property 'string' on / in .* to be assigned with " +
+        re.escape("'string = < (number) >;', not 'string = \"foo\\tbar baz\";'"))
+
+    # Test Property.to_nums()
+
+    def verify_to_nums(prop, signed, expected):
+        signed_str = "signed" if signed else "unsigned"
+        actual = dt.root.props[prop].to_nums(signed)
+        assert actual == expected, \
+            f"'{prop}' gives the wrong {signed_str} numbers"
+
+    def verify_to_nums_error_matches(prop, expected_re):
+        with pytest.raises(dtlib.DTError) as e:
+            dt.root.props[prop].to_nums()
+        assert re.fullmatch(expected_re, str(e.value)), \
+            f"'{prop}' to_nums gives the wrong error"
+
+    verify_to_nums("zero", False, [])
+    verify_to_nums("u", False, [1])
+    verify_to_nums("two_u", False, [1, 2])
+    verify_to_nums("two_u", True, [1, 2])
+    verify_to_nums("two_s", False, [0xFFFFFFFF, 0xFFFFFFFE])
+    verify_to_nums("two_s", True, [-1, -2])
+    verify_to_nums("three_u", False, [1, 2, 3])
+    verify_to_nums("three_u_split", False, [1, 2, 3])
+
+    verify_to_nums_error_matches(
+        "empty",
+        "expected property 'empty' on / in .* to be assigned with " +
+        re.escape("'empty = < (number) (number) ... >;', not 'empty;'"))
+    verify_to_nums_error_matches(
+        "string",
+        "expected property 'string' on / in .* to be assigned with " +
+        re.escape("'string = < (number) (number) ... >;', ") +
+        re.escape("not 'string = \"foo\\tbar baz\";'"))
+
+    # Test Property.to_bytes()
+
+    def verify_to_bytes(prop, expected):
+        actual = dt.root.props[prop].to_bytes()
+        assert actual == expected, f"'{prop}' gives the wrong bytes"
+
+    def verify_to_bytes_error_matches(prop, expected_re):
+        with pytest.raises(dtlib.DTError) as e:
+            dt.root.props[prop].to_bytes()
+        assert re.fullmatch(expected_re, str(e.value)), \
+            f"'{prop}' gives the wrong error"
+
+    verify_to_bytes("u8", b"\x01")
+    verify_to_bytes("bytes", b"\x01\x02\x03")
+
+    verify_to_bytes_error_matches(
+        "u16",
+        "expected property 'u16' on / in .* to be assigned with " +
+        re.escape("'u16 = [ (byte) (byte) ... ];', ") +
+        re.escape("not 'u16 = /bits/ 16 < 0x1 0x2 >;'"))
+    verify_to_bytes_error_matches(
+        "empty",
+        "expected property 'empty' on / in .* to be assigned with " +
+        re.escape("'empty = [ (byte) (byte) ... ];', not 'empty;'"))
+
+    # Test Property.to_string()
+
+    def verify_to_string(prop, expected):
+        actual = dt.root.props[prop].to_string()
+        assert actual == expected, f"'{prop}' to_string gives the wrong string"
+
+    def verify_to_string_error_matches(prop, expected_re):
+        with pytest.raises(dtlib.DTError) as e:
+            dt.root.props[prop].to_string()
+        assert re.fullmatch(expected_re, str(e.value)), \
+            f"'{prop}' gives the wrong error"
+
+    verify_to_string("empty_string", "")
+    verify_to_string("string", "foo\tbar baz")
+
+    verify_to_string_error_matches(
+        "u",
+        "expected property 'u' on / in .* to be assigned with " +
+        re.escape("'u = \"string\";', not 'u = < 0x1 >;'"))
+    verify_to_string_error_matches(
+        "strings",
+        "expected property 'strings' on / in .* to be assigned with " +
+        re.escape("'strings = \"string\";', ")+
+        re.escape("not 'strings = \"foo\", \"bar\", \"baz\";'"))
+    verify_to_string_error_matches(
+        "invalid_string",
+        re.escape(r"value of property 'invalid_string' (b'\xff\x00') on / ") +
+        "in .* is not valid UTF-8")
+
+    # Test Property.to_strings()
+
+    def verify_to_strings(prop, expected):
+        actual = dt.root.props[prop].to_strings()
+        assert actual == expected, f"'{prop}' to_strings gives the wrong value"
+
+    def verify_to_strings_error_matches(prop, expected_re):
+        with pytest.raises(dtlib.DTError) as e:
+            dt.root.props[prop].to_strings()
+        assert re.fullmatch(expected_re, str(e.value)), \
+            f"'{prop}' gives the wrong error"
+
+    verify_to_strings("empty_string", [""])
+    verify_to_strings("string", ["foo\tbar baz"])
+    verify_to_strings("strings", ["foo", "bar", "baz"])
+
+    verify_to_strings_error_matches(
+        "u",
+        "expected property 'u' on / in .* to be assigned with " +
+        re.escape("'u = \"string\", \"string\", ... ;', not 'u = < 0x1 >;'"))
+    verify_to_strings_error_matches(
+        "invalid_strings",
+        "value of property 'invalid_strings' " +
+        re.escape(r"(b'foo\x00\xff\x00bar\x00') on / in ") +
+        ".* is not valid UTF-8")
+
+    # Test Property.to_node()
+
+    def verify_to_node(prop, path):
+        actual = dt.root.props[prop].to_node().path
+        assert actual == path, f"'{prop}' points at wrong path"
+
+    def verify_to_node_error_matches(prop, expected_re):
+        with pytest.raises(dtlib.DTError) as e:
+            dt.root.props[prop].to_node()
+        assert re.fullmatch(expected_re, str(e.value)), \
+            f"'{prop} gives the wrong error"
+
+    verify_to_node("ref", "/target")
+
+    verify_to_node_error_matches(
+        "u",
+        "expected property 'u' on / in .* to be assigned with " +
+        re.escape("'u = < &foo >;', not 'u = < 0x1 >;'"))
+    verify_to_node_error_matches(
+        "string",
+        "expected property 'string' on / in .* to be assigned with " +
+        re.escape("'string = < &foo >;', not 'string = \"foo\\tbar baz\";'"))
+
+    # Test Property.to_nodes()
+
+    def verify_to_nodes(prop, paths):
+        actual = [node.path for node in dt.root.props[prop].to_nodes()]
+        assert actual == paths, f"'{prop} gives wrong node paths"
+
+    def verify_to_nodes_error_matches(prop, expected_re):
+        with pytest.raises(dtlib.DTError) as e:
+            dt.root.props[prop].to_nodes()
+        assert re.fullmatch(expected_re, str(e.value)), \
+            f"'{prop} gives wrong error"
+
+    verify_to_nodes("zero", [])
+    verify_to_nodes("ref", ["/target"])
+    verify_to_nodes("refs", ["/target", "/target2"])
+    verify_to_nodes("refs2", ["/target", "/target2"])
+
+    verify_to_nodes_error_matches(
+        "u",
+        "expected property 'u' on / in .* to be assigned with " +
+        re.escape("'u = < &foo &bar ... >;', not 'u = < 0x1 >;'"))
+    verify_to_nodes_error_matches(
+        "string",
+        "expected property 'string' on / in .* to be assigned with " +
+        re.escape("'string = < &foo &bar ... >;', ") +
+        re.escape("not 'string = \"foo\\tbar baz\";'"))
+
+    # Test Property.to_path()
+
+    def verify_to_path(prop, path):
+        actual = dt.root.props[prop].to_path().path
+        assert actual == path, f"'{prop} gives the wrong path"
+
+    def verify_to_path_error_matches(prop, expected_re):
+        with pytest.raises(dtlib.DTError) as e:
+            dt.root.props[prop].to_path()
+        assert re.fullmatch(expected_re, str(e.value)), \
+            f"'{prop} gives the wrong error"
+
+    verify_to_path("path", "/target")
+    verify_to_path("manualpath", "/target")
+
+    verify_to_path_error_matches(
+        "u",
+        "expected property 'u' on / in .* to be assigned with either " +
+        re.escape("'u = &foo' or 'u = \"/path/to/node\"', not 'u = < 0x1 >;'"))
+    verify_to_path_error_matches(
+        "missingpath",
+        "property 'missingpath' on / in .* points to the non-existent node "
+        '"/missing"')
+
+    # Test top-level to_num() and to_nums()
+
+    def verify_raw_to_num(fn, prop, length, signed, expected):
+        actual = fn(dt.root.props[prop].value, length, signed)
+        assert actual == expected, \
+            f"{fn.__name__}(<{prop}>, {length}, {signed}) gives wrong value"
+
+    def verify_raw_to_num_error(fn, data, length, msg):
+        with pytest.raises(dtlib.DTError) as e:
+            fn(data, length)
+        assert str(e.value) == msg, \
+            (f"{fn.__name__}() called with data='{data}', length='{length}' "
+             "gives the wrong error")
+
+    verify_raw_to_num(dtlib.to_num, "u", None, False, 1)
+    verify_raw_to_num(dtlib.to_num, "u", 4, False, 1)
+    verify_raw_to_num(dtlib.to_num, "s", None, False, 0xFFFFFFFF)
+    verify_raw_to_num(dtlib.to_num, "s", None, True, -1)
+    verify_raw_to_num(dtlib.to_nums, "empty", 4, False, [])
+    verify_raw_to_num(dtlib.to_nums, "u16", 2, False, [1, 2])
+    verify_raw_to_num(dtlib.to_nums, "two_s", 4, False, [0xFFFFFFFF, 0xFFFFFFFE])
+    verify_raw_to_num(dtlib.to_nums, "two_s", 4, True, [-1, -2])
+
+    verify_raw_to_num_error(dtlib.to_num, 0, 0, "'0' has type 'int', expected 'bytes'")
+    verify_raw_to_num_error(dtlib.to_num, b"", 0, "'length' must be greater than zero, was 0")
+    verify_raw_to_num_error(dtlib.to_num, b"foo", 2, "b'foo' is 3 bytes long, expected 2")
+    verify_raw_to_num_error(dtlib.to_nums, 0, 0, "'0' has type 'int', expected 'bytes'")
+    verify_raw_to_num_error(dtlib.to_nums, b"", 0, "'length' must be greater than zero, was 0")
+    verify_raw_to_num_error(dtlib.to_nums, b"foooo", 2, "b'foooo' is 5 bytes long, expected a length that's a a multiple of 2")
+
+def test_duplicate_labels():
+    '''
+    It is an error to duplicate labels in most conditions, but there
+    are some exceptions where it's OK.
+    '''
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	sub1 {
+		label: foo {
+		};
+	};
+
+	sub2 {
+		label: bar {
+		};
+	};
+};
+""",
+"Label 'label' appears on /sub1/foo and on /sub2/bar")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	sub {
+		label: foo {
+		};
+	};
+};
+/ {
+	sub {
+		label: bar {
+		};
+	};
+};
+""",
+"Label 'label' appears on /sub/bar and on /sub/foo")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo: a = < 0 >;
+	foo: node {
+	};
+};
+""",
+"Label 'foo' appears on /node and on property 'a' of node /")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo: a = < 0 >;
+	node {
+		foo: b = < 0 >;
+	};
+};
+""",
+"Label 'foo' appears on property 'a' of node / and on property 'b' of node /node")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo: a = foo: < 0 >;
+};
+""",
+"Label 'foo' appears in the value of property 'a' of node / and on property 'a' of node /")
+
+    # Giving the same label twice for the same node is fine
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	sub {
+		label: foo {
+		};
+	};
+};
+/ {
+
+	sub {
+		label: foo {
+		};
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	sub {
+		label: foo {
+		};
+	};
+};
+""")
+
+    # Duplicate labels are fine if one of the nodes is deleted
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	label: foo {
+	};
+	label: bar {
+	};
+};
+
+/delete-node/ &{/bar};
+""",
+"""
+/dts-v1/;
+
+/ {
+	label: foo {
+	};
+};
+""")
+
+    #
+    # Test overriding/deleting a property with references
+    #
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	x = &foo, < &foo >;
+	y = &foo, < &foo >;
+	foo: foo {
+	};
+};
+
+/ {
+	x = < 1 >;
+	/delete-property/ y;
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	x = < 0x1 >;
+	foo: foo {
+	};
+};
+""")
+
+    #
+    # Test self-referential node
+    #
+
+    verify_parse("""
+/dts-v1/;
+
+/ {
+	label: foo {
+		x = &{/foo}, &label, < &label >;
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	label: foo {
+		x = &{/foo}, &label, < &label >;
+		phandle = < 0x1 >;
+	};
+};
+""")
+
+    #
+    # Test /memreserve/
+    #
+
+    dt = verify_parse("""
+/dts-v1/;
+
+l1: l2: /memreserve/ (1 + 1) (2 * 2);
+/memreserve/ 0x100 0x200;
+
+/ {
+};
+""",
+"""
+/dts-v1/;
+
+l1: l2: /memreserve/ 0x0000000000000002 0x0000000000000004;
+/memreserve/ 0x0000000000000100 0x0000000000000200;
+
+/ {
+};
+""")
+
+    expected = [(["l1", "l2"], 2, 4), ([], 0x100, 0x200)]
+    assert dt.memreserves == expected
+
+    verify_error_endswith("""
+/dts-v1/;
+
+foo: / {
+};
+""",
+":3 (column 6): parse error: expected /memreserve/ after labels at beginning of file")
+
+def test_reprs():
+    '''Test the __repr__() functions.'''
+
+    dts = """
+/dts-v1/;
+
+/ {
+	x = < 0 >;
+	sub {
+		y = < 1 >;
+	};
+};
+"""
+
+    dt = parse(dts, include_path=("foo", "bar"))
+
+    assert re.fullmatch(r"DT\(filename='.*', include_path=.'foo', 'bar'.\)",
+                        repr(dt))
+    assert re.fullmatch("<Property 'x' at '/' in '.*'>",
+                        repr(dt.root.props["x"]))
+    assert re.fullmatch("<Node /sub in '.*'>",
+                        repr(dt.root.nodes["sub"]))
+
+    dt = parse(dts, include_path=iter(("foo", "bar")))
+
+    assert re.fullmatch(r"DT\(filename='.*', include_path=.'foo', 'bar'.\)",
+                        repr(dt))
+
+def test_names():
+    '''Tests for node/property names.'''
+
+    verify_parse(r"""
+/dts-v1/;
+
+/ {
+	// A leading \ is accepted but ignored in node/propert names
+	\aA0,._+*#?- = &_, &{/aA0,._+@-};
+
+	// Names that overlap with operators and integer literals
+
+	+ = [ 00 ];
+	* = [ 02 ];
+	- = [ 01 ];
+	? = [ 03 ];
+	0 = [ 04 ];
+	0x123 = [ 05 ];
+
+	// Node names are more restrictive than property names.
+	_: \aA0,._+@- {
+	};
+
+	0 {
+	};
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+	aA0,._+*#?- = &_, &{/aA0,._+@-};
+	+ = [ 00 ];
+	* = [ 02 ];
+	- = [ 01 ];
+	? = [ 03 ];
+	0 = [ 04 ];
+	0x123 = [ 05 ];
+	_: aA0,._+@- {
+	};
+	0 {
+	};
+};
+""")
+
+    verify_error_endswith(r"""
+/dts-v1/;
+
+/ {
+	foo@3;
+};
+""",
+":4 (column 7): parse error: '@' is only allowed in node names")
+
+    verify_error_endswith(r"""
+/dts-v1/;
+
+/ {
+	foo@3 = < 0 >;
+};
+""",
+":4 (column 8): parse error: '@' is only allowed in node names")
+
+    verify_error_endswith(r"""
+/dts-v1/;
+
+/ {
+	foo@2@3 {
+	};
+};
+""",
+":4 (column 10): parse error: multiple '@' in node name")
+
+def test_dense_input():
+    '''
+    Test that a densely written DTS input round-trips to something
+    readable.
+    '''
+
+    verify_parse("""
+/dts-v1/;/{l1:l2:foo{l3:l4:bar{l5:x=l6:/bits/8<l7:1 l8:2>l9:,[03],"a";};};};
+""",
+"""
+/dts-v1/;
+
+/ {
+	l1: l2: foo {
+		l3: l4: bar {
+			l5: x = l6: [ l7: 01 l8: 02 l9: ], [ 03 ], "a";
+		};
+	};
+};
+""")
+
+def test_misc():
+    '''Test miscellaneous errors and non-errors.'''
+
+    verify_error_endswith("", ":1 (column 1): parse error: expected '/dts-v1/;' at start of file")
+
+    verify_error_endswith("""
+/dts-v1/;
+""",
+":2 (column 1): parse error: no root node defined")
+
+    verify_error_endswith("""
+/dts-v1/; /plugin/;
+""",
+":1 (column 11): parse error: /plugin/ is not supported")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+	foo: foo {
+	};
+};
+
+// Only one label supported before label references at the top level
+l1: l2: &foo {
+};
+""",
+":9 (column 5): parse error: expected label reference (&foo)")
+
+    verify_error_endswith("""
+/dts-v1/;
+
+/ {
+        foo: {};
+};
+""",
+":4 (column 14): parse error: expected node or property name")
+
+    # Multiple /dts-v1/ at the start of a file is fine
+    verify_parse("""
+/dts-v1/;
+/dts-v1/;
+
+/ {
+};
+""",
+"""
+/dts-v1/;
+
+/ {
+};
+""")
+
+def test_dangling_alias():
+    dt = parse('''
+/dts-v1/;
+
+/ {
+	aliases { foo = "/missing"; };
+};
+''', force=True)
+    assert dt.get_node('/aliases').props['foo'].to_string() == '/missing'
diff --git a/Tools/dts/python-devicetree/tests/test_edtlib.py b/Tools/dts/python-devicetree/tests/test_edtlib.py
new file mode 100644
index 0000000000..56e0a2a134
--- /dev/null
+++ b/Tools/dts/python-devicetree/tests/test_edtlib.py
@@ -0,0 +1,588 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: BSD-3-Clause
+
+import contextlib
+import io
+from logging import WARNING
+import os
+from pathlib import Path
+
+import pytest
+
+from devicetree import edtlib
+
+# Test suite for edtlib.py.
+#
+# Run it using pytest (https://docs.pytest.org/en/stable/usage.html):
+#
+#   $ pytest testedtlib.py
+#
+# See the comment near the top of testdtlib.py for additional pytest advice.
+#
+# test.dts is the main test file. test-bindings/ and test-bindings-2/ has
+# bindings. The tests mostly use string comparisons via the various __repr__()
+# methods.
+
+HERE = os.path.dirname(__file__)
+
+@contextlib.contextmanager
+def from_here():
+    # Convenience hack to minimize diff from zephyr.
+    cwd = os.getcwd()
+    try:
+        os.chdir(HERE)
+        yield
+    finally:
+        os.chdir(cwd)
+
+def hpath(filename):
+    '''Convert 'filename' to the host path syntax.'''
+    return os.fspath(Path(filename))
+
+def test_warnings(caplog):
+    '''Tests for situations that should cause warnings.'''
+
+    with from_here(): edtlib.EDT("test.dts", ["test-bindings"])
+
+    enums_hpath = hpath('test-bindings/enums.yaml')
+    expected_warnings = [
+        f"'oldprop' is marked as deprecated in 'properties:' in {hpath('test-bindings/deprecated.yaml')} for node /test-deprecated.",
+        "unit address and first address in 'reg' (0x1) don't match for /reg-zero-size-cells/node",
+        "unit address and first address in 'reg' (0x5) don't match for /reg-ranges/parent/node",
+        "unit address and first address in 'reg' (0x30000000200000001) don't match for /reg-nested-ranges/grandparent/parent/node",
+        f"compatible 'enums' in binding '{enums_hpath}' has non-tokenizable enum for property 'string-enum': 'foo bar', 'foo_bar'",
+        f"compatible 'enums' in binding '{enums_hpath}' has enum for property 'tokenizable-lower-enum' that is only tokenizable in lowercase: 'bar', 'BAR'",
+    ]
+    assert caplog.record_tuples == [('devicetree.edtlib', WARNING, warning_message)
+                                    for warning_message in expected_warnings]
+
+def test_interrupts():
+    '''Tests for the interrupts property.'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    filenames = {i: hpath(f'test-bindings/interrupt-{i}-cell.yaml')
+                 for i in range(1, 4)}
+
+    assert str(edt.get_node("/interrupt-parent-test/node").interrupts) == \
+        f"[<ControllerAndData, name: foo, controller: <Node /interrupt-parent-test/controller in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 1), ('two', 2), ('three', 3)])>, <ControllerAndData, name: bar, controller: <Node /interrupt-parent-test/controller in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 4), ('two', 5), ('three', 6)])>]"
+
+    assert str(edt.get_node("/interrupts-extended-test/node").interrupts) == \
+        f"[<ControllerAndData, controller: <Node /interrupts-extended-test/controller-0 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('one', 1)])>, <ControllerAndData, controller: <Node /interrupts-extended-test/controller-1 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 2), ('two', 3)])>, <ControllerAndData, controller: <Node /interrupts-extended-test/controller-2 in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 4), ('two', 5), ('three', 6)])>]"
+
+    assert str(edt.get_node("/interrupt-map-test/node@0").interrupts) == \
+        f"[<ControllerAndData, controller: <Node /interrupt-map-test/controller-0 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('one', 0)])>, <ControllerAndData, controller: <Node /interrupt-map-test/controller-1 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 0), ('two', 1)])>, <ControllerAndData, controller: <Node /interrupt-map-test/controller-2 in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 0), ('two', 0), ('three', 2)])>]"
+
+    assert str(edt.get_node("/interrupt-map-test/node@1").interrupts) == \
+        f"[<ControllerAndData, controller: <Node /interrupt-map-test/controller-0 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('one', 3)])>, <ControllerAndData, controller: <Node /interrupt-map-test/controller-1 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 0), ('two', 4)])>, <ControllerAndData, controller: <Node /interrupt-map-test/controller-2 in 'test.dts', binding {filenames[3]}>, data: OrderedDict([('one', 0), ('two', 0), ('three', 5)])>]"
+
+    assert str(edt.get_node("/interrupt-map-bitops-test/node@70000000E").interrupts) == \
+        f"[<ControllerAndData, controller: <Node /interrupt-map-bitops-test/controller in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 3), ('two', 2)])>]"
+
+def test_ranges():
+    '''Tests for the ranges property'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/reg-ranges/parent").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0x1, parent-bus-cells: 0x2, parent-bus-addr: 0xa0000000b, length-cells 0x1, length 0x1>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x2, parent-bus-cells: 0x2, parent-bus-addr: 0xc0000000d, length-cells 0x1, length 0x2>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x4, parent-bus-cells: 0x2, parent-bus-addr: 0xe0000000f, length-cells 0x1, length 0x1>]"
+
+    assert str(edt.get_node("/reg-nested-ranges/grandparent").ranges) == \
+        "[<Range, child-bus-cells: 0x2, child-bus-addr: 0x0, parent-bus-cells: 0x3, parent-bus-addr: 0x30000000000000000, length-cells 0x2, length 0x200000002>]"
+
+    assert str(edt.get_node("/reg-nested-ranges/grandparent/parent").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0x0, parent-bus-cells: 0x2, parent-bus-addr: 0x200000000, length-cells 0x1, length 0x2>]"
+
+    assert str(edt.get_node("/ranges-zero-cells/node").ranges) == "[]"
+
+    assert str(edt.get_node("/ranges-zero-parent-cells/node").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0xa, parent-bus-cells: 0x0, length-cells 0x0>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x1a, parent-bus-cells: 0x0, length-cells 0x0>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x2a, parent-bus-cells: 0x0, length-cells 0x0>]"
+
+    assert str(edt.get_node("/ranges-one-address-cells/node").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0xa, parent-bus-cells: 0x0, length-cells 0x1, length 0xb>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x1a, parent-bus-cells: 0x0, length-cells 0x1, length 0x1b>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x2a, parent-bus-cells: 0x0, length-cells 0x1, length 0x2b>]"
+
+    assert str(edt.get_node("/ranges-one-address-two-size-cells/node").ranges) == \
+        "[<Range, child-bus-cells: 0x1, child-bus-addr: 0xa, parent-bus-cells: 0x0, length-cells 0x2, length 0xb0000000c>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x1a, parent-bus-cells: 0x0, length-cells 0x2, length 0x1b0000001c>, <Range, child-bus-cells: 0x1, child-bus-addr: 0x2a, parent-bus-cells: 0x0, length-cells 0x2, length 0x2b0000002c>]"
+
+    assert str(edt.get_node("/ranges-two-address-cells/node@1").ranges) == \
+        "[<Range, child-bus-cells: 0x2, child-bus-addr: 0xa0000000b, parent-bus-cells: 0x1, parent-bus-addr: 0xc, length-cells 0x1, length 0xd>, <Range, child-bus-cells: 0x2, child-bus-addr: 0x1a0000001b, parent-bus-cells: 0x1, parent-bus-addr: 0x1c, length-cells 0x1, length 0x1d>, <Range, child-bus-cells: 0x2, child-bus-addr: 0x2a0000002b, parent-bus-cells: 0x1, parent-bus-addr: 0x2c, length-cells 0x1, length 0x2d>]"
+
+    assert str(edt.get_node("/ranges-two-address-two-size-cells/node@1").ranges) == \
+        "[<Range, child-bus-cells: 0x2, child-bus-addr: 0xa0000000b, parent-bus-cells: 0x1, parent-bus-addr: 0xc, length-cells 0x2, length 0xd0000000e>, <Range, child-bus-cells: 0x2, child-bus-addr: 0x1a0000001b, parent-bus-cells: 0x1, parent-bus-addr: 0x1c, length-cells 0x2, length 0x1d0000001e>, <Range, child-bus-cells: 0x2, child-bus-addr: 0x2a0000002b, parent-bus-cells: 0x1, parent-bus-addr: 0x2c, length-cells 0x2, length 0x2d0000001d>]"
+
+    assert str(edt.get_node("/ranges-three-address-cells/node@1").ranges) == \
+        "[<Range, child-bus-cells: 0x3, child-bus-addr: 0xa0000000b0000000c, parent-bus-cells: 0x2, parent-bus-addr: 0xd0000000e, length-cells 0x1, length 0xf>, <Range, child-bus-cells: 0x3, child-bus-addr: 0x1a0000001b0000001c, parent-bus-cells: 0x2, parent-bus-addr: 0x1d0000001e, length-cells 0x1, length 0x1f>, <Range, child-bus-cells: 0x3, child-bus-addr: 0x2a0000002b0000002c, parent-bus-cells: 0x2, parent-bus-addr: 0x2d0000002e, length-cells 0x1, length 0x2f>]"
+
+    assert str(edt.get_node("/ranges-three-address-two-size-cells/node@1").ranges) == \
+        "[<Range, child-bus-cells: 0x3, child-bus-addr: 0xa0000000b0000000c, parent-bus-cells: 0x2, parent-bus-addr: 0xd0000000e, length-cells 0x2, length 0xf00000010>, <Range, child-bus-cells: 0x3, child-bus-addr: 0x1a0000001b0000001c, parent-bus-cells: 0x2, parent-bus-addr: 0x1d0000001e, length-cells 0x2, length 0x1f00000110>, <Range, child-bus-cells: 0x3, child-bus-addr: 0x2a0000002b0000002c, parent-bus-cells: 0x2, parent-bus-addr: 0x2d0000002e, length-cells 0x2, length 0x2f00000210>]"
+
+def test_reg():
+    '''Tests for the regs property'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/reg-zero-address-cells/node").regs) == \
+        "[<Register, size: 0x1>, <Register, size: 0x2>]"
+
+    assert str(edt.get_node("/reg-zero-size-cells/node").regs) == \
+        "[<Register, addr: 0x1>, <Register, addr: 0x2>]"
+
+    assert str(edt.get_node("/reg-ranges/parent/node").regs) == \
+        "[<Register, addr: 0x5, size: 0x1>, <Register, addr: 0xe0000000f, size: 0x1>, <Register, addr: 0xc0000000e, size: 0x1>, <Register, addr: 0xc0000000d, size: 0x1>, <Register, addr: 0xa0000000b, size: 0x1>, <Register, addr: 0x0, size: 0x1>]"
+
+    assert str(edt.get_node("/reg-nested-ranges/grandparent/parent/node").regs) == \
+        "[<Register, addr: 0x30000000200000001, size: 0x1>]"
+
+def test_pinctrl():
+    '''Test 'pinctrl-<index>'.'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/pinctrl/dev").pinctrls) == \
+        "[<PinCtrl, name: zero, configuration nodes: []>, <PinCtrl, name: one, configuration nodes: [<Node /pinctrl/pincontroller/state-1 in 'test.dts', no binding>]>, <PinCtrl, name: two, configuration nodes: [<Node /pinctrl/pincontroller/state-1 in 'test.dts', no binding>, <Node /pinctrl/pincontroller/state-2 in 'test.dts', no binding>]>]"
+
+def test_hierarchy():
+    '''Test Node.parent and Node.children'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert edt.get_node("/").parent is None
+
+    assert str(edt.get_node("/parent/child-1").parent) == \
+        "<Node /parent in 'test.dts', no binding>"
+
+    assert str(edt.get_node("/parent/child-2/grandchild").parent) == \
+        "<Node /parent/child-2 in 'test.dts', no binding>"
+
+    assert str(edt.get_node("/parent").children) == \
+        "OrderedDict([('child-1', <Node /parent/child-1 in 'test.dts', no binding>), ('child-2', <Node /parent/child-2 in 'test.dts', no binding>)])"
+
+    assert edt.get_node("/parent/child-1").children == {}
+
+def test_include():
+    '''Test 'include:' and the legacy 'inherits: !include ...' in bindings'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/binding-include").description) == \
+        "Parent binding"
+
+    assert str(edt.get_node("/binding-include").props) == \
+        "OrderedDict([('foo', <Property, name: foo, type: int, value: 0>), ('bar', <Property, name: bar, type: int, value: 1>), ('baz', <Property, name: baz, type: int, value: 2>), ('qaz', <Property, name: qaz, type: int, value: 3>)])"
+
+def test_include_filters():
+    '''Test property-allowlist and property-blocklist in an include.'''
+
+    fname2path = {'include.yaml': 'test-bindings-include/include.yaml',
+                  'include-2.yaml': 'test-bindings-include/include-2.yaml'}
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            edtlib.Binding("test-bindings-include/allow-and-blocklist.yaml", fname2path)
+    assert ("should not specify both 'property-allowlist:' and 'property-blocklist:'"
+            in str(e.value))
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            edtlib.Binding("test-bindings-include/allow-and-blocklist-child.yaml", fname2path)
+    assert ("should not specify both 'property-allowlist:' and 'property-blocklist:'"
+            in str(e.value))
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            edtlib.Binding("test-bindings-include/allow-not-list.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith("'property-allowlist' value")
+    assert value_str.endswith("should be a list")
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            edtlib.Binding("test-bindings-include/block-not-list.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith("'property-blocklist' value")
+    assert value_str.endswith("should be a list")
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            binding = edtlib.Binding("test-bindings-include/include-invalid-keys.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith(
+        "'include:' in test-bindings-include/include-invalid-keys.yaml should not have these "
+        "unexpected contents: ")
+    assert 'bad-key-1' in value_str
+    assert 'bad-key-2' in value_str
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            binding = edtlib.Binding("test-bindings-include/include-invalid-type.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith(
+        "'include:' in test-bindings-include/include-invalid-type.yaml "
+        "should be a string or list, but has type ")
+
+    with pytest.raises(edtlib.EDTError) as e:
+        with from_here():
+            binding = edtlib.Binding("test-bindings-include/include-no-name.yaml", fname2path)
+    value_str = str(e.value)
+    assert value_str.startswith("'include:' element")
+    assert value_str.endswith(
+        "in test-bindings-include/include-no-name.yaml should have a 'name' key")
+
+    with from_here():
+        binding = edtlib.Binding("test-bindings-include/allowlist.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'x'}  # 'x' is allowed
+
+        binding = edtlib.Binding("test-bindings-include/empty-allowlist.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == set()  # nothing is allowed
+
+        binding = edtlib.Binding("test-bindings-include/blocklist.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'y', 'z'}  # 'x' is blocked
+
+        binding = edtlib.Binding("test-bindings-include/empty-blocklist.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'x', 'y', 'z'}  # nothing is blocked
+
+        binding = edtlib.Binding("test-bindings-include/intermixed.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'x', 'a'}
+
+        binding = edtlib.Binding("test-bindings-include/include-no-list.yaml", fname2path)
+        assert set(binding.prop2specs.keys()) == {'x', 'y', 'z'}
+
+        binding = edtlib.Binding("test-bindings-include/filter-child-bindings.yaml", fname2path)
+        child = binding.child_binding
+        grandchild = child.child_binding
+        assert set(binding.prop2specs.keys()) == {'x'}
+        assert set(child.prop2specs.keys()) == {'child-prop-2'}
+        assert set(grandchild.prop2specs.keys()) == {'grandchild-prop-1'}
+
+
+def test_bus():
+    '''Test 'bus:' and 'on-bus:' in bindings'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert edt.get_node("/buses/foo-bus").bus == "foo"
+
+    # foo-bus does not itself appear on a bus
+    assert edt.get_node("/buses/foo-bus").on_bus is None
+    assert edt.get_node("/buses/foo-bus").bus_node is None
+
+    # foo-bus/node1 is not a bus node...
+    assert edt.get_node("/buses/foo-bus/node1").bus is None
+    # ...but is on a bus
+    assert edt.get_node("/buses/foo-bus/node1").on_bus == "foo"
+    assert edt.get_node("/buses/foo-bus/node1").bus_node.path == \
+        "/buses/foo-bus"
+
+    # foo-bus/node2 is not a bus node...
+    assert edt.get_node("/buses/foo-bus/node2").bus is None
+    # ...but is on a bus
+    assert edt.get_node("/buses/foo-bus/node2").on_bus == "foo"
+
+    # no-bus-node is not a bus node...
+    assert edt.get_node("/buses/no-bus-node").bus is None
+    # ... and is not on a bus
+    assert edt.get_node("/buses/no-bus-node").on_bus is None
+
+    # Same compatible string, but different bindings from being on different
+    # buses
+    assert str(edt.get_node("/buses/foo-bus/node1").binding_path) == \
+        hpath("test-bindings/device-on-foo-bus.yaml")
+    assert str(edt.get_node("/buses/foo-bus/node2").binding_path) == \
+        hpath("test-bindings/device-on-any-bus.yaml")
+    assert str(edt.get_node("/buses/bar-bus/node").binding_path) == \
+        hpath("test-bindings/device-on-bar-bus.yaml")
+    assert str(edt.get_node("/buses/no-bus-node").binding_path) == \
+        hpath("test-bindings/device-on-any-bus.yaml")
+
+    # foo-bus/node/nested also appears on the foo-bus bus
+    assert edt.get_node("/buses/foo-bus/node1/nested").on_bus == "foo"
+    assert str(edt.get_node("/buses/foo-bus/node1/nested").binding_path) == \
+        hpath("test-bindings/device-on-foo-bus.yaml")
+
+def test_child_binding():
+    '''Test 'child-binding:' in bindings'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    child1 = edt.get_node("/child-binding/child-1")
+    child2 = edt.get_node("/child-binding/child-2")
+    grandchild = edt.get_node("/child-binding/child-1/grandchild")
+
+    assert str(child1.binding_path) == hpath("test-bindings/child-binding.yaml")
+    assert str(child1.description) == "child node"
+    assert str(child1.props) == "OrderedDict([('child-prop', <Property, name: child-prop, type: int, value: 1>)])"
+
+    assert str(child2.binding_path) == hpath("test-bindings/child-binding.yaml")
+    assert str(child2.description) == "child node"
+    assert str(child2.props) == "OrderedDict([('child-prop', <Property, name: child-prop, type: int, value: 3>)])"
+
+    assert str(grandchild.binding_path) == hpath("test-bindings/child-binding.yaml")
+    assert str(grandchild.description) == "grandchild node"
+    assert str(grandchild.props) == "OrderedDict([('grandchild-prop', <Property, name: grandchild-prop, type: int, value: 2>)])"
+
+    with from_here():
+        binding_file = Path("test-bindings/child-binding.yaml").resolve()
+        top = edtlib.Binding(binding_file, {})
+    child = top.child_binding
+    assert Path(top.path) == binding_file
+    assert Path(child.path) == binding_file
+    assert top.compatible == 'top-binding'
+    assert child.compatible is None
+
+    with from_here():
+        binding_file = Path("test-bindings/child-binding-with-compat.yaml").resolve()
+        top = edtlib.Binding(binding_file, {})
+    child = top.child_binding
+    assert Path(top.path) == binding_file
+    assert Path(child.path) == binding_file
+    assert top.compatible == 'top-binding-with-compat'
+    assert child.compatible == 'child-compat'
+
+def test_props():
+    '''Test Node.props (derived from DT and 'properties:' in the binding)'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    filenames = {i: hpath(f'test-bindings/phandle-array-controller-{i}.yaml')
+                 for i in range(0, 4)}
+
+    assert str(edt.get_node("/props").props["int"]) == \
+        "<Property, name: int, type: int, value: 1>"
+
+    assert str(edt.get_node("/props").props["existent-boolean"]) == \
+        "<Property, name: existent-boolean, type: boolean, value: True>"
+
+    assert str(edt.get_node("/props").props["nonexistent-boolean"]) == \
+        "<Property, name: nonexistent-boolean, type: boolean, value: False>"
+
+    assert str(edt.get_node("/props").props["array"]) == \
+        "<Property, name: array, type: array, value: [1, 2, 3]>"
+
+    assert str(edt.get_node("/props").props["uint8-array"]) == \
+        r"<Property, name: uint8-array, type: uint8-array, value: b'\x124'>"
+
+    assert str(edt.get_node("/props").props["string"]) == \
+        "<Property, name: string, type: string, value: 'foo'>"
+
+    assert str(edt.get_node("/props").props["string-array"]) == \
+        "<Property, name: string-array, type: string-array, value: ['foo', 'bar', 'baz']>"
+
+    assert str(edt.get_node("/props").props["phandle-ref"]) == \
+        f"<Property, name: phandle-ref, type: phandle, value: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>>"
+
+    assert str(edt.get_node("/props").props["phandle-refs"]) == \
+        f"<Property, name: phandle-refs, type: phandles, value: [<Node /ctrl-1 in 'test.dts', binding {filenames[1]}>, <Node /ctrl-2 in 'test.dts', binding {filenames[2]}>]>"
+
+    assert str(edt.get_node("/props").props["phandle-array-foos"]) == \
+        f"<Property, name: phandle-array-foos, type: phandle-array, value: [<ControllerAndData, controller: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('one', 1)])>, <ControllerAndData, controller: <Node /ctrl-2 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 2), ('two', 3)])>]>"
+
+    assert str(edt.get_node("/props-2").props["phandle-array-foos"]) == \
+        ("<Property, name: phandle-array-foos, type: phandle-array, value: ["
+         f"<ControllerAndData, name: a, controller: <Node /ctrl-0-1 in 'test.dts', binding {filenames[0]}>, data: OrderedDict()>, "
+         "None, "
+         f"<ControllerAndData, name: b, controller: <Node /ctrl-0-2 in 'test.dts', binding {filenames[0]}>, data: OrderedDict()>]>")
+
+    assert str(edt.get_node("/props").props["foo-gpios"]) == \
+        f"<Property, name: foo-gpios, type: phandle-array, value: [<ControllerAndData, controller: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>, data: OrderedDict([('gpio-one', 1)])>]>"
+
+    assert str(edt.get_node("/props").props["path"]) == \
+        f"<Property, name: path, type: path, value: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>>"
+
+def test_nexus():
+    '''Test <prefix>-map via gpio-map (the most common case).'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    filename = hpath('test-bindings/gpio-dst.yaml')
+
+    assert str(edt.get_node("/gpio-map/source").props["foo-gpios"]) == \
+        f"<Property, name: foo-gpios, type: phandle-array, value: [<ControllerAndData, controller: <Node /gpio-map/destination in 'test.dts', binding {filename}>, data: OrderedDict([('val', 6)])>, <ControllerAndData, controller: <Node /gpio-map/destination in 'test.dts', binding {filename}>, data: OrderedDict([('val', 5)])>]>"
+
+    assert str(edt.get_node("/gpio-map/source").props["foo-gpios"].val[0].basename) == f"gpio"
+
+def test_prop_defaults():
+    '''Test property default values given in bindings'''
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+
+    assert str(edt.get_node("/defaults").props) == \
+        r"OrderedDict([('int', <Property, name: int, type: int, value: 123>), ('array', <Property, name: array, type: array, value: [1, 2, 3]>), ('uint8-array', <Property, name: uint8-array, type: uint8-array, value: b'\x89\xab\xcd'>), ('string', <Property, name: string, type: string, value: 'hello'>), ('string-array', <Property, name: string-array, type: string-array, value: ['hello', 'there']>), ('default-not-used', <Property, name: default-not-used, type: int, value: 234>)])"
+
+def test_prop_enums():
+    '''test properties with enum: in the binding'''
+
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"])
+    props = edt.get_node('/enums').props
+    int_enum = props['int-enum']
+    string_enum = props['string-enum']
+    tokenizable_enum = props['tokenizable-enum']
+    tokenizable_lower_enum = props['tokenizable-lower-enum']
+    no_enum = props['no-enum']
+
+    assert int_enum.val == 1
+    assert int_enum.enum_index == 0
+    assert not int_enum.spec.enum_tokenizable
+    assert not int_enum.spec.enum_upper_tokenizable
+
+    assert string_enum.val == 'foo_bar'
+    assert string_enum.enum_index == 1
+    assert not string_enum.spec.enum_tokenizable
+    assert not string_enum.spec.enum_upper_tokenizable
+
+    assert tokenizable_enum.val == '123 is ok'
+    assert tokenizable_enum.val_as_token == '123_is_ok'
+    assert tokenizable_enum.enum_index == 2
+    assert tokenizable_enum.spec.enum_tokenizable
+    assert tokenizable_enum.spec.enum_upper_tokenizable
+
+    assert tokenizable_lower_enum.val == 'bar'
+    assert tokenizable_lower_enum.val_as_token == 'bar'
+    assert tokenizable_lower_enum.enum_index == 0
+    assert tokenizable_lower_enum.spec.enum_tokenizable
+    assert not tokenizable_lower_enum.spec.enum_upper_tokenizable
+
+    assert no_enum.enum_index is None
+    assert not no_enum.spec.enum_tokenizable
+    assert not no_enum.spec.enum_upper_tokenizable
+
+def test_binding_inference():
+    '''Test inferred bindings for special zephyr-specific nodes.'''
+    warnings = io.StringIO()
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"], warnings)
+
+    assert str(edt.get_node("/zephyr,user").props) == r"OrderedDict()"
+
+    with from_here():
+        edt = edtlib.EDT("test.dts", ["test-bindings"], warnings,
+                         infer_binding_for_paths=["/zephyr,user"])
+    filenames = {i: hpath(f'test-bindings/phandle-array-controller-{i}.yaml')
+                 for i in range(1, 3)}
+
+    assert str(edt.get_node("/zephyr,user").props) == \
+        rf"OrderedDict([('boolean', <Property, name: boolean, type: boolean, value: True>), ('bytes', <Property, name: bytes, type: uint8-array, value: b'\x81\x82\x83'>), ('number', <Property, name: number, type: int, value: 23>), ('numbers', <Property, name: numbers, type: array, value: [1, 2, 3]>), ('string', <Property, name: string, type: string, value: 'text'>), ('strings', <Property, name: strings, type: string-array, value: ['a', 'b', 'c']>), ('handle', <Property, name: handle, type: phandle, value: <Node /ctrl-1 in 'test.dts', binding {filenames[1]}>>), ('phandles', <Property, name: phandles, type: phandles, value: [<Node /ctrl-1 in 'test.dts', binding {filenames[1]}>, <Node /ctrl-2 in 'test.dts', binding {filenames[2]}>]>), ('phandle-array-foos', <Property, name: phandle-array-foos, type: phandle-array, value: [<ControllerAndData, controller: <Node /ctrl-2 in 'test.dts', binding {filenames[2]}>, data: OrderedDict([('one', 1), ('two', 2)])>]>)])"
+
+def test_multi_bindings():
+    '''Test having multiple directories with bindings'''
+    with from_here():
+        edt = edtlib.EDT("test-multidir.dts", ["test-bindings", "test-bindings-2"])
+
+    assert str(edt.get_node("/in-dir-1").binding_path) == \
+        hpath("test-bindings/multidir.yaml")
+
+    assert str(edt.get_node("/in-dir-2").binding_path) == \
+        hpath("test-bindings-2/multidir.yaml")
+
+def test_dependencies():
+    ''''Test dependency relations'''
+    with from_here():
+        edt = edtlib.EDT("test-multidir.dts", ["test-bindings", "test-bindings-2"])
+
+    assert edt.get_node("/").dep_ordinal == 0
+    assert edt.get_node("/in-dir-1").dep_ordinal == 1
+    assert edt.get_node("/") in edt.get_node("/in-dir-1").depends_on
+    assert edt.get_node("/in-dir-1") in edt.get_node("/").required_by
+
+def test_slice_errs(tmp_path):
+    '''Test error messages from the internal _slice() helper'''
+
+    dts_file = tmp_path / "error.dts"
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <2>;
+
+	sub {
+		reg = <3>;
+	};
+};
+""",
+                 dts_file,
+                 f"'reg' property in <Node /sub in '{dts_file}'> has length 4, which is not evenly divisible by 12 (= 4*(<#address-cells> (= 1) + <#size-cells> (= 2))). Note that #*-cells properties come either from the parent node or from the controller (in the case of 'interrupts').")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	sub {
+		interrupts = <1>;
+		interrupt-parent = < &{/controller} >;
+	};
+	controller {
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+""",
+                 dts_file,
+                 f"'interrupts' property in <Node /sub in '{dts_file}'> has length 4, which is not evenly divisible by 8 (= 4*<#interrupt-cells>). Note that #*-cells properties come either from the parent node or from the controller (in the case of 'interrupts').")
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+
+	sub-1 {
+		#address-cells = <2>;
+		#size-cells = <3>;
+		ranges = <4 5>;
+
+		sub-2 {
+			reg = <1 2 3 4 5>;
+		};
+	};
+};
+""",
+                 dts_file,
+                 f"'ranges' property in <Node /sub-1 in '{dts_file}'> has length 8, which is not evenly divisible by 24 (= 4*(<#address-cells> (= 2) + <#address-cells for parent> (= 1) + <#size-cells> (= 3))). Note that #*-cells properties come either from the parent node or from the controller (in the case of 'interrupts').")
+
+def test_bad_compatible(tmp_path):
+    # An invalid compatible should cause an error, even on a node with
+    # no binding.
+
+    dts_file = tmp_path / "error.dts"
+
+    verify_error("""
+/dts-v1/;
+
+/ {
+	foo {
+		compatible = "no, whitespace";
+	};
+};
+""",
+                 dts_file,
+                 r"node '/foo' compatible 'no, whitespace' must match this regular expression: '^[a-zA-Z][a-zA-Z0-9,+\-._]+$'")
+
+def test_wrong_props():
+    '''Test Node.wrong_props (derived from DT and 'properties:' in the binding)'''
+
+    with from_here():
+        with pytest.raises(edtlib.EDTError) as e:
+            edtlib.Binding("test-wrong-bindings/wrong-specifier-space-type.yaml", None)
+        assert ("'specifier-space' in 'properties: wrong-type-for-specifier-space' has type 'phandle', expected 'phandle-array'"
+            in str(e.value))
+
+        with pytest.raises(edtlib.EDTError) as e:
+            edtlib.Binding("test-wrong-bindings/wrong-phandle-array-name.yaml", None)
+        value_str = str(e.value)
+        assert value_str.startswith("'wrong-phandle-array-name' in 'properties:'")
+        assert value_str.endswith("but no 'specifier-space' was provided.")
+
+
+def verify_error(dts, dts_file, expected_err):
+    # Verifies that parsing a file 'dts_file' with the contents 'dts'
+    # (a string) raises an EDTError with the message 'expected_err'.
+    #
+    # The path 'dts_file' is written with the string 'dts' before the
+    # test is run.
+
+    with open(dts_file, "w", encoding="utf-8") as f:
+        f.write(dts)
+        f.flush()  # Can't have unbuffered text IO, so flush() instead
+
+    with pytest.raises(edtlib.EDTError) as e:
+        edtlib.EDT(dts_file, [])
+
+    assert str(e.value) == expected_err
diff --git a/Tools/dts/python-devicetree/tox.ini b/Tools/dts/python-devicetree/tox.ini
new file mode 100644
index 0000000000..54b08ec094
--- /dev/null
+++ b/Tools/dts/python-devicetree/tox.ini
@@ -0,0 +1,19 @@
+[tox]
+envlist=py3
+
+[testenv]
+deps =
+    setuptools-scm
+    pytest
+    types-PyYAML
+    mypy
+setenv =
+    TOXTEMPDIR={envtmpdir}
+commands =
+  python -m pytest {posargs:tests}
+  python -m mypy --config-file={toxinidir}/tox.ini --package=devicetree
+
+[mypy]
+mypy_path=src
+ignore_missing_imports=True
+
diff --git a/boards/px4/fmu-v5x/board.dts b/boards/px4/fmu-v5x/board.dts
new file mode 100644
index 0000000000..366817712c
--- /dev/null
+++ b/boards/px4/fmu-v5x/board.dts
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2021 PX4
+ *
+ * SPDX-License-Identifier:
+ */
+
+/dts-v1/;
+
+#include <mem.h> // DT_SIZE_K()
+
+#include <st/f7/stm32f765.dtsi>
+#include <st/f7/stm32f765i(g-i)tx-pinctrl.dtsi>
+
+/ {
+	model = "PX4 FMUv5x";
+	compatible = "px4,px4_fmu-v5x";
+
+	chosen {
+		//zephyr,console = &usart1;
+		//zephyr,shell-uart = &usart1;
+		//zephyr,sram = &sram0;
+		//zephyr,flash = &flash0;
+		//zephyr,dtcm = &dtcm;
+		//zephyr,flash-controller = &mx25l51245g;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		red_led_1:led_1 {
+			gpios = <&gpioe 3 GPIO_ACTIVE_LOW>;
+			label = "LED RED";
+		};
+		green_led_2:led_2 {
+			gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+			label = "LED GREEN";
+		};
+		blue_led_3:led_3 {
+			gpios = <&gpioe 5 GPIO_ACTIVE_LOW>;
+			label = "LED BLUE";
+		};
+	};
+
+	aliases {
+		led0 = &red_led_1;
+		led1 = &green_led_2;
+		led2 = &blue_led_3;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(16)>;
+	status = "okay";
+};
+
+&pll {
+	div-m = <8>;
+	mul-n = <216>;
+	div-p = <2>;
+	div-q = <9>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(216)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <4>;
+	apb2-prescaler = <2>;
+};
+
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usart2 {
+	pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pa3>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usart3 {
+	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_ph14>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-0 = <&uart5_tx_pb9 &uart5_rx_pd2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usart6 {
+	pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-0 = <&uart7_tx_pe8 &uart7_rx_pf6>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart8 {
+	pinctrl-0 = <&uart8_tx_pe1 &uart8_rx_pe0>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3 {
+	pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c4 {
+	pinctrl-0 = <&i2c4_scl_pf14 &i2c4_sda_pf15>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pb4 &spi1_mosi_pb5>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi2 {
+	pinctrl-0 = <&spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi3 {
+	pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pb2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi5 {
+	pinctrl-0 = <&spi5_sck_pf7 &spi5_miso_pf8 &spi5_mosi_pf11>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi6 {
+	pinctrl-0 = <&spi6_sck_pb3 &spi6_miso_pa6 &spi6_mosi_pg14>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+
+&mac {
+	status = "okay";
+	pinctrl-0 = <&eth_mdc_pc1
+		     &eth_rxd0_pc4
+		     &eth_rxd1_pc5
+		     &eth_ref_clk_pa1
+		     &eth_mdio_pa2
+		     &eth_crs_dv_pa7
+		     &eth_tx_en_pb11
+		     &eth_txd0_pg13
+		     &eth_txd1_pb13>;
+	pinctrl-names = "default";
+};
+
+
+&sdmmc2 {
+	status = "okay";
+	pinctrl-0 = <&sdmmc2_d0_pg9  &sdmmc2_d1_pg10
+		     &sdmmc2_d2_pg11 &sdmmc2_d3_pg12
+		     &sdmmc2_ck_pd6  &sdmmc2_cmd_pd7>;
+	pinctrl-names = "default";
+	cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
+};
diff --git a/boards/px4/fmu-v5x/src/init.cpp b/boards/px4/fmu-v5x/src/init.cpp
index 1632e5891e..6e23d26fb6 100644
--- a/boards/px4/fmu-v5x/src/init.cpp
+++ b/boards/px4/fmu-v5x/src/init.cpp
@@ -77,6 +77,8 @@ extern "C" {
 #include <px4_platform/board_dma_alloc.h>
 #include <px4_platform/gpio/mcp23009.hpp>
 
+#include <include/devicetree.h>
+
 /****************************************************************************
  * Pre-Processor Definitions
  ****************************************************************************/
@@ -296,5 +298,8 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 		}
 	}
 
+	printf("DT_LABEL: %s\n", DT_LABEL(DT_NODELABEL(usart1)));
+
+
 	return OK;
 }
diff --git a/cmake/dts.cmake b/cmake/dts.cmake
new file mode 100644
index 0000000000..a0619ec98f
--- /dev/null
+++ b/cmake/dts.cmake
@@ -0,0 +1,281 @@
+# SPDX-License-Identifier: Apache-2.0
+
+file(MAKE_DIRECTORY ${PX4_BINARY_DIR}/dts/include/generated)
+
+function(check_dtc_flag flag ok)
+  execute_process(
+    COMMAND
+    ${DTC} ${flag} -v
+    ERROR_QUIET
+    OUTPUT_QUIET
+    RESULT_VARIABLE dtc_check_ret
+  )
+  if (dtc_check_ret EQUAL 0)
+    set(${ok} 1 PARENT_SCOPE)
+  else()
+    set(${ok} 0 PARENT_SCOPE)
+  endif()
+endfunction()
+
+# Zephyr code can configure itself based on a KConfig'uration with the
+# header file autoconf.h. There exists an analogous file devicetree_unfixed.h
+# that allows configuration based on information encoded in DTS.
+#
+# Here we call on dtc, the gcc preprocessor and
+# scripts/dts/gen_defines.py to generate various DT-related files at
+# CMake configure-time.
+#
+# See the Devicetree user guide in the Zephyr documentation for details.
+set(GEN_DEFINES_SCRIPT          ${PX4_SOURCE_DIR}/Tools/dts/gen_defines.py)
+set(BOARD_DTS                   ${PX4_BINARY_DIR}/dts/board.dts)
+# This contains the edtlib.EDT object created from zephyr.dts in Python's
+# pickle data marshalling format (https://docs.python.org/3/library/pickle.html)
+#
+# Its existence is an implementation detail used to speed up further
+# use of the devicetree by processes that run later on in the build,
+# and should not be made part of the documentation.
+set(EDT_PICKLE                  ${PX4_BINARY_DIR}/dts/edt.pickle)
+set(DEVICETREE_UNFIXED_H        ${PX4_BINARY_DIR}/dts/include/generated/devicetree_unfixed.h)
+set(DEVICE_EXTERN_H             ${PX4_BINARY_DIR}/dts/include/generated/device_extern.h)
+set(DTS_POST_CPP                ${PX4_BINARY_DIR}/dts/px4.dts.pre)
+set(DTS_DEPS                    ${PX4_BINARY_DIR}/dts/px4.dts.d)
+# The location of a list of known vendor prefixes.
+# This is relative to each element of DTS_ROOT.
+set(VENDOR_PREFIXES             dts/bindings/vendor-prefixes.txt)
+
+# Devicetree in CMake.
+set(DTS_CMAKE_SCRIPT            ${PX4_SOURCE_DIR}/Tools/dts/gen_dts_cmake.py)
+set(DTS_CMAKE                   ${PX4_BINARY_DIR}/dts/dts.cmake)
+
+set(DTS_SOURCE ${PX4_BOARD_DIR}/board.dts)
+
+# 'DTS_ROOT' is a list of directories where a directory tree with DT
+# files may be found. It always includes the application directory,
+# the board directory, and ${ZEPHYR_BASE}.
+list(APPEND DTS_ROOT
+  ${PX4_BOARD_DIR}
+  ${PX4_SOURCE_DIR}
+)
+list(REMOVE_DUPLICATES DTS_ROOT)
+
+# TODO: What to do about non-posix platforms where NOT CONFIG_HAS_DTS (xtensa)?
+# Drop support for NOT CONFIG_HAS_DTS perhaps?
+if(EXISTS ${DTS_SOURCE})
+  set(SUPPORTS_DTS 1)
+  if(BOARD_REVISION AND EXISTS ${PX4_BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.overlay)
+    list(APPEND DTS_SOURCE ${PX4_BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.overlay)
+  endif()
+else()
+  set(SUPPORTS_DTS 0)
+endif()
+
+set(dts_files
+  ${DTS_SOURCE}
+  ${shield_dts_files}
+  )
+
+if(SUPPORTS_DTS)
+  if(DTC_OVERLAY_FILE)
+    # Convert from space-separated files into file list
+    string(REPLACE " " ";" DTC_OVERLAY_FILE_RAW_LIST "${DTC_OVERLAY_FILE}")
+    foreach(file ${DTC_OVERLAY_FILE_RAW_LIST})
+      file(TO_CMAKE_PATH "${file}" cmake_path_file)
+      list(APPEND DTC_OVERLAY_FILE_AS_LIST ${cmake_path_file})
+    endforeach()
+    list(APPEND
+      dts_files
+      ${DTC_OVERLAY_FILE_AS_LIST}
+      )
+  endif()
+
+  set(i 0)
+  unset(DTC_INCLUDE_FLAG_FOR_DTS)
+  foreach(dts_file ${dts_files})
+    list(APPEND DTC_INCLUDE_FLAG_FOR_DTS
+         -include ${dts_file})
+
+    if(i EQUAL 0)
+      message(STATUS "Found BOARD.dts: ${dts_file}")
+    else()
+      message(STATUS "Found devicetree overlay: ${dts_file}")
+    endif()
+
+    math(EXPR i "${i}+1")
+  endforeach()
+
+  unset(DTS_ROOT_SYSTEM_INCLUDE_DIRS)
+  unset(DTS_ROOT_BINDINGS)
+  foreach(dts_root ${DTS_ROOT})
+    foreach(dts_root_path
+        src/include
+        dts/common
+        dts/${CONFIG_ARCH}
+        dts
+        platforms/nuttx/src/px4/stm/hal_stm32/dts
+        )
+      get_filename_component(full_path ${dts_root}/${dts_root_path} REALPATH)
+      if(EXISTS ${full_path})
+        list(APPEND
+          DTS_ROOT_SYSTEM_INCLUDE_DIRS
+          -isystem ${full_path}
+          )
+      endif()
+    endforeach()
+
+    set(bindings_path ${dts_root}/dts/bindings)
+    if(EXISTS ${bindings_path})
+      list(APPEND
+        DTS_ROOT_BINDINGS
+        ${bindings_path}
+        )
+    endif()
+
+    set(vendor_prefixes ${dts_root}/${VENDOR_PREFIXES})
+    if(EXISTS ${vendor_prefixes})
+      list(APPEND EXTRA_GEN_DEFINES_ARGS --vendor-prefixes ${vendor_prefixes})
+    endif()
+  endforeach()
+
+  # Cache the location of the root bindings so they can be used by
+  # scripts which use the build directory.
+  set(CACHED_DTS_ROOT_BINDINGS ${DTS_ROOT_BINDINGS} CACHE INTERNAL
+    "DT bindings root directories")
+
+  if(NOT DEFINED CMAKE_DTS_PREPROCESSOR)
+    set(CMAKE_DTS_PREPROCESSOR ${CMAKE_C_COMPILER})
+  endif()
+
+  # TODO: Cut down on CMake configuration time by avoiding
+  # regeneration of devicetree_unfixed.h on every configure. How
+  # challenging is this? What are the dts dependencies? We run the
+  # preprocessor, and it seems to be including all kinds of
+  # directories with who-knows how many header files.
+
+  # Run the preprocessor on the DTS input files. We are leaving
+  # linemarker directives enabled on purpose. This tells dtlib where
+  # each line actually came from, which improves error reporting.
+  execute_process(
+    COMMAND ${CMAKE_DTS_PREPROCESSOR}
+    -x assembler-with-cpp
+    -nostdinc
+    ${DTS_ROOT_SYSTEM_INCLUDE_DIRS}
+    ${DTC_INCLUDE_FLAG_FOR_DTS}  # include the DTS source and overlays
+    ${NOSYSDEF_CFLAG}
+    -D__DTS__
+    ${DTS_EXTRA_CPPFLAGS}
+    -E   # Stop after preprocessing
+    -MD  # Generate a dependency file as a side-effect
+    -MF ${DTS_DEPS}
+    -o ${DTS_POST_CPP}
+    ${PX4_SOURCE_DIR}/platforms/common/empty.c
+    WORKING_DIRECTORY ${PX4_SOURCE_DIR}
+    RESULT_VARIABLE ret
+    )
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "command failed with return code: ${ret}")
+  endif()
+
+  # Parse the generated dependency file to find the DT sources that
+  # were included, including any transitive includes, and then add
+  # them to the list of files that trigger a re-run of CMake.
+  # toolchain_parse_make_rule(${DTS_DEPS}
+  #   include_files # Output parameter
+  #   )
+
+  # set_property(DIRECTORY APPEND PROPERTY
+  #   CMAKE_CONFIGURE_DEPENDS
+  #   ${include_files}
+  #   ${GEN_DEFINES_SCRIPT}
+  #   ${DTS_CMAKE_SCRIPT}
+  #   )
+
+  #
+  # Run gen_defines.py to create a header file, zephyr.dts, and edt.pickle.
+  #
+
+  string(REPLACE ";" " " EXTRA_DTC_FLAGS_RAW "${EXTRA_DTC_FLAGS}")
+  set(CMD_EXTRACT ${PYTHON_EXECUTABLE} ${GEN_DEFINES_SCRIPT}
+  --dts ${DTS_POST_CPP}
+  --dtc-flags '${EXTRA_DTC_FLAGS_RAW}'
+  --bindings-dirs ${DTS_ROOT_BINDINGS}
+  --header-out ${DEVICETREE_UNFIXED_H}
+  --device-header-out ${DEVICE_EXTERN_H}
+  --dts-out ${BOARD_DTS} # for debugging and dtc
+  --edt-pickle-out ${EDT_PICKLE}
+  ${EXTRA_GEN_DEFINES_ARGS}
+  )
+
+  execute_process(
+    COMMAND ${CMD_EXTRACT}
+    WORKING_DIRECTORY ${PX4_BINARY_DIR}
+    RESULT_VARIABLE ret
+    )
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "gen_defines.py failed with return code: ${ret}")
+  else()
+    message(STATUS "Generated zephyr.dts: ${BOARD_DTS}")
+    message(STATUS "Generated devicetree_unfixed.h: ${DEVICETREE_UNFIXED_H}")
+    message(STATUS "Generated device_extern.h: ${DEVICE_EXTERN_H}")
+  endif()
+
+  execute_process(
+    COMMAND ${PYTHON_EXECUTABLE} ${DTS_CMAKE_SCRIPT}
+    --edt-pickle ${EDT_PICKLE}
+    --cmake-out ${DTS_CMAKE}
+    WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+    RESULT_VARIABLE ret
+    )
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "gen_dts_cmake.py failed with return code: ${ret}")
+  else()
+    message(STATUS "Including generated dts.cmake file: ${DTS_CMAKE}")
+    include(${DTS_CMAKE})
+  endif()
+
+  #
+  # Run dtc on the final devicetree source, just to catch any
+  # warnings/errors from it. dtlib and edtlib parse the devicetree files
+  # themselves, so we don't rely on dtc otherwise.
+  #
+
+  if(DTC)
+  set(DTC_WARN_UNIT_ADDR_IF_ENABLED "")
+  check_dtc_flag("-Wunique_unit_address_if_enabled" check)
+  if (check)
+    set(DTC_WARN_UNIT_ADDR_IF_ENABLED "-Wunique_unit_address_if_enabled")
+  endif()
+  set(DTC_NO_WARN_UNIT_ADDR "")
+  check_dtc_flag("-Wno-unique_unit_address" check)
+  if (check)
+    set(DTC_NO_WARN_UNIT_ADDR "-Wno-unique_unit_address")
+  endif()
+  set(VALID_EXTRA_DTC_FLAGS "")
+  foreach(extra_opt ${EXTRA_DTC_FLAGS})
+    check_dtc_flag(${extra_opt} check)
+    if (check)
+      list(APPEND VALID_EXTRA_DTC_FLAGS ${extra_opt})
+    endif()
+  endforeach()
+  set(EXTRA_DTC_FLAGS ${VALID_EXTRA_DTC_FLAGS})
+  execute_process(
+    COMMAND ${DTC}
+    -O dts
+    -o - # Write output to stdout, which we discard below
+    -b 0
+    -E unit_address_vs_reg
+    ${DTC_NO_WARN_UNIT_ADDR}
+    ${DTC_WARN_UNIT_ADDR_IF_ENABLED}
+    ${EXTRA_DTC_FLAGS} # User settable
+    ${BOARD_DTS}
+    OUTPUT_QUIET # Discard stdout
+    WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+    RESULT_VARIABLE ret
+    )
+  if(NOT "${ret}" STREQUAL "0")
+    message(FATAL_ERROR "command failed with return code: ${ret}")
+  endif()
+  endif(DTC)
+else()
+  file(WRITE ${DEVICETREE_UNFIXED_H} "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */")
+  file(WRITE ${DEVICE_EXTERN_H} "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */")
+endif(SUPPORTS_DTS)
diff --git a/dts/Kconfig b/dts/Kconfig
new file mode 100644
index 0000000000..f86101746d
--- /dev/null
+++ b/dts/Kconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+
+config HAS_DTS
+	bool
+	help
+	  This option specifies that the target platform supports device tree
+	  configuration.
+
+config HAS_DTS_GPIO
+	bool
+	depends on HAS_DTS
+	help
+	  This option specifies that the target platform supports device tree
+	  configuration for GPIO.
+
+config HAS_DTS_WDT
+	bool
+	depends on HAS_DTS
+	help
+	  This option specifies that the target platform supports device tree
+	  configuration for WDT.
diff --git a/dts/arm/armv6-m.dtsi b/dts/arm/armv6-m.dtsi
new file mode 100644
index 0000000000..18ccea2c5a
--- /dev/null
+++ b/dts/arm/armv6-m.dtsi
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&nvic>;
+		ranges;
+
+		nvic: interrupt-controller@e000e100  {
+			#address-cells = <1>;
+			compatible = "arm,v6m-nvic";
+			reg = <0xe000e100 0xc00>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		systick: timer@e000e010 {
+			compatible = "arm,armv6m-systick";
+			reg = <0xe000e010 0x10>;
+		};
+	};
+};
+
diff --git a/dts/arm/armv7-a.dtsi b/dts/arm/armv7-a.dtsi
new file mode 100644
index 0000000000..814c85187d
--- /dev/null
+++ b/dts/arm/armv7-a.dtsi
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};
diff --git a/dts/arm/armv7-m.dtsi b/dts/arm/armv7-m.dtsi
new file mode 100644
index 0000000000..9f2dc66734
--- /dev/null
+++ b/dts/arm/armv7-m.dtsi
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&nvic>;
+		ranges;
+
+		nvic: interrupt-controller@e000e100  {
+			#address-cells = <1>;
+			compatible = "arm,v7m-nvic";
+			reg = <0xe000e100 0xc00>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		systick: timer@e000e010 {
+			compatible = "arm,armv7m-systick";
+			reg = <0xe000e010 0x10>;
+		};
+	};
+};
+
diff --git a/dts/arm/armv7-r.dtsi b/dts/arm/armv7-r.dtsi
new file mode 100644
index 0000000000..814c85187d
--- /dev/null
+++ b/dts/arm/armv7-r.dtsi
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};
diff --git a/dts/arm/nxp/nxp_k66.dtsi b/dts/arm/nxp/nxp_k66.dtsi
new file mode 100644
index 0000000000..b20a39e6dd
--- /dev/null
+++ b/dts/arm/nxp/nxp_k66.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020 DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <nxp/nxp_k6x.dtsi>
+
+&flash0 {
+	reg = <0x00000000 DT_SIZE_M(2)>;
+};
+
+/ {
+	soc {
+		lpuart0: lpuart@400c4000 {
+			compatible = "nxp,kinetis-lpuart";
+			reg = <0x400c4000 0x14>;
+			interrupts = <86 0>;
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>;
+			label = "LPUART_0";
+			status = "disabled";
+		};
+
+		flexcan1: can@400a4000 {
+			compatible = "nxp,kinetis-flexcan";
+			reg = <0x400a4000 0x1000>;
+			interrupts = <94 0>, <95 0>, <96 0>, <97 0>, <98 0>, <99 0>;
+			interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning",
+			    "rx-warning", "wake-up";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 4>;
+			clk-source = <1>;
+			label = "CAN_1";
+			sjw = <1>;
+			prop-seg = <1>;
+			phase-seg1 = <3>;
+			phase-seg2 = <2>;
+			status = "disabled";
+		  };
+	};
+};
diff --git a/dts/arm/nxp/nxp_k6x.dtsi b/dts/arm/nxp/nxp_k6x.dtsi
new file mode 100644
index 0000000000..bfad01983e
--- /dev/null
+++ b/dts/arm/nxp/nxp_k6x.dtsi
@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <mem.h>
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/kinetis_sim.h>
+#include <dt-bindings/clock/kinetis_mcg.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+	aliases {
+		watchdog0 = &wdog;
+	};
+
+	chosen {
+		zephyr,entropy = &rnga;
+		zephyr,flash-controller = &ftfe;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
+	 * contiguous block in the memory map, however misaligned accesses
+	 * across the 0x2000_0000 boundary are not supported in the Arm
+	 * Cortex-M4 architecture. For clarity and to avoid the temptation for
+	 * someone to extend sram0 without solving this issue, we define two
+	 * separate memory nodes here and only use the upper one for now. A
+	 * potential solution has been proposed in binutils:
+	 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
+	 */
+	sram_l: memory@1fff0000 {
+		compatible = "mmio-sram";
+		reg = <0x1fff0000 DT_SIZE_K(64)>;
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	temp0: temp0 {
+		compatible = "nxp,kinetis-temperature";
+		io-channels = <&adc0 26>, <&adc0 27>;
+		io-channel-names = "SENSOR", "BANDGAP";
+		bandgap-voltage = <1000000>;
+		vtemp25 = <716000>;
+		sensor-slope-cold = <1620>;
+		sensor-slope-hot = <1620>;
+		label = "TEMP0";
+		status = "disabled";
+	};
+
+	temp1: temp1 {
+		compatible = "nxp,kinetis-temperature";
+		io-channels = <&adc1 26>, <&adc1 27>;
+		io-channel-names = "SENSOR", "BANDGAP";
+		bandgap-voltage = <1000000>;
+		vtemp25 = <716000>;
+		sensor-slope-cold = <1620>;
+		sensor-slope-hot = <1620>;
+		label = "TEMP1";
+		status = "disabled";
+	};
+
+	soc {
+		mpu: mpu@4000d000 {
+			compatible = "nxp,k64f-mpu";
+			reg = <0x4000d000 0x824>;
+
+			status = "disabled";
+		};
+
+		mcg: clock-controller@40064000 {
+			compatible = "nxp,kinetis-mcg";
+			reg = <0x40064000 0xd>;
+			label = "MCG";
+			#clock-cells = <1>;
+		};
+
+		osc: clock-controller@40065000 {
+			compatible = "nxp,k64f-osc";
+			reg = <0x40065000 0x4>;
+
+			enable-external-reference;
+		};
+
+		rtc: rtc@4003d000 {
+			compatible = "nxp,kinetis-rtc";
+			reg = <0x4003d000 0x1000>;
+			interrupts = <46 0>, <47 0>;
+			interrupt-names = "alarm", "seconds";
+			clock-frequency = <32768>;
+			prescaler = <32768>;
+			label = "RTC_0";
+		};
+
+		sim: sim@40047000 {
+			compatible = "nxp,kinetis-sim";
+			reg = <0x40047000 0x1060>;
+			label = "SIM";
+			#clock-cells = <3>;
+
+			core_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <1>;
+				#clock-cells = <0>;
+			};
+
+			bus_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <2>;
+				#clock-cells = <0>;
+			};
+
+			flexbus_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <3>;
+				#clock-cells = <0>;
+			};
+
+			flash_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <5>;
+				#clock-cells = <0>;
+			};
+		};
+
+		ftfe: flash-controller@40020000 {
+			compatible = "nxp,kinetis-ftfe";
+			label = "FLASH_CTRL";
+			reg = <0x40020000 0x18>;
+			interrupts = <18 0>, <19 0>;
+			interrupt-names = "command-complete", "read-collision";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				label = "MCUX_FLASH";
+				reg = <0 DT_SIZE_M(1)>;
+				erase-block-size = <4096>;
+				write-block-size = <8>;
+			};
+		};
+
+		i2c0: i2c@40066000 {
+			compatible = "nxp,kinetis-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40066000 0x1000>;
+			interrupts = <24 0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
+			label = "I2C_0";
+			status = "disabled";
+		};
+
+		i2c1: i2c@40067000 {
+			compatible = "nxp,kinetis-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40067000 0x1000>;
+			interrupts = <25 0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
+			label = "I2C_1";
+			status = "disabled";
+		};
+
+		i2c2: i2c@400e6000 {
+			compatible = "nxp,kinetis-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x400e6000 0x1000>;
+			interrupts = <74 0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
+			label = "I2C_2";
+			status = "disabled";
+		};
+
+		uart0: uart@4006a000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006a000 0x1000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
+			label = "UART_0";
+
+			status = "disabled";
+		};
+
+		uart1: uart@4006b000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006b000 0x1000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
+			label = "UART_1";
+
+			status = "disabled";
+		};
+
+		uart2: uart@4006c000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006c000 0x1000>;
+			interrupts = <35 0>, <36 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
+			label = "UART_2";
+
+			status = "disabled";
+		};
+
+		uart3: uart@4006d000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006d000 0x1000>;
+			interrupts = <37 0>, <38 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
+			label = "UART_3";
+
+			status = "disabled";
+		};
+
+		uart4: uart@400ea000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x400ea000 0x1000>;
+			interrupts = <66 0>, <67 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
+			label = "UART_4";
+
+			status = "disabled";
+		};
+
+		uart5: uart@400eb000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x400eb000 0x1000>;
+			interrupts = <68 0>, <69 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
+			label = "UART_5";
+
+			status = "disabled";
+		};
+
+		porta: pinmux@40049000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x40049000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
+		};
+
+		portb: pinmux@4004a000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004a000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
+		};
+
+		portc: pinmux@4004b000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004b000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
+		};
+
+		portd: pinmux@4004c000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004c000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
+		};
+
+		porte: pinmux@4004d000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004d000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
+		};
+
+		gpioa: gpio@400ff000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff000 0x40>;
+			interrupts = <59 2>;
+			label = "GPIO_0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porta>;
+		};
+
+		gpiob: gpio@400ff040 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff040 0x40>;
+			interrupts = <60 2>;
+			label = "GPIO_1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portb>;
+		};
+
+		gpioc: gpio@400ff080 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff080 0x40>;
+			interrupts = <61 2>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portc>;
+		};
+
+		gpiod: gpio@400ff0c0 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff0c0 0x40>;
+			interrupts = <62 2>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portd>;
+		};
+
+		gpioe: gpio@400ff100 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x400ff100 0x40>;
+			interrupts = <63 2>;
+			label = "GPIO_4";
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porte>;
+		};
+
+		spi0: spi@4002c000 {
+			compatible = "nxp,kinetis-dspi";
+			reg = <0x4002c000 0x88>;
+			interrupts = <26 3>;
+			label = "SPI_0";
+			dmas = <&edma0 0 14>, <&edma0 0 15>;
+			dma-names = "rx", "tx";
+			rx-fifo-size = <4>;
+			tx-fifo-size = <4>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@4002d000 {
+			compatible = "nxp,kinetis-dspi";
+			reg = <0x4002d000 0x88>;
+			interrupts = <27 3>;
+			label = "SPI_1";
+			dmas = <&edma0 0 16>, <&edma0 0 16>;
+			dma-names = "rx", "tx";
+			rx-fifo-size = <1>;
+			tx-fifo-size = <1>;
+			nxp,rx-tx-chn-share;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi@400ac000 {
+			compatible = "nxp,kinetis-dspi";
+			reg = <0x400ac000 0x88>;
+			interrupts = <65 3>;
+			label = "SPI_2";
+			dmas = <&edma0 0 17>, <&edma0 0 17>;
+			dma-names = "rx", "tx";
+			rx-fifo-size = <1>;
+			tx-fifo-size = <1>;
+			nxp,rx-tx-chn-share;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		wdog: watchdog@40052000 {
+			compatible = "nxp,kinetis-wdog";
+			reg = <0x40052000 16>;
+			interrupts = <22 0>;
+			clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
+			label = "WDT_0";
+		};
+
+		ftm0: ftm@40038000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x40038000 0x98>;
+			interrupts = <42 0>;
+			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
+			prescaler = <16>;
+			label = "FTM_0";
+			status = "disabled";
+		};
+
+		ftm1: ftm@40039000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x40039000 0x98>;
+			interrupts = <43 0>;
+			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
+			prescaler = <16>;
+			label = "FTM_1";
+			status = "disabled";
+		};
+
+		ftm2: ftm@4003a000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x4003a000 0x98>;
+			interrupts = <44 0>;
+			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
+			prescaler = <16>;
+			label = "FTM_2";
+			status = "disabled";
+		};
+
+		ftm3: ftm@400b9000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x400b9000 0x98>;
+			interrupts = <71 0>;
+			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
+			prescaler = <16>;
+			label = "FTM_3";
+			status = "disabled";
+		};
+
+		adc0: adc@4003b000{
+			compatible = "nxp,kinetis-adc16";
+			reg = <0x4003b000 0x70>;
+			clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>,
+				<&sim KINETIS_SIM_SIM_SOPT7 7 0x80>;
+			dmas = <&edma0 0 40>;
+			dma-names = "adc0";
+			clk-source = <0>;
+			interrupts = <39 0>;
+			label = "ADC_0";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		adc1: adc@400bb000{
+			compatible = "nxp,kinetis-adc16";
+			reg = <0x400bb000 0x70>;
+			clocks = <&sim KINETIS_SIM_SIM_SOPT7 8 0xF00>,
+				<&sim KINETIS_SIM_SIM_SOPT7 15 0x8000>;
+			dmas = <&edma0 0 41>;
+			dma-names = "adc1";
+			clk-source = <0>;
+			interrupts = <73 0>;
+			label = "ADC_1";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		dac0: dac@400cc000 {
+			compatible = "nxp,kinetis-dac";
+			reg = <0x400cc000 0x1000>;
+			interrupts = <56 0>;
+			voltage-reference = <1>;
+			label = "DAC_0";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		dac1: dac@400cd000 {
+			compatible = "nxp,kinetis-dac";
+			reg = <0x400cd000 0x1000>;
+			interrupts = <72 0>;
+			voltage-reference = <1>;
+			label = "DAC_1";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		usbotg: usbd@40072000 {
+			compatible = "nxp,kinetis-usbd";
+			reg = <0x40072000 0x1000>;
+			interrupts = <53 1>;
+			interrupt-names = "usb_otg";
+			num-bidir-endpoints = <16>;
+			status = "disabled";
+			label = "USBD";
+		};
+
+		enet: ethernet@400c0000 {
+			compatible = "nxp,kinetis-ethernet";
+			reg = <0x400c0000 0x620>;
+			interrupts = <83 0>, <84 0>, <85 0>;
+			interrupt-names = "TX", "RX", "ERR";
+			status = "disabled";
+			label = "ETH_0";
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0 0>;
+			ptp {
+				compatible = "nxp,kinetis-ptp";
+				status = "disabled";
+				interrupts = <82 0>;
+				interrupt-names = "IEEE1588_TMR";
+			};
+		};
+
+		rnga: random@40029000 {
+			compatible = "nxp,kinetis-rnga";
+			reg = <0x40029000 0x1000>;
+			status = "okay";
+			interrupts = <23 0>;
+			label = "RNGA";
+		};
+
+		flexcan0: can@40024000 {
+			compatible = "nxp,kinetis-flexcan";
+			reg = <0x40024000 0x1000>;
+			interrupts = <75 0>, <76 0>, <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", "rx-warning", "wake-up";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 4>;
+			clk-source = <1>;
+			label = "CAN_0";
+			sjw = <1>;
+			sample-point = <875>;
+			status = "disabled";
+		};
+
+		edma0: dma-controller@40008000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <16>;
+			dma-requests = <64>;
+			nxp,mem2mem;
+			reg = <0x40008000 0x1000>,
+				<0x40021000 0x1000>;
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+			clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>,
+				<&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>;
+			status = "disabled";
+			label = "DMA_0";
+		};
+
+		pit0: pit@40037000 {
+			compatible = "nxp,kinetis-pit";
+			reg = <0x40037000 0x1000>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
+			interrupts = <48 0>, <49 0>, <50 0>, <51 0>;
+			status = "disabled";
+			pit-channel = <0>;
+			pit-period = <1000000>;
+			clock-frequency = <60000000>;
+			label = "PIT0";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/nxp/nxp_rt1060.dtsi b/dts/arm/nxp/nxp_rt1060.dtsi
new file mode 100644
index 0000000000..5e3eee8059
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt1060.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019, Linaro
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt.dtsi>
+
+/* i.MX rt1060 has two continuous on-chip RAM, one is part of the
+ * FlexRAM mapped at 0x20280000 (vs 0x20280000 on rt1050) and is
+ * configurable (256KB by defaults), the other one is dedicated 512KB
+ * ram (OCRAM2) mapped at 0x20200000. In order to have a continuous
+ * region, we describe them in one 768Kb unique node.
+ */
+&ocram {
+	compatible = "mmio-sram";
+	reg = <0x20200000 DT_SIZE_K(768)>;
+};
+
+/* i.MX rt1060 has a second Ethernet controller. */
+/ {
+	soc {
+		enet2: ethernet@402d4000 {
+			compatible = "nxp,kinetis-ethernet";
+			reg = <0x402D4000 0x628>;
+			interrupts = <152 0>;
+			interrupt-names = "COMMON";
+			status = "disabled";
+			label = "ETH_1";
+			ptp {
+				compatible = "nxp,kinetis-ptp";
+				status = "disabled";
+				interrupts = <153 0>;
+				interrupt-names = "IEEE1588_TMR";
+			};
+		};
+	};
+};
diff --git a/dts/arm/nxp/nxp_rt1064.dtsi b/dts/arm/nxp/nxp_rt1064.dtsi
new file mode 100644
index 0000000000..4f1f9f0bb2
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt1064.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019, Linaro
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt1060.dtsi>
+
+&flexspi2 {
+	reg = <0x402a4000 0x4000>, <0x70000000 DT_SIZE_M(4)>;
+	/* WINBOND */
+	w25q32jvwj0: w25q32jvwj@0 {
+		compatible = "nxp,imx-flexspi-nor";
+		size = <33554432>;
+		label = "W25Q32JVWJ0";
+		reg = <0>;
+		spi-max-frequency = <133000000>;
+		status = "okay";
+		jedec-id = [ef 40 16];
+		erase-block-size = <4096>;
+		write-block-size = <1>;
+	};
+};
diff --git a/dts/arm/nxp/nxp_rt1160_cm4.dtsi b/dts/arm/nxp/nxp_rt1160_cm4.dtsi
new file mode 100644
index 0000000000..c54c71f323
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt1160_cm4.dtsi
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt11xx.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	/*
+	 * SRAM0 & SRAM1 are available only to the M4 core. EDMA_LPSR interrupts are connected
+	 * to the M4 core alone, hence this EDMA controller has been designated M4 only.
+	 * GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are
+	 * only accesssible to the M4.
+	 *
+	 * Refer to Chapter 3 of the Reference Manual
+	 */
+	soc {
+		sram0: memory@1ffe0000 {
+			compatible = "mmio-sram";
+			reg = <0x1ffe0000 DT_SIZE_K(128)>;
+		};
+
+		sram1: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(128)>;
+		};
+
+		/*
+		 * M4 uses different addresses from the M7 core for GPIO2 and
+		 * GPIO3, see pg. 1364 of RT1160 ref manual for example
+		 */
+		gpio2: gpio@40130000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x40130000 0x4000>;
+			interrupts = <102 0>, <103 0>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@40134000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x40134000 0x4000>;
+			interrupts = <104 0>, <105 0>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		edma_lpsr0: dma-controller@40c14000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <32>;
+			dma-requests = <208>;
+			nxp,mem2mem;
+			nxp,a_on;
+			reg = <0x40c14000 0x4000>,
+				<0x40c18000 0x4000>;
+			clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
+			status = "disabled";
+			label = "DMA_0";
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+		};
+
+	};
+
+};
+
+
+&gpio9 {
+	interrupts = <99 0>;
+};
+
+&gpio11 {
+	/* GPIO 7-11 share the same interrupt on the CM4 */
+	interrupts = <99 0>;
+	status = "disabled";
+};
diff --git a/dts/arm/nxp/nxp_rt1160_cm7.dtsi b/dts/arm/nxp/nxp_rt1160_cm7.dtsi
new file mode 100644
index 0000000000..a589db0c54
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt1160_cm7.dtsi
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt11xx.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+	/*
+	 * ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected
+	 * to the M7 core alone, hence this EDMA controller has been designated M7 only.
+	 * GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is
+	 * only accesssible to the M7.
+	 *
+	 * Refer to Chapter 3 of the Reference Manual
+	 */
+	soc {
+		flexram: flexram@40028000 {
+			reg = <0x40028000 0x4000>;
+			interrupts = <50 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itcm: itcm@0 {
+				compatible = "nxp,imx-itcm";
+				reg = <0x00000000 DT_SIZE_K(256)>;
+			};
+
+			dtcm: dtcm@20000000 {
+				compatible = "nxp,imx-dtcm";
+				reg = <0x20000000 DT_SIZE_K(256)>;
+			};
+		};
+
+		/*
+		 * M7 uses different addresses from the M4 core for GPIO2 and
+		 * GPIO3, see pg. 1460 of RT1160 ref manual for example
+		 */
+		gpio2: gpio@42008000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x42008000 0x4000>;
+			interrupts = <102 0>, <103 0>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@4200c000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x4200c000 0x4000>;
+			interrupts = <104 0>, <105 0>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		edma0: dma-controller@40070000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <32>;
+			dma-requests = <208>;
+			nxp,mem2mem;
+			nxp,a_on;
+			reg = <0x40070000 0x4000>,
+				<0x40074000 0x4000>;
+			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
+				status = "disabled";
+			label = "DMA_0";
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+		};
+	};
+};
+
+&gpio6 {
+	interrupts = <61 0>, <62 0>;
+};
diff --git a/dts/arm/nxp/nxp_rt1170_cm4.dtsi b/dts/arm/nxp/nxp_rt1170_cm4.dtsi
new file mode 100644
index 0000000000..ab131cf8b8
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt1170_cm4.dtsi
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt11xx.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	/*
+	 * SRAM0 & SRAM1 are available only to the M4 core. EDMA_LPSR interrupts are connected
+	 * to the M4 core alone, hence this EDMA controller has been designated M4 only.
+	 * GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are
+	 * only accesssible to the M4.
+	 *
+	 * Refer to Chapter 3 of the Reference Manual
+	 */
+	soc {
+		sram0: memory@1ffe0000 {
+			compatible = "mmio-sram";
+			reg = <0x1ffe0000 DT_SIZE_K(128)>;
+		};
+
+		sram1: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(128)>;
+			zephyr,memory-region = "SRAM1";
+		};
+
+		/*
+		 * M4 uses different addresses from the M7 core for GPIO2 and
+		 * GPIO3, see pg. 1410 of RT1170 ref manual for example
+		 */
+		gpio2: gpio@40130000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x40130000 0x4000>;
+			interrupts = <102 0>, <103 0>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@40134000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x40134000 0x4000>;
+			interrupts = <104 0>, <105 0>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		edma_lpsr0: dma-controller@40c14000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <32>;
+			dma-requests = <208>;
+			nxp,mem2mem;
+			nxp,a_on;
+			reg = <0x40c14000 0x4000>,
+				<0x40c18000 0x4000>;
+			clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
+			status = "disabled";
+			label = "DMA_0";
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+		};
+	};
+};
+
+&gpio9 {
+	interrupts = <99 0>;
+};
+
+&gpio11 {
+	/* GPIO 7-11 share the same interrupt on the CM4 */
+	interrupts = <99 0>;
+	status = "disabled";
+};
diff --git a/dts/arm/nxp/nxp_rt1170_cm7.dtsi b/dts/arm/nxp/nxp_rt1170_cm7.dtsi
new file mode 100644
index 0000000000..33e794450f
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt1170_cm7.dtsi
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_rt11xx.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+	/*
+	 * ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected
+	 * to the M7 core alone, hence this EDMA controller has been designated M7 only.
+	 * GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is
+	 * only accesssible to the M7.
+	 *
+	 * Refer to Chapter 3 of the Reference Manual
+	 */
+	soc {
+		flexram: flexram@40028000 {
+			reg = <0x40028000 0x4000>;
+			interrupts = <50 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itcm: itcm@0 {
+				compatible = "nxp,imx-itcm";
+				reg = <0x00000000 DT_SIZE_K(256)>;
+				zephyr,memory-region = "ITCM";
+			};
+
+			dtcm: dtcm@20000000 {
+				compatible = "nxp,imx-dtcm";
+				reg = <0x20000000 DT_SIZE_K(256)>;
+				zephyr,memory-region = "DTCM";
+			};
+		};
+
+		/*
+		 * M7 uses different addresses from the M4 core for GPIO2 and
+		 * GPIO3, see pg. 1460 of RT1170 ref manual for example
+		 */
+		gpio2: gpio@42008000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x42008000 0x4000>;
+			interrupts = <102 0>, <103 0>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@4200c000 {
+			compatible = "nxp,imx-gpio";
+			reg = <0x4200c000 0x4000>;
+			interrupts = <104 0>, <105 0>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		edma0: dma-controller@40070000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			dma-channels = <32>;
+			dma-requests = <208>;
+			nxp,mem2mem;
+			nxp,a_on;
+			reg = <0x40070000 0x4000>,
+				<0x40074000 0x4000>;
+			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
+				status = "disabled";
+			label = "DMA_0";
+			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+				<4 0>, <5 0>, <6 0>, <7 0>,
+				<8 0>, <9 0>, <10 0>, <11 0>,
+				<12 0>, <13 0>, <14 0>, <15 0>,
+				<16 0>;
+		};
+	};
+};
+
+&gpio6 {
+	interrupts = <61 0>, <62 0>;
+};
diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi
new file mode 100644
index 0000000000..3d85472701
--- /dev/null
+++ b/dts/arm/st/f0/stm32f0.dtsi
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2017 RnDity Sp. z o.o.
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv6-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m0";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(40)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f0-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32f0-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <3 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <2>;
+				/* maximum erase time for a 2K sector */
+				max-erase-time = <40>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32f0-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@40010400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40010400 0x400>;
+		};
+
+		pinctrl: pin-controller@48000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x48000000 0x1800>;
+
+			gpioa: gpio@48000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@48000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@48000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
+				label = "GPIOD";
+			};
+
+			gpiof: gpio@48001400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
+				label = "GPIOF";
+			};
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
+			interrupts = <27 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <28 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <23 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
+			interrupts = <25 3>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			interrupts = <2 0>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 2>;
+			status = "disabled";
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
+			interrupts = <13 0>, <14 0>;
+			interrupt-names = "brk_up_trg_com", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <16 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <17 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <18 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <19 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
+			interrupts = <20 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
+			interrupts = <21 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
+			interrupts = <22 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
+			interrupts = <12 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			interrupts = <9 0 10 0 10 0 11 0 11 0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>;
+};
diff --git a/dts/arm/st/f0/stm32f030.dtsi b/dts/arm/st/f0/stm32f030.dtsi
new file mode 100644
index 0000000000..57d40f4aa6
--- /dev/null
+++ b/dts/arm/st/f0/stm32f030.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <1024>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f030X4.dtsi b/dts/arm/st/f0/stm32f030X4.dtsi
new file mode 100644
index 0000000000..a38ece02f0
--- /dev/null
+++ b/dts/arm/st/f0/stm32f030X4.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f0/stm32f030.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(4)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(16)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f030X8.dtsi b/dts/arm/st/f0/stm32f030X8.dtsi
new file mode 100644
index 0000000000..5de6e2678e
--- /dev/null
+++ b/dts/arm/st/f0/stm32f030X8.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f030.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f030Xc.dtsi b/dts/arm/st/f0/stm32f030Xc.dtsi
new file mode 100644
index 0000000000..f9aef0d058
--- /dev/null
+++ b/dts/arm/st/f0/stm32f030Xc.dtsi
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f0/stm32f030.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		/*
+		 * USARTs 3-6 share the same IRQ on stm32f030Xc devices. This
+		 * configuration is not currently supported, so at most one of
+		 * these may be enabled at a time. Enabling more than one will
+		 * result in a build failure.
+		 */
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		usart4: serial@40004c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		usart5: serial@40005000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		usart6: serial@40011400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f031.dtsi b/dts/arm/st/f0/stm32f031.dtsi
new file mode 100644
index 0000000000..04533d0d7f
--- /dev/null
+++ b/dts/arm/st/f0/stm32f031.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <1024>;
+			};
+		};
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <15 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f031X6.dtsi b/dts/arm/st/f0/stm32f031X6.dtsi
new file mode 100644
index 0000000000..373437a187
--- /dev/null
+++ b/dts/arm/st/f0/stm32f031X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f0/stm32f031.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(4)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f051.dtsi b/dts/arm/st/f0/stm32f051.dtsi
new file mode 100644
index 0000000000..3add1bac17
--- /dev/null
+++ b/dts/arm/st/f0/stm32f051.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018 Nathan Tsoi <nathan@vertile.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <1024>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f051X8.dtsi b/dts/arm/st/f0/stm32f051X8.dtsi
new file mode 100644
index 0000000000..0b2e8a8af4
--- /dev/null
+++ b/dts/arm/st/f0/stm32f051X8.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f051.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f070.dtsi b/dts/arm/st/f0/stm32f070.dtsi
new file mode 100644
index 0000000000..497cc9caae
--- /dev/null
+++ b/dts/arm/st/f0/stm32f070.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <2048>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <31 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			status = "disabled";
+			label= "USB";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/f0/stm32f070Xb.dtsi b/dts/arm/st/f0/stm32f070Xb.dtsi
new file mode 100644
index 0000000000..07d9924004
--- /dev/null
+++ b/dts/arm/st/f0/stm32f070Xb.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f070.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f072.dtsi b/dts/arm/st/f0/stm32f072.dtsi
new file mode 100644
index 0000000000..7e315e5a98
--- /dev/null
+++ b/dts/arm/st/f0/stm32f072.dtsi
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <2048>;
+			};
+		};
+
+		pinctrl: pin-controller@48000000 {
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				label = "GPIOE";
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <15 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <31 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			status = "disabled";
+			label= "USB";
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <30 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <250000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/f0/stm32f072Xb.dtsi b/dts/arm/st/f0/stm32f072Xb.dtsi
new file mode 100644
index 0000000000..2327558183
--- /dev/null
+++ b/dts/arm/st/f0/stm32f072Xb.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f072.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f091.dtsi b/dts/arm/st/f0/stm32f091.dtsi
new file mode 100644
index 0000000000..2fb7a456d6
--- /dev/null
+++ b/dts/arm/st/f0/stm32f091.dtsi
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) Bobby Noelte
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f0/stm32f0.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <2048>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <15 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		pinctrl: pin-controller@48000000 {
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				label = "GPIOE";
+			};
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020400 0x400>;
+			interrupts = <10 0 10 0 11 0 11 0 11 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f091Xc.dtsi b/dts/arm/st/f0/stm32f091Xc.dtsi
new file mode 100644
index 0000000000..a840f078c0
--- /dev/null
+++ b/dts/arm/st/f0/stm32f091Xc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f091.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f0/stm32f098Xc.dtsi b/dts/arm/st/f0/stm32f098Xc.dtsi
new file mode 100644
index 0000000000..d1028a6920
--- /dev/null
+++ b/dts/arm/st/f0/stm32f098Xc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2019 The Chromium OS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/f0/stm32f091.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi
new file mode 100644
index 0000000000..d6a577443f
--- /dev/null
+++ b/dts/arm/st/f1/stm32f1.dtsi
@@ -0,0 +1,333 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m3";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(40)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f1-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <3 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <2>;
+				/* maximum erase time for a 2K sector */
+				max-erase-time = <40>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@40010400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40010400 0x400>;
+		};
+
+		pinctrl: pin-controller@40010800 {
+			compatible = "st,stm32f1-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40010800 0x1C00>;
+
+			gpioa: gpio@40010800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40010800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000005>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@40010c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40010c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000009>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@40011000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40011000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000011>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@40011400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40011400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000021>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@40011800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40011800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000041>;
+				label = "GPIOE";
+			};
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 5>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/f1/stm32f100Xb.dtsi b/dts/arm/st/f1/stm32f100Xb.dtsi
new file mode 100644
index 0000000000..1dab11abfd
--- /dev/null
+++ b/dts/arm/st/f1/stm32f100Xb.dtsi
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2020 Jonas Eriksson, Up to Code AB
+ *
+ * SoC device tree include for STM32F100xB SoCs
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f1.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	clocks {
+		/delete-node/ pll;
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f100-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+				erase-block-size = <DT_SIZE_K(1)>;
+			};
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f1/stm32f100Xe.dtsi b/dts/arm/st/f1/stm32f100Xe.dtsi
new file mode 100644
index 0000000000..93736ed582
--- /dev/null
+++ b/dts/arm/st/f1/stm32f100Xe.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020 Jonas Eriksson, Up to Code AB
+ *
+ * SoC device tree include for STM32F100xE SoCs
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f100Xb.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+	};
+};
diff --git a/dts/arm/st/f1/stm32f103X8.dtsi b/dts/arm/st/f1/stm32f103X8.dtsi
new file mode 100644
index 0000000000..5692e6dceb
--- /dev/null
+++ b/dts/arm/st/f1/stm32f103X8.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f1.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+				erase-block-size = <DT_SIZE_K(1)>;
+			};
+		};
+
+		/* spi2 is present on all STM32F103x8 SoCs except
+		 * STM32F103T8. Delete node in stm32f103t8.dtsi.
+		 */
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <20 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <512>;
+			status = "disabled";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			phys = <&usb_fs_phy>;
+			label= "USB";
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/f1/stm32f103Xb.dtsi b/dts/arm/st/f1/stm32f103Xb.dtsi
new file mode 100644
index 0000000000..c25e34665e
--- /dev/null
+++ b/dts/arm/st/f1/stm32f103Xb.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 I-SENSE group of ICCS
+ *
+ * SoC device tree include for STM32F103xB SoCs
+ * where 'x' is replaced for specific SoCs like {C,R,T,V}
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f103X8.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+				erase-block-size = <DT_SIZE_K(1)>;
+			};
+		};
+
+		/* spi2 is present on all STM32F103xB SoCs except
+		 * STM32F103TB. Delete node in stm32f103tb.dtsi.
+		 */
+	};
+
+};
diff --git a/dts/arm/st/f1/stm32f103Xc.dtsi b/dts/arm/st/f1/stm32f103Xc.dtsi
new file mode 100644
index 0000000000..446534c387
--- /dev/null
+++ b/dts/arm/st/f1/stm32f103Xc.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2017 I-SENSE group of ICCS
+ *
+ * SoC device tree include for STM32F103xC SoCs
+ * where 'x' is replaced for specific SoCs like {R,V,Z}
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f103Xb.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(48)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+				erase-block-size = <DT_SIZE_K(2)>;
+			};
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0X40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			label = "SPI_3";
+			status = "disabled";
+		};
+
+		pinctrl: pin-controller@40010800 {
+			reg = <0x40010800 0x2000>;
+
+			gpiof: gpio@40011c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40011c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000081>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@40012000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40012000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000101>;
+				label = "GPIOG";
+			};
+		};
+
+		adc2: adc@40012800 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
+			/* Shares vector with ADC1 */
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_2";
+			#io-channel-cells = <1>;
+		};
+
+		adc3: adc@40013c00 {
+			compatible = "st,stm32-adc";
+			reg = <0x40013c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
+			interrupts = <47 0>;
+			status = "disabled";
+			label = "ADC_3";
+			#io-channel-cells = <1>;
+		};
+
+		timers8: timers@40013400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			interrupts = < 56 0 57 0 58 0 59 0 60 0>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f1/stm32f103Xd.dtsi b/dts/arm/st/f1/stm32f103Xd.dtsi
new file mode 100644
index 0000000000..2c3935473e
--- /dev/null
+++ b/dts/arm/st/f1/stm32f103Xd.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021 Teltonika
+ *
+ * SoC device tree include for STM32F103xD SoCs
+ * where 'x' is replaced for specific SoCs like {R,V,Z}
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f103Xc.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(384)>;
+				erase-block-size = <DT_SIZE_K(2)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f1/stm32f103Xe.dtsi b/dts/arm/st/f1/stm32f103Xe.dtsi
new file mode 100644
index 0000000000..18c0dcc83f
--- /dev/null
+++ b/dts/arm/st/f1/stm32f103Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2017 I-SENSE group of ICCS
+ *
+ * SoC device tree include for STM32F103xE SoCs
+ * where 'x' is replaced for specific SoCs like {R,V,Z}
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f103Xd.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+				erase-block-size = <DT_SIZE_K(2)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f1/stm32f103Xg.dtsi b/dts/arm/st/f1/stm32f103Xg.dtsi
new file mode 100644
index 0000000000..5a54ac75d1
--- /dev/null
+++ b/dts/arm/st/f1/stm32f103Xg.dtsi
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2020 Google, LLC
+ *
+ * SoC device tree include for STM32F103xG SoCs
+ * where 'x' is replaced for specific SoCs like {R,V,Z}
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f103Xe.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(96)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				/* Note that there are actually two banks of
+				 * flash (512KB each) and two flash controllers.
+				 * This matters if you're doing in-application
+				 * flash programming and you need the
+				 * read-while-write capabilities, but is
+				 * otherwise a non-issue.
+				 */
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+				erase-block-size = <DT_SIZE_K(2)>;
+			};
+		};
+
+		timers9: timers@40014c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
+			/* Shared with TIM1_BRK */
+			interrupts = <24 0>;
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_9";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_9";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers10: timers@40015000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			/* Shared with TIM1_UP */
+			interrupts = <25 0>;
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_10";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_10";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers11: timers@40015400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			/* Shared with TIM1_TRG_COM */
+			interrupts = <26 0>;
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_11";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_11";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers12: timers@40001800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			/* Shared with TIM8_BRK */
+			interrupts = <43 0>;
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_12";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_12";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers13: timers@40001c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			/* Shared with TIM8_UP */
+			interrupts = <44 0>;
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_13";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_13";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			/* Shared with TIM8_TRG_COM */
+			interrupts = <45 0>;
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+		};
+
+	};
+};
diff --git a/dts/arm/st/f1/stm32f105.dtsi b/dts/arm/st/f1/stm32f105.dtsi
new file mode 100644
index 0000000000..25cf9b0503
--- /dev/null
+++ b/dts/arm/st/f1/stm32f105.dtsi
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2019 Argentum Systems Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f1/stm32f1.dtsi>
+
+/ {
+	clocks {
+		/delete-node/ pll;
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f105-pll-clock";
+			status = "disabled";
+		};
+
+		pll2: pll2 {
+			#clock-cells = <0>;
+			compatible = "st,stm32f105-pll2-clock";
+			clocks = <&clk_hse>;
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <DT_SIZE_K(2)>;
+			};
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <250000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		can2: can@40006800 {
+			compatible = "st,stm32-can";
+			reg = <0x40006800 0x400>;
+			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "CAN_2";
+			bus-speed = <250000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		usbotg_fs: usb@50000000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "otgfs";
+			num-bidir-endpoints = <4>;
+			ram-size = <1280>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00001000>;
+			phys = <&otgfs_phy>;
+			status = "disabled";
+			label = "OTGFS";
+		};
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGFS_PHY";
+	};
+};
diff --git a/dts/arm/st/f1/stm32f105Xc.dtsi b/dts/arm/st/f1/stm32f105Xc.dtsi
new file mode 100644
index 0000000000..e2151b4454
--- /dev/null
+++ b/dts/arm/st/f1/stm32f105Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Argentum Systems Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f105.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f1/stm32f107.dtsi b/dts/arm/st/f1/stm32f107.dtsi
new file mode 100644
index 0000000000..60f8b4396f
--- /dev/null
+++ b/dts/arm/st/f1/stm32f107.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2017 I-SENSE group of ICCS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f1/stm32f105.dtsi>
+
+/ {
+	soc {
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			interrupts = <56 0 57 0 58 0 59 0 60 0>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f1/stm32f107Xc.dtsi b/dts/arm/st/f1/stm32f107Xc.dtsi
new file mode 100644
index 0000000000..ea7ad2e491
--- /dev/null
+++ b/dts/arm/st/f1/stm32f107Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f1/stm32f107.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi
new file mode 100644
index 0000000000..c30eeef0fc
--- /dev/null
+++ b/dts/arm/st/f2/stm32f2.dtsi
@@ -0,0 +1,570 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m3";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f2-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@40023c00 {
+			compatible = "st,stm32-flash-controller", "st,stm32f2-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40023c00 0x400>;
+			interrupts = <4 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <1>;
+				/* maximum erase time(ms) for a 128K sector */
+				max-erase-time = <4000>;
+			};
+		};
+
+		rcc: rcc@40023800 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40023800 0x400>;
+		};
+
+		exti: interrupt-controller@40013c00 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40013c00 0x400>;
+		};
+
+		pinctrl: pin-controller@40020000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40020000 0x2000>;
+
+			gpioa: gpio@40020000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@40020400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@40020800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@40020c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@40021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@40021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@40021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioh: gpio@40021c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
+				label = "GPIOH";
+			};
+
+			gpioi: gpio@40022000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+				label = "GPIOI";
+			};
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			interrupts = <41 0>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		usart1: serial@40011000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		usart6: serial@40011400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			interrupts = <71 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+
+		uart4: serial@40004c00 {
+			compatible ="st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 5>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c3: i2c@40005c00 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <72 0>, <73 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_3";
+		};
+
+		usbotg_fs: usb@50000000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "otgfs";
+			num-bidir-endpoints = <4>;
+			ram-size = <1280>;
+			maximum-speed = "full-speed";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+			phys = <&otgfs_phy>;
+			status = "disabled";
+			label = "OTGFS";
+		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40026000 {
+			compatible = "st,stm32-dma-v1";
+			#dma-cells = <4>;
+			reg = <0x40026000 0x400>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40026400 {
+			compatible = "st,stm32-dma-v1";
+			#dma-cells = <4>;
+			reg = <0x40026400 0x400>;
+			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
+			st,mem2mem;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		timers1: timers@40010000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers8: timers@40010400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers9: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <24 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_9";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_9";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers12: timers@40001800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			interrupts = <43 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_12";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_12";
+				#pwm-cells = <3>;
+			};
+		};
+
+		rng: rng@50060800 {
+			compatible = "st,stm32-rng";
+			reg = <0x50060800 0x400>;
+			interrupts = <80 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		backup_sram: memory@40024000 {
+			compatible = "st,stm32-backup-sram";
+			reg = <0x40024000 DT_SIZE_K(4)>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
+			status = "disabled";
+		};
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGFS_PHY";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/f2/stm32f205Xe.dtsi b/dts/arm/st/f2/stm32f205Xe.dtsi
new file mode 100644
index 0000000000..2a2723a3ca
--- /dev/null
+++ b/dts/arm/st/f2/stm32f205Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Manuel Forcen <manuforcen@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f2/stm32f2.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f2/stm32f207.dtsi b/dts/arm/st/f2/stm32f207.dtsi
new file mode 100644
index 0000000000..4f35e0969c
--- /dev/null
+++ b/dts/arm/st/f2/stm32f207.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f2/stm32f2.dtsi>
+
+/ {
+	soc {
+		mac: ethernet@40028000 {
+			compatible = "st,stm32-ethernet";
+			reg = <0x40028000 0x8000>;
+			label = "ETH_0";
+			interrupts = <61 0>;
+			clock-names = "stmmaceth", "mac-clk-tx",
+				      "mac-clk-rx", "mac-clk-ptp";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm/st/f2/stm32f207Xe.dtsi b/dts/arm/st/f2/stm32f207Xe.dtsi
new file mode 100644
index 0000000000..fc9f1669ed
--- /dev/null
+++ b/dts/arm/st/f2/stm32f207Xe.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f2/stm32f207.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f2/stm32f207Xg.dtsi b/dts/arm/st/f2/stm32f207Xg.dtsi
new file mode 100644
index 0000000000..4dfbbbd1c1
--- /dev/null
+++ b/dts/arm/st/f2/stm32f207Xg.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f2/stm32f207.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi
new file mode 100644
index 0000000000..165389b89f
--- /dev/null
+++ b/dts/arm/st/f3/stm32f3.dtsi
@@ -0,0 +1,413 @@
+/*
+ * Copyright (c) 2017 I-SENSE group of ICCS
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(40)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f0-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32f3-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <4 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <2>;
+				erase-block-size = <2048>;
+				/* maximum erase time for a 2K sector */
+				max-erase-time = <40>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@40010400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40010400 0x400>;
+		};
+
+		pinctrl: pin-controller@48000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x48000000 0x1800>;
+
+			gpioa: gpio@48000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@48000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@48000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
+				label = "GPIOD";
+			};
+
+			gpiof: gpio@48001400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
+				label = "GPIOF";
+			};
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 5>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <20 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <512>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			status = "disabled";
+			label= "USB";
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <24 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <25 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			interrupts = <41 0>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/f3/stm32f302.dtsi b/dts/arm/st/f3/stm32f302.dtsi
new file mode 100644
index 0000000000..646dc61a07
--- /dev/null
+++ b/dts/arm/st/f3/stm32f302.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2018 Seitz & Associates
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f3/stm32f3.dtsi>
+
+/ {
+	soc {
+		usb: usb@40005c00 {
+			/* Remap USB_LP IRQ to enable use with CAN_1 */
+			interrupts = <75 0>;
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c3: i2c@40007800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			interrupts = <72 0>, <73 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_3";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0X40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@50000000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/f3/stm32f302X8.dtsi b/dts/arm/st/f3/stm32f302X8.dtsi
new file mode 100644
index 0000000000..a0b1ea09ac
--- /dev/null
+++ b/dts/arm/st/f3/stm32f302X8.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018 Seitz & Associates
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f3/stm32f302.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
+
+/delete-node/ &spi1;
diff --git a/dts/arm/st/f3/stm32f303.dtsi b/dts/arm/st/f3/stm32f303.dtsi
new file mode 100644
index 0000000000..f5fd90ab02
--- /dev/null
+++ b/dts/arm/st/f3/stm32f303.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2017 I-SENSE group of ICCS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f3/stm32f3.dtsi>
+
+/ {
+	soc {
+		usb: usb@40005c00 {
+			/* Remap USB_LP IRQ to enable use with CAN_1 */
+			interrupts = <75 0>;
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		pinctrl: pin-controller@48000000 {
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				label = "GPIOE";
+			};
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers8: timers@40013400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers20: timers@40015000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_20";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_20";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@50000000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/f3/stm32f303X8.dtsi b/dts/arm/st/f3/stm32f303X8.dtsi
new file mode 100644
index 0000000000..a141afdc9d
--- /dev/null
+++ b/dts/arm/st/f3/stm32f303X8.dtsi
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
+ *                    Fabian Paschke <fabian.paschke@eas.iis.fraunhofer.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f3/stm32f303.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(8)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(12)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+
+		dac2: dac@40009800 {
+			compatible = "st,stm32-dac";
+			reg = <0x40009800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "DAC_2";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/f3/stm32f303Xc.dtsi b/dts/arm/st/f3/stm32f303Xc.dtsi
new file mode 100644
index 0000000000..7b64ab0de6
--- /dev/null
+++ b/dts/arm/st/f3/stm32f303Xc.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f3/stm32f303.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(8)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(40)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			interrupts = <56 0 57 0 58 0 59 0 60 0>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f3/stm32f303Xe.dtsi b/dts/arm/st/f3/stm32f303Xe.dtsi
new file mode 100644
index 0000000000..75f61615ca
--- /dev/null
+++ b/dts/arm/st/f3/stm32f303Xe.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020 Paul M. Bendixen
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f3/stm32f303.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40020400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			interrupts = <56 0 57 0 58 0 59 0 60 0>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f3/stm32f334.dtsi b/dts/arm/st/f3/stm32f334.dtsi
new file mode 100644
index 0000000000..eee55fa08c
--- /dev/null
+++ b/dts/arm/st/f3/stm32f334.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f3/stm32f3.dtsi>
+
+/ {
+	soc {
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@50000000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+	};
+};
+
+/delete-node/ &usb;
diff --git a/dts/arm/st/f3/stm32f334X8.dtsi b/dts/arm/st/f3/stm32f334X8.dtsi
new file mode 100644
index 0000000000..d220d4203f
--- /dev/null
+++ b/dts/arm/st/f3/stm32f334X8.dtsi
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f3/stm32f334.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(12)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+
+		dac2: dac@40009800 {
+			compatible = "st,stm32-dac";
+			reg = <0x40009800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "DAC_2";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/f3/stm32f373.dtsi b/dts/arm/st/f3/stm32f373.dtsi
new file mode 100644
index 0000000000..b8669cd572
--- /dev/null
+++ b/dts/arm/st/f3/stm32f373.dtsi
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f3/stm32f3.dtsi>
+
+/ {
+	soc {
+		pinctrl: pin-controller@48000000 {
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				label = "GPIOE";
+			};
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers12: timers@40001800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			interrupts = <43 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_12";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_12";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers13: timers@40001c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			interrupts = <44 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_13";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_13";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers18: timers@40009c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40009c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
+			interrupts = <27 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_18";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_18";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers19: timers@40015c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
+			interrupts = <78 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_19";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_19";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+	};
+};
diff --git a/dts/arm/st/f3/stm32f373Xc.dtsi b/dts/arm/st/f3/stm32f373Xc.dtsi
new file mode 100644
index 0000000000..9c0355197b
--- /dev/null
+++ b/dts/arm/st/f3/stm32f373Xc.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f3/stm32f373.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2bis";
+			reg = <0x40020400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			interrupts = <56 0 57 0 58 0 59 0 60 0>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dac2: dac@40009800 {
+			compatible = "st,stm32-dac";
+			reg = <0x40009800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "DAC_2";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi
new file mode 100644
index 0000000000..fbab3ff4fb
--- /dev/null
+++ b/dts/arm/st/f4/stm32f4.dtsi
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f4-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@40023c00 {
+			compatible = "st,stm32-flash-controller", "st,stm32f4-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40023c00 0x400>;
+			interrupts = <4 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <1>;
+				/* maximum erase time (ms) for a 128K sector */
+				max-erase-time = <4000>;
+			};
+		};
+
+		rcc: rcc@40023800 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40023800 0x400>;
+		};
+
+		exti: interrupt-controller@40013c00 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40013c00 0x400>;
+		};
+
+		pinctrl: pin-controller@40020000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40020000 0x2000>;
+
+			gpioa: gpio@40020000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@40020400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@40020800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@40020c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@40021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@40021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@40021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioh: gpio@40021c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
+				label = "GPIOH";
+			};
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		usart1: serial@40011000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart6: serial@40011400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			interrupts = <71 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c3: i2c@40005c00 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <72 0>, <73 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_3";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 5>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		usbotg_fs: usb@50000000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "otgfs";
+			num-bidir-endpoints = <4>;
+			ram-size = <1280>;
+			maximum-speed = "full-speed";
+			phys = <&otgfs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+			status = "disabled";
+			label= "OTGFS";
+		};
+
+		timers1: timers@40010000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_2";
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_3";
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_4";
+			};
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_5";
+			};
+		};
+
+		timers9: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <24 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_9";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_9";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_9";
+			};
+		};
+
+		timers10: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <25 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_10";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_10";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_10";
+			};
+		};
+
+		timers11: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_11";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_11";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_11";
+			};
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			interrupts = <41 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40026000 {
+			compatible = "st,stm32-dma-v1";
+			#dma-cells = <4>;
+			reg = <0x40026000 0x400>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40026400 {
+			compatible = "st,stm32-dma-v1";
+			#dma-cells = <4>;
+			reg = <0x40026400 0x400>;
+			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
+			st,mem2mem;
+			status = "disabled";
+			label = "DMA_2";
+		};
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGFS_PHY";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/f4/stm32f401.dtsi b/dts/arm/st/f4/stm32f401.dtsi
new file mode 100644
index 0000000000..7c58c4e265
--- /dev/null
+++ b/dts/arm/st/f4/stm32f401.dtsi
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f4.dtsi>
+
+/ {
+	soc {
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		spi4: spi@40013400 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <84 5>;
+			status = "disabled";
+			label = "SPI_4";
+		};
+
+		i2s2: i2s@40003800 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			dmas = <&dma1 4 0 0x400 0x3
+				&dma1 3 0 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_2";
+		};
+
+		i2s3: i2s@40003c00 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			dmas = <&dma1 5 0 0x400 0x3
+				&dma1 0 0 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_3";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f401Xc.dtsi b/dts/arm/st/f4/stm32f401Xc.dtsi
new file mode 100644
index 0000000000..3d733a124a
--- /dev/null
+++ b/dts/arm/st/f4/stm32f401Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Linumiz
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f401.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f401Xe.dtsi b/dts/arm/st/f4/stm32f401Xe.dtsi
new file mode 100644
index 0000000000..087bcb9469
--- /dev/null
+++ b/dts/arm/st/f4/stm32f401Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f401.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(96)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f405.dtsi b/dts/arm/st/f4/stm32f405.dtsi
new file mode 100644
index 0000000000..fc6e3bfe50
--- /dev/null
+++ b/dts/arm/st/f4/stm32f405.dtsi
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f401.dtsi>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+	};
+
+	soc {
+		pinctrl: pin-controller@40020000 {
+			reg = <0x40020000 0x2400>;
+
+			gpiof: gpio@40021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@40021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioi: gpio@40022000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+				label = "GPIOI";
+			};
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible ="st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_6";
+			};
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_7";
+			};
+		};
+
+		timers8: timers@40010400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers12: timers@40001800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			interrupts = <43 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_12";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_12";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_12";
+			};
+		};
+
+		timers13: timers@40001c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			interrupts = <44 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_13";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_13";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_13";
+			};
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_14";
+			};
+		};
+
+		usbotg_hs: usb@40040000 {
+			compatible = "st,stm32-otghs";
+			reg = <0x40040000 0x40000>;
+			interrupts = <77 0>, <74 0>, <75 0>;
+			interrupt-names = "otghs", "ep1_out", "ep1_in";
+			num-bidir-endpoints = <6>;
+			ram-size = <4096>;
+			maximum-speed = "full-speed";
+			phys = <&otghs_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
+			status = "disabled";
+			label= "OTGHS";
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		can2: can@40006800 {
+			compatible = "st,stm32-can";
+			reg = <0x40006800 0x400>;
+			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
+			master-can-reg = <0x40006400>;
+			status = "disabled";
+			label = "CAN_2";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		rng: rng@50060800 {
+			compatible = "st,stm32-rng";
+			reg = <0x50060800 0x400>;
+			interrupts = <80 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		backup_sram: memory@40024000 {
+			compatible = "st,stm32-backup-sram";
+			reg = <0x40024000 DT_SIZE_K(4)>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
+			status = "disabled";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+	};
+
+	otghs_fs_phy: otghs_fs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGHS_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/f4/stm32f405Xg.dtsi b/dts/arm/st/f4/stm32f405Xg.dtsi
new file mode 100644
index 0000000000..3c2433a1a3
--- /dev/null
+++ b/dts/arm/st/f4/stm32f405Xg.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f405.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f407.dtsi b/dts/arm/st/f4/stm32f407.dtsi
new file mode 100644
index 0000000000..33e8a559d2
--- /dev/null
+++ b/dts/arm/st/f4/stm32f407.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f405.dtsi>
+
+/ {
+	soc {
+		mac: ethernet@40028000 {
+			compatible = "st,stm32-ethernet";
+			reg = <0x40028000 0x8000>;
+			label = "ETH_0";
+			interrupts = <61 0>;
+			clock-names = "stmmaceth", "mac-clk-tx",
+				      "mac-clk-rx", "mac-clk-ptp";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f407Xe.dtsi b/dts/arm/st/f4/stm32f407Xe.dtsi
new file mode 100644
index 0000000000..b95524130b
--- /dev/null
+++ b/dts/arm/st/f4/stm32f407Xe.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f407.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f407Xg.dtsi b/dts/arm/st/f4/stm32f407Xg.dtsi
new file mode 100644
index 0000000000..f67cbf096e
--- /dev/null
+++ b/dts/arm/st/f4/stm32f407Xg.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f407.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f410.dtsi b/dts/arm/st/f4/stm32f410.dtsi
new file mode 100644
index 0000000000..5ec6f224e0
--- /dev/null
+++ b/dts/arm/st/f4/stm32f410.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2020 Hans Unzner
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f4.dtsi>
+
+/ {
+	soc {
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi5: spi@40015000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <85 5>;
+			status = "disabled";
+			label = "SPI_5";
+		};
+
+		i2s1: i2s@40013000 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 5>;
+			dmas = <&dma2 3 3 0x400 0x3
+				&dma2 2 3 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_1";
+		};
+
+		i2s2: i2s@40003800 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			dmas = <&dma1 4 0 0x400 0x3
+				&dma1 3 0 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_2";
+		};
+
+		i2s5: i2s@40015000 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <85 5>;
+			dmas = <&dma2 6 7 0x400 0x3
+				&dma2 5 7 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_5";
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_6";
+			};
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+	};
+
+};
diff --git a/dts/arm/st/f4/stm32f410Xb.dtsi b/dts/arm/st/f4/stm32f410Xb.dtsi
new file mode 100644
index 0000000000..954f2c99e0
--- /dev/null
+++ b/dts/arm/st/f4/stm32f410Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Hans Unzner
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f410.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f411.dtsi b/dts/arm/st/f4/stm32f411.dtsi
new file mode 100644
index 0000000000..0daf3e5d2f
--- /dev/null
+++ b/dts/arm/st/f4/stm32f411.dtsi
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f401.dtsi>
+
+/ {
+	soc {
+		spi5: spi@40015000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <85 5>;
+			status = "disabled";
+			label = "SPI_5";
+		};
+
+		i2s1: i2s@40013000 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 5>;
+			dmas = <&dma2 3 3 0x400 0x3
+				&dma2 2 3 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_1";
+		};
+
+		i2s4: i2s@40013400 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <84 5>;
+			dmas = <&dma2 1 4 0x400 0x3
+				&dma2 0 4 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_4";
+		};
+
+		i2s5: i2s@40015000 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <85 5>;
+			dmas = <&dma2 6 7 0x400 0x3
+				&dma2 5 7 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_5";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f411Xe.dtsi b/dts/arm/st/f4/stm32f411Xe.dtsi
new file mode 100644
index 0000000000..bc9e8b2c2e
--- /dev/null
+++ b/dts/arm/st/f4/stm32f411Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f411.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f412.dtsi b/dts/arm/st/f4/stm32f412.dtsi
new file mode 100644
index 0000000000..9c6f1734b8
--- /dev/null
+++ b/dts/arm/st/f4/stm32f412.dtsi
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2017 Florian Vaussard, HEIG-VD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f411.dtsi>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+	};
+
+	soc {
+		pinctrl: pin-controller@40020000 {
+			reg = <0x40020000 0x1c00>;
+
+			gpiof: gpio@40021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@40021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				label = "GPIOG";
+			};
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_6";
+			};
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_7";
+			};
+		};
+
+		timers8: timers@40010400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers12: timers@40001800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			interrupts = <43 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_12";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_12";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_12";
+			};
+		};
+
+		timers13: timers@40001c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			interrupts = <44 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_13";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_13";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_13";
+			};
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+				label = "COUNTER_14";
+			};
+		};
+
+		rng: rng@50060800 {
+			compatible = "st,stm32-rng";
+			reg = <0x50060800 0x400>;
+			interrupts = <80 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		usbotg_fs: usb@50000000 {
+			num-bidir-endpoints = <6>;
+		};
+
+		quadspi: quadspi@a0001000 {
+			compatible = "st,stm32-qspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			reg = <0xa0001000 0x400>;
+			interrupts = <92 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000002>;
+			status = "disabled";
+			label = "QUADSPI";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f412Xe.dtsi b/dts/arm/st/f4/stm32f412Xe.dtsi
new file mode 100644
index 0000000000..764ba77d55
--- /dev/null
+++ b/dts/arm/st/f4/stm32f412Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f412.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(256)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f412Xg.dtsi b/dts/arm/st/f4/stm32f412Xg.dtsi
new file mode 100644
index 0000000000..a6958857db
--- /dev/null
+++ b/dts/arm/st/f4/stm32f412Xg.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f412.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(256)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f413.dtsi b/dts/arm/st/f4/stm32f413.dtsi
new file mode 100644
index 0000000000..efb2262951
--- /dev/null
+++ b/dts/arm/st/f4/stm32f413.dtsi
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2017 Florian Vaussard, HEIG-VD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f412.dtsi>
+
+/ {
+	soc {
+		uart4: serial@40004c00 {
+			compatible ="st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		uart7: serial@40007800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			interrupts = <82 0>;
+			status = "disabled";
+			label = "UART_7";
+		};
+
+		uart8: serial@40007c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			interrupts = <83 0>;
+			status = "disabled";
+			label = "UART_8";
+		};
+
+		uart9: serial@40011800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40011800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
+			interrupts = <88 0>;
+			status = "disabled";
+			label = "UART_9";
+		};
+
+		uart10: serial@40011c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			interrupts = <89 0>;
+			status = "disabled";
+			label = "UART_10";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f413Xg.dtsi b/dts/arm/st/f4/stm32f413Xg.dtsi
new file mode 100644
index 0000000000..62a8029fc4
--- /dev/null
+++ b/dts/arm/st/f4/stm32f413Xg.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f413.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(320)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f413Xh.dtsi b/dts/arm/st/f4/stm32f413Xh.dtsi
new file mode 100644
index 0000000000..6e79b06b78
--- /dev/null
+++ b/dts/arm/st/f4/stm32f413Xh.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f413.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(320)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1536)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f415.dtsi b/dts/arm/st/f4/stm32f415.dtsi
new file mode 100644
index 0000000000..ab3113fd42
--- /dev/null
+++ b/dts/arm/st/f4/stm32f415.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019, Kwon Tae-young <tykwon@m2i.co.kr>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f405.dtsi>
+
+/ {
+	soc {
+		cryp: cryp@50060000 {
+			compatible = "st,stm32-cryp";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			interrupts = <79 0>;
+			status = "disabled";
+			label = "CRYP";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f415Rg.dtsi b/dts/arm/st/f4/stm32f415Rg.dtsi
new file mode 100644
index 0000000000..52290ff5f4
--- /dev/null
+++ b/dts/arm/st/f4/stm32f415Rg.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, Kwon Tae-young <tykwon@m2i.co.kr>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f415.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f417.dtsi b/dts/arm/st/f4/stm32f417.dtsi
new file mode 100644
index 0000000000..697580d627
--- /dev/null
+++ b/dts/arm/st/f4/stm32f417.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f407.dtsi>
+
+/ {
+	soc {
+		cryp: cryp@50060000 {
+			compatible = "st,stm32-cryp";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			interrupts = <79 0>;
+			status = "disabled";
+			label = "CRYP";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f417Xe.dtsi b/dts/arm/st/f4/stm32f417Xe.dtsi
new file mode 100644
index 0000000000..54f5dbfff5
--- /dev/null
+++ b/dts/arm/st/f4/stm32f417Xe.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f417.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f417Xg.dtsi b/dts/arm/st/f4/stm32f417Xg.dtsi
new file mode 100644
index 0000000000..a133e270ed
--- /dev/null
+++ b/dts/arm/st/f4/stm32f417Xg.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f417.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f427.dtsi b/dts/arm/st/f4/stm32f427.dtsi
new file mode 100644
index 0000000000..4699fa10ec
--- /dev/null
+++ b/dts/arm/st/f4/stm32f427.dtsi
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f407.dtsi>
+#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40020000 {
+			reg = <0x40020000 0x2C00>;
+
+			gpioj: gpio@40022400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				label = "GPIOK";
+			};
+		};
+
+		uart7: serial@40007800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			interrupts = <82 0>;
+			status = "disabled";
+			label = "UART_7";
+		};
+
+		uart8: serial@40007c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			interrupts = <83 0>;
+			status = "disabled";
+			label = "UART_8";
+		};
+
+		spi4: spi@40013400 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <84 5>;
+			status = "disabled";
+			label = "SPI_4";
+		};
+
+		/* spi5 is present on all STM32F429XX SoCs except
+		 * STM32F429vX SoCs. Delete node in stm32f429vX.dtsi.
+		 */
+		 spi5: spi@40015000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <85 5>;
+			status = "disabled";
+			label = "SPI_5";
+		};
+
+		/* spi6 is present on all STM32F429XX SoCs except
+		 * STM32F429vX SoCs. Delete node in stm32f429vX.dtsi.
+		 */
+		spi6: spi@40015400 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			interrupts = <86 5>;
+			status = "disabled";
+			label = "SPI_6";
+		};
+
+		fmc: memory-controller@a0000000 {
+			compatible = "st,stm32-fmc";
+			reg = <0xa0000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+			label = "STM32_FMC";
+			status = "disabled";
+
+			sdram: sdram {
+				compatible = "st,stm32-fmc-sdram";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				label = "STM32_FMC_SDRAM";
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f427Xi.dtsi b/dts/arm/st/f4/stm32f427Xi.dtsi
new file mode 100644
index 0000000000..01b56ee6bb
--- /dev/null
+++ b/dts/arm/st/f4/stm32f427Xi.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f427.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f427vX.dtsi b/dts/arm/st/f4/stm32f427vX.dtsi
new file mode 100644
index 0000000000..b254effcf6
--- /dev/null
+++ b/dts/arm/st/f4/stm32f427vX.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f427.dtsi>
+
+/delete-node/ &spi5;
+
+/delete-node/ &spi6;
diff --git a/dts/arm/st/f4/stm32f427vi.dtsi b/dts/arm/st/f4/stm32f427vi.dtsi
new file mode 100644
index 0000000000..30f517cf7b
--- /dev/null
+++ b/dts/arm/st/f4/stm32f427vi.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f427vX.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
+
diff --git a/dts/arm/st/f4/stm32f429.dtsi b/dts/arm/st/f4/stm32f429.dtsi
new file mode 100644
index 0000000000..8a0fa50191
--- /dev/null
+++ b/dts/arm/st/f4/stm32f429.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2017, 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f427.dtsi>
+
+/ {
+	soc {
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f429Xi.dtsi b/dts/arm/st/f4/stm32f429Xi.dtsi
new file mode 100644
index 0000000000..7d46ef3514
--- /dev/null
+++ b/dts/arm/st/f4/stm32f429Xi.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f429.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f429vX.dtsi b/dts/arm/st/f4/stm32f429vX.dtsi
new file mode 100644
index 0000000000..afa86f77bb
--- /dev/null
+++ b/dts/arm/st/f4/stm32f429vX.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Daniel Wagenknecht
+ *
+ * Document the usage of /delete-node/ for device tree nodes
+ * that are missing on on only a small subset of SoCs of a given group
+ * of SoCs.
+ * Don't remove this file even if none of the SoCs currently
+ * implemented in zephyr use it.
+ *
+ * spi5 and spi6 are present on all STM32F429XX SoCs except
+ * STM32F429vX SoCs, so they are defined in stm32f429.dtsi and deleted
+ * here.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f429.dtsi>
+
+/delete-node/ &spi5;
+
+/delete-node/ &spi6;
diff --git a/dts/arm/st/f4/stm32f429vi.dtsi b/dts/arm/st/f4/stm32f429vi.dtsi
new file mode 100644
index 0000000000..878ecf0e99
--- /dev/null
+++ b/dts/arm/st/f4/stm32f429vi.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f429vX.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
+
diff --git a/dts/arm/st/f4/stm32f437.dtsi b/dts/arm/st/f4/stm32f437.dtsi
new file mode 100644
index 0000000000..3bb8947ed8
--- /dev/null
+++ b/dts/arm/st/f4/stm32f437.dtsi
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f407.dtsi>
+#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40020000 {
+			reg = <0x40020000 0x2C00>;
+
+			gpioj: gpio@40022400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				label = "GPIOK";
+			};
+		};
+
+		uart7: serial@40007800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			interrupts = <82 0>;
+			status = "disabled";
+			label = "UART_7";
+		};
+
+		uart8: serial@40007c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			interrupts = <83 0>;
+			status = "disabled";
+			label = "UART_8";
+		};
+
+		spi4: spi@40013400 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013400 0x400>;
+			interrupts = <84 5>;
+			status = "disabled";
+			label = "SPI_4";
+		};
+
+		/* spi5 is present on all STM32F437XX SoCs except
+		 * STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
+		 */
+		 spi5: spi@40015000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015000 0x400>;
+			interrupts = <85 5>;
+			status = "disabled";
+			label = "SPI_5";
+		};
+
+		/* spi6 is present on all STM32F437XX SoCs except
+		 * STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
+		 */
+		spi6: spi@40015400 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015400 0x400>;
+			interrupts = <86 5>;
+			status = "disabled";
+			label = "SPI_6";
+		};
+
+		fmc: memory-controller@a0000000 {
+			compatible = "st,stm32-fmc";
+			reg = <0xa0000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+			label = "STM32_FMC";
+			status = "disabled";
+
+			sdram: sdram {
+				compatible = "st,stm32-fmc-sdram";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				label = "STM32_FMC_SDRAM";
+				status = "disabled";
+			};
+		};
+
+		cryp: cryp@50060000 {
+			compatible = "st,stm32-cryp";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			interrupts = <79 0>;
+			status = "disabled";
+			label = "CRYP";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f437Xi.dtsi b/dts/arm/st/f4/stm32f437Xi.dtsi
new file mode 100644
index 0000000000..232199ff57
--- /dev/null
+++ b/dts/arm/st/f4/stm32f437Xi.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f437.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f437vX.dtsi b/dts/arm/st/f4/stm32f437vX.dtsi
new file mode 100644
index 0000000000..f4d2310c6e
--- /dev/null
+++ b/dts/arm/st/f4/stm32f437vX.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f437.dtsi>
+
+/delete-node/ &spi5;
+
+/delete-node/ &spi6;
diff --git a/dts/arm/st/f4/stm32f446.dtsi b/dts/arm/st/f4/stm32f446.dtsi
new file mode 100644
index 0000000000..35ce30f255
--- /dev/null
+++ b/dts/arm/st/f4/stm32f446.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2018 Philémon Jaermann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f401.dtsi>
+#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
+
+/ {
+	soc {
+		i2s1: i2s@40013000 {
+			compatible = "st,stm32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 5>;
+			dmas = <&dma2 3 3 0x400 0x3
+				&dma2 2 3 0x400 0x3>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+			label = "I2S_1";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible ="st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		can2: can@40006800 {
+			compatible = "st,stm32-can";
+			reg = <0x40006800 0x400>;
+			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			master-can-reg = <0x40006400>;
+			status = "disabled";
+			label = "CAN_2";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <5>;
+			phase-seg2 = <6>;
+		};
+
+		usbotg_fs: usb@50000000 {
+			num-bidir-endpoints = <6>;
+		};
+
+		usbotg_hs: usb@40040000 {
+			compatible = "st,stm32-otghs";
+			reg = <0x40040000 0x40000>;
+			interrupts = <77 0>, <74 0>, <75 0>;
+			interrupt-names = "otghs", "ep1_out", "ep1_in";
+			num-bidir-endpoints = <9>;
+			ram-size = <4096>;
+			maximum-speed = "full-speed";
+			phys = <&otghs_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
+			status = "disabled";
+			label= "OTGHS";
+		};
+
+		backup_sram: memory@40024000 {
+			compatible = "st,stm32-backup-sram";
+			reg = <0x40024000 DT_SIZE_K(4)>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
+			status = "disabled";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		fmc: memory-controller@a0000000 {
+			compatible = "st,stm32-fmc";
+			reg = <0xa0000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+			label = "STM32_FMC";
+			status = "disabled";
+
+			sdram: sdram {
+				compatible = "st,stm32-fmc-sdram";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				label = "STM32_FMC_SDRAM";
+				status = "disabled";
+			};
+		};
+	};
+
+	otghs_fs_phy: otghs_fs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGHS_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/f4/stm32f446Xe.dtsi b/dts/arm/st/f4/stm32f446Xe.dtsi
new file mode 100644
index 0000000000..e1c9929ef4
--- /dev/null
+++ b/dts/arm/st/f4/stm32f446Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f446.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f469.dtsi b/dts/arm/st/f4/stm32f469.dtsi
new file mode 100644
index 0000000000..9559824219
--- /dev/null
+++ b/dts/arm/st/f4/stm32f469.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f429.dtsi>
+
+/ {
+	soc {
+		usbotg_fs: usb@50000000 {
+			num-bidir-endpoints = <6>;
+		};
+
+		usbotg_hs: usb@40040000 {
+			num-bidir-endpoints = <9>;
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f469Xi.dtsi b/dts/arm/st/f4/stm32f469Xi.dtsi
new file mode 100644
index 0000000000..24fc34a016
--- /dev/null
+++ b/dts/arm/st/f4/stm32f469Xi.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f469.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(320)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi
new file mode 100644
index 0000000000..7ed878631c
--- /dev/null
+++ b/dts/arm/st/f7/stm32f7.dtsi
@@ -0,0 +1,775 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m7";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32f7-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		fmc: memory-controller@a0000000 {
+			compatible = "st,stm32-fmc";
+			reg = <0xa0000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+			label = "STM32_FMC";
+			status = "disabled";
+
+			sdram: sdram {
+				compatible = "st,stm32-fmc-sdram";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				label = "STM32_FMC_SDRAM";
+				status = "disabled";
+			};
+		};
+
+		flash: flash-controller@40023c00 {
+			compatible = "st,stm32-flash-controller", "st,stm32f7-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40023c00 0x400>;
+			interrupts = <4 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <1>;
+				/* maximum erase time (ms) for a 256K sector */
+				max-erase-time = <4000>;
+			};
+		};
+
+		rcc: rcc@40023800 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40023800 0x400>;
+		};
+
+		exti: interrupt-controller@40013c00 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40013c00 0x400>;
+		};
+
+		pinctrl: pin-controller@40020000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40020000 0x2400>;
+
+			gpioa: gpio@40020000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@40020400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@40020800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@40020C00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020C00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@40021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@40021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@40021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioh: gpio@40021C00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021C00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
+				label = "GPIOH";
+			};
+
+			gpioi: gpio@40022000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+				label = "GPIOI";
+			};
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		usart1: serial@40011000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible ="st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		usart6: serial@40011400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			interrupts = <71 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+
+		uart7: serial@40007800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			interrupts = <82 0>;
+			status = "disabled";
+			label = "UART_7";
+		};
+
+		uart8: serial@40007c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			interrupts = <83 0>;
+			status = "disabled";
+			label = "UART_8";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_2";
+		};
+
+		i2c3: i2c@40005c00 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <72 0>, <73 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_3";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 5>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		spi4: spi@40013400 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <84 5>;
+			status = "disabled";
+			label = "SPI_4";
+		};
+
+		spi5: spi@40015000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <85 5>;
+			status = "disabled";
+			label = "SPI_5";
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			status = "disabled";
+			label = "CAN_1";
+		};
+
+		timers1: timers@40010000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers8: timers@40010400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers9: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <24 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_9";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_9";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers10: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <25 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_10";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_10";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers11: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_11";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_11";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers12: timers@40001800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			interrupts = <43 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_12";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_12";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers13: timers@40001c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			interrupts = <44 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_13";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_13";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+		};
+
+		usbotg_fs: usb@50000000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "otgfs";
+			num-bidir-endpoints = <6>;
+			ram-size = <1280>;
+			maximum-speed = "full-speed";
+			phys = <&otgfs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+			status = "disabled";
+			label = "OTGFS";
+		};
+
+		usbotg_hs: usb@40040000 {
+			compatible = "st,stm32-otghs";
+			reg = <0x40040000 0x40000>;
+			interrupts = <77 0>, <74 0>, <75 0>;
+			interrupt-names = "otghs", "ep1_out", "ep1_in";
+			num-bidir-endpoints = <9>;
+			ram-size = <4096>;
+			maximum-speed = "full-speed";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
+			phys = <&otghs_fs_phy>;
+			status = "disabled";
+			label= "OTGHS";
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x300>;
+			interrupts = <41 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40026000 {
+			compatible = "st,stm32-dma-v1";
+			#dma-cells = <4>;
+			reg = <0x40026000 0x400>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40026400 {
+			compatible = "st,stm32-dma-v1";
+			#dma-cells = <4>;
+			reg = <0x40026400 0x400>;
+			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
+			st,mem2mem;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		rng: rng@50060800 {
+			compatible = "st,stm32-rng";
+			reg = <0x50060800 0x400>;
+			interrupts = <80 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		sdmmc1: sdmmc@40012c00 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <49 0>;
+			status = "disabled";
+			label = "SDMMC_1";
+		};
+
+		backup_sram: memory@40024000 {
+			compatible = "st,stm32-backup-sram";
+			reg = <0x40024000 DT_SIZE_K(4)>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
+			status = "disabled";
+		};
+
+		quadspi: quadspi@a0001000 {
+			compatible = "st,stm32-qspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			reg = <0xa0001000 0x34>;
+			interrupts = <92 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x2>;
+			status = "disabled";
+			label = "QUADSPI";
+		};
+	};
+
+	otghs_fs_phy: otghs_fs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGHS_FS_PHY";
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGFS_PHY";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/f7/stm32f723.dtsi b/dts/arm/st/f7/stm32f723.dtsi
new file mode 100644
index 0000000000..c6baaffd70
--- /dev/null
+++ b/dts/arm/st/f7/stm32f723.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2018 Aurelien Jarno
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f7.dtsi>
+
+/ {
+	/* 64KB DTCM @ 0x20000000, 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00 */
+
+	sram0: memory@20010000 {
+		compatible = "mmio-sram";
+		reg = <0x20010000 DT_SIZE_K(192)>;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	soc {
+		usbphyc: usbphyc@40017c00 {
+			compatible = "st,stm32-usbphyc";
+			reg = <0x40017c00 0x400>;
+			#phy-cells = <0>;
+			label = "USBPHYC";
+		};
+
+		usbotg_hs: usb@40040000 {
+			phys = <&usbphyc>;
+			maximum-speed = "high-speed";
+		};
+
+		sdmmc2: sdmmc@40011c00 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			interrupts = <103 0>;
+			status = "disabled";
+			label = "SDMMC_2";
+		};
+	};
+
+};
+
+/delete-node/ &otghs_fs_phy;
diff --git a/dts/arm/st/f7/stm32f723Xe.dtsi b/dts/arm/st/f7/stm32f723Xe.dtsi
new file mode 100644
index 0000000000..2a7adcd801
--- /dev/null
+++ b/dts/arm/st/f7/stm32f723Xe.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f723.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f745.dtsi b/dts/arm/st/f7/stm32f745.dtsi
new file mode 100644
index 0000000000..1e13bb95df
--- /dev/null
+++ b/dts/arm/st/f7/stm32f745.dtsi
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020 Kwon Tae-young <tykwon@m2i.co.kr>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f7.dtsi>
+
+/ {
+	/* 64KB DTCM @ 20000000, 240KB SRAM1 @ 20010000, 16KB SRAM2 @ 2004C000 */
+
+	sram0: memory@20010000 {
+		compatible = "mmio-sram";
+		reg = <0x20010000 DT_SIZE_K(256)>;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	soc {
+		pinctrl: pin-controller@40020000 {
+			reg = <0x40020000 0x2C00>;
+
+			gpioj: gpio@40022400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				label = "GPIOK";
+			};
+		};
+
+		i2c4: i2c@40006000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40006000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
+			interrupts = <95 0>, <96 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_4";
+		};
+
+		spi6: spi@40015400 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			interrupts = <86 5>;
+			status = "disabled";
+			label = "SPI_6";
+		};
+
+		can2: can@40006800 {
+			compatible = "st,stm32-can";
+			reg = <0x40006800 0x400>;
+			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "CAN_2";
+		};
+
+		mac: ethernet@40028000 {
+			compatible = "st,stm32-ethernet";
+			reg = <0x40028000 0x8000>;
+			label = "ETH_0";
+			interrupts = <61 0>;
+			clock-names = "stmmaceth", "mac-clk-tx",
+				      "mac-clk-rx", "mac-clk-ptp";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f745Xe.dtsi b/dts/arm/st/f7/stm32f745Xe.dtsi
new file mode 100644
index 0000000000..d46f619b2e
--- /dev/null
+++ b/dts/arm/st/f7/stm32f745Xe.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 Kwon Tae-young <tykwon@m2i.co.kr>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f745.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f745Xg.dtsi b/dts/arm/st/f7/stm32f745Xg.dtsi
new file mode 100644
index 0000000000..89f3cb466c
--- /dev/null
+++ b/dts/arm/st/f7/stm32f745Xg.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 Kwon Tae-young <tykwon@m2i.co.kr>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f745.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f746.dtsi b/dts/arm/st/f7/stm32f746.dtsi
new file mode 100644
index 0000000000..75f5996708
--- /dev/null
+++ b/dts/arm/st/f7/stm32f746.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f745.dtsi>
diff --git a/dts/arm/st/f7/stm32f746Xg.dtsi b/dts/arm/st/f7/stm32f746Xg.dtsi
new file mode 100644
index 0000000000..e9257195aa
--- /dev/null
+++ b/dts/arm/st/f7/stm32f746Xg.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f746.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f756.dtsi b/dts/arm/st/f7/stm32f756.dtsi
new file mode 100644
index 0000000000..ca322e6f08
--- /dev/null
+++ b/dts/arm/st/f7/stm32f756.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2018 AJ Palmer
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f746.dtsi>
diff --git a/dts/arm/st/f7/stm32f756Xg.dtsi b/dts/arm/st/f7/stm32f756Xg.dtsi
new file mode 100644
index 0000000000..439b9e7921
--- /dev/null
+++ b/dts/arm/st/f7/stm32f756Xg.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 AJ Palmer
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f756.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f765.dtsi b/dts/arm/st/f7/stm32f765.dtsi
new file mode 100644
index 0000000000..b8c6b1b11f
--- /dev/null
+++ b/dts/arm/st/f7/stm32f765.dtsi
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2021 Daniel Agar
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f7.dtsi>
+
+/ {
+	/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
+	 * 16KB SRAM2 @ 2007C000
+	 */
+
+	sram0: memory@20020000 {
+		compatible = "mmio-sram";
+		reg = <0x20020000 DT_SIZE_K(384)>;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	soc {
+		pinctrl: pin-controller@40020000 {
+			reg = <0x40020000 0x2C00>;
+
+			gpioj: gpio@40022400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				label = "GPIOK";
+			};
+		};
+
+		i2c4: i2c@40006000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40006000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
+			interrupts = <95 0>, <96 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_4";
+		};
+
+		spi6: spi@40015400 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			interrupts = <86 5>;
+			status = "disabled";
+			label = "SPI_6";
+		};
+
+		mac: ethernet@40028000 {
+			compatible = "st,stm32-ethernet";
+			reg = <0x40028000 0x8000>;
+			label = "ETH_0";
+			interrupts = <61 0>;
+			clock-names = "stmmaceth", "mac-clk-tx",
+				      "mac-clk-rx", "mac-clk-ptp";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			status = "disabled";
+		};
+
+		sdmmc2: sdmmc@40011c00 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			interrupts = <103 0>;
+			status = "disabled";
+			label = "SDMMC_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f767.dtsi b/dts/arm/st/f7/stm32f767.dtsi
new file mode 100644
index 0000000000..0e5879f253
--- /dev/null
+++ b/dts/arm/st/f7/stm32f767.dtsi
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2019 Roland Ma
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f7.dtsi>
+
+/ {
+	/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
+	 * 16KB SRAM2 @ 2007C000
+	 */
+
+	sram0: memory@20020000 {
+		compatible = "mmio-sram";
+		reg = <0x20020000 DT_SIZE_K(384)>;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	soc {
+		pinctrl: pin-controller@40020000 {
+			reg = <0x40020000 0x2C00>;
+
+			gpioj: gpio@40022400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				label = "GPIOK";
+			};
+		};
+
+		i2c4: i2c@40006000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40006000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
+			interrupts = <95 0>, <96 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_4";
+		};
+
+		spi6: spi@40015400 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			interrupts = <86 5>;
+			status = "disabled";
+			label = "SPI_6";
+		};
+
+		mac: ethernet@40028000 {
+			compatible = "st,stm32-ethernet";
+			reg = <0x40028000 0x8000>;
+			label = "ETH_0";
+			interrupts = <61 0>;
+			clock-names = "stmmaceth", "mac-clk-tx",
+				      "mac-clk-rx", "mac-clk-ptp";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			status = "disabled";
+		};
+
+		sdmmc2: sdmmc@40011c00 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			interrupts = <103 0>;
+			status = "disabled";
+			label = "SDMMC_2";
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f767Xi.dtsi b/dts/arm/st/f7/stm32f767Xi.dtsi
new file mode 100644
index 0000000000..c61f223167
--- /dev/null
+++ b/dts/arm/st/f7/stm32f767Xi.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019 Roland Ma
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f767.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f769.dtsi b/dts/arm/st/f7/stm32f769.dtsi
new file mode 100644
index 0000000000..7a757bd634
--- /dev/null
+++ b/dts/arm/st/f7/stm32f769.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f767.dtsi>
diff --git a/dts/arm/st/f7/stm32f769Xi.dtsi b/dts/arm/st/f7/stm32f769Xi.dtsi
new file mode 100644
index 0000000000..8947f8b9d4
--- /dev/null
+++ b/dts/arm/st/f7/stm32f769Xi.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f769.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+
+};
diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi
new file mode 100644
index 0000000000..318d632407
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0.dtsi
@@ -0,0 +1,393 @@
+/*
+ * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
+ * Copyright (c) 2019 ST Microelectronics
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ * Copyright (C) 2020 Framework Computer LLC <ktl@frame.work>
+ * Copyright (c) 2021 G-Technologies Sdn. Bhd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv6-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m0+";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32g0-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <3 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <8>;
+				erase-block-size = <2048>;
+				/* maximum erase time(ms) for a 2K sector */
+				max-erase-time = <40>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32f0-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@40021800 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40021800 0x400>;
+		};
+
+		pinctrl: pin-controller@50000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x50000000 0x2000>;
+
+			gpioa: gpio@50000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@50000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@50000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@50000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpiof: gpio@50001400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50001400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>;
+				label = "GPIOF";
+			};
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			interrupts = <2 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 2>;
+			status = "disabled";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <27 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <28 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		lptim1: timers@40007c00 {
+			compatible = "st,stm32-lptim";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007c00 0x400>;
+			interrupts = <17 1>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <13 0>, <14 0>;
+			interrupt-names = "brk_up_trg_com", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <16 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
+			interrupts = <19 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <21 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <22 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <23 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label = "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label = "I2C_2";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <25 0>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 0>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <12 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020000 0x400>;
+			interrupts = <9 0 10 0 10 0 11 0 11 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			dma-requests = <5>;
+			dma-offset = <0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		/* DMAMUX clock is enabled as long as DMA1 or DMA2 is enabled */
+		dmamux1: dmamux@40020800 {
+			compatible = "st,stm32-dmamux";
+			#dma-cells = <3>;
+			reg = <0x40020800 0x800>;
+			interrupts = <11 0>;
+			dma-channels = <5>;
+			dma-generators = <4>;
+			dma-requests= <49>;
+			status = "disabled";
+			label = "DMAMUX_1";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>;
+};
diff --git a/dts/arm/st/g0/stm32g030.dtsi b/dts/arm/st/g0/stm32g030.dtsi
new file mode 100644
index 0000000000..17153a71b0
--- /dev/null
+++ b/dts/arm/st/g0/stm32g030.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g0.dtsi>
diff --git a/dts/arm/st/g0/stm32g030X6.dtsi b/dts/arm/st/g0/stm32g030X6.dtsi
new file mode 100644
index 0000000000..d3ac3daf5e
--- /dev/null
+++ b/dts/arm/st/g0/stm32g030X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g030.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g030X8.dtsi b/dts/arm/st/g0/stm32g030X8.dtsi
new file mode 100644
index 0000000000..595584f038
--- /dev/null
+++ b/dts/arm/st/g0/stm32g030X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g030.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g031.dtsi b/dts/arm/st/g0/stm32g031.dtsi
new file mode 100644
index 0000000000..3db142f5fc
--- /dev/null
+++ b/dts/arm/st/g0/stm32g031.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 SEAL AG
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g030.dtsi>
+
+/ {
+	soc {
+		lpuart1: serial@40008000 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x40008000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <15 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g031X4.dtsi b/dts/arm/st/g0/stm32g031X4.dtsi
new file mode 100644
index 0000000000..67d983af81
--- /dev/null
+++ b/dts/arm/st/g0/stm32g031X4.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g031.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(16)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g031X6.dtsi b/dts/arm/st/g0/stm32g031X6.dtsi
new file mode 100644
index 0000000000..10e31f3e1f
--- /dev/null
+++ b/dts/arm/st/g0/stm32g031X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 SEAL AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g031.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g031X8.dtsi b/dts/arm/st/g0/stm32g031X8.dtsi
new file mode 100644
index 0000000000..c9fba20282
--- /dev/null
+++ b/dts/arm/st/g0/stm32g031X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g031.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g041.dtsi b/dts/arm/st/g0/stm32g041.dtsi
new file mode 100644
index 0000000000..e5a81de78f
--- /dev/null
+++ b/dts/arm/st/g0/stm32g041.dtsi
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g031.dtsi>
+#include <st/g0/stm32g0_crypt.dtsi>
diff --git a/dts/arm/st/g0/stm32g041X6.dtsi b/dts/arm/st/g0/stm32g041X6.dtsi
new file mode 100644
index 0000000000..d0af1d89d4
--- /dev/null
+++ b/dts/arm/st/g0/stm32g041X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g041.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g041X8.dtsi b/dts/arm/st/g0/stm32g041X8.dtsi
new file mode 100644
index 0000000000..5c23293d4d
--- /dev/null
+++ b/dts/arm/st/g0/stm32g041X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g041.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g050.dtsi b/dts/arm/st/g0/stm32g050.dtsi
new file mode 100644
index 0000000000..830a686b87
--- /dev/null
+++ b/dts/arm/st/g0/stm32g050.dtsi
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g030.dtsi>
+
+/ {
+	soc {
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <17 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <18 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
+			dma-requests = <7>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <7>;
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g050X6.dtsi b/dts/arm/st/g0/stm32g050X6.dtsi
new file mode 100644
index 0000000000..bcb5aecb09
--- /dev/null
+++ b/dts/arm/st/g0/stm32g050X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g050.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(18)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g050X8.dtsi b/dts/arm/st/g0/stm32g050X8.dtsi
new file mode 100644
index 0000000000..906332c5d4
--- /dev/null
+++ b/dts/arm/st/g0/stm32g050X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g050.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(18)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g051.dtsi b/dts/arm/st/g0/stm32g051.dtsi
new file mode 100644
index 0000000000..d20b201479
--- /dev/null
+++ b/dts/arm/st/g0/stm32g051.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g031.dtsi>
+
+/ {
+	soc {
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <17 0>;
+			interrupt-names = "global";
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <18 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <20 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
+			dma-requests = <7>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <7>;
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g051X6.dtsi b/dts/arm/st/g0/stm32g051X6.dtsi
new file mode 100644
index 0000000000..7a84fb6d98
--- /dev/null
+++ b/dts/arm/st/g0/stm32g051X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g051.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(18)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g051X8.dtsi b/dts/arm/st/g0/stm32g051X8.dtsi
new file mode 100644
index 0000000000..20df94c453
--- /dev/null
+++ b/dts/arm/st/g0/stm32g051X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g051.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(18)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g061.dtsi b/dts/arm/st/g0/stm32g061.dtsi
new file mode 100644
index 0000000000..ed85142752
--- /dev/null
+++ b/dts/arm/st/g0/stm32g061.dtsi
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g051.dtsi>
+#include <st/g0/stm32g0_crypt.dtsi>
diff --git a/dts/arm/st/g0/stm32g061X6.dtsi b/dts/arm/st/g0/stm32g061X6.dtsi
new file mode 100644
index 0000000000..3c1268dfa8
--- /dev/null
+++ b/dts/arm/st/g0/stm32g061X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g061.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(18)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g061X8.dtsi b/dts/arm/st/g0/stm32g061X8.dtsi
new file mode 100644
index 0000000000..d8d6f5fb0b
--- /dev/null
+++ b/dts/arm/st/g0/stm32g061X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g061.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(18)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g070.dtsi b/dts/arm/st/g0/stm32g070.dtsi
new file mode 100644
index 0000000000..a340a69f05
--- /dev/null
+++ b/dts/arm/st/g0/stm32g070.dtsi
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2019 Sierra Wireless
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g050.dtsi>
+
+/ {
+	soc {
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		usart4: serial@40004c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <20 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <53>;
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g070Xb.dtsi b/dts/arm/st/g0/stm32g070Xb.dtsi
new file mode 100644
index 0000000000..c40b313418
--- /dev/null
+++ b/dts/arm/st/g0/stm32g070Xb.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019 Eric Hay <ehay@sierrawireless.com>
+ * Copyright (c) 2019 Sierra Wireless
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g070.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(36)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g071.dtsi b/dts/arm/st/g0/stm32g071.dtsi
new file mode 100644
index 0000000000..ef1062b44f
--- /dev/null
+++ b/dts/arm/st/g0/stm32g071.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2021 The Chromium OS Authors
+ * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
+ * Copyright (c) 2019 ST Microelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g051.dtsi>
+
+/ {
+	soc {
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		usart4: serial@40004c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <57>;
+		};
+
+		ucpd1: ucpd@4000a000 {
+			compatible = "st,stm32-ucpd";
+			reg = <0x4000a000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			interrupts = <8 0>;
+			status = "disabled";
+			label = "UCPD_1";
+		};
+
+		ucpd2: ucpd@4000a400 {
+			compatible = "st,stm32-ucpd";
+			reg = <0x4000a400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			interrupts = <8 0>;
+			status = "disabled";
+			label = "UCPD_2";
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g071X8.dtsi b/dts/arm/st/g0/stm32g071X8.dtsi
new file mode 100644
index 0000000000..4694a445fb
--- /dev/null
+++ b/dts/arm/st/g0/stm32g071X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g071.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(36)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g071Xb.dtsi b/dts/arm/st/g0/stm32g071Xb.dtsi
new file mode 100644
index 0000000000..3e437d6bc3
--- /dev/null
+++ b/dts/arm/st/g0/stm32g071Xb.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
+ * Copyright (c) 2019 ST Microelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g071.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(36)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/arm/st/g0/stm32g081.dtsi b/dts/arm/st/g0/stm32g081.dtsi
new file mode 100644
index 0000000000..e1d1502e64
--- /dev/null
+++ b/dts/arm/st/g0/stm32g081.dtsi
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g071.dtsi>
+#include <st/g0/stm32g0_crypt.dtsi>
diff --git a/dts/arm/st/g0/stm32g081Xb.dtsi b/dts/arm/st/g0/stm32g081Xb.dtsi
new file mode 100644
index 0000000000..075d8dec25
--- /dev/null
+++ b/dts/arm/st/g0/stm32g081Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g081.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(36)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0_crypt.dtsi b/dts/arm/st/g0/stm32g0_crypt.dtsi
new file mode 100644
index 0000000000..89ddf39aa0
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0_crypt.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+	};
+
+	soc {
+		aes: aes@40026000 {
+			compatible = "st,stm32-aes";
+			reg = <0x40026000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00010000>;
+			interrupts = <31 0>;
+			status = "disabled";
+			label = "AES";
+		};
+
+		rng: rng@40025000 {
+			compatible = "st,stm32-rng";
+			reg = <0x40025000 0x400>;
+			interrupts = <31 1>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			status = "disabled";
+			label = "RNG";
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0b0.dtsi b/dts/arm/st/g0/stm32g0b0.dtsi
new file mode 100644
index 0000000000..c3cefdd9eb
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0b0.dtsi
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g070.dtsi>
+
+/ {
+	soc {
+		pinctrl: pin-controller@50000000 {
+			gpioe: gpio@50001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>;
+				label = "GPIOE";
+			};
+		};
+
+		usart5: serial@40005000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		usart6: serial@40013c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <16 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		i2c3: i2c@40008800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40008800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label = "I2C_3";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020400 0x400>;
+			interrupts = <11 0 11 0 11 0 11 0 11 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			dma-requests = <5>;
+			dma-offset = <7>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <12>;
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <8 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <2048>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00002000>;
+			status = "disabled";
+			label= "USB";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0b0Xe.dtsi b/dts/arm/st/g0/stm32g0b0Xe.dtsi
new file mode 100644
index 0000000000..2c604b4e21
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0b0Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g0b0.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(144)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0b1.dtsi b/dts/arm/st/g0/stm32g0b1.dtsi
new file mode 100644
index 0000000000..7fa819e1cc
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0b1.dtsi
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ * Copyright (c) 2021 G-Technologies Sdn. Bhd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g071.dtsi>
+
+/ {
+	soc {
+		pinctrl: pin-controller@50000000 {
+			gpioe: gpio@50001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>;
+				label = "GPIOE";
+			};
+		};
+
+		usart5: serial@40005000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		usart6: serial@40013c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+
+		lpuart2: serial@40008400 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x40008400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			interrupts = <28 0>;
+			status = "disabled";
+			label = "LPUART_2";
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <16 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		i2c3: i2c@40008800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40008800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label = "I2C_3";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020400 0x400>;
+			interrupts = <11 0 11 0 11 0 11 0 11 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			dma-requests = <5>;
+			dma-offset = <7>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <12>;
+			dma-requests = <73>;
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <8 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <2048>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00002000>;
+			status = "disabled";
+			label= "USB";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0b1Xb.dtsi b/dts/arm/st/g0/stm32g0b1Xb.dtsi
new file mode 100644
index 0000000000..b7903e6615
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0b1Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g0b1.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(144)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0b1Xc.dtsi b/dts/arm/st/g0/stm32g0b1Xc.dtsi
new file mode 100644
index 0000000000..1164d9706f
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0b1Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g0b1.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(144)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0b1Xe.dtsi b/dts/arm/st/g0/stm32g0b1Xe.dtsi
new file mode 100644
index 0000000000..08875cf1af
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0b1Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g0b1.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(144)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0c1.dtsi b/dts/arm/st/g0/stm32g0c1.dtsi
new file mode 100644
index 0000000000..e7d9b96200
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0c1.dtsi
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g0/stm32g0b1.dtsi>
+#include <st/g0/stm32g0_crypt.dtsi>
diff --git a/dts/arm/st/g0/stm32g0c1Xc.dtsi b/dts/arm/st/g0/stm32g0c1Xc.dtsi
new file mode 100644
index 0000000000..9e5dbdeb16
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0c1Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g0c1.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(144)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g0/stm32g0c1Xe.dtsi b/dts/arm/st/g0/stm32g0c1Xe.dtsi
new file mode 100644
index 0000000000..b097fa5aae
--- /dev/null
+++ b/dts/arm/st/g0/stm32g0c1Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g0/stm32g0c1.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(144)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi
new file mode 100644
index 0000000000..ce01f29fcd
--- /dev/null
+++ b/dts/arm/st/g4/stm32g4.dtsi
@@ -0,0 +1,621 @@
+/*
+ * Copyright (c) 2021 The Chromium OS Authors
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32g4-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		/*
+		 * Both adc instances cannot be used in parallel right now.
+		 */
+		adc1: adc@50000000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50000000 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		adc2: adc@50000100 {
+			compatible = "st,stm32-adc";
+			reg = <0x50000100 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_2";
+			#io-channel-cells = <1>;
+		};
+
+		dac1: dac@50000800 {
+			compatible = "st,stm32-dac";
+			reg = <0x50000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dac3: dac@50001000 {
+			compatible = "st,stm32-dac";
+			reg = <0x50001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
+			status = "disabled";
+			label = "DAC_3";
+			#io-channel-cells = <1>;
+		};
+
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32g4-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <3 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <8>;
+				erase-block-size = <2048>;
+				/* maximum erase time(ms) for a 2K sector */
+				max-erase-time = <25>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@40010400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40010400 0x400>;
+		};
+
+		pinctrl: pin-controller@48000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x48000000 0x2000>;
+
+			gpioa: gpio@48000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@48000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@48000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@48001400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@48001800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+				label = "GPIOG";
+			};
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		lpuart1: serial@40008000 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x40008000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
+			interrupts = <91 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c3: i2c@40007800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			interrupts = <92 0>, <93 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_3";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			interrupts = <35 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		can {
+			compatible = "bosch,m-can-base";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			std-filter-elements = <28>;
+			ext-filter-elements = <8>;
+			rx-fifo0-elements = <3>;
+			rx-fifo1-elements = <3>;
+			rx-buffer-elements = <0>;
+			tx-buffer-elements = <3>;
+
+			can1: can@40006400 {
+				compatible = "st,stm32-fdcan";
+				reg = <0x40006400 0x400>, <0x4000A400 0x350>;
+				reg-names = "m_can", "message_ram";
+				interrupts = <21 0>, <22 0>;
+				interrupt-names = "LINE_0", "LINE_1";
+				status = "disabled";
+				label = "CAN_1";
+			};
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers8: timers@40013400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <24 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <25 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			interrupts = <41 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		rng: rng@50060800 {
+			compatible = "st,stm32-rng";
+			reg = <0x50060800 0x400>;
+			interrupts = <90 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x04000000>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <20 0>, <19 0>;
+			interrupt-names = "usb", "usbhp";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			status = "disabled";
+			label= "USB";
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			dma-offset = <0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dmamux1: dmamux@40020800 {
+			compatible = "st,stm32-dmamux";
+			#dma-cells = <3>;
+			reg = <0x40020800 0x400>;
+			interrupts = <94 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
+			dma-generators = <4>;
+			dma-requests= <111>;
+			status = "disabled";
+			label = "DMAMUX_1";
+		};
+
+		ucpd1: ucpd@4000a000 {
+			compatible = "st,stm32-ucpd";
+			reg = <0x4000a000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <63 0>;
+			status = "disabled";
+			label = "UCPD_1";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/g4/stm32g431.dtsi b/dts/arm/st/g4/stm32g431.dtsi
new file mode 100644
index 0000000000..c2f18e2315
--- /dev/null
+++ b/dts/arm/st/g4/stm32g431.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g4.dtsi>
+
+/ {
+	soc {
+		dma1: dma@40020000 {
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0>;
+			dma-requests = <6>;
+		};
+
+		dma2: dma@40020400 {
+			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0>;
+			dma-requests = <6>;
+			dma-offset = <6>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <12>;
+		};
+
+	};
+};
diff --git a/dts/arm/st/g4/stm32g431X6.dtsi b/dts/arm/st/g4/stm32g431X6.dtsi
new file mode 100644
index 0000000000..cfa1b29991
--- /dev/null
+++ b/dts/arm/st/g4/stm32g431X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g431.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g431X8.dtsi b/dts/arm/st/g4/stm32g431X8.dtsi
new file mode 100644
index 0000000000..f5bcff95f6
--- /dev/null
+++ b/dts/arm/st/g4/stm32g431X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g431.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g431Xb.dtsi b/dts/arm/st/g4/stm32g431Xb.dtsi
new file mode 100644
index 0000000000..7bc59dee86
--- /dev/null
+++ b/dts/arm/st/g4/stm32g431Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g431.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g441.dtsi b/dts/arm/st/g4/stm32g441.dtsi
new file mode 100644
index 0000000000..1f340fa312
--- /dev/null
+++ b/dts/arm/st/g4/stm32g441.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g431.dtsi>
diff --git a/dts/arm/st/g4/stm32g441Xb.dtsi b/dts/arm/st/g4/stm32g441Xb.dtsi
new file mode 100644
index 0000000000..115dcedd7e
--- /dev/null
+++ b/dts/arm/st/g4/stm32g441Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g441.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g473.dtsi b/dts/arm/st/g4/stm32g473.dtsi
new file mode 100644
index 0000000000..7abf18626d
--- /dev/null
+++ b/dts/arm/st/g4/stm32g473.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g4.dtsi>
+
+/ {
+	soc {
+		timers5: timers@40000C00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers20: timers@40015000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_20";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_20";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
+			dma-requests = <8>;
+		};
+
+		dma2: dma@40020400 {
+			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
+			dma-requests = <8>;
+			dma-offset = <8>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <16>;
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g473Xb.dtsi b/dts/arm/st/g4/stm32g473Xb.dtsi
new file mode 100644
index 0000000000..fdc9e5535c
--- /dev/null
+++ b/dts/arm/st/g4/stm32g473Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g473.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g473Xc.dtsi b/dts/arm/st/g4/stm32g473Xc.dtsi
new file mode 100644
index 0000000000..306fffdbd2
--- /dev/null
+++ b/dts/arm/st/g4/stm32g473Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g473.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g473Xe.dtsi b/dts/arm/st/g4/stm32g473Xe.dtsi
new file mode 100644
index 0000000000..354fb8c46c
--- /dev/null
+++ b/dts/arm/st/g4/stm32g473Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g473.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g474.dtsi b/dts/arm/st/g4/stm32g474.dtsi
new file mode 100644
index 0000000000..9d4dbdc24b
--- /dev/null
+++ b/dts/arm/st/g4/stm32g474.dtsi
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g4.dtsi>
+
+/ {
+	soc {
+		can {
+			can2: can@40006800 {
+				compatible = "st,stm32-fdcan";
+				reg = <0x40006800 0x400>, <0x4000A750 0x350>;
+				reg-names = "m_can", "message_ram";
+				interrupts = <86 0>, <87 0>;
+				interrupt-names = "LINE_0", "LINE_1";
+				status = "disabled";
+				label = "CAN_2";
+			};
+
+			can3: can@40006C00 {
+				compatible = "st,stm32-fdcan";
+				reg = <0x40006C00 0x400>, <0x4000AAA0 0x350>;
+				reg-names = "m_can", "message_ram";
+				interrupts = <88 0>, <89 0>;
+				interrupt-names = "LINE_0", "LINE_1";
+				status = "disabled";
+				label = "CAN_3";
+			};
+		};
+
+		timers5: timers@40000C00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers20: timers@40015000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_20";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_20";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dac2: dac@50000c00 {
+			compatible = "st,stm32-dac";
+			reg = <0x50000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00020000>;
+			status = "disabled";
+			label = "DAC_2";
+			#io-channel-cells = <1>;
+		};
+
+		dac4: dac@50001400 {
+			compatible = "st,stm32-dac";
+			reg = <0x50001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00080000>;
+			status = "disabled";
+			label = "DAC_4";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
+			dma-requests = <8>;
+		};
+
+		dma2: dma@40020400 {
+			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
+			dma-requests = <8>;
+			dma-offset = <8>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <16>;
+		};
+
+		i2c4: i2c@40008400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40008400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
+			interrupts = <82 0>, <83 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_4";
+		};
+
+		spi4: spi@40013c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
+			interrupts = <84 5>;
+			status = "disabled";
+			label = "SPI_4";
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g474Xb.dtsi b/dts/arm/st/g4/stm32g474Xb.dtsi
new file mode 100644
index 0000000000..4a54bcc157
--- /dev/null
+++ b/dts/arm/st/g4/stm32g474Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Libre Solar Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g474.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g474Xc.dtsi b/dts/arm/st/g4/stm32g474Xc.dtsi
new file mode 100644
index 0000000000..bc0135a052
--- /dev/null
+++ b/dts/arm/st/g4/stm32g474Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Libre Solar Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g474.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g474Xe.dtsi b/dts/arm/st/g4/stm32g474Xe.dtsi
new file mode 100644
index 0000000000..701ffe694a
--- /dev/null
+++ b/dts/arm/st/g4/stm32g474Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g474.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g483.dtsi b/dts/arm/st/g4/stm32g483.dtsi
new file mode 100644
index 0000000000..7abf18626d
--- /dev/null
+++ b/dts/arm/st/g4/stm32g483.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g4.dtsi>
+
+/ {
+	soc {
+		timers5: timers@40000C00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers20: timers@40015000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_20";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_20";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
+			dma-requests = <8>;
+		};
+
+		dma2: dma@40020400 {
+			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
+			dma-requests = <8>;
+			dma-offset = <8>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <16>;
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g483Xe.dtsi b/dts/arm/st/g4/stm32g483Xe.dtsi
new file mode 100644
index 0000000000..d415feaccf
--- /dev/null
+++ b/dts/arm/st/g4/stm32g483Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g483.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g484.dtsi b/dts/arm/st/g4/stm32g484.dtsi
new file mode 100644
index 0000000000..7abf18626d
--- /dev/null
+++ b/dts/arm/st/g4/stm32g484.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g4.dtsi>
+
+/ {
+	soc {
+		timers5: timers@40000C00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers20: timers@40015000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_20";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_20";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
+			dma-requests = <8>;
+		};
+
+		dma2: dma@40020400 {
+			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
+			dma-requests = <8>;
+			dma-offset = <8>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <16>;
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g484Xe.dtsi b/dts/arm/st/g4/stm32g484Xe.dtsi
new file mode 100644
index 0000000000..bb129a3fc0
--- /dev/null
+++ b/dts/arm/st/g4/stm32g484Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g484.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g491.dtsi b/dts/arm/st/g4/stm32g491.dtsi
new file mode 100644
index 0000000000..de0ad563f4
--- /dev/null
+++ b/dts/arm/st/g4/stm32g491.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g4.dtsi>
+
+/ {
+	soc {
+		timers20: timers@40015000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_20";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_20";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
+			dma-requests = <8>;
+		};
+
+		dma2: dma@40020400 {
+			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
+			dma-requests = <8>;
+			dma-offset = <8>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <16>;
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g491Xc.dtsi b/dts/arm/st/g4/stm32g491Xc.dtsi
new file mode 100644
index 0000000000..e410c42305
--- /dev/null
+++ b/dts/arm/st/g4/stm32g491Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g491.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(112)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g491Xe.dtsi b/dts/arm/st/g4/stm32g491Xe.dtsi
new file mode 100644
index 0000000000..dbed63d217
--- /dev/null
+++ b/dts/arm/st/g4/stm32g491Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g491.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(112)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g4a1.dtsi b/dts/arm/st/g4/stm32g4a1.dtsi
new file mode 100644
index 0000000000..de0ad563f4
--- /dev/null
+++ b/dts/arm/st/g4/stm32g4a1.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g4.dtsi>
+
+/ {
+	soc {
+		timers20: timers@40015000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_20";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_20";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
+			dma-requests = <8>;
+		};
+
+		dma2: dma@40020400 {
+			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
+			dma-requests = <8>;
+			dma-offset = <8>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <16>;
+		};
+	};
+};
diff --git a/dts/arm/st/g4/stm32g4a1Xe.dtsi b/dts/arm/st/g4/stm32g4a1Xe.dtsi
new file mode 100644
index 0000000000..34b010d074
--- /dev/null
+++ b/dts/arm/st/g4/stm32g4a1Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/g4/stm32g4a1.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(112)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi
new file mode 100644
index 0000000000..9872dadb52
--- /dev/null
+++ b/dts/arm/st/h7/stm32h7.dtsi
@@ -0,0 +1,848 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ * Copyright (c) 2020 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m7";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <16>;
+			};
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			/* H7 clock driver may not always need this value */
+			/* but it is required by the binding */
+			clock-frequency = <DT_FREQ_M(25)>;
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "st,stm32h7-hsi-clock";
+			clock-frequency = <DT_FREQ_M(64)>;
+			status = "disabled";
+		};
+
+		clk_csi: clk-csi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(4)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll@0 {
+			#clock-cells = <0>;
+			compatible = "st,stm32h7-pll-clock";
+			reg = <0>;
+			status = "disabled";
+		};
+
+		pll3: pll@2 {
+			#clock-cells = <0>;
+			compatible = "st,stm32h7-pll-clock";
+			reg = <2>;
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@52002000 {
+			compatible = "st,stm32h7-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x52002000 0x400>;
+			interrupts = <4 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		rcc: rcc@58024400 {
+			compatible = "st,stm32h7-rcc";
+			#clock-cells = <2>;
+			reg = <0x58024400 0x400>;
+		};
+
+		exti: interrupt-controller@58000000 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x58000000 0x400>;
+		};
+
+		pinctrl: pin-controller@58020000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x58020000 0x2400>;
+
+			gpioa: gpio@58020000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58020000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@58020400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58020400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@58020800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58020800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@58020C00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58020C00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@58021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58021000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@58021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@58021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58021800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioh: gpio@58021C00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58021C00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
+				label = "GPIOH";
+			};
+
+			gpioi: gpio@58022000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58022000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
+				label = "GPIOI";
+			};
+
+			gpioj: gpio@58022400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58022400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@58022800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x58022800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
+				label = "GPIOK";
+			};
+		};
+
+		iwdg1: watchdog@58004800 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x58004800 0x400>;
+			label = "IWDG_1";
+			status = "disabled";
+		};
+
+		wwdg1: watchdog@50003000 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x50003000 0x1000>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
+			interrupts = <0 7>;
+			status = "disabled";
+			label = "WWDG_1";
+		};
+
+		usart1: serial@40011000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+		uart4: serial@40004c00 {
+			compatible ="st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+		usart6: serial@40011400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			interrupts = <71 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+		uart7: serial@40007800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			interrupts = <82 0>;
+			status = "disabled";
+			label = "UART_7";
+		};
+		uart8: serial@40007c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			interrupts = <83 0>;
+			status = "disabled";
+			label = "UART_8";
+		};
+
+		lpuart1: serial@58000c00 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x58000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000008>;
+			interrupts = <142 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		rtc: rtc@58004000 {
+			compatible = "st,stm32-rtc";
+			reg = <0x58004000 0x400>;
+			interrupts = <41 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_2";
+		};
+
+		i2c3: i2c@40005c00 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <72 0>, <73 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_3";
+		};
+
+		i2c4: i2c@58001c00 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58001c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000080>;
+			interrupts = <95 0>, <96 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_4";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 0>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 0>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 0>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		spi4: spi@40013400 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <84 0>;
+			status = "disabled";
+			label = "SPI_4";
+		};
+
+		spi5: spi@40015000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40015000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			interrupts = <85 0>;
+			status = "disabled";
+			label = "SPI_5";
+		};
+
+		spi6: spi@58001400 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000020>;
+			interrupts = <86 0>;
+			status = "disabled";
+			label = "SPI_6";
+		};
+
+		timers1: timers@40010000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers8: timers@40010400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers12: timers@40001800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			interrupts = <43 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_12";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_12";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers13: timers@40001c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			interrupts = <44 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_13";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_13";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers14: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_14";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_14";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <116 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <117 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <118 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@40022000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40022000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		adc2: adc@40022100 {
+			compatible = "st,stm32-adc";
+			reg = <0x40022100 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_2";
+			#io-channel-cells = <1>;
+		};
+
+		/* dual mode: adc1 and adc2 coupled */
+		adc1_2: adc@40022300 {
+			compatible = "st,stm32-adc";
+			reg = <0x40022300 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1_2";
+			#io-channel-cells = <1>;
+		};
+
+		adc3: adc@58026000 {
+			compatible = "st,stm32-adc";
+			reg = <0x58026000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x01000000>;
+			interrupts = <127 0>;
+			status = "disabled";
+			label = "ADC_3";
+			#io-channel-cells = <1>;
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v1";
+			#dma-cells = <4>;
+			reg = <0x40020000 0x400>;
+			interrupts = <11 0>, <12 0>, <13 0>, <14 0>, <15 0>, <16 0>,
+						 <17 0>, <47 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+			st,mem2mem;
+			dma-offset = <0>;
+			dma-requests = <8>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v1";
+			#dma-cells = <4>;
+			reg = <0x40020400 0x400>;
+			interrupts = <56 0>, <57 0>, <58 0>, <59 0>, <60 0>, <68 0>,
+						<69 0>, <70 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+			st,mem2mem;
+			dma-offset = <8>;
+			dma-requests = <8>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dmamux1: dmamux@40020800 {
+			compatible = "st,stm32-dmamux";
+			#dma-cells = <3>;
+			reg = <0x40020800 0x400>;
+			interrupts = <102 0>;
+			/* dmamux1 has no dedicated clock, so we enable dma1 clock */
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+			dma-channels = <16>;
+			dma-generators = <8>;
+			status = "disabled";
+			label = "DMAMUX_1";
+			/*
+			 * dma-requests is different among h7 socs,
+			 * so we set in specific dtsi files
+			 */
+		};
+
+		rng: rng@48021800 {
+			compatible = "st,stm32-rng";
+			reg = <0x48021800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			interrupts = <80 0>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		sdmmc1: sdmmc@52007000 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x52007000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>;
+			interrupts = <49 0>;
+			status = "disabled";
+			label = "SDMMC_1";
+		};
+
+		sdmmc2: sdmmc@48022400 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x48022400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
+			interrupts = <124 0>;
+			status = "disabled";
+			label = "SDMMC_2";
+		};
+
+		mac: ethernet@40028000 {
+			compatible = "st,stm32-ethernet";
+			reg = <0x40028000 0x8000>;
+			label = "ETH_0";
+			interrupts = <61 0>;
+			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00008000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x00010000>,
+				 <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
+			status = "disabled";
+		};
+
+		fmc: memory-controller@52004000 {
+			compatible = "st,stm32-fmc";
+			reg = <0x52004000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>;
+			label = "STM32_FMC";
+			status = "disabled";
+
+			sdram: sdram {
+				compatible = "st,stm32-fmc-sdram";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				label = "STM32_FMC_SDRAM";
+				status = "disabled";
+			};
+		};
+
+		backup_sram: memory@38800000 {
+			compatible = "st,stm32-backup-sram";
+			reg = <0x38800000 DT_SIZE_K(4)>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x10000000>;
+			label = "BACKUP_SRAM";
+			zephyr,memory-region = "BACKUP_SRAM";
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi
new file mode 100644
index 0000000000..14e545203b
--- /dev/null
+++ b/dts/arm/st/h7/stm32h723.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				write-block-size = <32>;
+				erase-block-size = <DT_SIZE_K(128)>;
+			};
+		};
+
+		uart9: serial@40011800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40011800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
+			interrupts = <155 0>;
+			status = "disabled";
+			label = "UART_9";
+		};
+
+		usart10: serial@40011c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			interrupts = <156 0>;
+			status = "disabled";
+			label = "UART_10";
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <129>;
+		};
+
+		rng: rng@48021800 {
+			health-test-magic = <0x17590abc>;
+			health-test-config = <0xaa74>;
+		};
+	};
+
+	/* DTCM memory directly coppled to CPU */
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	/* AXI SRAM in D1 domain (AXI bus) */
+	sram0: memory@24000000 {
+		reg = <0x24000000 DT_SIZE_K(128)>;
+		compatible = "mmio-sram";
+	};
+};
diff --git a/dts/arm/st/h7/stm32h723Xe.dtsi b/dts/arm/st/h7/stm32h723Xe.dtsi
new file mode 100644
index 0000000000..b2084732be
--- /dev/null
+++ b/dts/arm/st/h7/stm32h723Xe.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2021 STMicroelectronics
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h723.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h723Xg.dtsi b/dts/arm/st/h7/stm32h723Xg.dtsi
new file mode 100644
index 0000000000..456b9d4e3c
--- /dev/null
+++ b/dts/arm/st/h7/stm32h723Xg.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h723.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h735.dtsi b/dts/arm/st/h7/stm32h735.dtsi
new file mode 100644
index 0000000000..398c2a62d2
--- /dev/null
+++ b/dts/arm/st/h7/stm32h735.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2021 SILA Embedded Solutions GmbH
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				write-block-size = <32>;
+				erase-block-size = <DT_SIZE_K(128)>;
+			};
+		};
+
+		uart9: serial@40011800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40011800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
+			interrupts = <155 0>;
+			status = "disabled";
+			label = "UART_9";
+		};
+
+		usart10: serial@40011c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			interrupts = <156 0>;
+			status = "disabled";
+			label = "UART_10";
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <129>;
+		};
+
+		cryp: cryp@48021000 {
+			compatible = "st,stm32-cryp";
+			reg = <0x48021000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			interrupts = <79 0>;
+			status = "disabled";
+			label = "CRYP";
+		};
+
+		rng: rng@48021800 {
+			health-test-magic = <0x17590abc>;
+			health-test-config = <0xaa74>;
+		};
+	};
+
+	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
+	sram0: memory@24000000 {
+		reg = <0x24000000 DT_SIZE_K(320)>;
+		compatible = "mmio-sram";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
+	sram1: memory@30000000 {
+		reg = <0x30000000 DT_SIZE_K(16)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM1";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
+	sram2: memory@30040000 {
+		reg = <0x30040000 DT_SIZE_K(16)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM2";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
+	sram4: memory@38000000 {
+		reg = <0x38000000 DT_SIZE_K(16)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM4";
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+};
diff --git a/dts/arm/st/h7/stm32h735Xg.dtsi b/dts/arm/st/h7/stm32h735Xg.dtsi
new file mode 100644
index 0000000000..9e74c10d3d
--- /dev/null
+++ b/dts/arm/st/h7/stm32h735Xg.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2021 SILA Embedded Solutions GmbH
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h735.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h743.dtsi b/dts/arm/st/h7/stm32h743.dtsi
new file mode 100644
index 0000000000..a66326619e
--- /dev/null
+++ b/dts/arm/st/h7/stm32h743.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2020 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				write-block-size = <32>;
+				erase-block-size = <DT_SIZE_K(128)>;
+			};
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <107>;
+		};
+
+		usbotg_fs: usb@40080000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x40080000 0x40000>;
+			interrupts = <101 0>, <98 0>, <99 0>;
+			interrupt-names = "otgfs", "ep1_out", "ep1_in";
+			num-bidir-endpoints = <9>;
+			ram-size = <4096>;
+			maximum-speed = "full-speed";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x080000000>;
+			phys = <&otghs_fs_phy>;
+			status = "disabled";
+			label= "OTG_FS";
+		};
+	};
+
+	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
+	sram0: memory@24000000 {
+		reg = <0x24000000 DT_SIZE_K(512)>;
+		compatible = "mmio-sram";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
+	sram1: memory@30000000 {
+		reg = <0x30000000 DT_SIZE_K(128)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM1";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
+	sram2: memory@30020000 {
+		compatible = "mmio-sram";
+		reg = <0x30020000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "SRAM2";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
+	sram3: memory@30040000 {
+		compatible = "mmio-sram";
+		reg = <0x30040000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM3";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
+	sram4: memory@38000000 {
+		reg = <0x38000000 DT_SIZE_K(64)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM4";
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	otghs_fs_phy: otghs_fs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGHS_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/h7/stm32h743Xi.dtsi b/dts/arm/st/h7/stm32h743Xi.dtsi
new file mode 100644
index 0000000000..709610527c
--- /dev/null
+++ b/dts/arm/st/h7/stm32h743Xi.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h743.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h745.dtsi b/dts/arm/st/h7/stm32h745.dtsi
new file mode 100644
index 0000000000..76aa2ca2a9
--- /dev/null
+++ b/dts/arm/st/h7/stm32h745.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7_dualcore.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				write-block-size = <32>;
+				erase-block-size = <DT_SIZE_K(128)>;
+			};
+			flash1: flash@8100000 {
+				compatible = "soc-nv-flash";
+				write-block-size = <32>;
+				erase-block-size = <DT_SIZE_K(128)>;
+			};
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-requests= <107>;
+		};
+	};
+	/*
+	* The RAM memories placed here can be used by both cores M4/M7
+	* For more information see reference manual and datasheet to STM32H745
+	* (RM0399 Rev 3)
+	*/
+
+	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
+	sram0: memory@24000000 {
+		reg = <0x24000000 DT_SIZE_K(512)>;
+		compatible = "mmio-sram";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
+	sram1: memory@30000000 {
+		reg = <0x30000000 DT_SIZE_K(128)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM1";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
+	sram2: memory@30020000 {
+		compatible = "mmio-sram";
+		reg = <0x30020000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "SRAM2";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
+	sram3: memory@30040000 {
+		compatible = "mmio-sram";
+		reg = <0x30040000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM3";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
+	sram4: memory@38000000 {
+		reg = <0x38000000 DT_SIZE_K(64)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM4";
+	};
+};
diff --git a/dts/arm/st/h7/stm32h745Xi_m4.dtsi b/dts/arm/st/h7/stm32h745Xi_m4.dtsi
new file mode 100644
index 0000000000..793475c6ea
--- /dev/null
+++ b/dts/arm/st/h7/stm32h745Xi_m4.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h745.dtsi>
+
+/delete-node/ &flash0;
+
+/ {
+	chosen {
+		/* Flash controller support is not yet supported on M4 core */
+		/delete-property/ zephyr,flash-controller;
+	};
+
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash1: flash@8100000 {
+				label = "FLASH_STM32";
+				reg = <0x08100000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		mailbox@58026400 {
+			interrupts = <126 0>;
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h745Xi_m7.dtsi b/dts/arm/st/h7/stm32h745Xi_m7.dtsi
new file mode 100644
index 0000000000..cb75c1f1b6
--- /dev/null
+++ b/dts/arm/st/h7/stm32h745Xi_m7.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h745.dtsi>
+
+/delete-node/ &flash1;
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		mailbox@58026400 {
+			interrupts = <125 0>;
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h747.dtsi b/dts/arm/st/h7/stm32h747.dtsi
new file mode 100644
index 0000000000..0868d2434a
--- /dev/null
+++ b/dts/arm/st/h7/stm32h747.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h745.dtsi>
diff --git a/dts/arm/st/h7/stm32h747Xi_m4.dtsi b/dts/arm/st/h7/stm32h747Xi_m4.dtsi
new file mode 100644
index 0000000000..8998c0a8c7
--- /dev/null
+++ b/dts/arm/st/h7/stm32h747Xi_m4.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h747.dtsi>
+
+/delete-node/ &flash0;
+
+/ {
+	chosen {
+		/* Flash controller support is not yet supported on M4 core */
+		/delete-property/ zephyr,flash-controller;
+	};
+
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash1: flash@8100000 {
+				label = "FLASH_STM32";
+				reg = <0x08100000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		mailbox@58026400 {
+			interrupts = <126 0>;
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h747Xi_m7.dtsi b/dts/arm/st/h7/stm32h747Xi_m7.dtsi
new file mode 100644
index 0000000000..bd237db386
--- /dev/null
+++ b/dts/arm/st/h7/stm32h747Xi_m7.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h747.dtsi>
+
+/delete-node/ &flash1;
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		mailbox@58026400 {
+			interrupts = <125 0>;
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h750.dtsi b/dts/arm/st/h7/stm32h750.dtsi
new file mode 100644
index 0000000000..8e215c9eee
--- /dev/null
+++ b/dts/arm/st/h7/stm32h750.dtsi
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7.dtsi>
+
+/ {
+	soc {
+		dmamux1: dmamux@40020800 {
+			dma-requests= <107>;
+		};
+	};
+
+	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
+	sram0: memory@24000000 {
+		reg = <0x24000000 DT_SIZE_K(512)>;
+		compatible = "mmio-sram";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
+	sram1: memory@30000000 {
+		reg = <0x30000000 DT_SIZE_K(128)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM1";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
+	sram2: memory@30020000 {
+		compatible = "mmio-sram";
+		reg = <0x30020000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "SRAM2";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
+	sram3: memory@30040000 {
+		compatible = "mmio-sram";
+		reg = <0x30040000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAM3";
+	};
+
+	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
+	sram4: memory@38000000 {
+		reg = <0x38000000 DT_SIZE_K(64)>;
+		compatible = "mmio-sram";
+		zephyr,memory-region = "SRAM4";
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+};
diff --git a/dts/arm/st/h7/stm32h750Xb.dtsi b/dts/arm/st/h7/stm32h750Xb.dtsi
new file mode 100644
index 0000000000..22f52cf082
--- /dev/null
+++ b/dts/arm/st/h7/stm32h750Xb.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h750.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h753.dtsi b/dts/arm/st/h7/stm32h753.dtsi
new file mode 100644
index 0000000000..cc0b8f70a8
--- /dev/null
+++ b/dts/arm/st/h7/stm32h753.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 Petri Oksanen <petri@iote.ai>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h743.dtsi>
diff --git a/dts/arm/st/h7/stm32h753Xi.dtsi b/dts/arm/st/h7/stm32h753Xi.dtsi
new file mode 100644
index 0000000000..ea01fd0fca
--- /dev/null
+++ b/dts/arm/st/h7/stm32h753Xi.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020 Petri Oksanen <petri@iote.ai>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h753.dtsi>
+
+/ {
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h7_dualcore.dtsi b/dts/arm/st/h7/stm32h7_dualcore.dtsi
new file mode 100644
index 0000000000..941abf1fb1
--- /dev/null
+++ b/dts/arm/st/h7/stm32h7_dualcore.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020 Moonkwun Jung
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7.dtsi>
+
+/ {
+	cpus {
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		mailbox: mailbox@58026400 {
+			compatible = "st,stm32-hsem-mailbox";
+			reg = <0x58026400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x02000000>;
+			status = "disabled";
+			label = "MAILBOX_0";
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi
new file mode 100644
index 0000000000..8f03762179
--- /dev/null
+++ b/dts/arm/st/l0/stm32l0.dtsi
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv6-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m0+";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_msi: clk-msi {
+			#clock-cells = <0>;
+			compatible = "st,stm32l0-msi-clock";
+			msi-range = <5>; /* 2.1MHz (reset value) */
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32l0-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			interrupts = <2 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32l0-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <3 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <4>;
+				/* maximum erase time(ms) for a 128B page */
+				max-erase-time = <4>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@40010400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40010400 0x400>;
+		};
+
+		pinctrl: pin-controller@50000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x50000000 0x2000>;
+
+			gpioa: gpio@50000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@50000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@50000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@50000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioh: gpio@50001c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50001c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000080>;
+				label = "GPIOH";
+			};
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 2>;
+			status = "disabled";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <28 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		lpuart1: serial@40004800 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <29 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <23 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <25 3>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <15 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers21: timers@40010800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000004>;
+			interrupts = <20 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_21";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_21";
+				#pwm-cells = <3>;
+			};
+		};
+
+		lptim1: timers@40007c00 {
+			compatible = "st,stm32-lptim";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007c00 0x400>;
+			interrupts = <13 1>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <12 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020000 0x400>;
+			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		eeprom: eeprom@8080000{
+			compatible = "st,stm32-eeprom";
+			status = "disabled";
+			label = "EEPROM_0";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>;
+};
diff --git a/dts/arm/st/l0/stm32l010.dtsi b/dts/arm/st/l0/stm32l010.dtsi
new file mode 100644
index 0000000000..678f9f0ce2
--- /dev/null
+++ b/dts/arm/st/l0/stm32l010.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2019-2020 Grinn
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l0/stm32l0.dtsi>
+
+/ {
+	soc {
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 512>;
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l010Xb.dtsi b/dts/arm/st/l0/stm32l010Xb.dtsi
new file mode 100644
index 0000000000..f5a8debef3
--- /dev/null
+++ b/dts/arm/st/l0/stm32l010Xb.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021 Wouter Cappelle <wouter.cappelle@crodeon.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l010.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+
+		timers22: timers@40011400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			interrupts = <22 0>;
+			interrupt-names = "global";
+			status = "disabled";
+			label = "TIMERS_22";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_22";
+				#pwm-cells = <3>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l011X4.dtsi b/dts/arm/st/l0/stm32l011X4.dtsi
new file mode 100644
index 0000000000..e42fa1af64
--- /dev/null
+++ b/dts/arm/st/l0/stm32l011X4.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Grinn
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l010.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(2)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(16)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l031.dtsi b/dts/arm/st/l0/stm32l031.dtsi
new file mode 100644
index 0000000000..45cc5f04a1
--- /dev/null
+++ b/dts/arm/st/l0/stm32l031.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020 Steven Daglish <s.c.daglish@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l0/stm32l0.dtsi>
+
+/ {
+	soc {
+		timers22: timers@40011400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			interrupts = <22 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_22";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_22";
+				#pwm-cells = <3>;
+			};
+		};
+
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(1)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l031X6.dtsi b/dts/arm/st/l0/stm32l031X6.dtsi
new file mode 100644
index 0000000000..80bea705c5
--- /dev/null
+++ b/dts/arm/st/l0/stm32l031X6.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Steven Daglish <s.c.daglish@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l031.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l051.dtsi b/dts/arm/st/l0/stm32l051.dtsi
new file mode 100644
index 0000000000..5af4fd8650
--- /dev/null
+++ b/dts/arm/st/l0/stm32l051.dtsi
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021 Nomono AS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l0/stm32l0.dtsi>
+
+/ {
+	soc {
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <27 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		timers22: timers@40011400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			interrupts = <22 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_22";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_22";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <17 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(2)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l051X8.dtsi b/dts/arm/st/l0/stm32l051X8.dtsi
new file mode 100644
index 0000000000..34b687d188
--- /dev/null
+++ b/dts/arm/st/l0/stm32l051X8.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021 Nomono AS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l051.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000{
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+
+	};
+};
+
diff --git a/dts/arm/st/l0/stm32l053.dtsi b/dts/arm/st/l0/stm32l053.dtsi
new file mode 100644
index 0000000000..c3c45fd958
--- /dev/null
+++ b/dts/arm/st/l0/stm32l053.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018 Anthony Kreft <anthony.kreft@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l0/stm32l051.dtsi>
+
+/ {
+	soc {
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <31 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			maximum-speed = "full-speed";
+			phys = <&otgfs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			status = "disabled";
+			label = "USB";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		otgfs_phy: otgfs_phy {
+			compatible = "usb-nop-xceiv";
+			#phy-cells = <0>;
+			label = "OTGFS_PHY";
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l053X8.dtsi b/dts/arm/st/l0/stm32l053X8.dtsi
new file mode 100644
index 0000000000..52f9dade96
--- /dev/null
+++ b/dts/arm/st/l0/stm32l053X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l053.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l071.dtsi b/dts/arm/st/l0/stm32l071.dtsi
new file mode 100644
index 0000000000..d8640fd2fe
--- /dev/null
+++ b/dts/arm/st/l0/stm32l071.dtsi
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2020 Alexander Mihajlovic <a@abxy.se>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l0/stm32l0.dtsi>
+
+/ {
+	soc {
+		pinctrl: pin-controller@50000000 {
+			gpioe: gpio@50001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x50001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>;
+				label = "GPIOE";
+			};
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <24 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c3: i2c@40007800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			interrupts = <21 0>;
+			interrupt-names = "combined";
+			status = "disabled";
+			label= "I2C_3";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <26 3>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <16 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <17 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <18 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers22: timers@40011400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			interrupts = <22 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_22";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_22";
+				#pwm-cells = <3>;
+			};
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <27 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart4: serial@40004c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <14 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		usart5: serial@40005000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <14 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(6)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l071Xb.dtsi b/dts/arm/st/l0/stm32l071Xb.dtsi
new file mode 100644
index 0000000000..83e4efcc24
--- /dev/null
+++ b/dts/arm/st/l0/stm32l071Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Alexander Mihajlovic <a@abxy.se>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l071.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l072.dtsi b/dts/arm/st/l0/stm32l072.dtsi
new file mode 100644
index 0000000000..87710a49fa
--- /dev/null
+++ b/dts/arm/st/l0/stm32l072.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l0/stm32l071.dtsi>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+	};
+
+	soc {
+		usb: usb@40005c00 {
+			compatible = "st,stm32-usb";
+			reg = <0x40005c00 0x400>;
+			interrupts = <31 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			maximum-speed = "full-speed";
+			phys = <&otgfs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			status = "disabled";
+			label= "USB";
+		};
+
+		rng: rng@40025000 {
+			compatible = "st,stm32-rng";
+			reg = <0x40025000 0x400>;
+			interrupts = <29 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
+			status = "disabled";
+			label = "RNG";
+		};
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGFS_PHY";
+	};
+
+	dac1: dac@40007400 {
+		compatible = "st,stm32-dac";
+		reg = <0x40007400 0x400>;
+		clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+		status = "disabled";
+		label = "DAC_1";
+		#io-channel-cells = <1>;
+	};
+};
diff --git a/dts/arm/st/l0/stm32l072Xz.dtsi b/dts/arm/st/l0/stm32l072Xz.dtsi
new file mode 100644
index 0000000000..e30ac5d3d1
--- /dev/null
+++ b/dts/arm/st/l0/stm32l072Xz.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l072.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(192)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l073.dtsi b/dts/arm/st/l0/stm32l073.dtsi
new file mode 100644
index 0000000000..d212d6fc16
--- /dev/null
+++ b/dts/arm/st/l0/stm32l073.dtsi
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2018 Ilya Tagunov <tagunil@gmail.com>
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l0/stm32l072.dtsi>
diff --git a/dts/arm/st/l0/stm32l073Xz.dtsi b/dts/arm/st/l0/stm32l073Xz.dtsi
new file mode 100644
index 0000000000..27f6a57fe7
--- /dev/null
+++ b/dts/arm/st/l0/stm32l073Xz.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l073.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(192)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l1/stm32l1.dtsi b/dts/arm/st/l1/stm32l1.dtsi
new file mode 100644
index 0000000000..f25a46ae30
--- /dev/null
+++ b/dts/arm/st/l1/stm32l1.dtsi
@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2019 Linaro Ltd.
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m3";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_msi: clk-msi {
+			#clock-cells = <0>;
+			compatible = "st,stm32l0-msi-clock";
+			msi-range = <5>; /* 2.1MHz (reset value) */
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(37)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32l0-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+
+		flash: flash-controller@40023c00 {
+			compatible = "st,stm32-flash-controller", "st,stm32l1-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40023c00 0x400>;
+			interrupts = <4 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00008000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <4>;
+				/* maximum erase time(ms) for a 128B half-page
+				 */
+				max-erase-time = <4>;
+			};
+		};
+
+		rcc: rcc@40023800 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40023800 0x400>;
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			interrupts = <41 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <48 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <49 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v1";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			interrupts = <35 0>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 0>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		exti: interrupt-controller@40010400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40010400 0x400>;
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers9: timers@40010800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000004>;
+			interrupts = <25 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_9";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_9";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers10: timers@40010c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40010c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000008>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_10";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_10";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers11: timers@40011400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40011400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			interrupts = <27 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_11";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_11";
+				#pwm-cells = <3>;
+			};
+		};
+
+		pinctrl: pin-controller@40020000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40020000 0x2000>;
+
+			gpioa: gpio@40020000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@40020400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@40020800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@40020c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40020c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@40021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpioh: gpio@40021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				label = "GPIOH";
+			};
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			interrupts = <0 7>;
+			status = "disabled";
+			label = "WWDG";
+		};
+
+		eeprom: eeprom@8080000{
+			compatible = "st,stm32-eeprom";
+			status = "disabled";
+			label = "EEPROM_0";
+		};
+
+		dma1: dma@40026000 {
+			compatible = "st,stm32-dma-v2bis";
+			#dma-cells = <2>;
+			reg = <0x40026000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1000000>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/l1/stm32l151.dtsi b/dts/arm/st/l1/stm32l151.dtsi
new file mode 100644
index 0000000000..264c0e7d32
--- /dev/null
+++ b/dts/arm/st/l1/stm32l151.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l1/stm32l1.dtsi>
diff --git a/dts/arm/st/l1/stm32l151X8-a.dtsi b/dts/arm/st/l1/stm32l151X8-a.dtsi
new file mode 100644
index 0000000000..5cd0d1278a
--- /dev/null
+++ b/dts/arm/st/l1/stm32l151X8-a.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 eTactica ehf
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l1/stm32l151.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(4)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l1/stm32l151Xb-a.dtsi b/dts/arm/st/l1/stm32l151Xb-a.dtsi
new file mode 100644
index 0000000000..d2ee1621ef
--- /dev/null
+++ b/dts/arm/st/l1/stm32l151Xb-a.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l1/stm32l151.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(4)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l1/stm32l151Xb.dtsi b/dts/arm/st/l1/stm32l151Xb.dtsi
new file mode 100644
index 0000000000..70f5c3a50f
--- /dev/null
+++ b/dts/arm/st/l1/stm32l151Xb.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l1/stm32l151.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(4)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l1/stm32l151Xc.dtsi b/dts/arm/st/l1/stm32l151Xc.dtsi
new file mode 100644
index 0000000000..0b8ebb4351
--- /dev/null
+++ b/dts/arm/st/l1/stm32l151Xc.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020 Abel Sensors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l1/stm32l151.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+
+		timers5: timers@40000C00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(8)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l1/stm32l152.dtsi b/dts/arm/st/l1/stm32l152.dtsi
new file mode 100644
index 0000000000..757a2fd9c5
--- /dev/null
+++ b/dts/arm/st/l1/stm32l152.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * The STM32L151 and STM32L152 differ in that
+ * the STM32L152 features an LCD controller.
+ */
+#include <st/l1/stm32l151.dtsi>
diff --git a/dts/arm/st/l1/stm32l152Xc.dtsi b/dts/arm/st/l1/stm32l152Xc.dtsi
new file mode 100644
index 0000000000..af2cd73622
--- /dev/null
+++ b/dts/arm/st/l1/stm32l152Xc.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020 Abel Sensors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l1/stm32l152.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+
+		timers5: timers@40000C00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(8)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l1/stm32l152Xe.dtsi b/dts/arm/st/l1/stm32l152Xe.dtsi
new file mode 100644
index 0000000000..28975bc487
--- /dev/null
+++ b/dts/arm/st/l1/stm32l152Xe.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019, 2020 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l1/stm32l152.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(80)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+
+		timers5: timers@40000C00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		eeprom: eeprom@8080000{
+			reg = <0x08080000 DT_SIZE_K(16)>;
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi
new file mode 100644
index 0000000000..d437ff0d4d
--- /dev/null
+++ b/dts/arm/st/l4/stm32l4.dtsi
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_msi: clk-msi {
+			#clock-cells = <0>;
+			compatible = "st,stm32-msi-clock";
+			msi-range = <6>; /* 4MHz (reset value) */
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32l4-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <4 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <8>;
+				erase-block-size = <2048>;
+				/* maximum erase time(ms) for a 2K sector */
+				max-erase-time = <25>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@40010400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x40010400 0x400>;
+		};
+
+		pinctrl: pin-controller@48000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x48000000 0x2000>;
+
+			gpioa: gpio@48000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@48000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@48000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpioh: gpio@48001c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+				label = "GPIOH";
+			};
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		lpuart1: serial@40008000 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x40008000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
+			interrupts = <70 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c3: i2c@40005c00 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <72 0>, <73 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_3";
+		};
+
+		quadspi: quadspi@a0001000 {
+			compatible = "st,stm32-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa0001000 0x400>;
+			interrupts = <71 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
+			status = "disabled";
+			label = "QUADSPI";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			interrupts = <35 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers6: timers@40001000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			interrupts = <54 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_6";
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <24 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <25 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			interrupts = <41 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		adc1: adc@50040000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50040000 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		adc2: adc@50040100 {
+			compatible = "st,stm32-adc";
+			reg = <0x50040100 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_2";
+			#io-channel-cells = <1>;
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020000 0x400>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			dma-requests = <7>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020400 0x400>;
+			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			dma-requests = <7>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		lptim1: timers@40007c00 {
+			compatible = "st,stm32-lptim";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007c00 0x400>;
+			interrupts = <65 1>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
+
+		rng: rng@50060800 {
+			compatible = "st,stm32-rng";
+			reg = <0x50060800 0x400>;
+			interrupts = <80 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
+			status = "disabled";
+			label = "RNG";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/l4/stm32l412.dtsi b/dts/arm/st/l4/stm32l412.dtsi
new file mode 100644
index 0000000000..1f2a69c8e7
--- /dev/null
+++ b/dts/arm/st/l4/stm32l412.dtsi
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020 Aurelien Jarno
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l4.dtsi>
+
+/ {
+	soc {
+		usb: usb@40006800 {
+			compatible = "st,stm32-usb";
+			reg = <0x40006800 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			maximum-speed = "full-speed";
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "USB";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			interrupts = <36 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/l4/stm32l412X8.dtsi b/dts/arm/st/l4/stm32l412X8.dtsi
new file mode 100644
index 0000000000..9c66aa8ed6
--- /dev/null
+++ b/dts/arm/st/l4/stm32l412X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l412.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(40)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l412XB.dtsi b/dts/arm/st/l4/stm32l412XB.dtsi
new file mode 100644
index 0000000000..438e15a254
--- /dev/null
+++ b/dts/arm/st/l4/stm32l412XB.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Guðni Már Gilbert
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l412.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(40)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l422.dtsi b/dts/arm/st/l4/stm32l422.dtsi
new file mode 100644
index 0000000000..04cc777175
--- /dev/null
+++ b/dts/arm/st/l4/stm32l422.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 Aurelien Jarno
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l412.dtsi>
diff --git a/dts/arm/st/l4/stm32l422Xb.dtsi b/dts/arm/st/l4/stm32l422Xb.dtsi
new file mode 100644
index 0000000000..3284865f70
--- /dev/null
+++ b/dts/arm/st/l4/stm32l422Xb.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Aurelien Jarno
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l422.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(40)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l432.dtsi b/dts/arm/st/l4/stm32l432.dtsi
new file mode 100644
index 0000000000..9c869f2636
--- /dev/null
+++ b/dts/arm/st/l4/stm32l432.dtsi
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l4.dtsi>
+
+/ {
+	soc {
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <4>;
+			phase-seg2 = <5>;
+		};
+
+		usb: usb@40006800 {
+			compatible = "st,stm32-usb";
+			reg = <0x40006800 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			maximum-speed = "full-speed";
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "USB";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/l4/stm32l432Xc.dtsi b/dts/arm/st/l4/stm32l432Xc.dtsi
new file mode 100644
index 0000000000..59b6e23cb4
--- /dev/null
+++ b/dts/arm/st/l4/stm32l432Xc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l4/stm32l432.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l433.dtsi b/dts/arm/st/l4/stm32l433.dtsi
new file mode 100644
index 0000000000..f9567a2bbe
--- /dev/null
+++ b/dts/arm/st/l4/stm32l433.dtsi
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Markus Roppelt
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l432.dtsi>
+
+/ {
+	soc {
+		pinctrl: pin-controller@48000000 {
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				label = "GPIOE";
+			};
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/arm/st/l4/stm32l433Xb.dtsi b/dts/arm/st/l4/stm32l433Xb.dtsi
new file mode 100644
index 0000000000..0c0a1044ac
--- /dev/null
+++ b/dts/arm/st/l4/stm32l433Xb.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2020 Kwon Tae-young <tykwon@m2i.co.kr>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l4/stm32l433.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l433Xc.dtsi b/dts/arm/st/l4/stm32l433Xc.dtsi
new file mode 100644
index 0000000000..8dc414720e
--- /dev/null
+++ b/dts/arm/st/l4/stm32l433Xc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l4/stm32l433.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l452.dtsi b/dts/arm/st/l4/stm32l452.dtsi
new file mode 100644
index 0000000000..76c4fda22e
--- /dev/null
+++ b/dts/arm/st/l4/stm32l452.dtsi
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2018 Georgij Cernysiov
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l4.dtsi>
+
+/ {
+	soc {
+		pinctrl: pin-controller@48000000 {
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				label = "GPIOE";
+			};
+		};
+
+		usb: usb@40006800 {
+			compatible = "st,stm32-usb";
+			reg = <0x40006800 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			maximum-speed = "full-speed";
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "USB";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c4: i2c@40008400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40008400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
+			interrupts = <83 0>, <84 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_4";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <4>;
+			phase-seg2 = <5>;
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
diff --git a/dts/arm/st/l4/stm32l452Xc.dtsi b/dts/arm/st/l4/stm32l452Xc.dtsi
new file mode 100644
index 0000000000..8b35e5442d
--- /dev/null
+++ b/dts/arm/st/l4/stm32l452Xc.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Georgij Cernysiov
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l452.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(160)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l452Xe.dtsi b/dts/arm/st/l4/stm32l452Xe.dtsi
new file mode 100644
index 0000000000..619cbb72c2
--- /dev/null
+++ b/dts/arm/st/l4/stm32l452Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018 Libre Solar Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l452.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(160)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l462.dtsi b/dts/arm/st/l4/stm32l462.dtsi
new file mode 100644
index 0000000000..150d892503
--- /dev/null
+++ b/dts/arm/st/l4/stm32l462.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 Giancarlo Stasi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l452.dtsi>
diff --git a/dts/arm/st/l4/stm32l462Xe.dtsi b/dts/arm/st/l4/stm32l462Xe.dtsi
new file mode 100644
index 0000000000..d73342bb40
--- /dev/null
+++ b/dts/arm/st/l4/stm32l462Xe.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Giancarlo Stasi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l462.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(160)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l471.dtsi b/dts/arm/st/l4/stm32l471.dtsi
new file mode 100644
index 0000000000..799c55f1e3
--- /dev/null
+++ b/dts/arm/st/l4/stm32l471.dtsi
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l4.dtsi>
+
+/ {
+	soc {
+		pinctrl: pin-controller@48000000 {
+
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@48001400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@48001800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+				label = "GPIOG";
+			};
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+		};
+
+		timers8: timers@40013400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <4>;
+			phase-seg2 = <5>;
+		};
+
+		sdmmc1: sdmmc@40012800 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x40012800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
+			interrupts = <49 0>;
+			status = "disabled";
+			label = "SDMMC_1";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		adc3: adc@50040200 {
+			compatible = "st,stm32-adc";
+			reg = <0x50040200 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <47 0>;
+			status = "disabled";
+			label = "ADC_3";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l471Xg.dtsi b/dts/arm/st/l4/stm32l471Xg.dtsi
new file mode 100644
index 0000000000..d2c894eddb
--- /dev/null
+++ b/dts/arm/st/l4/stm32l471Xg.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Allterco Robotics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l471.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l475.dtsi b/dts/arm/st/l4/stm32l475.dtsi
new file mode 100644
index 0000000000..f769d58e20
--- /dev/null
+++ b/dts/arm/st/l4/stm32l475.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l471.dtsi>
+
+/ {
+	soc {
+		usbotg_fs: otgfs@50000000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "otgfs";
+			num-bidir-endpoints = <6>;
+			ram-size = <1280>;
+			maximum-speed = "full-speed";
+			phys = <&otgfs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>;
+			status = "disabled";
+			label= "OTGFS";
+		};
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGFS_PHY";
+	};
+};
diff --git a/dts/arm/st/l4/stm32l475Xg.dtsi b/dts/arm/st/l4/stm32l475Xg.dtsi
new file mode 100644
index 0000000000..98af4e3611
--- /dev/null
+++ b/dts/arm/st/l4/stm32l475Xg.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l4/stm32l475.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(96)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l476.dtsi b/dts/arm/st/l4/stm32l476.dtsi
new file mode 100644
index 0000000000..c4e638e621
--- /dev/null
+++ b/dts/arm/st/l4/stm32l476.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l475.dtsi>
+
+/ {
+	soc {
+		adc3: adc@50040200 {
+			compatible = "st,stm32-adc";
+			reg = <0x50040200 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <47 0>;
+			status = "disabled";
+			label = "ADC_3";
+		    #io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l476Xg.dtsi b/dts/arm/st/l4/stm32l476Xg.dtsi
new file mode 100644
index 0000000000..af29a4636f
--- /dev/null
+++ b/dts/arm/st/l4/stm32l476Xg.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l4/stm32l476.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(96)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l496.dtsi b/dts/arm/st/l4/stm32l496.dtsi
new file mode 100644
index 0000000000..e912fb1bd0
--- /dev/null
+++ b/dts/arm/st/l4/stm32l496.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l475.dtsi>
+
+/ {
+	soc {
+		i2c4: i2c@40008400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40008400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
+			interrupts = <83 0>, <84 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_4";
+		};
+
+		pinctrl: pin-controller@48000000 {
+			reg = <0x48000000 0x2400>;
+
+			gpioi: gpio@48002000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48002000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
+				label = "GPIOI";
+			};
+		};
+
+		adc3: adc@50040200 {
+			compatible = "st,stm32-adc";
+			reg = <0x50040200 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <47 0>;
+			status = "disabled";
+			label = "ADC_3";
+			#io-channel-cells = <1>;
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l496Xe.dtsi b/dts/arm/st/l4/stm32l496Xe.dtsi
new file mode 100644
index 0000000000..8c3c3fc325
--- /dev/null
+++ b/dts/arm/st/l4/stm32l496Xe.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l4/stm32l496.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(256)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l496Xg.dtsi b/dts/arm/st/l4/stm32l496Xg.dtsi
new file mode 100644
index 0000000000..76c9d482bd
--- /dev/null
+++ b/dts/arm/st/l4/stm32l496Xg.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l4/stm32l496.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(320)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l4r5.dtsi b/dts/arm/st/l4/stm32l4r5.dtsi
new file mode 100644
index 0000000000..a8ecbb25a8
--- /dev/null
+++ b/dts/arm/st/l4/stm32l4r5.dtsi
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2018 Pushpal Sidhu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l4.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(640)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				erase-block-size = <4096>;
+			};
+		};
+
+		pinctrl: pin-controller@48000000 {
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@48001400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@48001800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+				label = "GPIOG";
+			};
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c4: i2c@40008400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40008400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
+			interrupts = <83 0>, <84 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_4";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <30 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <50 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers7: timers@40001400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			interrupts = <55 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_7";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_7";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers8: timers@40013400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		can1: can@40006400 {
+			compatible = "st,stm32-can";
+			reg = <0x40006400 0x400>;
+			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
+			interrupt-names = "TX", "RX0", "RX1", "SCE";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
+			status = "disabled";
+			label = "CAN_1";
+			bus-speed = <125000>;
+			sjw = <1>;
+			prop-seg = <0>;
+			phase-seg1 = <4>;
+			phase-seg2 = <5>;
+		};
+
+		usbotg_fs: otgfs@50000000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67 0>;
+			interrupt-names = "otgfs";
+			num-bidir-endpoints = <6>;
+			ram-size = <1280>;
+			maximum-speed = "full-speed";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>;
+			phys = <&otgfs_phy>;
+			status = "disabled";
+			label= "OTGFS";
+		};
+
+		dma1: dma@40020000 {
+			dma-offset = <0>;
+		};
+
+		dma2: dma@40020400 {
+			dma-offset = <7>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			compatible = "st,stm32-dmamux";
+			#dma-cells = <3>;
+			reg = <0x40020800 0x400>;
+			interrupts = <94 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
+			dma-channels = <14>;
+			dma-generators = <4>;
+			dma-requests= <89>;
+			status = "disabled";
+			label = "DMAMUX_1";
+		};
+
+		sdmmc1: sdmmc@50062400 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x50062400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x400000>;
+			interrupts = <49 0>;
+			status = "disabled";
+			label = "SDMMC_1";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGFS_PHY";
+	};
+};
diff --git a/dts/arm/st/l4/stm32l4r5Xi.dtsi b/dts/arm/st/l4/stm32l4r5Xi.dtsi
new file mode 100644
index 0000000000..9154d8820f
--- /dev/null
+++ b/dts/arm/st/l4/stm32l4r5Xi.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 Pushpal Sidhu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l4r5.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l4r9.dtsi b/dts/arm/st/l4/stm32l4r9.dtsi
new file mode 100644
index 0000000000..b0f53d17c2
--- /dev/null
+++ b/dts/arm/st/l4/stm32l4r9.dtsi
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l4r5.dtsi>
+
diff --git a/dts/arm/st/l4/stm32l4r9Xi.dtsi b/dts/arm/st/l4/stm32l4r9Xi.dtsi
new file mode 100644
index 0000000000..82fe423ed1
--- /dev/null
+++ b/dts/arm/st/l4/stm32l4r9Xi.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l4r9.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l4s5.dtsi b/dts/arm/st/l4/stm32l4s5.dtsi
new file mode 100644
index 0000000000..423e0edb16
--- /dev/null
+++ b/dts/arm/st/l4/stm32l4s5.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l4/stm32l4r5.dtsi>
diff --git a/dts/arm/st/l4/stm32l4s5Xi.dtsi b/dts/arm/st/l4/stm32l4s5Xi.dtsi
new file mode 100644
index 0000000000..870b1d8c7a
--- /dev/null
+++ b/dts/arm/st/l4/stm32l4s5Xi.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l4/stm32l4s5.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi
new file mode 100644
index 0000000000..c738d0eae3
--- /dev/null
+++ b/dts/arm/st/l5/stm32l5.dtsi
@@ -0,0 +1,616 @@
+/*
+ * Copyright (c) 2021 The Chromium OS Authors
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <arm/armv8-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_msi: clk-msi {
+			#clock-cells = <0>;
+			compatible = "st,stm32-msi-clock";
+			msi-range = <6>; /* 4MHz (reset value) */
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32l4-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@40022000 {
+			compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <6 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+				write-block-size = <8>;
+				erase-block-size = <2048>;
+
+				/* using maximum erase time(ms) for 4K page, since
+				 * datasheet does not show the maximum erase
+				 * for a 2K(dual-bank) page.
+				 */
+				max-erase-time = <25>;
+			};
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "st,stm32-rcc";
+			clocks-controller;
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+		};
+
+		exti: interrupt-controller@4000f400 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x4000f400 0x400>;
+		};
+
+		pinctrl: pin-controller@42020000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x42020000 0x2000>;
+
+			gpioa: gpio@42020000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@42020400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@42020800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@42020c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@42021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@42021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@42021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioh: gpio@42021c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+				label = "GPIOH";
+			};
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <61 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <62 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <63 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <64 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <65 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		lpuart1: serial@40008000 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x40008000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
+			interrupts = <66 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		lptim1: timers@40007c00 {
+			compatible = "st,stm32-lptim";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007c00 0x400>;
+			interrupts = <67 1>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020000 0x400>;
+			interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			dma-requests = <8>;
+			dma-offset = <0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020400 0x400>;
+			interrupts = <80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			dma-requests = <8>;
+			dma-offset = <8>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dmamux1: dmamux@40020800 {
+			compatible = "st,stm32-dmamux";
+			#dma-cells = <3>;
+			reg = <0x40020800 0x400>;
+			interrupts = <27 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
+			dma-channels = <16>;
+			dma-generators = <4>;
+			dma-requests= <90>;
+			status = "disabled";
+			label = "DMAMUX_1";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <55 0>, <56 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <57 0>, <58 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_2";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			interrupts = <59 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			interrupts = <60 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			interrupts = <99 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		rng: rng@420c0800 {
+			compatible = "st,stm32-rng";
+			reg = <0x420c0800 0x400>;
+			interrupts = <94 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
+			health-test-magic = <0x17590abc>;
+			health-test-config = <0xa2b3>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <45 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers3: timers@40000400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			interrupts = <46 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_3";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_3";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			interrupts = <47 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_4";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_4";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers5: timers@40000c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			interrupts = <48 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_5";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_5";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers8: timers@40013400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <51 0>, <52 0>, <53 0>, <54 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_8";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_8";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			interrupts = <69 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_15";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_15";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <70 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <71 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@42028000 {
+			compatible = "st,stm32-adc";
+			reg = <0x42028000 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		adc2: adc@42028100 {
+			compatible = "st,stm32-adc";
+			reg = <0x42028100 0x100>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "ADC_2";
+			#io-channel-cells = <1>;
+		};
+
+		usb: usb@4000d400 {
+			compatible = "st,stm32-usb";
+			reg = <0x4000d400 0x400>;
+			interrupts = <73 0>;
+			interrupt-names = "usb";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			status = "disabled";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00200000>;
+			phys = <&usb_fs_phy>;
+			label = "USB";
+		};
+
+		ucpd1: ucpd@4000dc00 {
+			compatible = "st,stm32-ucpd";
+			reg = <0x4000dc00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <106 0>;
+			status = "disabled";
+			label = "UCPD_1";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/st/l5/stm32l552.dtsi b/dts/arm/st/l5/stm32l552.dtsi
new file mode 100644
index 0000000000..c59db74353
--- /dev/null
+++ b/dts/arm/st/l5/stm32l552.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l5/stm32l5.dtsi>
diff --git a/dts/arm/st/l5/stm32l552Xe.dtsi b/dts/arm/st/l5/stm32l552Xe.dtsi
new file mode 100644
index 0000000000..a5634a7319
--- /dev/null
+++ b/dts/arm/st/l5/stm32l552Xe.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l5/stm32l552.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l5/stm32l562.dtsi b/dts/arm/st/l5/stm32l562.dtsi
new file mode 100644
index 0000000000..bccb7e5f95
--- /dev/null
+++ b/dts/arm/st/l5/stm32l562.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/l5/stm32l5.dtsi>
+
+/ {
+	soc {
+		aes: aes@420c0000 {
+			compatible = "st,stm32-aes";
+			reg = <0x420c0000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			interrupts = <93 0>;
+			status = "disabled";
+			label = "AES";
+		};
+	};
+};
diff --git a/dts/arm/st/l5/stm32l562Xe.dtsi b/dts/arm/st/l5/stm32l562Xe.dtsi
new file mode 100644
index 0000000000..b0216949a2
--- /dev/null
+++ b/dts/arm/st/l5/stm32l562Xe.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/l5/stm32l562.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi
new file mode 100644
index 0000000000..cce0fd521c
--- /dev/null
+++ b/dts/arm/st/mp1/stm32mp157.dtsi
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4";
+			reg = <0>;
+		};
+	};
+
+	retram: memory0@0 {
+		compatible = "mmio-sram";
+		reg = <0x00000000 DT_SIZE_K(64)>;
+	};
+	mcusram: memory1@10000000 {
+		compatible = "mmio-sram";
+		reg = <0x10000000 DT_SIZE_K(320)>;
+	};
+
+	soc {
+		rcc: rcc@50000000 {
+			compatible = "st,stm32mp1-rcc";
+			reg = <0x50000000 0x1000>;
+			#clock-cells = <2>;
+		};
+
+		exti: interrupt-controller@5000d000 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x5000d000 0x400>;
+		};
+
+		pinctrl: pin-controller@50002000 {
+			compatible = "st,stm32-pinctrl";
+			reg = <0x50002000 0x9000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@50002000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50002000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@50003000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50003000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@50004000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50004000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@50005000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50005000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@50006000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50006000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@50007000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50007000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@50008000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50008000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioh: gpio@50009000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50009000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
+				label = "GPIOH";
+			};
+
+			gpioi: gpio@5000a000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x5000a000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
+				label = "GPIOI";
+			};
+
+			gpioj: gpio@5000b000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x5000b000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@5000c000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x5000c000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
+				label = "GPIOK";
+			};
+		};
+
+		wwdg1: watchdog@4000a000 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x4000A000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG_1";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		spi1: spi@44004000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			reg = <0x44004000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x100>;
+			interrupts = <35 5>;
+			label = "SPI_1";
+			status = "disabled";
+		};
+
+		spi2: spi@4000b000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			reg = <0x4000b000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x800>;
+			interrupts = <36 5>;
+			label = "SPI_2";
+			status = "disabled";
+		};
+
+		spi3: spi@4000c000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			reg = <0x4000c000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x1000>;
+			interrupts = <51 5>;
+			label = "SPI_3";
+			status = "disabled";
+		};
+
+		spi4: spi@44005000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			reg = <0x44005000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x200>;
+			interrupts = <84 5>;
+			label = "SPI_4";
+			status = "disabled";
+		};
+
+		spi5: spi@44009000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			reg = <0x44009000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x400>;
+			interrupts = <85 5>;
+			label = "SPI_5";
+			status = "disabled";
+		};
+
+		usart2: serial@4000e000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x4000e000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@4000f000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x4000f000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <39 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40010000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40010000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00010000>;
+			interrupts = <52 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40011000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40011000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <53 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		usart6: serial@44003000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x44003000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			interrupts = <71 0>;
+			status = "disabled";
+			label = "UART_6";
+		};
+
+		uart7: serial@40018000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40018000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <82 0>;
+			status = "disabled";
+			label = "UART_7";
+		};
+
+		uart8: serial@40019000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40019000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <83 0>;
+			status = "disabled";
+			label = "UART_8";
+		};
+
+		i2c5: i2c@40015000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			reg = <0x40015000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
+			interrupt-names = "event", "error";
+			interrupts = <107 0>, <108 0>;
+			status = "disabled";
+			label = "I2C_5";
+		};
+
+		mailbox: mailbox@4c001000 {
+			compatible = "st,stm32-ipcc-mailbox";
+			reg = <0x4c001000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>;
+			interrupts = <103 0>, <104 0>;
+			interrupt-names = "rxo", "txf";
+			status = "disabled";
+			label = "MAILBOX_0";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi
new file mode 100644
index 0000000000..9cc7862e9a
--- /dev/null
+++ b/dts/arm/st/u5/stm32u5.dtsi
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2021 The Chromium OS Authors
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <arm/armv8-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_msis: clk-msis {
+			#clock-cells = <0>;
+			compatible = "st,stm32u5-msi-clock";
+			msi-range = <4>; /* 4MHz (reset value) */
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll1: pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32u5-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash-controller@40022000 {
+			compatible = "st,stm32u5-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40022000 0x400>;
+			interrupts = <6 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+			};
+		};
+
+		rcc: rcc@46020c00 {
+			compatible = "st,stm32u5-rcc";
+			clocks-controller;
+			#clock-cells = <2>;
+			reg = <0x46020c00 0x400>;
+		};
+
+		exti: interrupt-controller@46022000 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x46022000 0x400>;
+		};
+
+		pinctrl: pin-controller@42020000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x42020000 0x2000>;
+
+			gpioa: gpio@42020000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@42020400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@42020800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@42020c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@42021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@42021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@42021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioh: gpio@42021c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+				label = "GPIOH";
+			};
+
+			gpioi: gpio@42022000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42022000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
+				label = "GPIOI";
+			};
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg1: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002c00 0x1000>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			interrupts = <0 7>;
+			status = "disabled";
+			label = "WWDG_1";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <61 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <62 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			interrupts = <63 0>;
+			status = "disabled";
+			label = "UART_3";
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			interrupts = <64 0>;
+			status = "disabled";
+			label = "UART_4";
+		};
+
+		uart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			interrupts = <65 0>;
+			status = "disabled";
+			label = "UART_5";
+		};
+
+		lpuart1: serial@46002400 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x46002400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>;
+			interrupts = <66 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			interrupts = <59 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			interrupts = <60 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@46002000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x46002000 0x400>;
+			interrupts = <99 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000020>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <55 0>, <56 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <57 0>, <58 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		lptim1: timers@46004400 {
+			compatible = "st,stm32-lptim";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x46004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
+			interrupts = <67 1>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
+
+		rng: rng@420c0800 {
+			compatible = "st,stm32-rng";
+			reg = <0x420c0800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
+			interrupts = <94 0>;
+			health-test-config = <0x9aae>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		dac1: dac@46021800 {
+			compatible = "st,stm32-dac";
+			reg = <0x46021800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000040>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		adc1: adc@42028000 {
+			compatible = "st,stm32-adc";
+			reg = <0x42028000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		adc4: adc@46021000 {
+			compatible = "st,stm32-adc";
+			reg = <0x46021000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000020>;
+			interrupts = <113 0>;
+			status = "disabled";
+			label = "ADC_4";
+			#io-channel-cells = <1>;
+		};
+
+		ucpd1: ucpd@4000dc00 {
+			compatible = "st,stm32-ucpd";
+			reg = <0x4000dc00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <106 0>;
+			status = "disabled";
+			label = "UCPD_1";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/u5/stm32u575.dtsi b/dts/arm/st/u5/stm32u575.dtsi
new file mode 100644
index 0000000000..1ab8fbebc8
--- /dev/null
+++ b/dts/arm/st/u5/stm32u575.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/u5/stm32u5.dtsi>
+
+
+/ {
+	soc {
+		usbotg_fs: otgfs@42040000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x42040000 0x80000>;
+			interrupts = <73 0>;
+			interrupt-names = "otgfs";
+			num-bidir-endpoints = <6>;
+			ram-size = <1280>;
+			maximum-speed = "full-speed";
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>;
+			phys = <&otgfs_phy>;
+			status = "disabled";
+			label= "OTGFS";
+		};
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "OTGFS_PHY";
+	};
+};
diff --git a/dts/arm/st/u5/stm32u575Xi.dtsi b/dts/arm/st/u5/stm32u575Xi.dtsi
new file mode 100644
index 0000000000..652493cc56
--- /dev/null
+++ b/dts/arm/st/u5/stm32u575Xi.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/u5/stm32u575.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(786)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_M(2)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/u5/stm32u585.dtsi b/dts/arm/st/u5/stm32u585.dtsi
new file mode 100644
index 0000000000..46d0dd9c99
--- /dev/null
+++ b/dts/arm/st/u5/stm32u585.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/u5/stm32u575.dtsi>
diff --git a/dts/arm/st/u5/stm32u585Xi.dtsi b/dts/arm/st/u5/stm32u585Xi.dtsi
new file mode 100644
index 0000000000..73066707d4
--- /dev/null
+++ b/dts/arm/st/u5/stm32u585Xi.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/u5/stm32u585.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(786)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_M(2)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi
new file mode 100644
index 0000000000..1927163c1b
--- /dev/null
+++ b/dts/arm/st/wb/stm32wb.dtsi
@@ -0,0 +1,460 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	sram1: memory@20030000 {
+		compatible = "mmio-sram";
+		reg = <0x20030000 0x2800>;
+		zephyr,memory-region = "SRAM1";
+	};
+
+	sram2: memory@20038000 {
+		compatible = "mmio-sram";
+		reg = <0x20038000 0x5000>;
+		zephyr,memory-region = "SRAM2";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			/* Expected clock-frequency on the whole series 32MHz */
+			clock-frequency = <DT_FREQ_M(32)>;
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_msi: clk-msi {
+			#clock-cells = <0>;
+			compatible = "st,stm32-msi-clock";
+			msi-range = <6>; /* 4MHz (reset value) */
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi1: clk-lsi1 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		clk_lsi2: clk-lsi2 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32wb-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@58004000 {
+			compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x58004000 0x400>;
+			interrupts = <4 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x02000000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <8>;
+				erase-block-size = <4096>;
+				/* maximum erase time(ms) for a 4K sector */
+				max-erase-time = <25>;
+			};
+		};
+
+		rcc: rcc@58000000 {
+			compatible = "st,stm32wb-rcc";
+			#clock-cells = <2>;
+			reg = <0x58000000 0x400>;
+		};
+
+		exti: interrupt-controller@58000800 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x58000800 0x400>;
+		};
+
+		pinctrl: pin-controller@48000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x48000000 0x2000>;
+
+			gpioa: gpio@48000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@48000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@48000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@48000c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@48001000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpioh: gpio@48001c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+				label = "GPIOH";
+			};
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <36 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <30 0>, <31 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c3: i2c@40005c00 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <32 0>, <33 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_3";
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			interrupts = <41 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			interrupts = <34 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			interrupts = <35 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		lpuart1: serial@40008000 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x40008000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <25 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		adc1: adc@50040000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50040000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+		};
+
+		lptim1: timers@40007c00 {
+			compatible = "st,stm32-lptim";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007c00 0x400>;
+			interrupts = <47 1>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020000 0x400>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			dma-requests = <7>;
+			dma-offset = <0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020400 0x400>;
+			interrupts = <55 0 56 0 57 0 58 0 59 0 60 0 61 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			dma-requests = <7>;
+			dma-offset = <7>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dmamux1: dmamux@40020800 {
+			compatible = "st,stm32-dmamux";
+			#dma-cells = <3>;
+			reg = <0x40020800 0x400>;
+			interrupts = <62 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
+			dma-channels = <14>;
+			dma-generators = <4>;
+			dma-requests= <36>;
+			status = "disabled";
+			label = "DMAMUX_1";
+		};
+
+		usb: usb@40006800 {
+			compatible = "st,stm32-usb";
+			reg = <0x40006800 0x400>;
+			interrupts = <20 0>, <19 0>;
+			interrupt-names = "usb", "usbhp";
+			num-bidir-endpoints = <8>;
+			ram-size = <1024>;
+			phys = <&usb_fs_phy>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			status = "disabled";
+			label = "USB";
+		};
+
+		quadspi: quadspi@a0001000 {
+			compatible = "st,stm32-qspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			reg = <0xa0001000 0x400>;
+			interrupts = <0x32 0x0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x100>;
+			status = "disabled";
+			label = "QUADSPI";
+		};
+
+		rng: rng@58001000 {
+			compatible = "st,stm32-rng";
+			reg = <0x58001000 0x400>;
+			interrupts = <53 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00040000>;
+			status = "disabled";
+			label = "RNG";
+		};
+	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		label = "USB_FS_PHY";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/wb/stm32wb55.dtsi b/dts/arm/st/wb/stm32wb55.dtsi
new file mode 100644
index 0000000000..d77bb20b15
--- /dev/null
+++ b/dts/arm/st/wb/stm32wb55.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/wb/stm32wb.dtsi>
diff --git a/dts/arm/st/wb/stm32wb55Xg.dtsi b/dts/arm/st/wb/stm32wb55Xg.dtsi
new file mode 100644
index 0000000000..bb13593446
--- /dev/null
+++ b/dts/arm/st/wb/stm32wb55Xg.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wb/stm32wb55.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(96)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(808)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wl.dtsi b/dts/arm/st/wl/stm32wl.dtsi
new file mode 100644
index 0000000000..9af81f6813
--- /dev/null
+++ b/dts/arm/st/wl/stm32wl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Copyright (c) 2020 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/lora/sx126x.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+		zephyr,flash-controller = &flash;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32wl-hse-clock";
+			/* Expected clock-frequency on the whole series 32MHz */
+			clock-frequency = <DT_FREQ_M(32)>;
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			status = "disabled";
+		};
+
+		clk_msi: clk-msi {
+			#clock-cells = <0>;
+			compatible = "st,stm32-msi-clock";
+			msi-range = <6>; /* 4MHz (reset value) */
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32wb-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		flash: flash-controller@58004000 {
+			compatible = "st,stm32-flash-controller", "st,stm32wl-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x58004000 0x400>;
+			interrupts = <4 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "st,stm32-nv-flash", "soc-nv-flash";
+				label = "FLASH_STM32";
+
+				write-block-size = <8>;
+				erase-block-size = <2048>;
+				/* maximum erase time(ms) for a 2K sector */
+				max-erase-time = <25>;
+			};
+		};
+
+		rcc: rcc@58000000 {
+			compatible = "st,stm32wl-rcc";
+			#clock-cells = <2>;
+			reg = <0x58000000 0x400>;
+			label = "STM32_CLK_RCC";
+		};
+
+		exti: interrupt-controller@58000800 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x58000800 0x400>;
+		};
+
+		pinctrl: pin-controller@48000000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x48000000 0x2000>;
+
+			gpioa: gpio@48000000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000000 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@48000400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@48000800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48000800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpioh: gpio@48001c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x48001c00 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+				label = "GPIOH";
+			};
+		};
+
+		lptim1: timers@40007c00 {
+			compatible = "st,stm32-lptim";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007c00 0x400>;
+			interrupts = <39 1>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			interrupts = <42 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
+			prescaler = <32768>;
+			status = "disabled";
+			label = "RTC_0";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 0x400>;
+			label = "IWDG";
+			status = "disabled";
+		};
+
+		wwdg: watchdog@40002c00 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x40002C00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			label = "WWDG";
+			interrupts = <0 7>;
+			status = "disabled";
+		};
+
+		usart1: serial@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			interrupts = <36 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			interrupts = <37 0>;
+			status = "disabled";
+			label = "UART_2";
+		};
+
+		lpuart1: serial@40008000 {
+			compatible = "st,stm32-lpuart", "st,stm32-uart";
+			reg = <0x40008000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
+			interrupts = <38 0>;
+			status = "disabled";
+			label = "LPUART_1";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <30 0>, <31 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <32 0>, <33 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		i2c3: i2c@40005c00 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			interrupts = <48 0>, <49 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_3";
+		};
+
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			interrupts = <34 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			interrupts = <35 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		subghzspi: spi@58010000 {
+			compatible = "st,stm32-spi-subghz", "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58010000 0x400>;
+			interrupts = <44 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000001>;
+			status = "disabled";
+			label = "SUBGHZSPI";
+			use-subghzspi-nss;
+
+			radio@0 {
+				compatible = "st,stm32wl-subghz-radio";
+				reg = <0>;
+				interrupts = <50 0>;
+				spi-max-frequency = <12000000>;
+				status = "disabled";
+				label = "subghz-radio";
+			};
+		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+			#io-channel-cells = <1>;
+		};
+
+		dac1: dac@40007400 {
+			compatible = "st,stm32-dac";
+			reg = <0x40007400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			status = "disabled";
+			label = "DAC_1";
+			#io-channel-cells = <1>;
+		};
+
+		timers1: timers@40012c00 {
+			compatible = "st,stm32-timers";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			interrupts = <23 0>, <24 0>, <25 0>, <26 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_1";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_1";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers2: timers@40000000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			interrupts = <27 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_2";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_2";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers16: timers@40014400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			interrupts = <28 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_16";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_16";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timers17: timers@40014800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			interrupts = <29 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+			label = "TIMERS_17";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				label = "PWM_17";
+				#pwm-cells = <3>;
+			};
+		};
+
+		aes: aes@58001800 {
+			compatible = "st,stm32-aes";
+			reg = <0x58001800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00020000>;
+			interrupts = <51 0>;
+			status = "disabled";
+			label = "AES";
+		};
+
+		rng: rng@58001000 {
+			compatible = "st,stm32-rng";
+			reg = <0x58001000 0x400>;
+			interrupts = <52 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00040000>;
+			health-test-magic = <0x17590abc>;
+			health-test-config = <0xaa74>;
+			status = "disabled";
+			label = "RNG";
+		};
+
+		dma1: dma@40020000 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020000 0x400>;
+			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			dma-requests = <7>;
+			dma-offset = <0>;
+			status = "disabled";
+			label = "DMA_1";
+		};
+
+		dma2: dma@40020400 {
+			compatible = "st,stm32-dma-v2";
+			#dma-cells = <3>;
+			reg = <0x40020400 0x400>;
+			interrupts = <54 0 55 0 56 0 57 0 58 0 59 0 60 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			dma-requests = <7>;
+			dma-offset = <7>;
+			status = "disabled";
+			label = "DMA_2";
+		};
+
+		dmamux1: dmamux@40020800 {
+			compatible = "st,stm32-dmamux";
+			#dma-cells = <3>;
+			reg = <0x40020800 0x400>;
+			interrupts = <61 0>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
+			dma-channels = <14>;
+			dma-generators = <4>;
+			dma-requests= <38>;
+			status = "disabled";
+			label = "DMAMUX_1";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/wl/stm32wl54Xc.dtsi b/dts/arm/st/wl/stm32wl54Xc.dtsi
new file mode 100644
index 0000000000..a7c64b9a9d
--- /dev/null
+++ b/dts/arm/st/wl/stm32wl54Xc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wl/stm32wl55.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wl55.dtsi b/dts/arm/st/wl/stm32wl55.dtsi
new file mode 100644
index 0000000000..38d364b567
--- /dev/null
+++ b/dts/arm/st/wl/stm32wl55.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/wl/stm32wl.dtsi>
diff --git a/dts/arm/st/wl/stm32wl55Xc.dtsi b/dts/arm/st/wl/stm32wl55Xc.dtsi
new file mode 100644
index 0000000000..7c32ca481a
--- /dev/null
+++ b/dts/arm/st/wl/stm32wl55Xc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2020 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wl/stm32wl55.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wle4X8.dtsi b/dts/arm/st/wl/stm32wle4X8.dtsi
new file mode 100644
index 0000000000..925c00a502
--- /dev/null
+++ b/dts/arm/st/wl/stm32wle4X8.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wl/stm32wle5.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wle4Xb.dtsi b/dts/arm/st/wl/stm32wle4Xb.dtsi
new file mode 100644
index 0000000000..9567980282
--- /dev/null
+++ b/dts/arm/st/wl/stm32wle4Xb.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wl/stm32wle5.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(48)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wle4Xc.dtsi b/dts/arm/st/wl/stm32wle4Xc.dtsi
new file mode 100644
index 0000000000..2b47872d42
--- /dev/null
+++ b/dts/arm/st/wl/stm32wle4Xc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wl/stm32wle5.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wle5.dtsi b/dts/arm/st/wl/stm32wle5.dtsi
new file mode 100644
index 0000000000..c07d8ab3b0
--- /dev/null
+++ b/dts/arm/st/wl/stm32wle5.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/wl/stm32wl.dtsi>
diff --git a/dts/arm/st/wl/stm32wle5X8.dtsi b/dts/arm/st/wl/stm32wle5X8.dtsi
new file mode 100644
index 0000000000..925c00a502
--- /dev/null
+++ b/dts/arm/st/wl/stm32wle5X8.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wl/stm32wle5.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wle5Xb.dtsi b/dts/arm/st/wl/stm32wle5Xb.dtsi
new file mode 100644
index 0000000000..9567980282
--- /dev/null
+++ b/dts/arm/st/wl/stm32wle5Xb.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wl/stm32wle5.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(48)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wle5Xc.dtsi b/dts/arm/st/wl/stm32wle5Xc.dtsi
new file mode 100644
index 0000000000..2b47872d42
--- /dev/null
+++ b/dts/arm/st/wl/stm32wle5Xc.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wl/stm32wle5.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@58004000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/binding-template.yaml b/dts/binding-template.yaml
new file mode 100644
index 0000000000..f44a58e096
--- /dev/null
+++ b/dts/binding-template.yaml
@@ -0,0 +1,10 @@
+# The contents of this file have been moved to the documentation.
+#
+# See this page in the HTML documentation:
+#
+#       User and Developer Guides >
+#       Devicetree Guide >
+#       Devicetree bindings
+#
+# For the latest version:
+# https://docs.zephyrproject.org/latest/guides/dts/bindings.html
diff --git a/dts/bindings/adc/adc-controller.yaml b/dts/bindings/adc/adc-controller.yaml
new file mode 100644
index 0000000000..6010ae92fa
--- /dev/null
+++ b/dts/bindings/adc/adc-controller.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for ADC controllers
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    "#io-channel-cells":
+      type: int
+      required: true
diff --git a/dts/bindings/adc/arduino,uno-adc.yaml b/dts/bindings/adc/arduino,uno-adc.yaml
new file mode 100644
index 0000000000..1b37aca947
--- /dev/null
+++ b/dts/bindings/adc/arduino,uno-adc.yaml
@@ -0,0 +1,34 @@
+# Copyright (C) 2019 Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ADC channels exposed on Arduino Uno (R3) headers.
+
+    The Arduino Uno layout provides a 6-pin Analog Input header.  This
+    has analog input signals labeled from A0 at the top through A5 at
+    the bottom.
+
+    This binding provides a nexus mapping for these pins where parent
+    pins 0 through 5 correspond to A0 through A5.
+
+compatible: "arduino,uno-adc"
+
+include: base.yaml
+
+properties:
+    io-channel-map:
+      type: compound
+      required: true
+
+    io-channel-map-mask:
+      type: compound
+      required: false
+
+    io-channel-map-pass-thru:
+      type: compound
+      required: false
+
+    "#io-channel-cells":
+      type: int
+      required: true
+      description: Number of items to expect in an ADC specifier
diff --git a/dts/bindings/adc/atmel,sam-afec.yaml b/dts/bindings/adc/atmel,sam-afec.yaml
new file mode 100644
index 0000000000..1f468fa820
--- /dev/null
+++ b/dts/bindings/adc/atmel,sam-afec.yaml
@@ -0,0 +1,35 @@
+description: Atmel SAM family AFEC
+
+compatible: "atmel,sam-afec"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    pinctrl-0:
+      type: phandles
+      required: true
+      description: |
+        PIO pin configuration for ADTRG signal.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the I2C on SAME7x would be
+           pinctrl-0 = <&pa8b_afec0_adtrg>;
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/atmel,sam0-adc.yaml b/dts/bindings/adc/atmel,sam0-adc.yaml
new file mode 100644
index 0000000000..48acee8b7b
--- /dev/null
+++ b/dts/bindings/adc/atmel,sam0-adc.yaml
@@ -0,0 +1,48 @@
+# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 family ADC
+
+compatible: "atmel,sam0-adc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    clock-names:
+      required: true
+
+    gclk:
+      type: int
+      required: true
+      description: generic clock generator source
+
+    prescaler:
+      type: int
+      required: true
+      description: clock prescaler divisor applied to the generic clock
+
+    "#io-channel-cells":
+      const: 1
+
+    calib-offset:
+      type: int
+      required: false
+      description: |
+        bit position offset in NVM SW Calib for start of ADC0 BIASCOMP field.
+        This property is expected to be set on SAM{D,E}5x family of SoCs.
+        For ADC0 this should be 0, and for ADC1 this should be 14.
+      enum:
+        - 0
+        - 14
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/ite,it8xxx2-adc.yaml b/dts/bindings/adc/ite,it8xxx2-adc.yaml
new file mode 100644
index 0000000000..3ad4e7879b
--- /dev/null
+++ b/dts/bindings/adc/ite,it8xxx2-adc.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it8xxx2 ADC
+
+compatible: "ite,it8xxx2-adc"
+
+include: adc-controller.yaml
+
+properties:
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
diff --git a/dts/bindings/adc/microchip,mcp3204.yaml b/dts/bindings/adc/microchip,mcp3204.yaml
new file mode 100644
index 0000000000..62d3c82997
--- /dev/null
+++ b/dts/bindings/adc/microchip,mcp3204.yaml
@@ -0,0 +1,5 @@
+description: Microchip MCP3204
+
+compatible: "microchip,mcp3204"
+
+include: microchip,mcp320x-base.yaml
diff --git a/dts/bindings/adc/microchip,mcp3208.yaml b/dts/bindings/adc/microchip,mcp3208.yaml
new file mode 100644
index 0000000000..518ed7ab0e
--- /dev/null
+++ b/dts/bindings/adc/microchip,mcp3208.yaml
@@ -0,0 +1,5 @@
+description: Microchip MCP3208
+
+compatible: "microchip,mcp3208"
+
+include: microchip,mcp320x-base.yaml
diff --git a/dts/bindings/adc/microchip,mcp320x-base.yaml b/dts/bindings/adc/microchip,mcp320x-base.yaml
new file mode 100644
index 0000000000..8ab984605f
--- /dev/null
+++ b/dts/bindings/adc/microchip,mcp320x-base.yaml
@@ -0,0 +1,10 @@
+# Common fields for Microchip MCP3204/MCP3208
+
+include: [adc-controller.yaml, spi-device.yaml]
+
+properties:
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - channel
diff --git a/dts/bindings/adc/microchip,xec-adc-v2.yaml b/dts/bindings/adc/microchip,xec-adc-v2.yaml
new file mode 100644
index 0000000000..479daa29d9
--- /dev/null
+++ b/dts/bindings/adc/microchip,xec-adc-v2.yaml
@@ -0,0 +1,48 @@
+# Copyright (c) 2019, Intel Corporation
+# Copyright (c) 2021, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC ADC
+
+compatible: "microchip,xec-adc-v2"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    girqs:
+      type: array
+      required: true
+      description: Array of pairs of GIRQ number and bit position
+
+    pcrs:
+      type: array
+      required: true
+      description: ADC PCR register index and bit position
+
+    "#girq-cells":
+      type: int
+      const: 2
+
+    "#pcr-cells":
+      type: int
+      const: 2
+
+io-channel-cells:
+    - input
+
+girq-cells:
+    - girqnum
+    - bitpos
+
+pcr-cells:
+    - regidx
+    - bitpos
diff --git a/dts/bindings/adc/microchip,xec-adc.yaml b/dts/bindings/adc/microchip,xec-adc.yaml
new file mode 100644
index 0000000000..6d8216b7d6
--- /dev/null
+++ b/dts/bindings/adc/microchip,xec-adc.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC ADC
+
+compatible: "microchip,xec-adc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    clktime:
+      type: int
+      required: true
+      description: ADC clock high & low time count value <1:255>
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/nordic,nrf-adc.yaml b/dts/bindings/adc/nordic,nrf-adc.yaml
new file mode 100644
index 0000000000..bd42c6e248
--- /dev/null
+++ b/dts/bindings/adc/nordic,nrf-adc.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: nRF ADC node
+
+compatible: "nordic,nrf-adc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/nordic,nrf-saadc.yaml b/dts/bindings/adc/nordic,nrf-saadc.yaml
new file mode 100644
index 0000000000..881d620668
--- /dev/null
+++ b/dts/bindings/adc/nordic,nrf-saadc.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic Semiconductor nRF family SAADC node
+
+compatible: "nordic,nrf-saadc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/nxp,kinetis-adc12.yaml b/dts/bindings/adc/nxp,kinetis-adc12.yaml
new file mode 100644
index 0000000000..914adcf7ee
--- /dev/null
+++ b/dts/bindings/adc/nxp,kinetis-adc12.yaml
@@ -0,0 +1,41 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis ADC12
+
+compatible: "nxp,kinetis-adc12"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clk-source:
+      type: int
+      required: true
+      description: converter clock source
+
+    clk-divider:
+      type: int
+      required: true
+      description: clock divider for the converter
+
+    alternate-voltage-reference:
+      type: boolean
+      required: false
+      description: use alternate voltage reference source
+
+    sample-time:
+      type: int
+      required: true
+      description: sample time in clock cycles
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/nxp,kinetis-adc16.yaml b/dts/bindings/adc/nxp,kinetis-adc16.yaml
new file mode 100644
index 0000000000..8558374c34
--- /dev/null
+++ b/dts/bindings/adc/nxp,kinetis-adc16.yaml
@@ -0,0 +1,63 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis ADC16
+
+compatible: "nxp,kinetis-adc16"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    channel-mux-b:
+      type: boolean
+      required: false
+      description: |
+        Use alternate set (b instead of a) of ADC channels
+
+    interrupts:
+      required: true
+
+    periodic-trigger:
+      type: boolean
+      required: false
+      description: if periodic trigger enabled
+
+    "#io-channel-cells":
+      const: 1
+
+    clk-source:
+      type: int
+      required: false
+      description: use alternate clock reference source
+
+    long-sample:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 4
+      description: long sample mode
+
+    continuous-convert:
+      type: boolean
+      required: false
+      description: If use continuous convert
+
+    high-speed:
+      type: boolean
+      required: false
+      description: If use high speed
+
+    hw-trigger-src:
+      type: int
+      required: false
+      description: hardware trigger source (See ADCxTRGSEL field in user manual for more details)
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/nxp,mcux-12b1msps-sar.yaml b/dts/bindings/adc/nxp,mcux-12b1msps-sar.yaml
new file mode 100644
index 0000000000..3f9a36c5e8
--- /dev/null
+++ b/dts/bindings/adc/nxp,mcux-12b1msps-sar.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUA 12B1MSPS SAR ADC
+
+compatible: "nxp,mcux-12b1msps-sar"
+
+include: adc-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clk-divider:
+    type: int
+    required: true
+    description: clock divider for the converter
+
+  sample-period-mode:
+    type: int
+    required: true
+    description: sample period mode
+
+  "#io-channel-cells":
+    const: 1
+
+io-channel-cells:
+  - input
diff --git a/dts/bindings/adc/st,stm32-adc.yaml b/dts/bindings/adc/st,stm32-adc.yaml
new file mode 100644
index 0000000000..ab4aa56c7d
--- /dev/null
+++ b/dts/bindings/adc/st,stm32-adc.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2018, Endre Karlson
+# Copyright (c) 2018, Song Qiang <songqiang1304521@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST STM32 family ADC
+
+compatible: "st,stm32-adc"
+
+include: [adc-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/ti,cc32xx-adc.yaml b/dts/bindings/adc/ti,cc32xx-adc.yaml
new file mode 100644
index 0000000000..9a8457f328
--- /dev/null
+++ b/dts/bindings/adc/ti,cc32xx-adc.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2021 Pavlo Hamov <pasha.gamov@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: cc32xx ADC node
+
+compatible: "ti,cc32xx-adc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/adc/ti,lmp90077.yaml b/dts/bindings/adc/ti,lmp90077.yaml
new file mode 100644
index 0000000000..1ad99c2eb6
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90077.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90077 AFE binding
+
+compatible: "ti,lmp90077"
+
+include: ti,lmp90xxx-base.yaml
diff --git a/dts/bindings/adc/ti,lmp90078.yaml b/dts/bindings/adc/ti,lmp90078.yaml
new file mode 100644
index 0000000000..1dc44a6137
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90078.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90078 AFE binding
+
+compatible: "ti,lmp90078"
+
+include: ti,lmp90xxx-current.yaml
diff --git a/dts/bindings/adc/ti,lmp90079.yaml b/dts/bindings/adc/ti,lmp90079.yaml
new file mode 100644
index 0000000000..478bad76b4
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90079.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90079 AFE binding
+
+compatible: "ti,lmp90079"
+
+include: ti,lmp90xxx-base.yaml
diff --git a/dts/bindings/adc/ti,lmp90080.yaml b/dts/bindings/adc/ti,lmp90080.yaml
new file mode 100644
index 0000000000..8693d76eb2
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90080.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90080 AFE binding
+
+compatible: "ti,lmp90080"
+
+include: ti,lmp90xxx-current.yaml
diff --git a/dts/bindings/adc/ti,lmp90097.yaml b/dts/bindings/adc/ti,lmp90097.yaml
new file mode 100644
index 0000000000..e8992783f3
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90097.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90097 AFE binding
+
+compatible: "ti,lmp90097"
+
+include: ti,lmp90xxx-base.yaml
diff --git a/dts/bindings/adc/ti,lmp90098.yaml b/dts/bindings/adc/ti,lmp90098.yaml
new file mode 100644
index 0000000000..0b3a5ce50b
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90098.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90098 AFE binding
+
+compatible: "ti,lmp90098"
+
+include: ti,lmp90xxx-current.yaml
diff --git a/dts/bindings/adc/ti,lmp90099.yaml b/dts/bindings/adc/ti,lmp90099.yaml
new file mode 100644
index 0000000000..8c8b5a31f7
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90099.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90099 AFE binding
+
+compatible: "ti,lmp90099"
+
+include: ti,lmp90xxx-base.yaml
diff --git a/dts/bindings/adc/ti,lmp90100.yaml b/dts/bindings/adc/ti,lmp90100.yaml
new file mode 100644
index 0000000000..0d000e0fb2
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90100.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90100 AFE binding
+
+compatible: "ti,lmp90100"
+
+include: ti,lmp90xxx-current.yaml
diff --git a/dts/bindings/adc/ti,lmp90xxx-base.yaml b/dts/bindings/adc/ti,lmp90xxx-base.yaml
new file mode 100644
index 0000000000..dd12e34564
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90xxx-base.yaml
@@ -0,0 +1,18 @@
+# Common fields for Texas Instruments LMP90xxx AFEs
+
+include: [adc-controller.yaml, spi-device.yaml]
+
+bus: lmp90xxx
+
+properties:
+    drdyb-gpios:
+      type: phandle-array
+      required: false
+      description: Data Ready Bar
+
+    "#io-channel-cells":
+      const: 2
+
+io-channel-cells:
+    - positive
+    - negative
diff --git a/dts/bindings/adc/ti,lmp90xxx-current.yaml b/dts/bindings/adc/ti,lmp90xxx-current.yaml
new file mode 100644
index 0000000000..7c77ad7f26
--- /dev/null
+++ b/dts/bindings/adc/ti,lmp90xxx-current.yaml
@@ -0,0 +1,9 @@
+# Common fields for Texas Instruments LMP90xxx AFEs with current sources
+
+include: ti,lmp90xxx-base.yaml
+
+properties:
+    rtd-current:
+      type: int
+      required: false
+      description: RTD current in microampere
diff --git a/dts/bindings/adc/voltage-divider.yaml b/dts/bindings/adc/voltage-divider.yaml
new file mode 100644
index 0000000000..7506d7892c
--- /dev/null
+++ b/dts/bindings/adc/voltage-divider.yaml
@@ -0,0 +1,40 @@
+# Copyright (c) 2019, Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Description for a voltage divider, with optional ability to measure
+    resistance of the upper leg.
+
+compatible: "voltage-divider"
+
+include: base.yaml
+
+properties:
+    io-channels:
+      required: true
+      description: |
+        Channels available with this divider configuration.
+
+    output-ohms:
+      type: int
+      required: true
+      description: |
+        Resistance of the lower leg of the voltage divider
+
+    full-ohms:
+      type: int
+      required: false
+      description: |
+        Resistance of the full path through the voltage divider.
+
+        If absent or zero the driver assumes that the upper leg is a
+        resistance-based sensor.
+
+    power-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Control power to the voltage divider inputs.
+
+        If present the corresponding GPIO must be set to an active level
+        to enable the divider input.
diff --git a/dts/bindings/adc/zephyr,adc-emul.yaml b/dts/bindings/adc/zephyr,adc-emul.yaml
new file mode 100644
index 0000000000..9bc956af03
--- /dev/null
+++ b/dts/bindings/adc/zephyr,adc-emul.yaml
@@ -0,0 +1,46 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr ADC Emulator
+
+compatible: "zephyr,adc-emul"
+
+include: adc-controller.yaml
+
+properties:
+    nchannels:
+        type: int
+        required: true
+        description: Number of emulated ADC channels. Should be in 1-32 range.
+
+    ref-internal-mv:
+        type: int
+        required: false
+        default: 0
+        description:
+          Internal reference voltage in mV. If not provided or set to zero,
+          channel setup with ADC_REF_INTERNAL will fail.
+
+    ref-vdd-mv:
+        type: int
+        required: false
+        default: 0
+        description:
+          VDD reference voltage in mV. If not provided or set to zero,
+          channel setup with ADC_REF_VDD_X will fail.
+
+    ref-external0-mv:
+        type: int
+        required: false
+        default: 0
+        description:
+          External 0 reference voltage in mV. If not provided or set to zero,
+          channel setup with ADC_REF_EXTERNAL0 will fail.
+
+    ref-external1-mv:
+        type: int
+        required: false
+        default: 0
+        description:
+          External 1 reference voltage in mV. If not provided or set to zero,
+          channel setup with ADC_REF_EXTERNAL1 will fail.
diff --git a/dts/bindings/arc/arc,dccm.yaml b/dts/bindings/arc/arc,dccm.yaml
new file mode 100644
index 0000000000..31e526cb76
--- /dev/null
+++ b/dts/bindings/arc/arc,dccm.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2017, synopsy
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARC DCCM
+
+compatible: "arc,dccm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arc/arc,iccm.yaml b/dts/bindings/arc/arc,iccm.yaml
new file mode 100644
index 0000000000..2bbc85c468
--- /dev/null
+++ b/dts/bindings/arc/arc,iccm.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2017, synopsys
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARC ICCM
+
+compatible: "arc,iccm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/arm,dtcm.yaml b/dts/bindings/arm/arm,dtcm.yaml
new file mode 100644
index 0000000000..8622b9845a
--- /dev/null
+++ b/dts/bindings/arm/arm,dtcm.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cortex-M DTCM (Data Tightly Coupled Memory)
+
+compatible: "arm,dtcm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/arm,itcm.yaml b/dts/bindings/arm/arm,itcm.yaml
new file mode 100644
index 0000000000..455947dbb3
--- /dev/null
+++ b/dts/bindings/arm/arm,itcm.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cortex-M ITCM (Instruction Tightly Coupled Memory)
+
+compatible: "arm,itcm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/arm,scc.yaml b/dts/bindings/arm/arm,scc.yaml
new file mode 100644
index 0000000000..189b108588
--- /dev/null
+++ b/dts/bindings/arm/arm,scc.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Serial Configuration Control (SCC)
+
+compatible: "arm,scc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/atmel,sam-ssc.yaml b/dts/bindings/arm/atmel,sam-ssc.yaml
new file mode 100644
index 0000000000..bae2da8b9e
--- /dev/null
+++ b/dts/bindings/arm/atmel,sam-ssc.yaml
@@ -0,0 +1,52 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM SSC (Synchronous Serial Controller) controller
+
+compatible: "atmel,sam-ssc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      description: |
+        PIO pin configuration for RF, RK, RD, TF, TK, & TD signals.
+        We expect that the phandles will reference pinctrl nodes.
+        These nodes will have a nodelabel that matches the Atmel SoC HAL
+        defines and be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the SSC on SAME7x would be
+           pinctrl-0 = <&pd24b_ssc_rf &pa22a_ssc_rk &pa10c_ssc_rd
+                        &pb0d_ssc_tf &pb1d_ssc_tk &pb5d_ssc_td>;
+
+      required: true
+
+    dmas:
+      required: true
+      description: |
+        TX & RX dma specifiers.  Each specifier will have a phandle
+        reference to the dma controller, the channel number, and peripheral
+        trigger source.
+
+        For example dmas for TX, RX would look like
+           dmas = <&xdmac 22 DMA_PERID_SSC_TX>, <&xdmac 23 DMA_PERID_SSC_RX>;
+
+    dma-names:
+      required: true
+      description: |
+        This should be "tx" and "rx" to match the dmas property.
+
+        For example
+           dma-names = "tx", "rx";
diff --git a/dts/bindings/arm/atmel,sam0-id.yaml b/dts/bindings/arm/atmel,sam0-id.yaml
new file mode 100644
index 0000000000..6b5de233f0
--- /dev/null
+++ b/dts/bindings/arm/atmel,sam0-id.yaml
@@ -0,0 +1,10 @@
+description: |
+    For locating the Device ID (serial number) on Atmel SAM0 devices
+
+compatible: "atmel,sam0-id"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/atmel,sam0-sercom.yaml b/dts/bindings/arm/atmel,sam0-sercom.yaml
new file mode 100644
index 0000000000..448a4f7d7e
--- /dev/null
+++ b/dts/bindings/arm/atmel,sam0-sercom.yaml
@@ -0,0 +1,15 @@
+description: Atmel SAM0 multi-protocol (UART, SPI, I2C) SERCOM unit
+
+compatible: "atmel,sam0-sercom"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
diff --git a/dts/bindings/arm/atmel,samd2x-pm.yaml b/dts/bindings/arm/atmel,samd2x-pm.yaml
new file mode 100644
index 0000000000..88af94202c
--- /dev/null
+++ b/dts/bindings/arm/atmel,samd2x-pm.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAMD2x Power Manger (PM)
+
+compatible: "atmel,samd2x-pm"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - offset
+  - bit
diff --git a/dts/bindings/arm/nordic,nrf-dppic.yaml b/dts/bindings/arm/nordic,nrf-dppic.yaml
new file mode 100644
index 0000000000..90d3294495
--- /dev/null
+++ b/dts/bindings/arm/nordic,nrf-dppic.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Nordic DPPIC (Distributed Programmable Peripheral Interconnect Controller)
+
+compatible: "nordic,nrf-dppic"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/nordic,nrf-egu.yaml b/dts/bindings/arm/nordic,nrf-egu.yaml
new file mode 100644
index 0000000000..269bc8b37e
--- /dev/null
+++ b/dts/bindings/arm/nordic,nrf-egu.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic EGU (Event Generator Unit)
+
+compatible: "nordic,nrf-egu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/arm/nordic,nrf-ficr.yaml b/dts/bindings/arm/nordic,nrf-ficr.yaml
new file mode 100644
index 0000000000..c1f7be9caa
--- /dev/null
+++ b/dts/bindings/arm/nordic,nrf-ficr.yaml
@@ -0,0 +1,9 @@
+description: Nordic FICR (Factory Information Configuration Registers)
+
+compatible: "nordic,nrf-ficr"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/nordic,nrf-kmu.yaml b/dts/bindings/arm/nordic,nrf-kmu.yaml
new file mode 100644
index 0000000000..34442733c5
--- /dev/null
+++ b/dts/bindings/arm/nordic,nrf-kmu.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic KMU (Key Management Unit)
+
+compatible: "nordic,nrf-kmu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/arm/nordic,nrf-spu.yaml b/dts/bindings/arm/nordic,nrf-spu.yaml
new file mode 100644
index 0000000000..18578d2c34
--- /dev/null
+++ b/dts/bindings/arm/nordic,nrf-spu.yaml
@@ -0,0 +1,12 @@
+description: Nordic SPU (System Protection Unit)
+
+compatible: "nordic,nrf-spu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/arm/nordic,nrf-uicr.yaml b/dts/bindings/arm/nordic,nrf-uicr.yaml
new file mode 100644
index 0000000000..f149f72a7f
--- /dev/null
+++ b/dts/bindings/arm/nordic,nrf-uicr.yaml
@@ -0,0 +1,9 @@
+description: Nordic UICR (User Information Configuration Registers)
+
+compatible: "nordic,nrf-uicr"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/nxp,imx-dtcm.yaml b/dts/bindings/arm/nxp,imx-dtcm.yaml
new file mode 100644
index 0000000000..8b16228913
--- /dev/null
+++ b/dts/bindings/arm/nxp,imx-dtcm.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX DTCM (Data Tightly Coupled Memory)
+
+compatible: "nxp,imx-dtcm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/nxp,imx-epit.yaml b/dts/bindings/arm/nxp,imx-epit.yaml
new file mode 100644
index 0000000000..2e12021eca
--- /dev/null
+++ b/dts/bindings/arm/nxp,imx-epit.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX Enhanced Periodic Interrupt Timer (EPIT)
+
+compatible: "nxp,imx-epit"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  label:
+      required: true
+
+  prescaler:
+     type: int
+     required: true
+     description: Set the EPIT prescaler between 0 and 4095
+
+  rdc:
+     type: int
+     required: true
+     description: Set the RDC permission for this peripheral
diff --git a/dts/bindings/arm/nxp,imx-itcm.yaml b/dts/bindings/arm/nxp,imx-itcm.yaml
new file mode 100644
index 0000000000..755093ae30
--- /dev/null
+++ b/dts/bindings/arm/nxp,imx-itcm.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX ITCM (Instruction Tightly Coupled Memory)
+
+compatible: "nxp,imx-itcm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/arm/nxp,imx-mu.yaml b/dts/bindings/arm/nxp,imx-mu.yaml
new file mode 100644
index 0000000000..94a3412698
--- /dev/null
+++ b/dts/bindings/arm/nxp,imx-mu.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX Messaging Unit
+
+compatible: "nxp,imx-mu"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  label:
+      required: true
+
+  rdc:
+     type: int
+     required: true
+     description: Set the RDC permission for this peripheral
diff --git a/dts/bindings/arm/nxp,kinetis-ftm.yaml b/dts/bindings/arm/nxp,kinetis-ftm.yaml
new file mode 100644
index 0000000000..dc895f5daf
--- /dev/null
+++ b/dts/bindings/arm/nxp,kinetis-ftm.yaml
@@ -0,0 +1,29 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis FTM
+
+compatible: "nxp,kinetis-ftm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+      description: Input clock prescaler
diff --git a/dts/bindings/arm/nxp,kinetis-ke1xf-sim.yaml b/dts/bindings/arm/nxp,kinetis-ke1xf-sim.yaml
new file mode 100644
index 0000000000..b91624796b
--- /dev/null
+++ b/dts/bindings/arm/nxp,kinetis-ke1xf-sim.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis KE1xF System Integration Module (SIM) IP node
+
+compatible: "nxp,kinetis-ke1xf-sim"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    clkout-source:
+      type: int
+      required: false
+      description: clkout clock source
+
+    clkout-divider:
+      type: int
+      required: false
+      description: clkout divider
diff --git a/dts/bindings/arm/nxp,kinetis-mcg.yaml b/dts/bindings/arm/nxp,kinetis-mcg.yaml
new file mode 100644
index 0000000000..2a95112df3
--- /dev/null
+++ b/dts/bindings/arm/nxp,kinetis-mcg.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis Multipurpose Clock generator (MCG) IP node
+
+compatible: "nxp,kinetis-mcg"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - name
diff --git a/dts/bindings/arm/nxp,kinetis-pcc.yaml b/dts/bindings/arm/nxp,kinetis-pcc.yaml
new file mode 100644
index 0000000000..2d52f54b4d
--- /dev/null
+++ b/dts/bindings/arm/nxp,kinetis-pcc.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis PCC (Peripheral Clock Controller) IP node
+
+compatible: "nxp,kinetis-pcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - name
+  - ip-source
diff --git a/dts/bindings/arm/nxp,kinetis-scg.yaml b/dts/bindings/arm/nxp,kinetis-scg.yaml
new file mode 100644
index 0000000000..658b5e9bd6
--- /dev/null
+++ b/dts/bindings/arm/nxp,kinetis-scg.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2019-2021 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis SCG (System Clock Generator) IP node
+
+compatible: "nxp,kinetis-scg"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    sosc-mode:
+      type: int
+      description: system oscillator mode
+      required: false
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - name
diff --git a/dts/bindings/arm/nxp,kinetis-sim.yaml b/dts/bindings/arm/nxp,kinetis-sim.yaml
new file mode 100644
index 0000000000..5051b77c88
--- /dev/null
+++ b/dts/bindings/arm/nxp,kinetis-sim.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis System Integration Module (SIM) IP node
+
+compatible: "nxp,kinetis-sim"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    pllfll-select:
+      type: int
+      required: true
+      description: pll/fll selection for clock system
+
+    er32k-select:
+      type: int
+      required: true
+      description: er32k selection for clock system
+
+    clkout-source:
+      type: int
+      required: false
+      description: clkout clock source
+
+    clkout-divider:
+      type: int
+      required: false
+      description: clkout divider
+
+    "#clock-cells":
+      type: int
+      required: false
+      const: 3
+
+clock-cells:
+  - name
+  - offset
+  - bits
diff --git a/dts/bindings/arm/nxp,lpc-flexcomm.yaml b/dts/bindings/arm/nxp,lpc-flexcomm.yaml
new file mode 100644
index 0000000000..5cb603a70b
--- /dev/null
+++ b/dts/bindings/arm/nxp,lpc-flexcomm.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC Flexcomm node
+
+compatible: "nxp,lpc-flexcomm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/arm/st,stm32-ccm.yaml b/dts/bindings/arm/st,stm32-ccm.yaml
new file mode 100644
index 0000000000..d3d89b2bd1
--- /dev/null
+++ b/dts/bindings/arm/st,stm32-ccm.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 CCM (Core Coupled Memory)
+
+compatible: "st,stm32-ccm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/audio/intel,dmic.yaml b/dts/bindings/audio/intel,dmic.yaml
new file mode 100644
index 0000000000..33022489f0
--- /dev/null
+++ b/dts/bindings/audio/intel,dmic.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Digital PDM Microphone (DMIC) node
+
+compatible: "intel,dmic"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/audio/nordic,nrf-pdm.yaml b/dts/bindings/audio/nordic,nrf-pdm.yaml
new file mode 100644
index 0000000000..fbc888faf8
--- /dev/null
+++ b/dts/bindings/audio/nordic,nrf-pdm.yaml
@@ -0,0 +1,52 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic PDM (Pulse Density Modulation interface)
+
+compatible: "nordic,nrf-pdm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clk-pin:
+      type: int
+      required: true
+      description: CLK pin
+
+    din-pin:
+      type: int
+      required: true
+      description: DIN pin
+
+    clock-source:
+      type: string
+      required: false
+      default: "PCLK32M_HFXO"
+      description: |
+        Clock source to be used by the PDM peripheral. The following options
+        are available:
+        - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
+        - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
+          (HFXO) for better clock accuracy and jitter performance
+        - "ACLK": Audio PLL clock with configurable frequency (frequency for
+          this clock must be set via the "hfclkaudio-frequency" property
+          in the "nordic,nrf-clock" node); this clock source is only available
+          in the nRF53 Series SoCs and it requires the use of HFXO
+      enum:
+        - "PCLK32M"
+        - "PCLK32M_HFXO"
+        - "ACLK"
+
+    queue-size:
+      type: int
+      required: false
+      default: 4
+      description: |
+        Size of the queue of received audio data blocks to be used
+        by the driver.
diff --git a/dts/bindings/audio/st,mpxxdtyy-i2s.yaml b/dts/bindings/audio/st,mpxxdtyy-i2s.yaml
new file mode 100644
index 0000000000..4fde58488d
--- /dev/null
+++ b/dts/bindings/audio/st,mpxxdtyy-i2s.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics MPXXDTYY digital PDM microphone family
+
+compatible: "st,mpxxdtyy"
+
+include: i2s-device.yaml
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/audio/ti,tlv320dac.yaml b/dts/bindings/audio/ti,tlv320dac.yaml
new file mode 100644
index 0000000000..7475144f44
--- /dev/null
+++ b/dts/bindings/audio/ti,tlv320dac.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2018, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments TLV320DAC310x Audio DAC
+
+compatible: "ti,tlv320dac"
+
+include: i2c-device.yaml
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: true
diff --git a/dts/bindings/base/base.yaml b/dts/bindings/base/base.yaml
new file mode 100644
index 0000000000..f99e83642e
--- /dev/null
+++ b/dts/bindings/base/base.yaml
@@ -0,0 +1,110 @@
+# Common fields for all devices
+
+include: [pm.yaml]
+
+properties:
+    status:
+        type: string
+        required: false
+        description: indicates the operational status of a device
+        enum:
+           - "ok" # Deprecated form
+           - "okay"
+           - "disabled"
+           - "reserved"
+           - "fail"
+           - "fail-sss"
+
+    compatible:
+        type: string-array
+        required: true
+        description: compatible strings
+
+    reg:
+        type: array
+        description: register space
+        required: false
+
+    reg-names:
+        type: string-array
+        description: name of each register space
+        required: false
+
+    interrupts:
+        type: array
+        required: false
+        description: interrupts for device
+
+    # Does not follow the 'type: phandle-array' scheme, but gets type-checked
+    # by the code. Declare it here just so that other bindings can make it
+    # 'required: true' easily if they want to.
+    interrupts-extended:
+        type: compound
+        required: false
+        description: extended interrupt specifier for device
+
+    interrupt-names:
+        type: string-array
+        required: false
+        description: name of each interrupt
+
+    interrupt-parent:
+        type: phandle
+        required: false
+        description: phandle to interrupt controller node
+
+    label:
+        type: string
+        required: false
+        description: Human readable string describing the device (used as device_get_binding() argument)
+
+    clocks:
+        type: phandle-array
+        required: false
+        description: Clock gate information
+
+    clock-names:
+        type: string-array
+        required: false
+        description: name of each clock
+
+    "#address-cells":
+        type: int
+        required: false
+        description: number of address cells in reg property
+
+    "#size-cells":
+        type: int
+        required: false
+        description: number of size cells in reg property
+
+    dmas:
+      required: false
+      type: phandle-array
+      description: DMA channels specifiers
+
+    dma-names:
+      required: false
+      type: string-array
+      description: Provided names of DMA channel specifiers
+
+    io-channels:
+      required: false
+      type: phandle-array
+      description: IO channels specifiers
+
+    io-channel-names:
+      required: false
+      type: string-array
+      description: Provided names of IO channel specifiers
+
+    mboxes:
+      required: false
+      type: phandle-array
+      description: mailbox / IPM channels specifiers
+      specifier-space: mbox
+
+    mbox-names:
+      required: false
+      type: string-array
+      description: Provided names of mailbox / IPM channel specifiers
diff --git a/dts/bindings/base/mem-region.yaml b/dts/bindings/base/mem-region.yaml
new file mode 100644
index 0000000000..a555faf508
--- /dev/null
+++ b/dts/bindings/base/mem-region.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2021, CSIRO
+# SPDX-License-Identifier: Apache-2.0
+# Common fields for devices resulting in linker memory regions
+
+properties:
+  zephyr,memory-region:
+    type: string
+    required: false
+    description: |
+      Signify that this node should result in a dedicated linker script
+      memory region in the final executable. The region address and size
+      is taken from the <reg> property, while the name is the value of
+      this property.
diff --git a/dts/bindings/base/pm.yaml b/dts/bindings/base/pm.yaml
new file mode 100644
index 0000000000..a0d3bae203
--- /dev/null
+++ b/dts/bindings/base/pm.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Intel Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+# Properties for Power Management (PM)
+
+properties:
+    wakeup-source:
+      required: false
+      type: boolean
+      description: |
+        Property to identify that a device can be used as wake up source.
+
+        When this property is provided a specific flag is set into the
+        device that tells the system that the device is capable of
+        wake up the system.
+
+        Wake up capable devices are disabled (interruptions will not wake up
+        the system) by default but they can be enabled at runtime if necessary.
diff --git a/dts/bindings/base/power.yaml b/dts/bindings/base/power.yaml
new file mode 100644
index 0000000000..0599b8973b
--- /dev/null
+++ b/dts/bindings/base/power.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2020, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Properties for nodes with controllable power supplies.
+
+properties:
+    supply-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        GPIO specifier that controls power to the device.
+
+        This property should be provided when the device has a dedicated
+        switch that controls power to the device.  The supply state is
+        entirely the responsibility of the device driver.
+
+        Contrast with vin-supply.
+
+    vin-supply:
+      type: phandle
+      required: false
+      description: |
+        Reference to the regulator that controls power to the device.
+        The referenced devicetree node must have a regulator compatible.
+
+        This property should be provided when device power is supplied
+        by a shared regulator.  The supply state is dependent on the
+        request status of all devices fed by the regulator.
+
+        Contrast with supply-gpios.  If both properties are provided
+        then the regulator must be requested before the supply GPIOS is
+        set to an active state, and the supply GPIOS must be set to an
+        inactive state before releasing the regulator.
diff --git a/dts/bindings/bluetooth/zephyr,bt-hci-spi-slave.yaml b/dts/bindings/bluetooth/zephyr,bt-hci-spi-slave.yaml
new file mode 100644
index 0000000000..6c98086254
--- /dev/null
+++ b/dts/bindings/bluetooth/zephyr,bt-hci-spi-slave.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Configures SPI slave settings for a Bluetooth controller that uses
+    Zephyr's Bluetooth Host Controller Interface SPI (HCI SPI) driver.
+
+    A node defined via devicetree overlay should look like this:
+
+       &myspi {
+            bt-hci@0 {
+                    compatible = "zephyr,bt-hci-spi-slave";
+                    reg = <0>;
+                    irq-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+            };
+       };
+
+    The bt-hci@0 node configures an HCI SPI slave on SPI slave
+    interface myspi.
+
+    The host interrupt GPIO is set to gpio1 pin 2 via irq-gpios. The
+    GPIO flags are just for example and may be different depending on
+    hardware.
+
+compatible: "zephyr,bt-hci-spi-slave"
+
+include: base.yaml
+
+on-bus: spi
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: true
diff --git a/dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml b/dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml
new file mode 100644
index 0000000000..85bba49eff
--- /dev/null
+++ b/dts/bindings/bluetooth/zephyr,bt-hci-spi.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2018, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Bluetooth module that uses Zephyr's Bluetooth Host Controller Interface SPI
+    driver (e.g. nRF51822)
+
+compatible: "zephyr,bt-hci-spi"
+
+include: spi-device.yaml
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: true
+
+    reset-gpios:
+      type: phandle-array
+      required: true
diff --git a/dts/bindings/can/bosch,m-can-base.yaml b/dts/bindings/can/bosch,m-can-base.yaml
new file mode 100644
index 0000000000..44e0271ce3
--- /dev/null
+++ b/dts/bindings/can/bosch,m-can-base.yaml
@@ -0,0 +1,28 @@
+description: Bosch m_can CAN-FD controller base
+
+compatible: "bosch,m-can-base"
+
+properties:
+    std-filter-elements:
+      type: int
+      required: true
+
+    ext-filter-elements:
+      type: int
+      required: true
+
+    rx-fifo0-elements:
+      type: int
+      required: true
+
+    rx-fifo1-elements:
+      type: int
+      required: true
+
+    rx-buffer-elements:
+      type: int
+      required: true
+
+    tx-buffer-elements:
+      type: int
+      required: true
diff --git a/dts/bindings/can/bosch,m-can.yaml b/dts/bindings/can/bosch,m-can.yaml
new file mode 100644
index 0000000000..8710b41cef
--- /dev/null
+++ b/dts/bindings/can/bosch,m-can.yaml
@@ -0,0 +1,12 @@
+description: Bosch m_can CAN-FD controller
+
+compatible: "bosch,m-can"
+
+include: can-fd-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/can/can-controller.yaml b/dts/bindings/can/can-controller.yaml
new file mode 100644
index 0000000000..bf7bfa13c6
--- /dev/null
+++ b/dts/bindings/can/can-controller.yaml
@@ -0,0 +1,36 @@
+# Common fields for CAN controllers
+
+include: base.yaml
+
+bus: can
+
+properties:
+    label:
+      required: true
+    bus-speed:
+      type: int
+      required: true
+      description: bus speed in Baud/s
+    sjw:
+      type: int
+      required: true
+      description: Resynchronization jump width (ISO 11898-1)
+    prop-seg:
+      type: int
+      required: false
+      description: Time quantums of propagation segment (ISO 11898-1)
+    phase-seg1:
+      type: int
+      required: false
+      description: Time quantums of phase buffer 1 segment (ISO 11898-1)
+    phase-seg2:
+      type: int
+      required: false
+      description: Time quantums of phase buffer 2 segment (ISO 11898-1)
+    sample-point:
+      type: int
+      required: false
+      description: >
+        Sample point in permille.
+        This param is required if segments are not given.
+        If the sample point is given, the segments are ignored.
diff --git a/dts/bindings/can/can-device.yaml b/dts/bindings/can/can-device.yaml
new file mode 100644
index 0000000000..5176bba566
--- /dev/null
+++ b/dts/bindings/can/can-device.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018 Alexander Wachter
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for CAN devices
+
+include: base.yaml
+
+on-bus: can
+
+properties:
+    reg:
+      required: true
+    label:
+      required: true
diff --git a/dts/bindings/can/can-fd-controller.yaml b/dts/bindings/can/can-fd-controller.yaml
new file mode 100644
index 0000000000..d4f546d578
--- /dev/null
+++ b/dts/bindings/can/can-fd-controller.yaml
@@ -0,0 +1,36 @@
+# Common fields for CAN-FD controllers
+
+include: can-controller.yaml
+
+properties:
+    bus-speed-data:
+      type: int
+      required: true
+      description: data phase bus speed in Baud/s
+    sjw-data:
+      type: int
+      required: true
+      description: Resynchronization jump width for the data phase. (ISO11898-1:2015)
+    prop-seg-data:
+      type: int
+      required: false
+      description: Time quantums of propagation segment for the data phase. (ISO11898-1:2015)
+    phase-seg1-data:
+      type: int
+      required: false
+      description: Time quantums of phase buffer 1 segment for the data phase. (ISO11898-1:2015)
+    phase-seg2-data:
+      type: int
+      required: false
+      description: Time quantums of phase buffer 2 segment for the data phase. (ISO11898-1:2015)
+    sample-point-data:
+      type: int
+      required: false
+      description: >
+        Sample point in permille for the data phase.
+        This param is required if segments are not given.
+        If the sample point is given, the segments are ignored.
+    tx-delay-comp-offset:
+      type: int
+      required: false
+      default: 0
diff --git a/dts/bindings/can/microchip,mcp2515.yaml b/dts/bindings/can/microchip,mcp2515.yaml
new file mode 100644
index 0000000000..df1555a94f
--- /dev/null
+++ b/dts/bindings/can/microchip,mcp2515.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2019 Karsten Koenig
+# SPDX-License-Identifier: Apache-2.0
+
+description: MCP2515 SPI CAN controller
+
+compatible: "microchip,mcp2515"
+
+include: [spi-device.yaml, can-controller.yaml]
+
+properties:
+    osc-freq:
+      type: int
+      required: true
+      description: Frequency of the external oscillator
+    int-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        Interrupt pin.
+
+        This pin signals active low when produced by the controller. The
+        property value should ensure the flags properly describe the signal
+        that is presented to the driver.
+    reg:
+      type: array
+      required: true
diff --git a/dts/bindings/can/nxp,kinetis-flexcan.yaml b/dts/bindings/can/nxp,kinetis-flexcan.yaml
new file mode 100644
index 0000000000..1d618d434e
--- /dev/null
+++ b/dts/bindings/can/nxp,kinetis-flexcan.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexCAN controller
+
+compatible: "nxp,kinetis-flexcan"
+
+include: can-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    clk-source:
+      type: int
+      required: true
+      description: CAN engine clock source
diff --git a/dts/bindings/can/renesas,rcar-can.yaml b/dts/bindings/can/renesas,rcar-can.yaml
new file mode 100644
index 0000000000..baef0b6105
--- /dev/null
+++ b/dts/bindings/can/renesas,rcar-can.yaml
@@ -0,0 +1,15 @@
+description: Renesas R-Car CAN controller
+
+compatible: "renesas,rcar-can"
+
+include: can-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
diff --git a/dts/bindings/can/st,stm32-can.yaml b/dts/bindings/can/st,stm32-can.yaml
new file mode 100644
index 0000000000..623733dcd0
--- /dev/null
+++ b/dts/bindings/can/st,stm32-can.yaml
@@ -0,0 +1,26 @@
+description: STM32 CAN controller
+
+compatible: "st,stm32-can"
+
+include: [can-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
+    master-can-reg:
+      type: int
+      required: false
+      description: master can reg when different from current instance
diff --git a/dts/bindings/can/st,stm32-fdcan.yaml b/dts/bindings/can/st,stm32-fdcan.yaml
new file mode 100644
index 0000000000..e111a7e0ee
--- /dev/null
+++ b/dts/bindings/can/st,stm32-fdcan.yaml
@@ -0,0 +1,5 @@
+description: Bosch m_can CAN-FD controller
+
+compatible: "st,stm32-fdcan"
+
+include: ["bosch,m-can.yaml", "pinctrl-device.yaml"]
diff --git a/dts/bindings/clock/atmel,samd2x-gclk.yaml b/dts/bindings/clock/atmel,samd2x-gclk.yaml
new file mode 100644
index 0000000000..29cce3b598
--- /dev/null
+++ b/dts/bindings/clock/atmel,samd2x-gclk.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAMD2x Generic Clock Controller (GCLK)
+
+compatible: "atmel,samd2x-gclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - clkctrl_id
diff --git a/dts/bindings/clock/atmel,samd5x-gclk.yaml b/dts/bindings/clock/atmel,samd5x-gclk.yaml
new file mode 100644
index 0000000000..65a9cadc55
--- /dev/null
+++ b/dts/bindings/clock/atmel,samd5x-gclk.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAMD5x Generic Clock Controller (GCLK)
+
+compatible: "atmel,samd5x-gclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - periph_ch
diff --git a/dts/bindings/clock/atmel,samd5x-mclk.yaml b/dts/bindings/clock/atmel,samd5x-mclk.yaml
new file mode 100644
index 0000000000..53b1ce93c0
--- /dev/null
+++ b/dts/bindings/clock/atmel,samd5x-mclk.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAMD5x Generic Clock Controller (MCLK)
+
+compatible: "atmel,samd5x-mclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - offset
+  - bit
diff --git a/dts/bindings/clock/clock-controller.yaml b/dts/bindings/clock/clock-controller.yaml
new file mode 100644
index 0000000000..7bb24b4505
--- /dev/null
+++ b/dts/bindings/clock/clock-controller.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for clock controllers
+
+properties:
+    "#clock-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a Clock specifier
diff --git a/dts/bindings/clock/espressif,esp32-rtc.yaml b/dts/bindings/clock/espressif,esp32-rtc.yaml
new file mode 100644
index 0000000000..38b694571a
--- /dev/null
+++ b/dts/bindings/clock/espressif,esp32-rtc.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2020, Mohamed ElShahawi
+# SPDX-License-Identifier: Apache-2.0
+
+description: ESP32 RTC (Power & Clock Controller Module) Module
+
+compatible: "espressif,esp32-rtc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    xtal-freq:
+      type: int
+      required: true
+      description: Value of the external XTAL connected to ESP32.
+
+    xtal-div:
+      type: int
+      required: false
+      description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - offset  # Index of the peripheral in esp32 modules list (Check esp32_clock.h)
diff --git a/dts/bindings/clock/fixed-clock.yaml b/dts/bindings/clock/fixed-clock.yaml
new file mode 100644
index 0000000000..97eaf2f7be
--- /dev/null
+++ b/dts/bindings/clock/fixed-clock.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic fixed-rate clock provider
+
+compatible: "fixed-clock"
+
+include: clock-controller.yaml
+
+properties:
+    label:
+      type: string
+      required: false
+      description: Human readable string describing the device (used as device_get_binding() argument)
+
+    clock-frequency:
+      type: int
+      description: output clock frequency (Hz)
+      required: true
+
+    clocks:
+      type: array
+      required: false
+      description: input clock source
+
+    "#clock-cells":
+      const: 0
diff --git a/dts/bindings/clock/fixed-factor-clock.yaml b/dts/bindings/clock/fixed-factor-clock.yaml
new file mode 100644
index 0000000000..dd9f571f81
--- /dev/null
+++ b/dts/bindings/clock/fixed-factor-clock.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2021 Prevas A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic fixed factor clock provider
+
+compatible: "fixed-factor-clock"
+
+include: clock-controller.yaml
+
+properties:
+    clock-div:
+      type: int
+      description: fixed clock divider
+
+    clock-mult:
+      type: int
+      description: fixed clock multiplier
+
+    clocks:
+      type: phandle-array
+      description: input clock source
+
+    "#clock-cells":
+      const: 0
diff --git a/dts/bindings/clock/litex,clk.yaml b/dts/bindings/clock/litex,clk.yaml
new file mode 100644
index 0000000000..e54f622c37
--- /dev/null
+++ b/dts/bindings/clock/litex,clk.yaml
@@ -0,0 +1,93 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+include: [clock-controller.yaml, base.yaml]
+
+description: |
+  LiteX Mixed Mode Clock Manager
+  Common clock driver with MMCM unit for dynamic reconfiguration
+  of up to 7 clock outputs with ability to change frequency, duty
+  cycle and phase offset
+
+compatible: "litex,clk"
+
+clock-cells:
+  - id
+
+properties:
+
+  reg:
+    description: Base address and lengths of the register space
+
+  "#clock-cells":
+    required: true
+    const: 1
+
+  clock-output-names:
+    required: true
+    type: string-array
+    description: |
+      List of strings of clock output signal names indexed
+      by the first cell in the clock specifier.
+
+  litex,lock-timeout:
+    required: true
+    type: int
+    description: |
+      Number of ms to wait for MMCM to assert LOCK signal
+  litex,drdy-timeout:
+    required: true
+    type: int
+    description: |
+      Number of ms to wait for MMCM to assert DRDY signal
+  litex,sys-clock-frequency:
+    required: true
+    type: int
+    description: |
+      System clock frequency
+  litex,divclk-divide-min:
+    required: true
+    type: int
+    description: |
+      minimal global divider
+  litex,divclk-divide-max:
+    required: true
+    type: int
+    description: |
+      maximal global divider
+  litex,clkfbout-mult-min:
+    required: true
+    type: int
+    description: |
+      minimal global multiplier
+  litex,clkfbout-mult-max:
+    required: true
+    type: int
+    description: |
+      maximal global multiplier
+  litex,vco-freq-min:
+    required: true
+    type: int
+    description: |
+      minimal frequency after global divider and multiplier
+  litex,vco-freq-max:
+    required: true
+    type: int
+    description: |
+      maximal frequency after global divider and multiplier
+  litex,clkout-divide-min:
+    required: true
+    type: int
+    description: |
+      minimal clock output divider
+  litex,clkout-divide-max:
+    required: true
+    type: int
+    description: |
+      maximal clock output divider
+  litex,vco-margin:
+    required: true
+    type: int
+    description: |
+      tolerancy for vco frequency
+    const: 0
diff --git a/dts/bindings/clock/litex,clkout.yaml b/dts/bindings/clock/litex,clkout.yaml
new file mode 100644
index 0000000000..df92dad0ef
--- /dev/null
+++ b/dts/bindings/clock/litex,clkout.yaml
@@ -0,0 +1,67 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+include: base.yaml
+
+description: |
+  LiteX Mixed Mode Clock Manager clock output binding
+
+compatible: "litex,clkout"
+
+properties:
+
+  "#clock-cells":
+    required: true
+    type: int
+    description: |
+      Number of cells in a clock specifier;
+      Typically 0 for nodes with a single clock output
+      and 1 for nodes with multiple clock outputs.
+    const: 1
+
+  clock-output-names:
+    required: true
+    type: string
+    description: |
+      string of clock output signal name.
+
+  litex,clock-frequency:
+    required: true
+    type: int
+    description: |
+      default frequency in Hz for clock output
+
+  litex,clock-phase:
+    required: true
+    type: int
+    description: |
+      default phase offset given in degrees
+
+  litex,clock-duty-num:
+    required: true
+    type: int
+    description: |
+      default duty cycle numerator value
+
+  litex,clock-duty-den:
+    required: true
+    type: int
+    description: |
+      default duty cycle denominator value
+
+  litex,clock-margin:
+    required: true
+    type: int
+    description: |
+      clock output margin coefficient
+
+  litex,clock-margin-exp:
+    required: true
+    type: int
+    description: |
+      exponent for clkout margin
+      effective clkout margin shall be
+      margin * 10^(-exponent) * 100%
+
+clock-cells:
+  - id
diff --git a/dts/bindings/clock/microchip,xec-pcr.yaml b/dts/bindings/clock/microchip,xec-pcr.yaml
new file mode 100644
index 0000000000..45412a1430
--- /dev/null
+++ b/dts/bindings/clock/microchip,xec-pcr.yaml
@@ -0,0 +1,52 @@
+# Copyright (c) 2021, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC Power Clock Reset and VBAT register (PCR)
+
+compatible: "microchip,xec-pcr"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    core-clock-div:
+      type: int
+      required: true
+      description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
+
+    slow-clock-div:
+      type: int
+      required: false
+      description: |
+        PWM and TACH clock domain divided down from 48 MHz AHB clock. The
+        default value is 480 for 100 kHz.
+
+    pll-32k-src:
+      type: int
+      required: true
+      description: 32 KHz clock source for PLL
+
+    periph-32k-src:
+      type: int
+      required: true
+      description: 32 KHz clock source for peripherals
+
+    xtal-single-ended:
+      type: boolean
+      required: false
+      description: Use single ended crystal connection to XTAL2 pin.
+
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - regidx
+  - bitpos
diff --git a/dts/bindings/clock/nordic,nrf-clock.yaml b/dts/bindings/clock/nordic,nrf-clock.yaml
new file mode 100644
index 0000000000..3bc5bd014f
--- /dev/null
+++ b/dts/bindings/clock/nordic,nrf-clock.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF clock control node
+
+compatible: "nordic,nrf-clock"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    hfclkaudio-frequency:
+      type: int
+      required: false
+      description: |
+        Frequency of the HFCLKAUDIO clock in Hz. Adjustable with 3.3 ppm
+        resolution in two frequency bands - 11.176 MHz to 11.402 MHz, and
+        12.165 MHz to 12.411 MHz (refer to the relevant Product Specification).
+        The HFCLKAUDIO clock is only available in the nRF53 Series SoCs.
diff --git a/dts/bindings/clock/nuvoton,npcx-pcc.yaml b/dts/bindings/clock/nuvoton,npcx-pcc.yaml
new file mode 100644
index 0000000000..7f66dd0f90
--- /dev/null
+++ b/dts/bindings/clock/nuvoton,npcx-pcc.yaml
@@ -0,0 +1,224 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nuvoton, NPCX PCC (Power and Clock Controller) node.
+  Besides power management, this node is also in charge of configuring the
+  Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
+  High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
+  and most of NPCX hardware modules.
+
+  Here is an example of configuring OFMCLK and the other clock sources derived
+  from it in board dts file.
+  &pcc {
+      clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
+      core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
+      apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
+      apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
+      apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
+  };
+
+compatible: "nuvoton,npcx-pcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+        required: true
+
+    clock-frequency:
+        required: true
+        type: int
+        description: |
+          Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
+          only the following values are allowed:
+            100000000, 100 MHz
+            96000000, 96 MHz
+            90000000, 90 MHz
+            80000000, 80 MHz
+            66000000, 66 MHz
+            50000000, 50 MHz
+            48000000, 48 MHz
+            40000000, 40 MHz (default value after reset)
+            33000000, 33 MHz
+        enum:
+          - 100000000
+          - 96000000
+          - 90000000
+          - 80000000
+          - 66000000
+          - 50000000
+          - 48000000
+          - 40000000
+          - 33000000
+
+    core-prescaler:
+        type: int
+        required: true
+        description: |
+          Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
+          dividing OFMCLK(MCLK) and needs to meet the following requirements.
+          - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
+          = Only the following values are allowed:
+            1, CORE_CLK = OFMCLK
+            2, CORE_CLK = OFMCLK / 2
+            3, CORE_CLK = OFMCLK / 3
+            4, CORE_CLK = OFMCLK / 4
+            5, CORE_CLK = OFMCLK / 5
+            6, CORE_CLK = OFMCLK / 6
+            7, CORE_CLK = OFMCLK / 7
+            8, CORE_CLK = OFMCLK / 8
+            9, CORE_CLK = OFMCLK / 9
+            10, CORE_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    apb1-prescaler:
+        type: int
+        required: true
+        description: |
+          APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
+          OFMCLK(MCLK) and needs to meet the following requirements.
+          - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
+          - APB1_CLK must be an integer division (including 1) of CORE_CLK.
+          = Only the following values are allowed:
+            1, APB1_CLK = OFMCLK
+            2, APB1_CLK = OFMCLK / 2
+            3, APB1_CLK = OFMCLK / 3
+            4, APB1_CLK = OFMCLK / 4
+            5, APB1_CLK = OFMCLK / 5
+            6, APB1_CLK = OFMCLK / 6
+            7, APB1_CLK = OFMCLK / 7
+            8, APB1_CLK = OFMCLK / 8
+            9, APB1_CLK = OFMCLK / 9
+            10, APB1_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    apb2-prescaler:
+        type: int
+        required: true
+        description: |
+          APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
+          OFMCLK(MCLK) and needs to meet the following requirements.
+          - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
+          - APB2_CLK must be an integer division (including 1) of CORE_CLK.
+          = Only the following values are allowed:
+            1, APB2_CLK = OFMCLK
+            2, APB2_CLK = OFMCLK / 2
+            3, APB2_CLK = OFMCLK / 3
+            4, APB2_CLK = OFMCLK / 4
+            5, APB2_CLK = OFMCLK / 5
+            6, APB2_CLK = OFMCLK / 6
+            7, APB2_CLK = OFMCLK / 7
+            8, APB2_CLK = OFMCLK / 8
+            9, APB2_CLK = OFMCLK / 9
+            10, APB2_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    apb3-prescaler:
+        type: int
+        required: true
+        description: |
+          APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
+          OFMCLK(MCLK) and needs to meet the following requirements.
+          - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
+          - APB3_CLK must be an integer division (including 1) of CORE_CLK.
+          = Only the following values are allowed:
+            1, APB3_CLK = OFMCLK
+            2, APB3_CLK = OFMCLK / 2
+            3, APB3_CLK = OFMCLK / 3
+            4, APB3_CLK = OFMCLK / 4
+            5, APB3_CLK = OFMCLK / 5
+            6, APB3_CLK = OFMCLK / 6
+            7, APB3_CLK = OFMCLK / 7
+            8, APB3_CLK = OFMCLK / 8
+            9, APB3_CLK = OFMCLK / 9
+            10, APB3_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    apb4-prescaler:
+        type: int
+        required: false
+        description: |
+          APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
+          OFMCLK(MCLK) and needs to meet the following requirements.
+          - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
+          - APB4_CLK must be an integer division (including 1) of CORE_CLK.
+          = Only the following values are allowed:
+            1, APB4_CLK = OFMCLK
+            2, APB4_CLK = OFMCLK / 2
+            3, APB4_CLK = OFMCLK / 3
+            4, APB4_CLK = OFMCLK / 4
+            5, APB4_CLK = OFMCLK / 5
+            6, APB4_CLK = OFMCLK / 6
+            7, APB4_CLK = OFMCLK / 7
+            8, APB4_CLK = OFMCLK / 8
+            9, APB4_CLK = OFMCLK / 9
+            10, APB4_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    ram-pd-depth:
+        required: false
+        type: int
+        enum:
+          - 12
+          - 15
+        description: |
+          Valid bit-depth of RAM block Power-Down control (RAM_PD) registers.
+          Each bit in RAM_PDn can power down the relevant RAM block by setting
+          itself to 1 for better power consumption and this valid bit-depth
+          varies in different NPCX series.
+
+clock-cells:
+    - bus
+    - ctl
+    - bit
diff --git a/dts/bindings/clock/nxp,imx-anatop.yaml b/dts/bindings/clock/nxp,imx-anatop.yaml
new file mode 100644
index 0000000000..362968dd4c
--- /dev/null
+++ b/dts/bindings/clock/nxp,imx-anatop.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX ANATOP (Analog Clock Controller Module) IP node
+
+compatible: "nxp,imx-anatop"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+        required: true
+
+    label:
+        required: true
+
+    "#clock-cells":
+        type: int
+        const: 4
+        required: true
+        description: Number of items to expect in a clock specifier
+
+    "#pll-clock-cells":
+        type: int
+        const: 3
+        required: true
+        description: Number of items to expect in a PLL specifier
+
+clock-cells:
+    - name
+    - offset
+    - bits
+    - value
+
+pll-clock-cells:
+    - offset
+    - bits
+    - value
diff --git a/dts/bindings/clock/nxp,imx-ccm-rev2.yaml b/dts/bindings/clock/nxp,imx-ccm-rev2.yaml
new file mode 100644
index 0000000000..b49202a3d1
--- /dev/null
+++ b/dts/bindings/clock/nxp,imx-ccm-rev2.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX CCM Rev2 (Clock Controller Module) IP node
+
+compatible: "nxp,imx-ccm-rev2"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 3
+
+clock-cells:
+  - name
+  - offset
+  - bits
diff --git a/dts/bindings/clock/nxp,imx-ccm.yaml b/dts/bindings/clock/nxp,imx-ccm.yaml
new file mode 100644
index 0000000000..2cc4611f0c
--- /dev/null
+++ b/dts/bindings/clock/nxp,imx-ccm.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX CCM (Clock Controller Module) IP node
+
+compatible: "nxp,imx-ccm"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 3
+
+clock-cells:
+  - name
+  - offset
+  - bits
diff --git a/dts/bindings/clock/nxp,lpc-syscon.yaml b/dts/bindings/clock/nxp,lpc-syscon.yaml
new file mode 100644
index 0000000000..0d5b40164b
--- /dev/null
+++ b/dts/bindings/clock/nxp,lpc-syscon.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2020, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC SYSCON & CLKCTL IP node
+
+compatible: "nxp,lpc-syscon"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - name
diff --git a/dts/bindings/clock/nxp,lpc11u6x-syscon.yaml b/dts/bindings/clock/nxp,lpc11u6x-syscon.yaml
new file mode 100644
index 0000000000..b667b39c4d
--- /dev/null
+++ b/dts/bindings/clock/nxp,lpc11u6x-syscon.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2020, Seagate
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC11U6X clock controller node
+
+compatible: "nxp,lpc11u6x-syscon"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    pinmuxs:
+      type: phandle-array
+      required: true
+      description: system oscillator pinmux configuration
+
+    pinmux-names:
+      type: string-array
+      required: false
+      description: system oscillator pins names
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - clkid
diff --git a/dts/bindings/clock/renesas,rcar-cpg-mssr.yaml b/dts/bindings/clock/renesas,rcar-cpg-mssr.yaml
new file mode 100644
index 0000000000..2dd74f8e92
--- /dev/null
+++ b/dts/bindings/clock/renesas,rcar-cpg-mssr.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2020, IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas Clock Pulse Generator / Module Standby and Software Reset
+
+compatible: "renesas,rcar-cpg-mssr"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - domain
+  - module
diff --git a/dts/bindings/clock/st,stm32-hse-clock.yaml b/dts/bindings/clock/st,stm32-hse-clock.yaml
new file mode 100644
index 0000000000..631652c9d0
--- /dev/null
+++ b/dts/bindings/clock/st,stm32-hse-clock.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 HSE Clock
+
+compatible: "st,stm32-hse-clock"
+
+include: [fixed-clock.yaml]
+
+properties:
+    hse-bypass:
+      type: boolean
+      required: false
+      description: |
+        HSE crystal oscillator bypass
+        Set to the property to by-pass the oscillator with an external clock.
diff --git a/dts/bindings/clock/st,stm32-msi-clock.yaml b/dts/bindings/clock/st,stm32-msi-clock.yaml
new file mode 100644
index 0000000000..58ed913fa9
--- /dev/null
+++ b/dts/bindings/clock/st,stm32-msi-clock.yaml
@@ -0,0 +1,36 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 MSI Clock
+
+compatible: "st,stm32-msi-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    msi-range:
+      required: true
+      type: int
+      default: 6
+      description: |
+        MSI clock ranges
+      enum:
+        - 0 # range 0 around 100 kHz
+        - 1 # range 1 around 200 kHz
+        - 2 # range 2 around 400 kHz
+        - 3 # range 3 around 800 kHz
+        - 4 # range 4 around 1M Hz
+        - 5 # range 5 around 2 MHz
+        - 6 # range 6 around 4 MHz (reset value)
+        - 7 # range 7 around 8 MHz
+        - 8 # range 8 around 16 MHz
+        - 9 # range 9 around 24 MHz
+        - 10 # range 10 around 32 MHz
+        - 11 # range 11 around 48 MHz
+
+    msi-pll-mode:
+      type: boolean
+      required: false
+      description: |
+        MSI clock PLL enable
+        Enables the PLL part of the MSI clock source.
diff --git a/dts/bindings/clock/st,stm32-rcc.yaml b/dts/bindings/clock/st,stm32-rcc.yaml
new file mode 100644
index 0000000000..cc4319d775
--- /dev/null
+++ b/dts/bindings/clock/st,stm32-rcc.yaml
@@ -0,0 +1,96 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 Reset and Clock controller node.
+  This node is in charge of system clock ('SYSCLK') source selection and controlling
+  clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
+
+  Configuring STM32 Reset and Clock controller node:
+
+  System clock source should be selected amongst the clock nodes available in "clocks"
+  node (typically 'clk_hse, clk_hsi', 'pll', ...).
+  As part of this node configuration, SYSCLK frequency should also be defined, using
+  "clock-frequency" property.
+  Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
+  prescaler properties.
+  Here is an example of correctly configured rcc node:
+  &rcc {
+           clocks = <&pll>;  /* Set pll as SYSCLK source */
+           clock-frequency = <DT_FREQ_M(80)>; /* SYSCLK runs at 80MHz */
+           ahb-prescaler = <1>;
+           apb1-presacler = <1>;
+           apb2-presacler = <1>;
+  }
+
+  Specifying a gated clock:
+
+  To specify a gated clock, a peripheral should define a "clocks" property encoded
+  in the following way:
+  ... {
+           ...
+           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+           ...
+  }
+  After the phandle referring to rcc node, the first index specifies the registers of
+  the bus controlling the peripheral and the second index specifies the bit used to
+  control the peripheral clock in that bus register.
+
+compatible: "st,stm32-rcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+    clock-frequency:
+      required: true
+      type: int
+      description: |
+        default frequency in Hz for clock output
+
+    ahb-prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 64
+        - 128
+        - 256
+        - 512
+      description: |
+          AHB prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
+          lower than SYSCLK frequency (actual core frequency).
+          The HCLK clocks CPU, AHB, memories and DMA.
+
+    apb1-prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+    apb2-prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+clock-cells:
+  - bus
+  - bits
diff --git a/dts/bindings/clock/st,stm32f0-pll-clock.yaml b/dts/bindings/clock/st,stm32f0-pll-clock.yaml
new file mode 100644
index 0000000000..bc3e2c4236
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f0-pll-clock.yaml
@@ -0,0 +1,40 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Main PLL node binding for STM32F0 and STM32F3 devices.
+
+  Takes one of clk_hse or clk_hsi as input clock.
+
+  Note: Some STM32F0 SoC variants (STM32072 for instance) may also support HSI48
+  as input clock. This case is not supported yet.
+
+  Frequency calculation for output clock is as follows:
+
+    f(PLLCLK) = f(PLLIN) x PLLMUL   --> SYSCLK (System Clock)
+
+    with, depending on the case:
+            If input_clk = clk_hse
+              f(PLLIN) = f(input_clk) / PREDIV
+            If input_clk = clk_hsi
+              On STM32F3, STM32F03x, STM32F05x, STM32F030x4, STM32F030x6 and STM32F030x8
+                f(PLLIN) = f(input_clk) / 2
+              On STM32F04x, STM32F07x, STM32F09x, STM32F070x6, STM32F070xB and STM32F030xC
+                f(PLLIN) = f(input_clk) / PREDIV
+
+  The PLL output frequency must be set in range 16-48MHz
+
+compatible: "st,stm32f0-pll-clock"
+
+include:
+  - name: st,stm32f105-pll-clock.yaml
+    property-blocklist:
+      - mul
+
+properties:
+    mul:
+      type: int
+      required: true
+      description: |
+          PLL multiplication factor for output clock
+          Valid range: 2 - 16
diff --git a/dts/bindings/clock/st,stm32f0-rcc.yaml b/dts/bindings/clock/st,stm32f0-rcc.yaml
new file mode 100644
index 0000000000..c85205ab8f
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f0-rcc.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32F0 and G0 Reset and Clock controller node.
+  For more description confere st,stm32-rcc.yaml
+
+compatible: "st,stm32f0-rcc"
+
+include:
+  - name: st,stm32-rcc.yaml
+    property-blocklist:
+      - apb2-prescaler
diff --git a/dts/bindings/clock/st,stm32f1-pll-clock.yaml b/dts/bindings/clock/st,stm32f1-pll-clock.yaml
new file mode 100644
index 0000000000..5906faa256
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f1-pll-clock.yaml
@@ -0,0 +1,47 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
+
+  Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
+  as input clock.
+
+  Up to 2 output clocks could be supported and for each output clock, the
+  frequency can be computed with the following formula:
+
+    f(PLLCLK) = f(input clk) x PLLMUL  --> SYSCLK (System Clock)
+    f(USBCLK) = f(PLLCLK) / USBPRE     --> USB
+
+  The PLL output frequency must not exceed 72 MHz.
+
+
+compatible: "st,stm32f1-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    mul:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCO
+          Valid range: 2 - 16
+
+    xtpre:
+      type: boolean
+      required: false
+      description: |
+          Otpional HSE divider for PLL entry
+
+    usbpre:
+      type: int
+      required: false
+      description: |
+          Otpional HSE divider for PLL entry
diff --git a/dts/bindings/clock/st,stm32f100-pll-clock.yaml b/dts/bindings/clock/st,stm32f100-pll-clock.yaml
new file mode 100644
index 0000000000..5789cf8cf3
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f100-pll-clock.yaml
@@ -0,0 +1,36 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Main PLL node binding for STM32F100 devices
+
+  Takes one of clk_hse or clk_hsi as input clock.
+  When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
+  pll2, configurable prescaler is used.
+
+  Up to 2 output clocks could be supported and for each output clock, the
+  frequency can be computed with the following formula:
+
+    f(PLLCLK) = f(PLLIN) x PLLMUL       --> SYSCLK (System Clock)
+
+    with, depending on the case:
+            f(PLLIN) = f(input_clk) / 2       if input_clk = clk_hsi
+            f(PLLIN) = f(input_clk) / PREDIV  if input_clk = clk_hse
+
+  The PLL output frequency must not exceed 24 MHz.
+
+
+compatible: "st,stm32f100-pll-clock"
+
+include:
+  - name: st,stm32f105-pll-clock.yaml
+    property-blocklist:
+      - mul
+
+properties:
+    mul:
+      type: int
+      required: true
+      description: |
+          PLL multiplication factor for output clock
+          Valid range: 2 - 16
diff --git a/dts/bindings/clock/st,stm32f105-pll-clock.yaml b/dts/bindings/clock/st,stm32f105-pll-clock.yaml
new file mode 100644
index 0000000000..b65ea38670
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f105-pll-clock.yaml
@@ -0,0 +1,55 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
+
+  Takes one of clk_hse, pll2 or clk_hsi as input clock.
+  When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
+  pll2, configurable prescaler is used.
+
+  Up to 2 output clocks could be supported and for each output clock, the
+  frequency can be computed with the following formula:
+
+    f(PLLCLK) = f(PLLIN) x PLLMUL       --> SYSCLK (System Clock)
+    f(USBCLK) = f(PLLCLK) * 2 / USBPRE  --> USB
+
+    with, depending on the case:
+            f(PLLIN) = f(input_clk) / 2       if input_clk = clk_hsi
+            f(PLLIN) = f(input_clk) / PREDIV  if input_clk = clk_hse or pll2
+
+  The PLL output frequency must not exceed 72 MHz.
+
+
+compatible: "st,stm32f105-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    mul:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCO.
+          Note: For x6.5 multiplier value, please use "mul = <15>;"
+      enum:
+        - 4   # x4
+        - 5   # x5
+        - 6   # x6
+        - 7   # x7
+        - 8   # x8
+        - 9   # x9
+        - 15  # x6.5
+
+    prediv:
+      type: int
+      required: false
+      description: |
+          Configurable prescaler
+          Valid range: 1 - 16
diff --git a/dts/bindings/clock/st,stm32f105-pll2-clock.yaml b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml
new file mode 100644
index 0000000000..4c5043484a
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml
@@ -0,0 +1,36 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)
+
+  Takes clk_hse as input clock, using prediv as prescaler.
+
+  Each PLL as its own output clock.
+
+    f(PLL2CLK) = f(PLL2IN) / PREDIV * PLLMUL --> PLL (System Clock)
+
+
+compatible: "st,stm32f105-pll2-clock"
+
+include:
+  - name: st,stm32f105-pll-clock.yaml
+    property-blocklist:
+      - mul
+
+properties:
+    mul:
+      type: int
+      required: true
+      description: |
+          PLL multiplication factor for output clock
+      enum:
+        - 8
+        - 9
+        - 10
+        - 11
+        - 12
+        - 13
+        - 14
+        - 16
+        - 20
diff --git a/dts/bindings/clock/st,stm32f2-pll-clock.yaml b/dts/bindings/clock/st,stm32f2-pll-clock.yaml
new file mode 100644
index 0000000000..0ed37dd8ea
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f2-pll-clock.yaml
@@ -0,0 +1,61 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32F2 Main PLL node binding:
+
+  Takes one of clk_hse or clk_hsi as input clock.
+
+  Up to 2 output clocks could be supported and for each output clock, the
+  frequency can be computed with the following formula:
+
+    f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
+    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  The PLL output frequency must not exceed 168 MHz.
+
+
+compatible: "st,stm32f2-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Division factor for the PLL input clock
+          Valid range: 2 - 63
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          PLL multiplication factor for VCO
+          Valid range: 192 - 432
+
+    div-p:
+      type: int
+      required: true
+      description: |
+          PLL division factor for PLLCLK
+      enum:
+        - 2
+        - 4
+        - 6
+        - 8
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          PLL division factor for PLL48CK
+          Valid range: 2 - 15
diff --git a/dts/bindings/clock/st,stm32f4-pll-clock.yaml b/dts/bindings/clock/st,stm32f4-pll-clock.yaml
new file mode 100644
index 0000000000..82f0987660
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f4-pll-clock.yaml
@@ -0,0 +1,64 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32L4 Main PLL node binding:
+
+  Takes one of clk_hse or clk_hsi as input clock, with an
+  input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
+  in this acceptable range.
+
+  Up to 2 output clocks could be supported and for each output clock, the
+  frequency can be computed with the following formula:
+
+    f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
+    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  The PLL output frequency must not exceed 80 MHz.
+
+
+compatible: "st,stm32f4-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Division factor for the PLL input clock
+          Valid range: 2 - 63
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCO
+          Valid range: 50 - 432
+
+    div-p:
+      type: int
+      required: true
+      description: |
+          Main PLL division factor for PLLSAI2CLK
+      enum:
+        - 2
+        - 4
+        - 6
+        - 8
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
+          generator clocks.
+          Valid range: 2 - 15
diff --git a/dts/bindings/clock/st,stm32f7-pll-clock.yaml b/dts/bindings/clock/st,stm32f7-pll-clock.yaml
new file mode 100644
index 0000000000..15ee75f96c
--- /dev/null
+++ b/dts/bindings/clock/st,stm32f7-pll-clock.yaml
@@ -0,0 +1,59 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32F7 Main PLL node binding:
+
+  Takes one of clk_hse or clk_hsi as input clock.
+
+  Up to 2 output clocks could be supported and for each output clock, the
+  frequency can be computed with the following formula:
+
+    f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
+    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+
+compatible: "st,stm32f7-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Division factor for the PLL input clock
+          Valid range: 2 - 63
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          PLL multiplication factor for VCO
+          Valid range: 50 - 432
+
+    div-p:
+      type: int
+      required: true
+      description: |
+          PLL division factor for PLLCLK
+      enum:
+        - 2
+        - 4
+        - 6
+        - 8
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          PLL division factor for PLL48CK
+          Valid range: 2 - 15
diff --git a/dts/bindings/clock/st,stm32g0-pll-clock.yaml b/dts/bindings/clock/st,stm32g0-pll-clock.yaml
new file mode 100644
index 0000000000..6c80ec883e
--- /dev/null
+++ b/dts/bindings/clock/st,stm32g0-pll-clock.yaml
@@ -0,0 +1,66 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL node binding for STM32G0 devices
+
+  It can take one of clk_hse or clk_hsi as input clock, with
+  an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  PLL can have up to 3 output clocks and for each output clock, the
+  frequency can be computed with the following formulae:
+
+    f(PLL_P) = f(VCO clock) / PLLP  --> to I2S
+    f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
+    f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  The PLL output frequency must not exceed 64 MHz.
+
+compatible: "st,stm32g0-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Division factor for PLL input clock
+          Valid range: 1 - 8
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCO
+          Valid range: 8 - 86
+
+    div-p:
+      type: int
+      required: false
+      description: |
+          PLL division factor for PLL P output
+          Valid range: 2 - 32
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          PLL division factor for PLL Q output
+          Valid range: 2 - 8
+
+    div-r:
+      type: int
+      required: true
+      description: |
+          PLL division factor for PLLCLK (system clock)
+          Valid range: 2 - 8
diff --git a/dts/bindings/clock/st,stm32g4-pll-clock.yaml b/dts/bindings/clock/st,stm32g4-pll-clock.yaml
new file mode 100644
index 0000000000..583b672e39
--- /dev/null
+++ b/dts/bindings/clock/st,stm32g4-pll-clock.yaml
@@ -0,0 +1,44 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL node binding for STM32G4 devices
+
+  It can take one of clk_hse or clk_hsi as input clock, with
+  an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  PLL can have up to 3 output clocks and for each output clock, the
+  frequency can be computed with the following formulae:
+
+    f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
+    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48MCLK (for USB, RNG)
+    f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  The PLL output frequency must not exceed 170 MHz.
+
+compatible: "st,stm32g4-pll-clock"
+
+include:
+  - name: st,stm32l4-pll-clock.yaml
+    property-blocklist:
+      - div-m
+      - mul-n
+
+properties:
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Division factor for PLL input clock
+          Valid range: 1 - 16
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCO
+          Valid range: 8 - 127
diff --git a/dts/bindings/clock/st,stm32h7-hsi-clock.yaml b/dts/bindings/clock/st,stm32h7-hsi-clock.yaml
new file mode 100644
index 0000000000..4a92e86002
--- /dev/null
+++ b/dts/bindings/clock/st,stm32h7-hsi-clock.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 HSI Clock
+
+compatible: "st,stm32h7-hsi-clock"
+
+include: [fixed-clock.yaml]
+
+properties:
+    hsi-div:
+      type: int
+      required: true
+      description: |
+        HSI clock divider. Configures the output HSI clock frequency
+      enum:
+        - 1 # hsi_clk = 64MHz
+        - 2 # hsi_clk = 32MHz
+        - 4 # hsi_clk = 16MHz
+        - 8 # hsi_clk = 8MHz
diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml
new file mode 100644
index 0000000000..580f3f3456
--- /dev/null
+++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml
@@ -0,0 +1,70 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL node binding for STM32H7 devices
+
+  It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
+  Only PLL1 and PLL3 are supported for now.
+
+  These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
+  an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  Each PLL can have up to 3 output clocks and for each output clock, the
+  frequency can be computed with the following formulae:
+
+    f(PLL_Px) = f(VCOx clock) / PLLPx   -> pllx_p_ck ((pll1_p_ck : sys_ck))
+    f(PLL_Qx) = f(VCOx clock) / PLLQx   -> pllx_q_ck
+    f(PLL_Rx) = f(VCOx clock) / PLLRx   -> pllx_r_ck
+
+      with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
+
+  The PLL output frequency must not exceed 80 MHz.
+
+compatible: "st,stm32h7-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Division factor for PLLx
+          input clock
+          Valid range: 0 - 63
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCOx
+          Valid range: 4 - 512
+
+    div-p:
+      type: int
+      required: false
+      description: |
+          PLL division factor for pllx_p_ck
+          Valid range: 1 - 128
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          PLL division factor for pllx_q_ck
+          Valid range: 1 - 128
+
+    div-r:
+      type: int
+      required: false
+      description: |
+          PLL division factor for pllx_r_ck
+          Valid range: 1 - 128
diff --git a/dts/bindings/clock/st,stm32h7-rcc.yaml b/dts/bindings/clock/st,stm32h7-rcc.yaml
new file mode 100644
index 0000000000..b4f32e77bc
--- /dev/null
+++ b/dts/bindings/clock/st,stm32h7-rcc.yaml
@@ -0,0 +1,137 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 Reset and Clock controller node for STM32H7 devices
+  This node is in charge of system clock ('SYSCLK') source selection and
+  System Clock Generation.
+
+  Configuring STM32 Reset and Clock controller node:
+
+  System clock source should be selected amongst the clock nodes available in "clocks"
+  node (typically 'clk_hse, clk_csi', 'pll', ...).
+  As part of this node configuration, SYSCLK frequency should also be defined, using
+  "clock-frequency" property.
+  Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
+  prescaler properties.
+  Here is an example of correctly configured rcc node:
+  &rcc {
+           clocks = <&pll>;  /* Set pll as SYSCLK source */
+           clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
+           d1cpre = <1>;
+           hpre = <1>;
+           d1ppre = <1>;
+           d2ppre1 = <1>;
+           d2ppre2 = <1>;
+           d3ppre = <1>;
+  }
+
+  Specifying a gated clock:
+
+  To specify a gated clock, a peripheral should define a "clocks" property encoded
+  in the following way:
+  ... {
+           ...
+           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+           ...
+  }
+  After the phandle referring to rcc node, the first index specifies the registers of
+  the bus controlling the peripheral and the second index specifies the bit used to
+  control the peripheral clock in that bus register.
+
+compatible: "st,stm32h7-rcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+    clock-frequency:
+      required: true
+      type: int
+      description: |
+        default frequency in Hz for clock output
+
+    d1cpre:
+      type: int
+      required: true
+      enum:
+        - 1
+      description: |
+          D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
+          lower than SYSCLK frequency (actual core frequency).
+          Zephyr doesn't make a difference today between these two clocks.
+          Changing this prescaler is not allowed until it is made possible to
+          use them independently in Zephyr clock subsystem.
+
+    hpre:
+      type: int
+      required: true
+      description: |
+          D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 64
+        - 128
+        - 256
+        - 512
+
+    d1ppre:
+      type: int
+      required: true
+      description: |
+          D1 domain, APB3 peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+    d2ppre1:
+      type: int
+      required: true
+      description: |
+          D2 domain, APB1 peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+    d2ppre2:
+      type: int
+      required: true
+      description: |
+          D2 domain, APB2 peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+    d3ppre:
+      type: int
+      required: true
+      description: |
+          D3 domain, APB4 peripheral prescaler
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+
+clock-cells:
+  - bus
+  - bits
diff --git a/dts/bindings/clock/st,stm32l0-msi-clock.yaml b/dts/bindings/clock/st,stm32l0-msi-clock.yaml
new file mode 100644
index 0000000000..bbbd7dc9fa
--- /dev/null
+++ b/dts/bindings/clock/st,stm32l0-msi-clock.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32L0 and STM32L1 Multi Speed Internal Clock
+
+compatible: "st,stm32l0-msi-clock"
+
+include:
+  - name: st,stm32-msi-clock.yaml
+    property-blocklist:
+      - msi-range
+
+properties:
+    msi-range:
+      required: true
+      type: int
+      default: 5
+      description: |
+        MSI clock ranges
+        0: range 0 around 65.536 kHz
+        1: range 1 around 131.072 kHz
+        2: range 2 around 262.144 kHz
+        3: range 3 around 524.288 kHz
+        4: range 4 around 1.048 MHz
+        5: range 5 around 2.097 MHz (reset value)
+        6: range 6 around 4.194 MHz
diff --git a/dts/bindings/clock/st,stm32l0-pll-clock.yaml b/dts/bindings/clock/st,stm32l0-pll-clock.yaml
new file mode 100644
index 0000000000..c5caddd959
--- /dev/null
+++ b/dts/bindings/clock/st,stm32l0-pll-clock.yaml
@@ -0,0 +1,59 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32L0 and STM32L1 Main PLL node binding:
+
+  Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
+  input frequency from 2 to 24 MHz.
+
+  The desired PLL frequency can be computed with the following formula:
+
+    f(PLL) = f(VCO clock) / PLLDIV  --> PLLCLK (System Clock)
+
+      with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
+
+  The PLL output frequency must not exceed 32 MHz.
+
+compatible: "st,stm32l0-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div:
+      type: int
+      required: true
+      description: |
+          PLL output division
+      enum:
+        - 2
+        - 3
+        - 4
+
+    mul:
+      type: int
+      required: true
+      description: |
+          PLL multiplication factor for VCO
+          The PLL VCO clock frequency must not exceed:
+          - 96 MHz when the product is in Range 1
+          - 48 MHz when the product is in Range 2
+          - 24 MHz when the product is in Range 3
+          If the USB uses the PLL as clock source, the PLL VCO clock must be
+          programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
+      enum:
+        - 3
+        - 4
+        - 6
+        - 8
+        - 12
+        - 16
+        - 24
+        - 32
+        - 48
diff --git a/dts/bindings/clock/st,stm32l4-pll-clock.yaml b/dts/bindings/clock/st,stm32l4-pll-clock.yaml
new file mode 100644
index 0000000000..25cbcab19a
--- /dev/null
+++ b/dts/bindings/clock/st,stm32l4-pll-clock.yaml
@@ -0,0 +1,80 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL node binding for STM32L4 and STM32L5 devices
+
+  It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
+  Only main PLL is supported for now.
+
+  These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
+  an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  Each PLL can have up to 3 output clocks and for each output clock, the
+  frequency can be computed with the following formulae:
+
+    f(PLL_P) = f(VCO clock) / PLLP  --> PLLSAI3CLK
+    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48M1CLK
+    f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  The PLL output frequency must not exceed 80 MHz.
+
+compatible: "st,stm32l4-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
+          input clock
+          Valid range: 1 - 8
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCO
+          Valid range: 8 - 86
+
+    div-p:
+      type: int
+      required: false
+      description: |
+          Main PLL division factor for PLLSAI3CLK
+      enum:
+        - 7
+        - 17
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          Main PLL division factor for PLL48M1CLK (48 MHz clock).
+      enum:
+        - 2
+        - 4
+        - 6
+        - 8
+
+    div-r:
+      type: int
+      required: true
+      description: |
+          Main PLL division factor for PLLCLK (system clock)
+      enum:
+        - 2
+        - 4
+        - 6
+        - 8
diff --git a/dts/bindings/clock/st,stm32mp1-rcc.yaml b/dts/bindings/clock/st,stm32mp1-rcc.yaml
new file mode 100644
index 0000000000..39f51f02f1
--- /dev/null
+++ b/dts/bindings/clock/st,stm32mp1-rcc.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32MP1 Reset and Clock controller node.
+  On STM32MP1 platforms, clock control configuration is performed on A9 side.
+  As a consequence, the only property to be set in devicetree node is the
+  clock-frequency (mlhclk_ck).
+
+compatible: "st,stm32mp1-rcc"
+
+include:
+  - name: st,stm32-rcc.yaml
+    property-blocklist:
+      - ahb-prescaler
+      - apb1-prescaler
+      - apb2-prescaler
diff --git a/dts/bindings/clock/st,stm32u5-msi-clock.yaml b/dts/bindings/clock/st,stm32u5-msi-clock.yaml
new file mode 100644
index 0000000000..52398b3f5d
--- /dev/null
+++ b/dts/bindings/clock/st,stm32u5-msi-clock.yaml
@@ -0,0 +1,37 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32U5 Multi Speed Internal Clock
+
+compatible: "st,stm32u5-msi-clock"
+
+include:
+  - name: st,stm32-msi-clock.yaml
+    property-blocklist:
+      - msi-range
+
+properties:
+
+    msi-range:
+      default: 4
+      required: true
+      type: int
+      description: |
+        MSI clock ranges
+      enum:
+        - 0 # range 0 around 48 MHz
+        - 1 # range 1 around 24 MHz
+        - 2 # range 2 around 16 MHz
+        - 3 # range 3 around 12 MHz
+        - 4 # range 4 around 4 MHz (reset value)
+        - 5 # range 5 around 2 MHz
+        - 6 # range 6 around 1.33 MHz
+        - 7 # range 7 around 1 MHz
+        - 8 # range 8 around 3.072 MHz
+        - 9 # range 9 around 1.536 MHz
+        - 10 # range 10 around 1.024 MHz
+        - 11 # range 11 around 768 KHz
+        - 12 # range 12 around 400 KHz
+        - 13 # range 13 around 200 KHz
+        - 14 # range 14 around 133 KHz
+        - 15 # range 14 around 100 KHz
diff --git a/dts/bindings/clock/st,stm32u5-pll-clock.yaml b/dts/bindings/clock/st,stm32u5-pll-clock.yaml
new file mode 100644
index 0000000000..6e2fb6db4f
--- /dev/null
+++ b/dts/bindings/clock/st,stm32u5-pll-clock.yaml
@@ -0,0 +1,67 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL node binding for STM32U5 devices
+
+  It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
+  Only main PLL (PLL1) is supported for now.
+
+  These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
+  an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  Each PLL can have up to 3 output clocks and for each output clock, the
+  frequency can be computed with the following formulae:
+
+    f(PLL_P) = f(VCO clock) / PLLP
+    f(PLL_Q) = f(VCO clock) / PLLQ
+    f(PLL_R) = f(VCO clock) / PLLR
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  Note: To reduce the power consumption, it is recommended to configure the VCOx
+        clock output to the lowest frequency.
+
+  The PLL output frequency must not exceed 160 MHz.
+
+compatible: "st,stm32u5-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Prescaler for PLLx
+          input clock
+          Valid range: 1 - 16
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          PLLx multiplication factor for VCO
+          Valid range: 4 - 512
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          PLLx DIVQ division factor
+          Valid range: 2 - 128
+
+    div-r:
+      type: int
+      required: true
+      description: |
+          PLLx DIVR division factor
+          Valid range: 2 - 128
diff --git a/dts/bindings/clock/st,stm32u5-rcc.yaml b/dts/bindings/clock/st,stm32u5-rcc.yaml
new file mode 100644
index 0000000000..cea21ffef9
--- /dev/null
+++ b/dts/bindings/clock/st,stm32u5-rcc.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32U5 Reset and Clock controller node.
+  For more description confere st,stm32-rcc.yaml
+
+compatible: "st,stm32u5-rcc"
+
+include: st,stm32-rcc.yaml
+
+properties:
+
+    apb3-prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
diff --git a/dts/bindings/clock/st,stm32wb-pll-clock.yaml b/dts/bindings/clock/st,stm32wb-pll-clock.yaml
new file mode 100644
index 0000000000..6ab37c1cbd
--- /dev/null
+++ b/dts/bindings/clock/st,stm32wb-pll-clock.yaml
@@ -0,0 +1,71 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32WB and STM32WL PLL node.
+
+  It can be used to describe 2 different PLLs: PLL, PLLSAI1.
+  Only main PLL is supported for now.
+
+  These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
+  an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  Each PLL can have up to 3 output clocks and for each output clock, the
+  frequency can be computed with the following formulae:
+
+    f(PLL_P) = f(VCO clock) / PLLP  --> PLLPCLK
+    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLLQCLK
+    f(PLL_R) = f(VCO clock) / PLLR  --> PLLRCLK (System Clock)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  The PLL output frequency must not exceed:
+          - 64 MHz on STM32WB
+          - 62 MHz on STM32WL
+
+compatible: "st,stm32wb-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 0
+
+    clocks:
+      required: true
+
+    div-m:
+      type: int
+      required: true
+      description: |
+          Main PLL division factor for PLL input clock
+          Valid range: 1 - 8
+
+    mul-n:
+      type: int
+      required: true
+      description: |
+          Main PLL multiplication factor for VCO
+          Valid range: 6 - 127
+
+    div-p:
+      type: int
+      required: false
+      description: |
+          Main PLL division factor for PLLPCLK
+          Valid range: 2 - 32
+
+    div-q:
+      type: int
+      required: false
+      description: |
+          Main PLL division factor for PLLQCLK
+          Valid range: 2 - 8
+
+    div-r:
+      type: int
+      required: true
+      description: |
+          Main PLL division factor for PLLRCLK (system clock)
+          Valid range: 2 - 8
diff --git a/dts/bindings/clock/st,stm32wb-rcc.yaml b/dts/bindings/clock/st,stm32wb-rcc.yaml
new file mode 100644
index 0000000000..dce60755fd
--- /dev/null
+++ b/dts/bindings/clock/st,stm32wb-rcc.yaml
@@ -0,0 +1,77 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32WB Reset and Clock controller node.
+  For more description confere st,stm32-rcc.yaml
+
+compatible: "st,stm32wb-rcc"
+
+include:
+  - name: st,stm32-rcc.yaml
+    property-blocklist:
+      - ahb-prescaler
+
+properties:
+    cpu1-prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 3
+        - 4
+        - 5
+        - 6
+        - 8
+        - 10
+        - 16
+        - 32
+        - 64
+        - 128
+        - 256
+        - 512
+      description: |
+          CPU1 prescaler. Sets a HCLK1 frequency (feeding Cortex-M Systick)
+          lower than SYSCLK frequency (actual core frequency).
+          The HCLK1 clocks CPU1, AHB1, AHB2, AHB3 and SRAM1.
+
+    cpu2-prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+        - 256
+        - 512
+      description: |
+          CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
+          (A.K.A C2HPRE)
+
+    ahb4-prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+        - 256
+        - 512
+      description: |
+          HCLK4 shared prescaler (AHB4, Flash memory and SRAM2).
+          (A.K.A SHDHPRE)
+
+clock-cells:
+  - bus
+  - bits
diff --git a/dts/bindings/clock/st,stm32wl-hse-clock.yaml b/dts/bindings/clock/st,stm32wl-hse-clock.yaml
new file mode 100644
index 0000000000..ef573387d8
--- /dev/null
+++ b/dts/bindings/clock/st,stm32wl-hse-clock.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32WL HSE Clock
+
+compatible: "st,stm32wl-hse-clock"
+
+include: [fixed-clock.yaml]
+
+properties:
+    hse-tcxo:
+      type: boolean
+      required: false
+      description: |
+        When set, TCXO is selected as external source clock for HSE.
+        Otherwise, external cyrstal is selected as HSE source clock.
+
+    hse-div2:
+      type: boolean
+      required: false
+      description: |
+        When set HSE output clock is divided by 2.
+        Otherwise, no prescaler is used.
diff --git a/dts/bindings/clock/st,stm32wl-rcc.yaml b/dts/bindings/clock/st,stm32wl-rcc.yaml
new file mode 100644
index 0000000000..f2f2387f4f
--- /dev/null
+++ b/dts/bindings/clock/st,stm32wl-rcc.yaml
@@ -0,0 +1,55 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32WL Reset and Clock controller node.
+  For more description confere st,stm32-rcc.yaml
+
+compatible: "st,stm32wl-rcc"
+
+include:
+  - name: st,stm32wb-rcc.yaml
+    property-blocklist:
+      - ahb4-prescaler
+      - cpu2-prescaler
+
+properties:
+    cpu2-prescaler:
+      type: int
+      required: false
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+        - 256
+        - 512
+      description: |
+          CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
+          (A.K.A C2HPRE)
+
+    ahb3-prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+        - 256
+        - 512
+      description: |
+          HCLK3 shared prescaler (AHB3, Flash memory, SRAM1 and SRAM2).
+          (A.K.A SHDHPRE)
+
+clock-cells:
+  - bus
+  - bits
diff --git a/dts/bindings/counter/st,stm32-counter.yaml b/dts/bindings/counter/st,stm32-counter.yaml
new file mode 100644
index 0000000000..a7e9bfb4cd
--- /dev/null
+++ b/dts/bindings/counter/st,stm32-counter.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2021, Kent Hall
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 counters
+
+compatible: "st,stm32-counter"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/cpu/altr,nios2f.yaml b/dts/bindings/cpu/altr,nios2f.yaml
new file mode 100644
index 0000000000..6b101dcfb7
--- /dev/null
+++ b/dts/bindings/cpu/altr,nios2f.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Altera NIOS-2F CPU
+
+compatible: "altr,nios2f"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
diff --git a/dts/bindings/cpu/arm,cortex-a53.yaml b/dts/bindings/cpu/arm,cortex-a53.yaml
new file mode 100644
index 0000000000..ef47d27155
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-a53.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: This is a representation of ARM Cortex-A53 CPU.
+
+compatible: "arm,cortex-a53"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-a72.yaml b/dts/bindings/cpu/arm,cortex-a72.yaml
new file mode 100644
index 0000000000..7d3bf52fbe
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-a72.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: This is a representation of ARM Cortex-A72 CPU.
+
+compatible: "arm,cortex-a72"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m.yaml b/dts/bindings/cpu/arm,cortex-m.yaml
new file mode 100644
index 0000000000..82997d8684
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for ARM Cortex-M CPU
+
+include: cpu.yaml
+
+properties:
+    swo-ref-frequency:
+      type: int
+      required: false
+      description: Reference clock frequency for SWO if different than CPU clock.
diff --git a/dts/bindings/cpu/arm,cortex-m0+.yaml b/dts/bindings/cpu/arm,cortex-m0+.yaml
new file mode 100644
index 0000000000..677646dbcb
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m0+.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M0+ CPU
+
+compatible: "arm,cortex-m0+"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m0.yaml b/dts/bindings/cpu/arm,cortex-m0.yaml
new file mode 100644
index 0000000000..bcca72748d
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m0.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M0 CPU
+
+compatible: "arm,cortex-m0"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m1.yaml b/dts/bindings/cpu/arm,cortex-m1.yaml
new file mode 100644
index 0000000000..4a9dc5b510
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m1.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M1 CPU
+
+compatible: "arm,cortex-m1"
+
+include: arm,cortex-m.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m23.yaml b/dts/bindings/cpu/arm,cortex-m23.yaml
new file mode 100644
index 0000000000..55088a28b8
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m23.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M23 CPU
+
+compatible: "arm,cortex-m23"
+
+include: arm,cortex-m.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m3.yaml b/dts/bindings/cpu/arm,cortex-m3.yaml
new file mode 100644
index 0000000000..9cc6f0c336
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m3.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M3 CPU
+
+compatible: "arm,cortex-m3"
+
+include: arm,cortex-m.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m33.yaml b/dts/bindings/cpu/arm,cortex-m33.yaml
new file mode 100644
index 0000000000..bcd78e65f0
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m33.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M33 CPU
+
+compatible: "arm,cortex-m33"
+
+include: arm,cortex-m.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m33f.yaml b/dts/bindings/cpu/arm,cortex-m33f.yaml
new file mode 100644
index 0000000000..96ada8b3b3
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m33f.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M33F CPU
+
+compatible: "arm,cortex-m33f"
+
+include: arm,cortex-m.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m4.yaml b/dts/bindings/cpu/arm,cortex-m4.yaml
new file mode 100644
index 0000000000..cc7ba9ceae
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m4.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M4 CPU
+
+compatible: "arm,cortex-m4"
+
+include: arm,cortex-m.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m4f.yaml b/dts/bindings/cpu/arm,cortex-m4f.yaml
new file mode 100644
index 0000000000..1d7b375e5a
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m4f.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M4F CPU
+
+compatible: "arm,cortex-m4f"
+
+include: arm,cortex-m.yaml
diff --git a/dts/bindings/cpu/arm,cortex-m7.yaml b/dts/bindings/cpu/arm,cortex-m7.yaml
new file mode 100644
index 0000000000..b72f4b88f5
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-m7.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M7 CPU
+
+compatible: "arm,cortex-m7"
+
+include: arm,cortex-m.yaml
diff --git a/dts/bindings/cpu/arm,cortex-r4.yaml b/dts/bindings/cpu/arm,cortex-r4.yaml
new file mode 100644
index 0000000000..8253223d77
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-r4.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R4 CPU
+
+compatible: "arm,cortex-r4"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-r4f.yaml b/dts/bindings/cpu/arm,cortex-r4f.yaml
new file mode 100644
index 0000000000..6fb421039b
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-r4f.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R4F CPU
+
+compatible: "arm,cortex-r4f"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-r5.yaml b/dts/bindings/cpu/arm,cortex-r5.yaml
new file mode 100644
index 0000000000..f2ded67036
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-r5.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R5 CPU
+
+compatible: "arm,cortex-r5"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-r5f.yaml b/dts/bindings/cpu/arm,cortex-r5f.yaml
new file mode 100644
index 0000000000..8f931c8422
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-r5f.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R5F CPU
+
+compatible: "arm,cortex-r5f"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-r7.yaml b/dts/bindings/cpu/arm,cortex-r7.yaml
new file mode 100644
index 0000000000..c7ecd06298
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-r7.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R7 CPU
+
+compatible: "arm,cortex-r7"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/arm,cortex-r82.yaml b/dts/bindings/cpu/arm,cortex-r82.yaml
new file mode 100644
index 0000000000..2bcf3027bb
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-r82.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: This is a representation of ARM Cortex-R82 CPU.
+
+compatible: "arm,cortex-r82"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/cdns,tensilica-xtensa-lx4.yaml b/dts/bindings/cpu/cdns,tensilica-xtensa-lx4.yaml
new file mode 100644
index 0000000000..baa88a264e
--- /dev/null
+++ b/dts/bindings/cpu/cdns,tensilica-xtensa-lx4.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence Tensilica Xtensa LX4 CPU
+
+compatible: "cdns,tensilica-xtensa-lx4"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/cdns,tensilica-xtensa-lx6.yaml b/dts/bindings/cpu/cdns,tensilica-xtensa-lx6.yaml
new file mode 100644
index 0000000000..d56d45df48
--- /dev/null
+++ b/dts/bindings/cpu/cdns,tensilica-xtensa-lx6.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence Tensilica Xtensa LX6 CPU
+
+compatible: "cdns,tensilica-xtensa-lx6"
+
+include: cpu.yaml
+
+properties:
+    clock-source:
+      type: int
+      description: cpu clock source
+      required: false
diff --git a/dts/bindings/cpu/cdns,tensilica-xtensa-lx7.yaml b/dts/bindings/cpu/cdns,tensilica-xtensa-lx7.yaml
new file mode 100644
index 0000000000..4e3bac07ee
--- /dev/null
+++ b/dts/bindings/cpu/cdns,tensilica-xtensa-lx7.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence Tensilica Xtensa LX7 CPU
+
+compatible: "cdns,tensilica-xtensa-lx7"
+
+include: cpu.yaml
+
+properties:
+    clock-source:
+      type: int
+      description: cpu clock source
+      required: false
diff --git a/dts/bindings/cpu/cpu.yaml b/dts/bindings/cpu/cpu.yaml
new file mode 100644
index 0000000000..9b4ca58b04
--- /dev/null
+++ b/dts/bindings/cpu/cpu.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for CPUs
+
+include: base.yaml
+
+properties:
+    clock-frequency:
+      type: int
+      required: false
+      description: Clock frequency in Hz
+    cpu-power-states:
+       type: phandles
+       required: false
+       description: List of power management states supported by this cpu
+    i-cache-line-size:
+      type: int
+      required: false
+      description: i-cache line size
+    d-cache-line-size:
+      type: int
+      required: false
+      description: d-cache line size
diff --git a/dts/bindings/cpu/espressif,riscv.yml b/dts/bindings/cpu/espressif,riscv.yml
new file mode 100644
index 0000000000..41dbb7481b
--- /dev/null
+++ b/dts/bindings/cpu/espressif,riscv.yml
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Espressif RISC-V CPU
+
+compatible: "esp,riscv"
+
+include: cpu.yaml
+
+properties:
+    clock-source:
+      type: int
+      description: cpu clock source
+      required: false
diff --git a/dts/bindings/cpu/intel,apollo_lake.yaml b/dts/bindings/cpu/intel,apollo_lake.yaml
new file mode 100644
index 0000000000..3ac47c0a05
--- /dev/null
+++ b/dts/bindings/cpu/intel,apollo_lake.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Apollo lake CPU
+
+compatible: "intel,apollo_lake"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/intel,atom.yaml b/dts/bindings/cpu/intel,atom.yaml
new file mode 100644
index 0000000000..d6c4dd771c
--- /dev/null
+++ b/dts/bindings/cpu/intel,atom.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Atom CPU
+
+compatible: "intel,atom"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/intel,elkhart_lake.yaml b/dts/bindings/cpu/intel,elkhart_lake.yaml
new file mode 100644
index 0000000000..bafa1a317a
--- /dev/null
+++ b/dts/bindings/cpu/intel,elkhart_lake.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Elkhart Lake CPU
+
+compatible: "intel,elkhart_lake"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/intel,lakemont.yml b/dts/bindings/cpu/intel,lakemont.yml
new file mode 100644
index 0000000000..04904e4c77
--- /dev/null
+++ b/dts/bindings/cpu/intel,lakemont.yml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Lakemont CPU
+
+compatible: "intel,lakemont"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/intel,x86.yaml b/dts/bindings/cpu/intel,x86.yaml
new file mode 100644
index 0000000000..487dd39977
--- /dev/null
+++ b/dts/bindings/cpu/intel,x86.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic x86 qemu CPU
+
+compatible: "intel,x86"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/ite,riscv-ite.yaml b/dts/bindings/cpu/ite,riscv-ite.yaml
new file mode 100644
index 0000000000..0f0651d059
--- /dev/null
+++ b/dts/bindings/cpu/ite,riscv-ite.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE IT8XXX2 RISC-V CPU
+
+compatible: "ite,riscv-ite"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/neorv32-cpu.yaml b/dts/bindings/cpu/neorv32-cpu.yaml
new file mode 100644
index 0000000000..417ce963ce
--- /dev/null
+++ b/dts/bindings/cpu/neorv32-cpu.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: NEORV32 RISC-V CPU
+
+compatible: "neorv32-cpu"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/nuclei,bumblebee.yaml b/dts/bindings/cpu/nuclei,bumblebee.yaml
new file mode 100644
index 0000000000..e5eaa74cc9
--- /dev/null
+++ b/dts/bindings/cpu/nuclei,bumblebee.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuclei Bumblebee RISC-V Core
+
+compatible: "nuclei,bumblebee"
+
+include: cpu.yaml
+
+properties:
+  mcause-exception-mask:
+    type: int
+    required: true
+    description:  Specify the bits to use for exception code in mcause register.
diff --git a/dts/bindings/cpu/qemu,nios2-zephyr.yaml b/dts/bindings/cpu/qemu,nios2-zephyr.yaml
new file mode 100644
index 0000000000..654bc982a9
--- /dev/null
+++ b/dts/bindings/cpu/qemu,nios2-zephyr.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: QEMU NIOS2 Zephyr CPU
+
+compatible: "qemu,nios2-zephyr"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
diff --git a/dts/bindings/cpu/sample_controller.yaml b/dts/bindings/cpu/sample_controller.yaml
new file mode 100644
index 0000000000..7450cb6266
--- /dev/null
+++ b/dts/bindings/cpu/sample_controller.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sample controller CPU
+
+compatible: "sample_controller"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/snps,arcem.yaml b/dts/bindings/cpu/snps,arcem.yaml
new file mode 100644
index 0000000000..5f04c3b955
--- /dev/null
+++ b/dts/bindings/cpu/snps,arcem.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys ARC EM CPU
+
+compatible: "snps,arcem"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/telink,b91.yaml b/dts/bindings/cpu/telink,b91.yaml
new file mode 100644
index 0000000000..f70640234d
--- /dev/null
+++ b/dts/bindings/cpu/telink,b91.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink RISC-V CPU
+
+compatible: "telink,b91"
+
+include: cpu.yaml
diff --git a/dts/bindings/crypto/arm,cryptocell-310.yaml b/dts/bindings/crypto/arm,cryptocell-310.yaml
new file mode 100644
index 0000000000..0d148cd155
--- /dev/null
+++ b/dts/bindings/crypto/arm,cryptocell-310.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM TrustZone CryptoCell 310
+
+compatible: "arm,cryptocell-310"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/crypto/arm,cryptocell-312.yaml b/dts/bindings/crypto/arm,cryptocell-312.yaml
new file mode 100644
index 0000000000..40bf4d5c4b
--- /dev/null
+++ b/dts/bindings/crypto/arm,cryptocell-312.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM TrustZone CryptoCell 312
+
+compatible: "arm,cryptocell-312"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/crypto/nordic,nrf-cc310.yaml b/dts/bindings/crypto/nordic,nrf-cc310.yaml
new file mode 100644
index 0000000000..e5180c7689
--- /dev/null
+++ b/dts/bindings/crypto/nordic,nrf-cc310.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic Control Interface for ARM TrustZone CryptoCell 310
+
+compatible: "nordic,nrf-cc310"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/crypto/nordic,nrf-cc312.yaml b/dts/bindings/crypto/nordic,nrf-cc312.yaml
new file mode 100644
index 0000000000..bb76401f8c
--- /dev/null
+++ b/dts/bindings/crypto/nordic,nrf-cc312.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018, 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic Control Interface for ARM TrustZone CryptoCell 312
+
+compatible: "nordic,nrf-cc312"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/crypto/nordic,nrf-ecb.yaml b/dts/bindings/crypto/nordic,nrf-ecb.yaml
new file mode 100644
index 0000000000..aefcaab2e7
--- /dev/null
+++ b/dts/bindings/crypto/nordic,nrf-ecb.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic ECB (AES electronic codebook mode encryption)
+
+compatible: "nordic,nrf-ecb"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/crypto/st,stm32-aes.yaml b/dts/bindings/crypto/st,stm32-aes.yaml
new file mode 100644
index 0000000000..62fdc859f9
--- /dev/null
+++ b/dts/bindings/crypto/st,stm32-aes.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Thomas Stranger
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 AES Accelerator
+
+compatible: "st,stm32-aes"
+
+include: st,stm32-crypto-common.yaml
diff --git a/dts/bindings/crypto/st,stm32-cryp.yaml b/dts/bindings/crypto/st,stm32-cryp.yaml
new file mode 100644
index 0000000000..0de9db877b
--- /dev/null
+++ b/dts/bindings/crypto/st,stm32-cryp.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 Cryptographic Accelerator
+
+compatible: "st,stm32-cryp"
+
+include: st,stm32-crypto-common.yaml
diff --git a/dts/bindings/crypto/st,stm32-crypto-common.yaml b/dts/bindings/crypto/st,stm32-crypto-common.yaml
new file mode 100644
index 0000000000..034ecd0121
--- /dev/null
+++ b/dts/bindings/crypto/st,stm32-crypto-common.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2020, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
diff --git a/dts/bindings/dac/atmel,sam-dac.yaml b/dts/bindings/dac/atmel,sam-dac.yaml
new file mode 100644
index 0000000000..0de2771808
--- /dev/null
+++ b/dts/bindings/dac/atmel,sam-dac.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2021 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM family DAC
+
+compatible: "atmel,sam-dac"
+
+include: dac-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: |
+        peripheral ID
+
+    prescaler:
+      type: int
+      required: false
+      default: 15
+      description: |
+        Peripheral Clock to DAC Clock Ratio. Prescaler value is calcuated as
+        PRESCAL = (MCK / DACClock) - 2. Should be in range from 0 to 15. The
+        value will be written to DACC_MR.PRESCALER bit-field. The property is
+        applicable only to SAME70, SAMV71 series devices.
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - output
diff --git a/dts/bindings/dac/atmel,sam0-dac.yaml b/dts/bindings/dac/atmel,sam0-dac.yaml
new file mode 100644
index 0000000000..931f69803c
--- /dev/null
+++ b/dts/bindings/dac/atmel,sam0-dac.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2020 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 family DAC
+
+compatible: "atmel,sam0-dac"
+
+include: dac-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+    clock-names:
+      required: true
+
+    label:
+      required: true
+
+    reference:
+      type: string
+      required: false
+      description: Reference voltage source
+      enum:
+        - "intref"
+        - "vddana"
+        - "vrefa"
+
+    "#io-channel-cells":
+      const: 0
diff --git a/dts/bindings/dac/dac-controller.yaml b/dts/bindings/dac/dac-controller.yaml
new file mode 100644
index 0000000000..9af71a7bc4
--- /dev/null
+++ b/dts/bindings/dac/dac-controller.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2020 Libre Solar Technologies GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for DAC controllers
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    "#io-channel-cells":
+      type: int
+      required: true
diff --git a/dts/bindings/dac/gd,gd32-dac.yaml b/dts/bindings/dac/gd,gd32-dac.yaml
new file mode 100644
index 0000000000..0ad2ff2b95
--- /dev/null
+++ b/dts/bindings/dac/gd,gd32-dac.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: GigaDevice GD32 series DAC module
+
+compatible: "gd,gd32-dac"
+
+include: [dac-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    rcu-periph-clock:
+      type: int
+      description: Reset Control Unit Peripheral Clock ID
+      required: true
+
+    num-channels:
+      type: int
+      description: Number of DAC output channels
+      required: true
+
+    reset-val:
+      type: int
+      default: 0
+      description: Reset value of DAC output. Defaults to 0, the SoC default.
+      required: false
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - output
diff --git a/dts/bindings/dac/microchip,mcp4725.yaml b/dts/bindings/dac/microchip,mcp4725.yaml
new file mode 100644
index 0000000000..4a33ee37a1
--- /dev/null
+++ b/dts/bindings/dac/microchip,mcp4725.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021 Laird Connectivity
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip MCP4725 12-bit DAC
+
+compatible: "microchip,mcp4725"
+
+include: [dac-controller.yaml, i2c-device.yaml]
+
+properties:
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - output
diff --git a/dts/bindings/dac/nxp,kinetis-dac.yaml b/dts/bindings/dac/nxp,kinetis-dac.yaml
new file mode 100644
index 0000000000..78bf6b5338
--- /dev/null
+++ b/dts/bindings/dac/nxp,kinetis-dac.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis MCUX DAC
+
+compatible: "nxp,kinetis-dac"
+
+include: dac-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    voltage-reference:
+      type: int
+      required: true
+      description: DAC voltage reference select
+
+    low-power-mode:
+      type: boolean
+      required: false
+      description: Enable low-power mode
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - output
diff --git a/dts/bindings/dac/nxp,kinetis-dac32.yaml b/dts/bindings/dac/nxp,kinetis-dac32.yaml
new file mode 100644
index 0000000000..2feca3b344
--- /dev/null
+++ b/dts/bindings/dac/nxp,kinetis-dac32.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis MCUX DAC32
+
+compatible: "nxp,kinetis-dac32"
+
+include: dac-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    voltage-reference:
+      type: int
+      required: true
+      description: DAC voltage reference select
+
+    low-power-mode:
+      type: boolean
+      required: false
+      description: Enable low-power mode
+
+    buffered:
+      type: boolean
+      required: false
+      description: Enable output buffer
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - output
diff --git a/dts/bindings/dac/st,stm32-dac.yaml b/dts/bindings/dac/st,stm32-dac.yaml
new file mode 100644
index 0000000000..c339bbb70a
--- /dev/null
+++ b/dts/bindings/dac/st,stm32-dac.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2020 Libre Solar Technologies GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST STM32 family DAC
+
+compatible: "st,stm32-dac"
+
+include: [dac-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
+io-channel-cells:
+    - output
diff --git a/dts/bindings/dac/ti,dac43608.yaml b/dts/bindings/dac/ti,dac43608.yaml
new file mode 100644
index 0000000000..37f362c095
--- /dev/null
+++ b/dts/bindings/dac/ti,dac43608.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Matija Tudan
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI DAC43608 8-bit 8 channel DAC
+
+compatible: "ti,dac43608"
+
+include: ti,dacx3608-base.yaml
diff --git a/dts/bindings/dac/ti,dac53608.yaml b/dts/bindings/dac/ti,dac53608.yaml
new file mode 100644
index 0000000000..6ddc262181
--- /dev/null
+++ b/dts/bindings/dac/ti,dac53608.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Matija Tudan
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI DAC53608 10-bit 8 channel DAC
+
+compatible: "ti,dac53608"
+
+include: ti,dacx3608-base.yaml
diff --git a/dts/bindings/dac/ti,dac60508.yaml b/dts/bindings/dac/ti,dac60508.yaml
new file mode 100644
index 0000000000..469cbaa8f5
--- /dev/null
+++ b/dts/bindings/dac/ti,dac60508.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 M2I Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI DAC60508 12-bit DAC
+
+compatible: "ti,dac60508"
+
+include: ti,dacx0508-base.yaml
diff --git a/dts/bindings/dac/ti,dac70508.yaml b/dts/bindings/dac/ti,dac70508.yaml
new file mode 100644
index 0000000000..e7a5c258a6
--- /dev/null
+++ b/dts/bindings/dac/ti,dac70508.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 M2I Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI DAC70508 14-bit DAC
+
+compatible: "ti,dac70508"
+
+include: ti,dacx0508-base.yaml
diff --git a/dts/bindings/dac/ti,dac80508.yaml b/dts/bindings/dac/ti,dac80508.yaml
new file mode 100644
index 0000000000..1b79996a13
--- /dev/null
+++ b/dts/bindings/dac/ti,dac80508.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 M2I Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI DAC80508 16-bit DAC
+
+compatible: "ti,dac80508"
+
+include: ti,dacx0508-base.yaml
diff --git a/dts/bindings/dac/ti,dacx0508-base.yaml b/dts/bindings/dac/ti,dacx0508-base.yaml
new file mode 100644
index 0000000000..6899dc90e0
--- /dev/null
+++ b/dts/bindings/dac/ti,dacx0508-base.yaml
@@ -0,0 +1,83 @@
+# Copyright (c) 2020 M2I Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+include: [dac-controller.yaml, spi-device.yaml]
+
+properties:
+    voltage-reference:
+      type: int
+      required: true
+      description: |
+        DAC voltage reference select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    channel0-gain:
+      type: int
+      required: true
+      description: |
+        Channel 0 gain select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    channel1-gain:
+      type: int
+      required: true
+      description: |
+        Channel 1 gain select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    channel2-gain:
+      type: int
+      required: true
+      description: |
+        Channel 2 gain select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    channel3-gain:
+      type: int
+      required: true
+      description: |
+        Channel 3 gain select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    channel4-gain:
+      type: int
+      required: true
+      description: |
+        Channel 4 gain select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    channel5-gain:
+      type: int
+      required: true
+      description: |
+        Channel 5 gain select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    channel6-gain:
+      type: int
+      required: true
+      description: |
+        Channel 6 gain select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    channel7-gain:
+      type: int
+      required: true
+      description: |
+        Channel 7 gain select
+
+        See constants in dt-bindings/dac/dacx0508.h.
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - output
diff --git a/dts/bindings/dac/ti,dacx3608-base.yaml b/dts/bindings/dac/ti,dacx3608-base.yaml
new file mode 100644
index 0000000000..660b75d94c
--- /dev/null
+++ b/dts/bindings/dac/ti,dacx3608-base.yaml
@@ -0,0 +1,11 @@
+# Copyright (c) 2020 Matija Tudan
+# SPDX-License-Identifier: Apache-2.0
+
+include: [dac-controller.yaml, i2c-device.yaml]
+
+properties:
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - output
diff --git a/dts/bindings/display/display-controller.yaml b/dts/bindings/display/display-controller.yaml
new file mode 100644
index 0000000000..60d6fd8936
--- /dev/null
+++ b/dts/bindings/display/display-controller.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# Common fields for display controllers
+
+include: base.yaml
+
+properties:
+    height:
+      type: int
+      required: true
+      description: |
+        Height of the panel driven by the controller, with the units in pixels.
+
+    width:
+      type: int
+      required: true
+      description: |
+        Width of the panel driven by the controller, with the units in pixels.
+
+    label:
+      required: true
diff --git a/dts/bindings/display/fsl,imx6sx-lcdif.yaml b/dts/bindings/display/fsl,imx6sx-lcdif.yaml
new file mode 100644
index 0000000000..94e5565d71
--- /dev/null
+++ b/dts/bindings/display/fsl,imx6sx-lcdif.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP i.MX eLCDIF (Enhanced LCD Interface) controller
+
+compatible: "fsl,imx6sx-lcdif"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/display/ftdi,ft800.yaml b/dts/bindings/display/ftdi,ft800.yaml
new file mode 100644
index 0000000000..b4d3437f6b
--- /dev/null
+++ b/dts/bindings/display/ftdi,ft800.yaml
@@ -0,0 +1,107 @@
+# Copyright (c) 2020 Hubert Miś <hubert.mis@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: FTDI FT800 graphic controller
+
+compatible: "ftdi,ft800"
+
+include: spi-device.yaml
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: Optional IRQ line of FT800 controller
+
+    pclk:
+      type: int
+      required: true
+      description: |
+        The value to divide the main clock by for PCLK. If the
+        typical main clock was 48MHz and this value is 5, the PCLK
+        will be 9.6 MHz. Must be positive value to enable the screen
+
+    pclk_pol:
+      type: int
+      required: true
+      description: |
+        Polarity of PCLK. If it is set to zero, PCLK polarity is on
+        the rising edge. If it is set to one, PCLK polarity is on
+        the falling edge.
+
+    cspread:
+      type: int
+      required: true
+      description: |
+        Controls the transition of RGB signals with PCLK active clock
+        edge. When set to 0, R[7:2],G[7:2] and B[7:2] signals change
+        following the active edge of PCLK. When set to 1, R[7:2]
+        changes a PCLK clock early and B[7:2] a PCLK clock later,
+        which helps reduce the system noise.
+
+    swizzle:
+      type: int
+      required: true
+      description: |
+        Controls the arrangement of output RGB pins, which may help
+        support different LCD panel. Please check FT800 Programmers
+        Guide for details.
+
+    vsize:
+      type: int
+      required: true
+      description: Number of visible lines of pixels in one frame
+
+    voffset:
+      type: int
+      required: true
+      description: Number of invisible lines at the beginning of a new frame
+
+    vcycle:
+      type: int
+      required: true
+      description: |
+        Number of all lines in a frame. It includes all visible and
+        invisible lines at the beginning and at the end of a frame.
+
+    vsync0:
+      type: int
+      required: true
+      description: |
+        Number of lines for the high state of signal VSYNC at
+        the start of new frame.
+
+    vsync1:
+      type: int
+      required: true
+      description: |
+        Number of lines for signal VSYNC toggle takes at the start
+        of new frame.
+
+    hsize:
+      type: int
+      required: true
+      description: Number of PCLK cycles per visible part of horizontal line
+
+    hoffset:
+      type: int
+      required: true
+      description: |
+        Number of PCLK cycles before pixels are scanned out for
+        given line
+
+    hcycle:
+      type: int
+      required: true
+      description: Number of total PCLK cycles per horizontal line scan.
+
+    hsync0:
+      type: int
+      required: true
+      description: Number of PCLK cycles of HSYNC high state during start of
+        line
+
+    hsync1:
+      type: int
+      required: true
+      description: Number of PCLK cycles for HSYNC toggle during start of line.
diff --git a/dts/bindings/display/gooddisplay,gd7965.yaml b/dts/bindings/display/gooddisplay,gd7965.yaml
new file mode 100644
index 0000000000..fe7de8eac2
--- /dev/null
+++ b/dts/bindings/display/gooddisplay,gd7965.yaml
@@ -0,0 +1,56 @@
+# Copyright (c) 2020, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: GD7965 EPD display controller
+
+compatible: "gooddisplay,gd7965"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: RESET pin.
+
+        The RESET pin of GD7965 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    dc-gpios:
+      type: phandle-array
+      required: true
+      description: DC pin.
+
+        The DC pin of GD7965 is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    busy-gpios:
+      type: phandle-array
+      required: true
+      description: BUSY pin.
+
+        The BUSY pin of GD7965 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    pwr:
+      type: uint8-array
+      required: true
+      description: Power Setting (PWR) values
+
+    softstart:
+      type: uint8-array
+      required: true
+      description: Booster Soft Start (BTST) values
+
+    cdi:
+      type: int
+      required: true
+      description: VCOM and data interval value
+
+    tcon:
+      type: int
+      required: true
+      description: TCON setting value
diff --git a/dts/bindings/display/ilitek,ili9340.yaml b/dts/bindings/display/ilitek,ili9340.yaml
new file mode 100644
index 0000000000..4efbc846cc
--- /dev/null
+++ b/dts/bindings/display/ilitek,ili9340.yaml
@@ -0,0 +1,97 @@
+# Copyright (c) 2018, Jan Van Winkel <jan.van_winkel@dxplore.eu>
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ILI9340 320x240 display controller
+
+compatible: "ilitek,ili9340"
+
+include: ilitek,ili9xxx-common.yaml
+
+properties:
+    gamset:
+      type: uint8-array
+      default: [0x01]
+      description:
+        Gamma set (GAMSET) register value.
+
+    frmctr1:
+      type: uint8-array
+      default: [0x00, 0x1b]
+      description:
+        Frame rate control (in normal mode / full colors) (FRMCTR1) register value.
+
+    disctrl:
+      type: uint8-array
+      default: [0x0a, 0x82, 0x27]
+      description:
+        Display function control (DISCTRL) register value. Note that changing
+        default SS bit value (0) may interfere with display rotation.
+
+    pwctrl1:
+      type: uint8-array
+      default: [0x26, 0x00]
+      description:
+        Power control 1 (PWCTRL1) register values.
+
+    pwctrl2:
+      type: uint8-array
+      default: [0x00]
+      description:
+        Power control 2 (PWCTRL2) register values.
+
+    vmctrl1:
+      type: uint8-array
+      default: [0x31, 0x3c]
+      description:
+        VCOM control 1 (VMCTRL1) register values.
+
+    vmctrl2:
+      type: uint8-array
+      default: [0xc0]
+      description:
+        VCOM control 2 (VMCTRL2) register values.
+
+    pgamctrl:
+      type: uint8-array
+      default: [
+        0x0f,
+        0x22,
+        0x1f,
+        0x0a,
+        0x0e,
+        0x06,
+        0x4d,
+        0x76,
+        0x3b,
+        0x03,
+        0x0e,
+        0x04,
+        0x13,
+        0x0e,
+        0x0c
+      ]
+      description:
+        Positive gamma correction (PGAMCTRL) register values.
+
+    ngamctrl:
+      type: uint8-array
+      default: [
+        0x0c,
+        0x23,
+        0x26,
+        0x04,
+        0x10,
+        0x04,
+        0x39,
+        0x24,
+        0x4b,
+        0x03,
+        0x0b,
+        0x0b,
+        0x33,
+        0x37,
+        0x0f
+      ]
+      description:
+        Negative gamma correction (NGAMCTRL) register values.
diff --git a/dts/bindings/display/ilitek,ili9341.yaml b/dts/bindings/display/ilitek,ili9341.yaml
new file mode 100644
index 0000000000..e8cfbe9683
--- /dev/null
+++ b/dts/bindings/display/ilitek,ili9341.yaml
@@ -0,0 +1,146 @@
+# Copyright (c) 2018, Jan Van Winkel <jan.van_winkel@dxplore.eu>
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# Copyright (c) 2021, Krivorot Oleg <krivorot.oleg@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ILI9341 320x240 display controller
+
+compatible: "ilitek,ili9341"
+
+include: ilitek,ili9xxx-common.yaml
+
+properties:
+    pwctrla:
+      type: uint8-array
+      default: [0x39, 0x2c, 0x00, 0x34, 0x02]
+      description:
+        Power control A (PWCTRLA) register value.
+
+    pwctrlb:
+      type: uint8-array
+      default: [0x00, 0x8b, 0x30]
+      description:
+        Power control B (PWCTRLB) register value.
+
+    pwseqctrl:
+      type: uint8-array
+      default: [0x55, 0x01, 0x23, 0x01]
+      description:
+        Power on sequence control (PWSEQCTRL) register value.
+
+    timctrla:
+      type: uint8-array
+      default: [0x84, 0x11, 0x7a]
+      description:
+        Driver timing control A (TIMCTRLA) register value.
+
+    timctrlb:
+      type: uint8-array
+      default: [0x00, 0x00]
+      description:
+        Driver timing control B (TIMCTRLB) register value.
+
+    pumpratioctrl:
+      type: uint8-array
+      default: [0x10]
+      description:
+        Pump ratio control (PUMPRATIOCTRL) register value.
+
+    enable3g:
+      type: uint8-array
+      default: [0x02]
+      description:
+        Enable 3G (ENABLE3G) register value.
+
+    etmod:
+      type: uint8-array
+      default: [ 0x06 ]
+      description:
+        Entry Mode Set (ETMOD) register value.
+
+    gamset:
+      type: uint8-array
+      default: [0x01]
+      description:
+        Gamma set (GAMSET) register value.
+
+    frmctr1:
+      type: uint8-array
+      default: [0x00, 0x1b]
+      description:
+        Frame rate control (in normal mode / full colors) (FRMCTR1) register value.
+
+    disctrl:
+      type: uint8-array
+      default: [0x0a, 0x82, 0x27]
+      description:
+        Display function control (DISCTRL) register value. Note that changing
+        default SS bit value (0) may interfere with display rotation.
+
+    pwctrl1:
+      type: uint8-array
+      default: [0x21]
+      description:
+        Power control 1 (PWCTRL1) register values.
+
+    pwctrl2:
+      type: uint8-array
+      default: [0x10]
+      description:
+        Power control 2 (PWCTRL2) register values.
+
+    vmctrl1:
+      type: uint8-array
+      default: [0x31, 0x3c]
+      description:
+        VCOM control 1 (VMCTRL1) register values.
+
+    vmctrl2:
+      type: uint8-array
+      default: [0xc0]
+      description:
+        VCOM control 2 (VMCTRL2) register values.
+
+    pgamctrl:
+      type: uint8-array
+      default: [
+        0x0f,
+        0x22,
+        0x1f,
+        0x0a,
+        0x0e,
+        0x06,
+        0x4d,
+        0x76,
+        0x3b,
+        0x03,
+        0x0e,
+        0x04,
+        0x13,
+        0x0e,
+        0x0c
+      ]
+      description:
+        Positive gamma correction (PGAMCTRL) register values.
+
+    ngamctrl:
+      type: uint8-array
+      default: [
+        0x0c,
+        0x23,
+        0x26,
+        0x04,
+        0x10,
+        0x04,
+        0x39,
+        0x24,
+        0x4b,
+        0x03,
+        0x0b,
+        0x0b,
+        0x33,
+        0x37,
+        0x0f
+      ]
+      description:
+        Negative gamma correction (NGAMCTRL) register values.
diff --git a/dts/bindings/display/ilitek,ili9488.yaml b/dts/bindings/display/ilitek,ili9488.yaml
new file mode 100644
index 0000000000..e948595bcd
--- /dev/null
+++ b/dts/bindings/display/ilitek,ili9488.yaml
@@ -0,0 +1,84 @@
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ILI9488 320x480 display controller
+
+compatible: "ilitek,ili9488"
+
+include: ilitek,ili9xxx-common.yaml
+
+properties:
+    frmctr1:
+      type: uint8-array
+      default: [0xb0, 0x11]
+      description:
+        Frame rate control (in normal mode / full colors) (FRMCTR1) register value.
+
+    disctrl:
+      type: uint8-array
+      default: [0x02, 0x02, 0x3b]
+      description:
+        Display function control (DISCTRL) register value. Note that changing
+        default SS bit value (0) may interfere with display rotation.
+
+    pwctrl1:
+      type: uint8-array
+      default: [0x0e, 0x0e]
+      description:
+        Power control 1 (PWCTRL1) register values.
+
+    pwctrl2:
+      type: uint8-array
+      default: [0x43]
+      description:
+        Power control 2 (PWCTRL2) register values.
+
+    vmctrl:
+      type: uint8-array
+      default: [0x00, 0x40, 0x00, 0x40]
+      description:
+        VCOM control (VMCTRL) register values.
+
+    pgamctrl:
+      type: uint8-array
+      default: [
+        0x0f,
+        0x1f,
+        0x1c,
+        0x0b,
+        0x0e,
+        0x09,
+        0x48,
+        0x99,
+        0x38,
+        0x0a,
+        0x14,
+        0x06,
+        0x11,
+        0x09,
+        0x00
+      ]
+      description:
+        Positive gamma correction (PGAMCTRL) register values.
+
+    ngamctrl:
+      type: uint8-array
+      default: [
+        0x0f,
+        0x36,
+        0x2e,
+        0x09,
+        0x0a,
+        0x04,
+        0x46,
+        0x66,
+        0x37,
+        0x06,
+        0x10,
+        0x04,
+        0x24,
+        0x20,
+        0x00
+      ]
+      description:
+        Negative gamma correction (NGAMCTRL) register values.
diff --git a/dts/bindings/display/ilitek,ili9xxx-common.yaml b/dts/bindings/display/ilitek,ili9xxx-common.yaml
new file mode 100644
index 0000000000..99e6da7490
--- /dev/null
+++ b/dts/bindings/display/ilitek,ili9xxx-common.yaml
@@ -0,0 +1,54 @@
+# Copyright (c) 2018, Jan Van Winkel <jan.van_winkel@dxplore.eu>
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ILI9XXX display controllers common properties.
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: RESET pin.
+
+        The RESET pin of ILI9340 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    cmd-data-gpios:
+      type: phandle-array
+      required: true
+      description: D/CX pin.
+
+        The D/CX pin of ILI9340 is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    pixel-format:
+      type: int
+      default: 0
+      enum:
+        - 0 # RGB565
+        - 1 # RGB888
+      description:
+        Display pixel format. Note that when RGB888 pixel format is selected
+        only 6 color bits are actually used being in practice equivalent to
+        RGB666.
+
+    rotation:
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 90
+        - 180
+        - 270
+      description:
+        Display rotation (CW) in degrees.
+
+    display-inversion:
+      type: boolean
+      description:
+        Display inversion mode. Every bit is inverted from the frame memory to
+        the display.
diff --git a/dts/bindings/display/nordic,nrf-led-matrix.yaml b/dts/bindings/display/nordic,nrf-led-matrix.yaml
new file mode 100644
index 0000000000..c5553671a8
--- /dev/null
+++ b/dts/bindings/display/nordic,nrf-led-matrix.yaml
@@ -0,0 +1,82 @@
+# Copyright (c) 2021, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic LED matrix driven by nRF SoC GPIOs
+
+compatible: "nordic,nrf-led-matrix"
+
+include: display-controller.yaml
+
+properties:
+    row-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        Array of GPIOs to be used as rows of the matrix.
+
+    col-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        Array of GPIOs to be used as columns of the matrix.
+
+    pixel-mapping:
+      type: uint8-array
+      required: true
+      description: |
+        Array of bytes that specify which rows and columns of the matrix
+        control its particular pixels, line by line. Each byte in this
+        array corresponds to one pixel of the matrix and specifies the row
+        index in the high nibble and the column index in the low nibble.
+
+        For example, the following snippet (from the bbc_microbit board DTS):
+
+          width = <5>;
+          height = <5>;
+          pixel-mapping = [00 13 01 14 02
+                           23 24 25 26 27
+                           ...
+
+        specifies that:
+        - pixel (0,0) is controlled by row 0 and column 0
+        - pixel (1,0) is controlled by row 1 and column 3
+        - pixel (0,1) is controlled by row 2 and column 3
+        - pixel (1,1) is controlled by row 2 and column 4
+        and so on.
+
+    refresh-frequency:
+      type: int
+      required: true
+      description: |
+        Frequency of refreshing the matrix, in Hz.
+
+    timer:
+      type: phandle
+      required: true
+      description: |
+        Reference to a TIMER instance for controlling refreshing of the matrix.
+
+    pwm:
+      type: phandle
+      required: false
+      description: |
+        Reference to a PWM instance for generating pulse signals on column
+        GPIOs. If not provided, GPIOTE and PPI channels are allocated and
+        used instead for generating those pulses.
+
+    pixel-group-size:
+      type: int
+      required: true
+      description: |
+        This value specifies the maximum number of LEDs in one row that can
+        be lit simultaneously.
+        If set to 1, only a single LED is turned on in a particular time slot.
+        Bigger values increase the maximum achievable brightness of the LEDs
+        and lower the CPU load by decreasing the frequency of execution of
+        the timer interrupt handler.
+        In case GPIOTE and PPI channels are used for generating the pixel pulse
+        signals, the number of channels that need to be allocated is equal to
+        this value.
+        If GPIOTE and PPI channels are used, the upper limit for the value is
+        defined by the number of CC channels in the used timer minus one.
+        If PWM is used, the upper limit is the number of PWM channels.
diff --git a/dts/bindings/display/rocktech,rk043fn02h-ct.yaml b/dts/bindings/display/rocktech,rk043fn02h-ct.yaml
new file mode 100644
index 0000000000..9c16e0b1af
--- /dev/null
+++ b/dts/bindings/display/rocktech,rk043fn02h-ct.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Rocktech LCD module with LED backlight and capacitive touch panel
+
+compatible: "rocktech,rk043fn02h-ct"
+
+include: base.yaml
diff --git a/dts/bindings/display/sharp,ls0xx.yaml b/dts/bindings/display/sharp,ls0xx.yaml
new file mode 100644
index 0000000000..cd6a941a60
--- /dev/null
+++ b/dts/bindings/display/sharp,ls0xx.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2020, Rohit Gujarathi
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sharp memory display controller
+
+compatible: "sharp,ls0xx"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    extcomin-gpios:
+      type: phandle-array
+      required: false
+      description: EXTCOMIN pin
+
+        The EXTCOMIN pin is where a square pulse for toggling VCOM will
+        be given
+
+    extcomin-frequency:
+      type: int
+      required: false
+      description: EXTCOMIN pin toggle frequency
+
+        The frequency with which the EXTCOMIN pin should be toggled. See
+        datasheet of particular display. Higher frequency gives better
+        contrast while low frequency saves power.
+
+    disp-en-gpios:
+      type: phandle-array
+      required: false
+      description: DISPLAY pin
+
+        The DISPLAY pin controls if the LCD displays memory contents or
+        white screen. If defined, the pin will be set high during driver
+        initialization. display blanking apis can be used to control it.
diff --git a/dts/bindings/display/sitronix,st7735r.yaml b/dts/bindings/display/sitronix,st7735r.yaml
new file mode 100644
index 0000000000..f08c7b3d50
--- /dev/null
+++ b/dts/bindings/display/sitronix,st7735r.yaml
@@ -0,0 +1,117 @@
+# Copyright (c) 2020, Kim Bøndergaard <kim@fam-boendergaard.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST7735R 160x128 display controller
+
+compatible: "sitronix,st7735r"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: RESET pin.
+
+        The RESET pin of ST7735R is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    cmd-data-gpios:
+      type: phandle-array
+      required: true
+      description: D/CX pin.
+
+        The D/CX pin of ST7735R is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    x-offset:
+      type: int
+      required: true
+      description: The column offset in pixels of the LCD to the controller memory
+
+    y-offset:
+      type: int
+      required: true
+      description: The row offset in pixels of the LCD to the controller memory
+
+    madctl:
+      type: int
+      default: 0x00
+      description: Memory Data Access Control
+
+    colmod:
+      type: int
+      default: 0x06
+      description: Interface Pixel Format
+
+    pwctr1:
+      type: uint8-array
+      default: [0xb4, 0x14, 0x04]
+      description: Power Control 1 Parameter
+
+    pwctr2:
+      type: uint8-array
+      default: [0xc0]
+      description: Power Control 2 Parameter
+
+    pwctr3:
+      type: uint8-array
+      default: [0x0a, 0x00]
+      description: Power Control 3 Parameter
+
+    pwctr4:
+      type: uint8-array
+      default: [0x8a, 0x26]
+      description: Power Control 4 Parameter
+
+    pwctr5:
+      type: uint8-array
+      default: [0x8a, 0xee]
+      description: Power Control 5 Parameter
+
+    gamctrp1:
+      type: uint8-array
+      required: true
+      description: Positive Voltage Gamma Control Parameter
+
+    gamctrn1:
+      type: uint8-array
+      required: true
+      description: Negative Voltage Gamma Control Parameter
+
+    frmctr1:
+      type: uint8-array
+      default: [0x05, 0x3a, 0x3a]
+      description: Frame rate control (normal mode / full colors)
+
+    frmctr2:
+      type: uint8-array
+      default: [0x05, 0x3a, 0x3a]
+      description: Frame rate control (idle mode / 8 colors)
+
+    frmctr3:
+      type: uint8-array
+      default: [0x05, 0x3a, 0x3a, 0x05, 0x3a, 0x3a]
+      description: Frame rate control (partial mode / full colors)
+
+    caset:
+      type: uint8-array
+      default: [0x00, 0x00, 0x00, 0x7f]
+      description: Column Address Set
+
+    raset:
+      type: uint8-array
+      default: [0x00, 0x00, 0x00, 0x9f]
+      description: Row Address Set
+
+    vmctr1:
+      type: int
+      default: 0x0a
+      description: VCOM Control 1
+
+    invctr:
+      type: int
+      default: 0x07
+      description: Display Inversion Control
diff --git a/dts/bindings/display/sitronix,st7789v.yaml b/dts/bindings/display/sitronix,st7789v.yaml
new file mode 100644
index 0000000000..4baa544a67
--- /dev/null
+++ b/dts/bindings/display/sitronix,st7789v.yaml
@@ -0,0 +1,115 @@
+# Copyright (c) 2019, Marc Reilly <marc@cpdesign.com.au>
+# Copyright (c) 2019, PHYTEC Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST7789V 320x240 display controller
+
+compatible: "sitronix,st7789v"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        RESET pin.
+
+        The RESET pin of ST7789V is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    cmd-data-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        D/CX pin.
+
+        The D/CX pin of ST7789V is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    x-offset:
+      type: int
+      required: true
+      description: The column offset in pixels of the LCD to the controller memory
+
+    y-offset:
+      type: int
+      required: true
+      description: The row offset in pixels of the LCD to the controller memory
+
+    vcom:
+      type: int
+      required: true
+      description: VCOM Setting
+
+    gctrl:
+      type: int
+      required: true
+      description: Gate Control
+
+    vrhs:
+      type: int
+      required: false
+      description: VRH Setting
+
+    vdvs:
+      type: int
+      required: false
+      description: VDV Setting
+
+    mdac:
+      type: int
+      required: true
+      description: Memory Data Access Control
+
+    lcm:
+      type: int
+      required: true
+      description: LCM Setting
+
+    colmod:
+      type: int
+      required: true
+      description: Interface Pixel Format
+
+    gamma:
+      type: int
+      required: true
+      description: Gamma Setting
+
+    porch-param:
+      type: uint8-array
+      required: true
+      description: Porch Setting
+
+    cmd2en-param:
+      type: uint8-array
+      required: true
+      description: Command 2 Enable Parameter
+
+    pwctrl1-param:
+      type: uint8-array
+      required: true
+      description: Power Control 1 Parameter
+
+    pvgam-param:
+      type: uint8-array
+      required: true
+      description: Positive Voltage Gamma Control Parameter
+
+    nvgam-param:
+      type: uint8-array
+      required: true
+      description: Negative Voltage Gamma Control Parameter
+
+    ram-param:
+      type: uint8-array
+      required: true
+      description: RAM Control Parameter
+
+    rgb-param:
+      type: uint8-array
+      required: true
+      description: RGB Interface Control Parameter
diff --git a/dts/bindings/display/solomon,ssd1306fb-common.yaml b/dts/bindings/display/solomon,ssd1306fb-common.yaml
new file mode 100644
index 0000000000..3fef7ab99d
--- /dev/null
+++ b/dts/bindings/display/solomon,ssd1306fb-common.yaml
@@ -0,0 +1,54 @@
+# Copyright (c) 2018, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+include: display-controller.yaml
+
+properties:
+    segment-offset:
+      type: int
+      required: true
+      description: 8-bit column start address for Page Addressing Mode
+
+    page-offset:
+      type: int
+      required: true
+      description: Start address for Page Addressing Mode
+
+    display-offset:
+      type: int
+      required: true
+      description: mapping of the display start line to one of COM0 .. COM63
+
+    multiplex-ratio:
+      type: int
+      required: true
+      description: Multiplex Ratio
+
+    segment-remap:
+      type: boolean
+      required: false
+      description: Last column address is mapped to first segment
+
+    com-invdir:
+      type: boolean
+      required: false
+      description: Scan direction is from last COM output to first COM output
+
+    com-sequential:
+      type: boolean
+      required: false
+      description: Sequential COM pin configuration
+
+    prechargep:
+      type: int
+      required: true
+      description: Duration of the pre-charge period
+
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: RESET pin.
+
+        The RESET pin of SSD1306 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
diff --git a/dts/bindings/display/solomon,ssd1306fb-i2c.yaml b/dts/bindings/display/solomon,ssd1306fb-i2c.yaml
new file mode 100644
index 0000000000..2874f40f70
--- /dev/null
+++ b/dts/bindings/display/solomon,ssd1306fb-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020, Marco Peter
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD1306 128x64 dot-matrix display controller on I2C bus
+
+compatible: "solomon,ssd1306fb"
+
+include: ["solomon,ssd1306fb-common.yaml", "i2c-device.yaml"]
diff --git a/dts/bindings/display/solomon,ssd1306fb-spi.yaml b/dts/bindings/display/solomon,ssd1306fb-spi.yaml
new file mode 100644
index 0000000000..a286887ac7
--- /dev/null
+++ b/dts/bindings/display/solomon,ssd1306fb-spi.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2020, Marco Peter
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD1306 128x64 dot-matrix display controller on SPI bus
+
+compatible: "solomon,ssd1306fb"
+
+include: ["solomon,ssd1306fb-common.yaml", "spi-device.yaml"]
+
+properties:
+    data_cmd-gpios:
+      type: phandle-array
+      required: true
+      description: D/C# pin.
diff --git a/dts/bindings/display/solomon,ssd16xxfb.yaml b/dts/bindings/display/solomon,ssd16xxfb.yaml
new file mode 100644
index 0000000000..66be38c084
--- /dev/null
+++ b/dts/bindings/display/solomon,ssd16xxfb.yaml
@@ -0,0 +1,93 @@
+# Copyright (c) 2018, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD16XX 250x150 EPD display controller
+
+compatible: "solomon,ssd16xxfb"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    pp-height-bits:
+      type: int
+      required: true
+      description: Number of bits used for the height parameters
+
+    pp-width-bits:
+      type: int
+      required: true
+      description: Number of bits used for the width parameters
+
+    gdv:
+      type: uint8-array
+      required: true
+      description: Gate driving voltage values
+
+    sdv:
+      type: uint8-array
+      required: true
+      description: Source driving voltage values
+
+    vcom:
+      type: int
+      required: true
+      description: VCOM voltage
+
+    border-waveform:
+      type: int
+      required: true
+      description: Border waveform
+
+    softstart:
+      type: uint8-array
+      required: false
+      description: Booster soft start values
+
+    orientation-flipped:
+      type: boolean
+      required: false
+      description: Last column address is mapped to first segment
+
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: RESET pin.
+
+        The RESET pin of SSD16XX is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    dc-gpios:
+      type: phandle-array
+      required: true
+      description: DC pin.
+
+        The DC pin of SSD16XX is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    busy-gpios:
+      type: phandle-array
+      required: true
+      description: BUSY pin.
+
+        The BUSY pin of SSD16XX is active high.
+        If connected directly the MCU pin should be configured
+        as active high.
+
+    lut-initial:
+      type: uint8-array
+      required: false
+
+    lut-default:
+      type: uint8-array
+      required: false
+
+    tssv:
+      type: int
+      required: false
+      description: Temperature Sensor Selection Value
+
+        Display controller can have integrated temperature sensor or
+        an external temperature sensor is connected to the controller.
+        The value selects which sensor should be used.
diff --git a/dts/bindings/display/zephyr,dummy-dc.yaml b/dts/bindings/display/zephyr,dummy-dc.yaml
new file mode 100644
index 0000000000..fde144466b
--- /dev/null
+++ b/dts/bindings/display/zephyr,dummy-dc.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Dummy display controller
+
+compatible: "zephyr,dummy-dc"
+
+include: display-controller.yaml
diff --git a/dts/bindings/display/zephyr,sdl-dc.yaml b/dts/bindings/display/zephyr,sdl-dc.yaml
new file mode 100644
index 0000000000..444bcbbe19
--- /dev/null
+++ b/dts/bindings/display/zephyr,sdl-dc.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: SDL based emulated display controller
+
+compatible: "zephyr,sdl-dc"
+
+include: display-controller.yaml
diff --git a/dts/bindings/dma/altr,msgdma.yaml b/dts/bindings/dma/altr,msgdma.yaml
new file mode 100644
index 0000000000..dd7c662de7
--- /dev/null
+++ b/dts/bindings/dma/altr,msgdma.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Altera mSGDMA (Modular Scatter-Gather DMA)
+
+compatible: "altr,msgdma"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#dma-cells":
+      const: 0
diff --git a/dts/bindings/dma/arm,dma-pl330.yaml b/dts/bindings/dma/arm,dma-pl330.yaml
new file mode 100644
index 0000000000..784cb189bc
--- /dev/null
+++ b/dts/bindings/dma/arm,dma-pl330.yaml
@@ -0,0 +1,45 @@
+# Copyright 2020 Broadcom
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PL330 DMA Controller
+
+  A phandle to the DMA controller plus "channel" integer cell specifying
+  channel to be used for data transfer
+
+  Example for pl330 DMA Controller
+     pl330: pl330@48300000 {
+                  compatible = "arm,dma-pl330";
+                  ...
+                  dma-channels = <8>;
+                  #dma-cells = <1>;
+                  label = "PL330";
+            };
+
+  If PCIe EP client uses channel 0 for Tx DMA and channel 1 for Rx DMA
+     pcie0_ep: pcie@4e100000 {
+                  compatible = "brcm,iproc-pcie-ep";
+                  ...
+                  dmas = <&pl330 0>, <&pl330 1>;
+                  dma-names = "txdma", "rxdma";
+                  label = "PCIE_0";
+            };
+compatible: "arm,dma-pl330"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+    microcode:
+      type: array
+      required: true
+      description: microcode's physical memory address
+    label:
+      required: true
+    "#dma-cells":
+      const: 1
+
+# Parameter syntax
+dma-cells:
+  - channel
diff --git a/dts/bindings/dma/atmel,sam-xdmac.yaml b/dts/bindings/dma/atmel,sam-xdmac.yaml
new file mode 100644
index 0000000000..10b8ca0dd3
--- /dev/null
+++ b/dts/bindings/dma/atmel,sam-xdmac.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM XDMAC controller
+
+compatible: "atmel,sam-xdmac"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    "#dma-cells":
+      const: 2
+
+dma-cells:
+  - channel
+  - perid
diff --git a/dts/bindings/dma/atmel,sam0-dmac.yaml b/dts/bindings/dma/atmel,sam0-dmac.yaml
new file mode 100644
index 0000000000..9a39b18e2d
--- /dev/null
+++ b/dts/bindings/dma/atmel,sam0-dmac.yaml
@@ -0,0 +1,39 @@
+description: Atmel SAM0 DMA controller
+
+compatible: "atmel,sam0-dmac"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#dma-cells":
+      const: 2
+
+# #dma-cells : Must be <2>.
+# The 1st cell specifies the DMAC channel to be used for the data transfer.
+#   This channel should be unique between all peripherals that are using the
+#   DMAC instance.
+# The 2nd cell defines the peripheral trigger which is the source of the transfer.
+#   For details on trigger selection and trigger modes, refer to
+#   "Transfer Triggers and Actions".
+#   See the SoC's reference manual for all the supported request sources.
+#
+# Example of devicetree dma channel configuration:
+#
+# &sercom3 {
+#     /* Configure DMA channels for async operation */
+#     dmas = <&dmac 10 7>, <&dmac 11 8>;
+#     dma-names = "rx", "tx";
+# };
+#
+# In above fragment 10 and 11 represents the different channels used to
+# transfer data between peripheral and ram. The numbers 7/8 are, for instance,
+# uart_rx/tx peripheral trigger for sercom3.
+dma-cells:
+  - channel
+  - trigsrc
diff --git a/dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml b/dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml
new file mode 100644
index 0000000000..0287622215
--- /dev/null
+++ b/dts/bindings/dma/brcm,iproc-pax-dma-v1.yaml
@@ -0,0 +1,38 @@
+# Copyright 2020 Broadcom
+# SPDX-License-Identifier: Apache-2.0
+
+description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 1
+
+include: dma-controller.yaml
+
+compatible: brcm,iproc-pax-dma-v1
+
+properties:
+    reg:
+      description: |
+        Register space for the memory mapped PAX DMA controller registers,
+        It includes data mover engine(dme), ring manager, ring manager common
+        registers.
+      required: true
+    label:
+      required: true
+    bd-memory:
+      type: array
+      description: Uncached memory address to populate dma buffer descriptors
+      required: true
+    scr-addr-loc:
+      type: int
+      description: Location where address of the scratch buffer host has populated
+      required: true
+    scr-size-loc:
+      type: int
+      description: Location where size of the scratch buffer host has populated
+      required: true
+    interrupts:
+      type: array
+      description: Ring manager line interrupt number
+      required: false
+    pcie-ep:
+      type: phandle
+      description: Pcie endpoint handle
+      required: true
diff --git a/dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml b/dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml
new file mode 100644
index 0000000000..d83ce03cbe
--- /dev/null
+++ b/dts/bindings/dma/brcm,iproc-pax-dma-v2.yaml
@@ -0,0 +1,38 @@
+# Copyright 2020 Broadcom
+# SPDX-License-Identifier: Apache-2.0
+
+description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 2
+
+include: dma-controller.yaml
+
+compatible: brcm,iproc-pax-dma-v2
+
+properties:
+    reg:
+      description: |
+        Register space for the memory mapped PAX DMA controller registers,
+        It includes data mover engine(dme), ring manager, ring manager common
+        registers.
+      required: true
+    label:
+      required: true
+    bd-memory:
+      type: array
+      description: Uncached memory address to populate dma buffer descriptors
+      required: true
+    scr-addr-loc:
+      type: int
+      description: Location where address of the scratch buffer host has populated
+      required: true
+    scr-size-loc:
+      type: int
+      description: Location where size of the scratch buffer host has populated
+      required: true
+    interrupts:
+      type: array
+      description: Ring manager line interrupt number
+      required: false
+    pcie-ep:
+      type: phandle
+      description: Pcie endpoint handle
+      required: true
diff --git a/dts/bindings/dma/dma-controller.yaml b/dts/bindings/dma/dma-controller.yaml
new file mode 100644
index 0000000000..aa2c948e63
--- /dev/null
+++ b/dts/bindings/dma/dma-controller.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for DMA controllers
+
+include: base.yaml
+
+bus: dma
+
+properties:
+    label:
+      required: true
+
+    "#dma-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a DMA specifier
+
+    dma-channel-mask:
+      type: int
+      required: false
+      description: |
+        Bitmask of available DMA channels in ascending order that are
+        not reserved by firmware and are available to the
+        kernel. i.e. first channel corresponds to LSB.
+
+    dma-channels:
+      type: int
+      required: false
+      description: Number of DMA channels supported by the controller
+
+    dma-requests:
+      type: int
+      required: false
+      description: Number of DMA request signals supported by the controller.
diff --git a/dts/bindings/dma/dmamux-controller.yaml b/dts/bindings/dma/dmamux-controller.yaml
new file mode 100644
index 0000000000..cb8f2a2736
--- /dev/null
+++ b/dts/bindings/dma/dmamux-controller.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2019, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for DMAMUX controllers
+
+include: base.yaml
+
+bus: dmamux
+
+properties:
+    label:
+      required: true
+
+    "#dma-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a DMA specifier (see dma V2)
+
+    dma-channels:
+      type: int
+      required: true
+      description: Number of DMAMUX output request channels supported by the controller
+
+    dma-generators:
+      type: int
+      required: false
+      description: Number of DMAMUX Request generator supported by the controller
+
+    dma-requests:
+      type: int
+      required: true
+      description: |
+        Number of DMAMUX Peripheral Request Line inputs supported by the controller
+        This is not directly the value to program in the DMAREQ_ID of the DMAMUX_CxCR
diff --git a/dts/bindings/dma/nxp,lpc-dma.yaml b/dts/bindings/dma/nxp,lpc-dma.yaml
new file mode 100644
index 0000000000..3e1b7c3571
--- /dev/null
+++ b/dts/bindings/dma/nxp,lpc-dma.yaml
@@ -0,0 +1,29 @@
+# Copyright (c) 2020, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC DMA controller
+
+compatible: "nxp,lpc-dma"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    dma-channels:
+      required: true
+
+    "#dma-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a DMA specifier
+
+#- #dma-cells : Must be <1>.
+# channel: the dma channel, each channel supports one DMA request line
+
+dma-cells:
+  - channel
diff --git a/dts/bindings/dma/nxp,mcux-edma.yaml b/dts/bindings/dma/nxp,mcux-edma.yaml
new file mode 100644
index 0000000000..a95afeff46
--- /dev/null
+++ b/dts/bindings/dma/nxp,mcux-edma.yaml
@@ -0,0 +1,54 @@
+# Copyright (c) 2020, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUX EDMA controller
+
+compatible: "nxp,mcux-edma"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    dma-channels:
+      required: true
+
+    dma-requests:
+      required: true
+
+    nxp,mem2mem:
+      type: boolean
+      description: If the DMA controller supports memory to memory transfer
+
+    nxp,a_on:
+      type: boolean
+      description: If the DMA controller supports always on
+
+    "#dma-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a DMAMUX specifier
+
+# Parameter syntax of NXP follows the dmamux client dts syntax
+# in the Linux kernel declared in
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/tree/Bindings/dma/fsl-edma.txt
+#
+#- #dma-cells : Must be <2>.
+#  The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
+#    Specific request source can only be multiplexed by specific channels
+#    group called DMAMUX.
+#  The 2nd cell specifies the request source(slot) ID.
+#    See the SoC's reference manual for all the supported request sources.
+# * DMA clients
+# DMA client drivers that uses the DMA function must use the format described
+# in the dma.txt file, using a two-cell specifier for each channel: the 1st
+# specifies the channel group(DMAMUX) in which this request can be multiplexed,
+# and the 2nd specifies the request source.
+
+dma-cells:
+  - mux
+  - source
diff --git a/dts/bindings/dma/snps,designware-dma.yaml b/dts/bindings/dma/snps,designware-dma.yaml
new file mode 100644
index 0000000000..d7c9132f1e
--- /dev/null
+++ b/dts/bindings/dma/snps,designware-dma.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys Designware DMA Controller node
+
+compatible: "snps,designware-dma"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#dma-cells":
+      const: 1
+
+dma-cells:
+  - channel
diff --git a/dts/bindings/dma/st,stm32-dma-v1.yaml b/dts/bindings/dma/st,stm32-dma-v1.yaml
new file mode 100644
index 0000000000..9fb5cb364e
--- /dev/null
+++ b/dts/bindings/dma/st,stm32-dma-v1.yaml
@@ -0,0 +1,90 @@
+# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 DMA controller (V1)
+
+  It is present on stm32 devices like stm32F4 or stm32F2.
+  This DMA controller includes FIFO control registers.
+  DMA clients connected to the STM32 DMA controller must use the format
+  described in the dma.txt file, using a four-cell specifier for each
+  channel: a phandle to the DMA controller plus the following four integer cells:
+    1. channel: the dma stream from 0 to <dma-requests>
+    2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
+    this value is 0 for Memory-to-memory transfers
+    or a value between <1> .. <dma-generators> (not supported yet)
+    or a value beweeen <dma-generators>+1  ..  <dma-generators>+<dma-requests>
+    3. channel-config: A 32bit mask specifying the DMA channel configuration
+    which is device dependent:
+        -bit 6-7 : Direction  (see dma.h)
+               0x0: MEM to MEM
+               0x1: MEM to PERIPH
+               0x2: PERIPH to MEM
+               0x3: reserved for PERIPH to PERIPH
+        -bit 9 : Peripheral Increment Address
+               0x0: no address increment between transfers
+               0x1: increment address between transfers
+        -bit 10 : Memory Increment Address
+               0x0: no address increment between transfers
+               0x1: increment address between transfers
+        -bit 11-12 : Peripheral data size
+               0x0: Byte (8 bits)
+               0x1: Half-word (16 bits)
+               0x2: Word (32 bits)
+               0x3: reserved
+        -bit 13-14 : Memory data size
+               0x0: Byte (8 bits)
+               0x1: Half-word (16 bits)
+               0x2: Word (32 bits)
+               0x3: reserved
+        -bit 15: Peripheral Increment Offset Size
+               0x0: offset size is linked to the peripheral bus width
+               0x1: offset size is fixed to 4 (32-bit alignment)
+        -bit 16-17 : Priority level
+               0x0: low
+               0x1: medium
+               0x2: high
+               0x3: very high
+    4. features: A 32bit bitfield value specifying DMA features
+        -bit 0-1: DMA FIFO threshold selection
+               0x0: 1/4 full FIFO
+               0x1: 1/2 full FIFO
+               0x2: 3/4 full FIFO
+               0x3: full FIFO
+
+    examples for stm32f411
+     dma2: dma-controller@40020400 {
+         compatible = "st,stm32-dma-v1";
+         ...
+         st,mem2mem;
+         dma-requests = <7>;
+         status = "disabled";
+         label = "DMA_2";
+        };
+
+  For the client part, example for stm32f411 on DMA2 instance
+    Tx using stream 5 on channel 3 (stream 2 on channel 2 is also possible)
+    Rx using stream 2 on channel 3 (stream 0 on channel 3 is also possible)
+    spi1 {
+     dmas = <&dma2 5 3 0x28440 0x03>,
+           <&dma2 2 3 0x28480 0x03>;
+     dma-names = "tx", "rx";
+     };
+
+compatible: "st,stm32-dma-v1"
+
+include: st,stm32-dma.yaml
+
+properties:
+    "#dma-cells":
+      const: 4
+
+# Parameter syntax of stm32 follows the dma client dts syntax
+# in the Linux kernel declared in
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
+
+dma-cells:
+  - channel
+  - slot
+  - channel-config
+  - features
diff --git a/dts/bindings/dma/st,stm32-dma-v2.yaml b/dts/bindings/dma/st,stm32-dma-v2.yaml
new file mode 100644
index 0000000000..c2bc7cc6b3
--- /dev/null
+++ b/dts/bindings/dma/st,stm32-dma-v2.yaml
@@ -0,0 +1,83 @@
+# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 DMA controller (V2)
+
+  It is present on stm32 devices like stm32L4 or stm32WB.
+  This DMA controller includes several channels with different requests.
+  DMA clients connected to the STM32 DMA controller must use the format
+  described in the dma.txt file, using a four-cell specifier for each
+  capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
+  DMA clients connected to the STM32 DMA controller must use the format
+  described in the dma.txt file, using a 3-cell specifier for each
+  channel: a phandle to the DMA controller plus the following four integer cells:
+    1. channel: the dma stream from 1 to <dma-requests>
+    2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
+    this value is 0 for Memory-to-memory transfers
+    or a value between <1> .. <dma-generators> (not supported yet)
+    or a value beweeen <dma-generators>+1  ..  <dma-generators>+<dma-requests>
+    3. channel-config: A 32bit mask specifying the DMA channel configuration
+    which is device dependent:
+        -bit 6-7 : Direction  (see dma.h)
+               0x0: MEM to MEM
+               0x1: MEM to PERIPH
+               0x2: PERIPH to MEM
+               0x3: reserved for PERIPH to PERIPH
+        -bit 9 : Peripheral Increment Address
+               0x0: no address increment between transfers
+               0x1: increment address between transfers
+        -bit 10 : Memory Increment Address
+               0x0: no address increment between transfers
+               0x1: increment address between transfers
+        -bit 11-12 : Peripheral data size
+               0x0: Byte (8 bits)
+               0x1: Half-word (16 bits)
+               0x2: Word (32 bits)
+               0x3: reserved
+        -bit 13-14 : Memory data size
+               0x0: Byte (8 bits)
+               0x1: Half-word (16 bits)
+               0x2: Word (32 bits)
+               0x3: reserved
+        -bit 15: Reserved
+        -bit 16-17 : Priority level
+               0x0: low
+               0x1: medium
+               0x2: high
+               0x3: very high
+  Example of dma node for stm32wb55x
+     dma2: dma-controller@40020400 {
+         compatible = "st,stm32-dma-v2";
+         ...
+         dma-requests = <7>;
+         status = "disabled";
+         label = "DMA_2";
+        };
+
+  For the client part, example for stm32l476 on DMA1 instance
+    Tx using channel 3 with request 1
+    Rx using channel 2 with request 1
+    spi1 {
+     compatible = "st,stm32-spi";
+     dmas = <&dma1 3 1 0x20440>,
+            <&dma1 2 1 0x20480>;
+     dma-names = "tx", "rx";
+    };
+
+compatible: "st,stm32-dma-v2"
+
+include: st,stm32-dma.yaml
+
+properties:
+    "#dma-cells":
+      const: 3
+
+# Parameter syntax of stm32 follows the dma client dts syntax
+# in the Linux kernel declared in
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
+
+dma-cells:
+  - channel
+  - slot
+  - channel-config
diff --git a/dts/bindings/dma/st,stm32-dma-v2bis.yaml b/dts/bindings/dma/st,stm32-dma-v2bis.yaml
new file mode 100644
index 0000000000..0cf3a1c0b5
--- /dev/null
+++ b/dts/bindings/dma/st,stm32-dma-v2bis.yaml
@@ -0,0 +1,77 @@
+# Copyright (c) 2021, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
+
+  This DMA controller includes several channels with different requests.
+  All the requests ar ORed before entering the DMA, so that only one request
+  must be enabled at a time.
+  DMA clients connected to the STM32 DMA controller must use the format
+  described in the dma.txt file, using a 2-cell specifier for each
+  channel: a phandle to the DMA controller plus the following four integer cells:
+    1. channel: the dma stream from 1 to <dma-requests>
+    2. channel-config: A 32bit mask specifying the DMA channel configuration
+    which is device dependent:
+        -bit 6-7 : Direction  (see dma.h)
+               0x0: MEM to MEM
+               0x1: MEM to PERIPH
+               0x2: PERIPH to MEM
+               0x3: reserved for PERIPH to PERIPH
+        -bit 9 : Peripheral Increment Address
+               0x0: no address increment between transfers
+               0x1: increment address between transfers
+        -bit 10 : Memory Increment Address
+               0x0: no address increment between transfers
+               0x1: increment address between transfers
+        -bit 11-12 : Peripheral data size
+               0x0: Byte (8 bits)
+               0x1: Half-word (16 bits)
+               0x2: Word (32 bits)
+               0x3: reserved
+        -bit 13-14 : Memory data size
+               0x0: Byte (8 bits)
+               0x1: Half-word (16 bits)
+               0x2: Word (32 bits)
+               0x3: reserved
+        -bit 15: Reserved
+        -bit 16-17 : Priority level
+               0x0: low
+               0x1: medium
+               0x2: high
+               0x3: very high
+  Example of dma node for stm32f103
+     dma1: dma-controller@40020400 {
+         compatible = "st,stm32-dma-v2bis";
+         ...
+         dma-requests = <7>;
+         status = "disabled";
+         label = "DMA_1";
+        };
+
+  For the client part, example for stm32f103 on DMA1 instance
+    Tx using channel 3
+    Rx using channel 2
+    spi1 {
+     compatible = "st,stm32-spi";
+     dmas = <&dma1 3 0x20440>,
+            <&dma1 2 0x20480>;
+     dma-names = "tx", "rx";
+    };
+
+compatible: "st,stm32-dma-v2bis"
+
+include:
+  - name: st,stm32-dma.yaml
+
+properties:
+    "#dma-cells":
+      const: 2
+
+# Parameter syntax of stm32 follows the dma client dts syntax
+# in the Linux kernel declared in
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
+
+dma-cells:
+  - channel
+  - channel-config
diff --git a/dts/bindings/dma/st,stm32-dma.yaml b/dts/bindings/dma/st,stm32-dma.yaml
new file mode 100644
index 0000000000..10db20e87b
--- /dev/null
+++ b/dts/bindings/dma/st,stm32-dma.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 DMA controller
+
+  The STM32 DMA is a general-purpose direct memory access controller
+  capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
+  Each stm32 soc with a DMA is of a special version type, which could be
+  V1 like stm32F4 or stm32F2 socs, they include FIFO control registers
+  or V2 like stm32L4 soc or stm322WB, some also have DMAMUX controller
+  or V2bis like stm32F1 or stm32L1, where requests are multiplexed
+
+compatible: "st,stm32-dma"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    st,mem2mem:
+      type: boolean
+      required: false
+      description: If the DMA controller V1 supports memory to memory transfer
+
+    dma-offset:
+      type: int
+      required: false
+      description: |
+        offset in the table of channels when mapping to a DMAMUX
+        for 1st dma instance, offset is 0,
+        for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
+        for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
+        plus the nb of dma channels of the 1st dma instance, etc.
diff --git a/dts/bindings/dma/st,stm32-dmamux.yaml b/dts/bindings/dma/st,stm32-dmamux.yaml
new file mode 100644
index 0000000000..bfe8eb87ce
--- /dev/null
+++ b/dts/bindings/dma/st,stm32-dmamux.yaml
@@ -0,0 +1,83 @@
+# Copyright (c) 2019, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 DMAMUX controller
+
+  The STM32 DMAMUX is a direct memory access multiplexer
+  capable of supporting independent DMA channels.
+  DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
+  for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
+    1. channel: the mux channel from 0 to <dma-channels> - 1
+    2. slot: the request line Multiplexer ID
+    3. channel-config: A 32bit mask specifying the DMA channel configuration
+    which is device dependent:
+        -bit 6-7 : Direction  (see dma.h)
+               0x0: MEM to MEM
+               0x1: MEM to PERIPH
+               0x2: PERIPH to MEM
+               0x3: reserved for PERIPH to PERIPH
+        -bit 9 : Peripheral Increment Address
+               0x0: no address increment between transfers
+               0x1: increment address between transfers
+        -bit 10 : Memory Increment Address
+               0x0: no address increment between transfers
+               0x1: increment address between transfers
+        -bit 11-12 : Peripheral data size
+               0x0: Byte (8 bits)
+               0x1: Half-word (16 bits)
+               0x2: Word (32 bits)
+               0x3: reserved
+        -bit 13-14 : Memory data size
+               0x0: Byte (8 bits)
+               0x1: Half-word (16 bits)
+               0x2: Word (32 bits)
+               0x3: reserved
+        -bit 15: Peripheral Increment Offset Size not USED for DMA V2
+               0x0: offset size is linked to the peripheral bus width
+               0x1: offset size is fixed to 4 (32-bit alignment)
+        -bit 16-17 : Priority level
+               0x0: low
+               0x1: medium
+               0x2: high
+               0x3: very high
+   exemple for stm32wb55x
+     dmamux1: dmamux@40020800 {
+         compatible = "st,stm32-dmamux";
+         ...
+         dma-channels = <14>;
+         dma-generators = <4>;
+         dma-requests= <36>;
+         status = "disabled";
+         label = "DMAMUX_1";
+        };
+    for client SPI of stm32wb55x
+     spi1: spi@40013000 {
+         compatible = "st,stm32-spi";
+         dmas = <&dmamux1 11 7 0x20440
+                  &dmamux1 1 6 0x20480>;
+         dma-names = "tx", "rx";
+        };
+
+compatible: "st,stm32-dmamux"
+
+include: dmamux-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#dma-cells":
+      const: 3
+
+# Parameter syntax of stm32 follows the dma client dts syntax
+# in the Linux kernel declared in
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dmamux.yaml
+
+dma-cells:
+  - channel
+  - slot
+  - channel-config
diff --git a/dts/bindings/dsa/microchip,ksz8794.yaml b/dts/bindings/dsa/microchip,ksz8794.yaml
new file mode 100644
index 0000000000..fced9b37cb
--- /dev/null
+++ b/dts/bindings/dsa/microchip,ksz8794.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2020 DENX Software Engineering GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    KSZ8794 ethernet switch with SPI interface
+
+compatible: "microchip,ksz8794"
+
+include: [microchip_dsa.yaml]
+properties:
+    workaround:
+        type: int
+        required: false
+        description: |
+          Define the applied workaround for the switch used for
+          short connections. Use bitmask to select the workaround or more
+          0x01: Short Cable Problems with the KSZ8795 Family
+          0x02: 1) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family
+          0x04: 2) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family
+    mii-lowspeed-drivestrength:
+        type: int
+        required: false
+        description: |
+          Define the Low-Speed Interface Drive Strength for MII and RMMI
+          Supported values 2,4,8,12,16,20,24,28mA
+          see Register 163 (0xA3): Global Control 20 for more details
+        enum:
+          - 2
+          - 4
+          - 8
+          - 12
+          - 16
+          - 20
+          - 24
+          - 28
diff --git a/dts/bindings/dsa/microchip,ksz8863.yaml b/dts/bindings/dsa/microchip,ksz8863.yaml
new file mode 100644
index 0000000000..3411b72c7f
--- /dev/null
+++ b/dts/bindings/dsa/microchip,ksz8863.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2021 IP-Logix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    KSZ8863 ethernet switch
+
+compatible: "microchip,ksz8863"
+
+include: [microchip_dsa.yaml]
diff --git a/dts/bindings/dsa/microchip_dsa.yaml b/dts/bindings/dsa/microchip_dsa.yaml
new file mode 100644
index 0000000000..bfb911a05d
--- /dev/null
+++ b/dts/bindings/dsa/microchip_dsa.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2020 DENX Software Engineering GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    DSA Device
+
+include: [spi-device.yaml]
+properties:
+    dsa-master-port:
+       type: phandle
+       required: false
+       description: Phandle to master port.
+    dsa-slave-ports:
+       type: int
+       required: false
+       description: Number of slave ports on the switch
+    spi-cpha:
+       type: boolean
+       required: false
+       description: |
+          Set to indicate phase starts with asserted half-phase (CPHA=1).
+          For this driver using this property requires also using cpol.
+    spi-cpol:
+        type: boolean
+        required: false
+        description: |
+          Set to indicate clock leading edge is falling (CPOL=1).
+          For this driver using this property requires also using cpha.
+    reset-gpios:
+        type: phandle-array
+        required: false
+        description: |
+          The pin is asserted for 10ms during boot to reset the KSZ8794.
+
+child-binding:
+    description: Properties of slave port
+    properties:
+        label:
+            type: string
+            required: true
+        local-mac-address:
+            type: uint8-array
+            required: false
+            description: |
+              Specifies the MAC address that was assigned to the port
diff --git a/dts/bindings/ec_host_cmd_perhip/zephyr,sim-ec-host-cmd-periph.yaml b/dts/bindings/ec_host_cmd_perhip/zephyr,sim-ec-host-cmd-periph.yaml
new file mode 100644
index 0000000000..a6b12b8d40
--- /dev/null
+++ b/dts/bindings/ec_host_cmd_perhip/zephyr,sim-ec-host-cmd-periph.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Simulated Host Command Peripheral
+
+compatible: "zephyr,sim-ec-host-cmd-periph"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/edac/intel,ibecc.yaml b/dts/bindings/edac/intel,ibecc.yaml
new file mode 100644
index 0000000000..718ab6b2ee
--- /dev/null
+++ b/dts/bindings/edac/intel,ibecc.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2021, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: EDAC In-Band Error Correcting Code (IBECC)
+
+compatible: "intel,ibecc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: false
diff --git a/dts/bindings/espi/espi-controller.yaml b/dts/bindings/espi/espi-controller.yaml
new file mode 100644
index 0000000000..ad16de4d49
--- /dev/null
+++ b/dts/bindings/espi/espi-controller.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for ESPI devices
+
+include: base.yaml
+
+bus: espi
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/espi/microchip,xec-espi-host-dev.yaml b/dts/bindings/espi/microchip,xec-espi-host-dev.yaml
new file mode 100644
index 0000000000..db2c1385f1
--- /dev/null
+++ b/dts/bindings/espi/microchip,xec-espi-host-dev.yaml
@@ -0,0 +1,95 @@
+# Copyright (c) 2021, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC eSPI Host devices
+
+compatible: "microchip,xec-espi-host-dev"
+
+include: [base.yaml]
+
+on-bus: espi
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    interrupt-names:
+      required: false
+
+    ldn:
+      type: int
+      required: true
+      description: logical device number
+
+    girqs:
+      type: array
+      required: false
+      description: array of GIRQ and bit positions
+
+    pcrs:
+      type: array
+      required: false
+      description: PCR sleep register index and bit position
+
+# optional properties application to different host facing devices
+    host-io:
+      type: int
+      required: false
+      description: |
+        Logical device Host I/O (x86) base. Refer to SoC documentation for the
+        number of I/O decoders implemented by a device (1 or 2) and the fixed
+        I/O masks.
+
+    host-io-addr-mask:
+      type: int
+      required: false
+      description: |
+        Host I/O address mask. This value is fixed for all HW and is only
+        used by Port80 BIOS debug alias device to specify the byte lane the
+        alias address is mapped to in the 80h to 83h I/O range.
+
+    host-mem:
+      type: int
+      required: false
+      description: |
+        Logical device Host memory (x86) base address. Refer to SoC
+        documentation for which logical devices implement a memory decoder
+        and the fixed memory address masking.
+
+    emi-mems:
+      type: array
+      required: false
+      description: |
+        Each EMI host device supports Host access to two SoC data memory
+        regions. Each region requires three configuration parameters:
+        Base address in the SoC data memory, read limit, and write limit.
+        If bits[14:2] of the address written by the Host to the EC address
+        register is less than the limit value the access is allowed. Bit[15]
+        of the EC address selects which of the two memory regions is accessed.
+
+    "emi-mem-cells":
+      type: int
+      const: 3
+
+    "#girq-cells":
+      type: int
+      const: 1
+
+    "#pcr-cells":
+      type: int
+      const: 2
+
+emi-mem-cells:
+    - base
+    - rdlimit
+    - wrlimit
+
+girq-cells:
+    - girqinfo
+
+pcr-cells:
+    - reg_idx
+    - bitpos
diff --git a/dts/bindings/espi/microchip,xec-espi-saf.yaml b/dts/bindings/espi/microchip,xec-espi-saf.yaml
new file mode 100644
index 0000000000..392413bd61
--- /dev/null
+++ b/dts/bindings/espi/microchip,xec-espi-saf.yaml
@@ -0,0 +1,44 @@
+# Copyright (c) 2019 Intel Corporation
+# Copyright (c) 2020 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip ESPI SAF controller
+
+compatible: "microchip,xec-espi-saf"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    io_girq:
+      type: int
+      description: soc group irq index for eSPI I/O
+      required: false
+
+    poll_timeout:
+      type: int
+      description: poll flash busy timeout in 32KHz periods
+      required: false
+
+    poll_interval:
+      type: int
+      description: interval between flash busy poll in 20 ns units
+      required: false
+
+    consec_rd_timeout:
+      type: int
+      description: timeout after last read to resume supended operations in 20 ns units
+      required: false
+
+    sus_chk_delay:
+      type: int
+      description: hold off poll after suspend in 20 ns units
+      required: false
+
+    sus_rsm_interval:
+      type: int
+      description: force suspended erase or program to resume in 32KHz periods
+      required: false
diff --git a/dts/bindings/espi/microchip,xec-espi-v2.yaml b/dts/bindings/espi/microchip,xec-espi-v2.yaml
new file mode 100644
index 0000000000..563dc93a52
--- /dev/null
+++ b/dts/bindings/espi/microchip,xec-espi-v2.yaml
@@ -0,0 +1,44 @@
+# Copyright (c) 2019 Intel Corporation
+# Copyright (c) 2021 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip ESPI V2 controller
+
+compatible: "microchip,xec-espi-v2"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    reg-names:
+      required: true
+      description: Name of each register space
+
+    girqs:
+      type: array
+      required: true
+      description: |
+        Array of encoded interrupt information
+
+    pcrs:
+      type: array
+      required: true
+      description: eSPI PCR register index and bit position
+
+    "#girq-cells":
+      type: int
+      const: 1
+
+    "#pcr-cells":
+      type: int
+      const: 2
+
+girq-cells:
+    - girqinfo
+
+pcr-cells:
+    - regidx
+    - bitpos
diff --git a/dts/bindings/espi/microchip,xec-espi-vw-routing.yaml b/dts/bindings/espi/microchip,xec-espi-vw-routing.yaml
new file mode 100644
index 0000000000..e743994d8d
--- /dev/null
+++ b/dts/bindings/espi/microchip,xec-espi-vw-routing.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2021 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC eSPI Virtual Wire routing
+
+compatible: "microchip,xec-espi-vw-routing"
+
+child-binding:
+    description: |
+      Child node containing the routing of an eSPI virtual wire to the SoC
+      VW registers and ECIA GIRQ registers.
+    properties:
+       vw-reg:
+          type: array
+          required: true
+          description: vw signal's register index and vw bitmask.
+
+       vw-girq:
+        type: array
+        required: false
+        description: |
+            Routing of MSVW source to aggregated GIRQs
+
+            Example: OOB_RST_WARN is source 2 of MSVW01 routed to GIRQ24 b[5]
+               vw-girq = <24 5>;
diff --git a/dts/bindings/espi/microchip,xec-espi.yaml b/dts/bindings/espi/microchip,xec-espi.yaml
new file mode 100644
index 0000000000..0c0700975e
--- /dev/null
+++ b/dts/bindings/espi/microchip,xec-espi.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip ESPI controller
+
+compatible: "microchip,xec-espi"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    io_girq:
+      type: int
+      description: soc group irq index for eSPI I/O
+      required: true
+
+    vw_girqs:
+      type: array
+      description: soc group irq indexes for eSPI virtual wires channel
+      required: true
+
+    pc_girq:
+      type: int
+      description: soc group irq index for eSPI peripheral channel
+      required: true
diff --git a/dts/bindings/espi/nuvoton,npcx-espi-vw-conf.yaml b/dts/bindings/espi/nuvoton,npcx-espi-vw-conf.yaml
new file mode 100644
index 0000000000..ec21973dd1
--- /dev/null
+++ b/dts/bindings/espi/nuvoton,npcx-espi-vw-conf.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton NPCX eSPI Virtual Wire (VW) mapping child node
+
+compatible: "nuvoton,npcx-espi-vw-conf"
+
+child-binding:
+    description: Child node to to present the mapping between VW signal, its core register and input source of MIWU
+    properties:
+       vw-reg:
+          type: array
+          required: true
+          description: vw signal's register index and vw bitmask.
+
+       vw-wui:
+        type: phandle
+        description: |
+            Mapping table between Wake-Up Input (WUI) and vw input signal.
+
+            For example the WUI mapping on NPCX7 for VW_SLP5 would be
+               vw-wui = <&wui_vw_slp_s5>;
diff --git a/dts/bindings/espi/nuvoton,npcx-espi.yaml b/dts/bindings/espi/nuvoton,npcx-espi.yaml
new file mode 100644
index 0000000000..1334912b0e
--- /dev/null
+++ b/dts/bindings/espi/nuvoton,npcx-espi.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-eSPI node
+
+compatible: "nuvoton,npcx-espi"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    clocks:
+        required: true
+        description: configurations of device source clock controller
+
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of pinmux controllers
+
+    espi-rst-wui:
+        type: phandle
+        required: true
+        description: |
+            Mapping table between Wake-Up Input (WUI) and ESPI_RST signal.
+
+            For example the WUI mapping on NPCX7 would be
+               espi-rst-wui = <&wui_cr_sin1>;
diff --git a/dts/bindings/espi/nuvoton,npcx-host-sub.yaml b/dts/bindings/espi/nuvoton,npcx-host-sub.yaml
new file mode 100644
index 0000000000..c75bd0c44c
--- /dev/null
+++ b/dts/bindings/espi/nuvoton,npcx-host-sub.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-Host Sub-Modules node
+
+compatible: "nuvoton,npcx-host-sub"
+
+include: [base.yaml]
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    clocks:
+        required: true
+        description: configurations of device source clock controller
+
+    host-acc-wui:
+        type: phandle
+        required: true
+        description: |
+            Mapping table between Wake-Up Input (WUI) and any legacy host
+            access transactions.
+
+            For example the WUI mapping on NPCX7 would be
+               host-acc-wui = <&wui_host_acc>;
diff --git a/dts/bindings/espi/nuvoton,npcx-host-uart.yaml b/dts/bindings/espi/nuvoton,npcx-host-uart.yaml
new file mode 100644
index 0000000000..c3413ad6f9
--- /dev/null
+++ b/dts/bindings/espi/nuvoton,npcx-host-uart.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-Host UART IO node
+
+compatible: "nuvoton,npcx-host-uart"
+
+include: [base.yaml]
+
+properties:
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of host uart pinmux controllers
diff --git a/dts/bindings/espi/zephyr,espi-emul-controller.yaml b/dts/bindings/espi/zephyr,espi-emul-controller.yaml
new file mode 100644
index 0000000000..cc6eb08282
--- /dev/null
+++ b/dts/bindings/espi/zephyr,espi-emul-controller.yaml
@@ -0,0 +1,12 @@
+# Copyright 2020 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr eSPI Emulation controller
+
+compatible: "zephyr,espi-emul-controller"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/ethernet/atmel,gmac-common.yaml b/dts/bindings/ethernet/atmel,gmac-common.yaml
new file mode 100644
index 0000000000..70a8b3559f
--- /dev/null
+++ b/dts/bindings/ethernet/atmel,gmac-common.yaml
@@ -0,0 +1,73 @@
+# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+# Copyright (c) 2020-2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+include: ethernet.yaml
+
+properties:
+    reg:
+      required: true
+
+    num-queues:
+      type: int
+      required: true
+      description: |
+        Number of hardware TX and RX queues.
+
+    max-frame-size:
+      type: int
+      default: 1518
+      description: |
+        Maximum ethernet frame size.  The current ethernet frame sizes
+        supported by hardware are 1518, 1536 and 10240 (jumbo frames).  This
+        means that normally gmac will reject any frame above max-frame-size
+        value.  The default value is 1518, which represents an usual
+        IEEE 802.3 ethernet frame:
+
+          Ethernet Frame [ 14 MAC HEADER | 1500 MTU | 4 FCS ] = 1518 bytes
+
+        When using value 1536 it is possible extend ethernet MAC HEADER up
+        to 32 bytes.  The hardware have support to jumbo frames and it can be
+        enabled by selecting the value 10240.
+
+    max-speed:
+      type: int
+      default: 100
+      description: |
+        This specifies maximum speed in Mbit/s supported by the device.  The
+        gmac driver supports 10Mbit/s and 100Mbit/s.  Using 100, as default
+        value, enables driver to configure 10 and 100Mbit/s speeds.
+
+    phy-connection-type:
+      type: string
+      enum:
+        - "rmii"
+        - "mii"
+      default: "rmii"
+      description: |
+        Phy connection type define the physical interface connection between
+        PHY and MAC.  The default value uses gmac register reset value, which
+        represents Reduced Media-Independent Interface (RMII) mode.
+
+        This property must be used with pinctrl-0.
+
+    pinctrl-0:
+      type: phandles
+      required: false
+      description: |
+        PIO pin configuration for the various GMAC signals that include GTXCK,
+        GTXEN, GTX[3..0], GTXER, GRXCK, GRXDV, GRX[3..0], GRXER, GCRS, GCOL,
+        GMDC, and GMDIO.  Which signals are used vary based on if the PHY
+        connection is MII or RMII (see datasheet for more details).  We expect
+        that the phandles will reference pinctrl nodes.  These nodes will have
+        a nodelabel that matches the Atmel SoC HAL defines and be of the form
+        p<port><pin><periph>_<inst>_<signal>.
+
+        For example the GMAC on SAME7x would be for RMII
+          pinctrl-0 = <&pd0a_gmac_gtxck &pd1a_gmac_gtxen
+                       &pd2a_gmac_gtx0 &pd3a_gmac_gtx1
+                       &pd4a_gmac_grxdv &pd5a_gmac_grx0
+                       &pd6a_gmac_grx1 &pd7a_gmac_grxer
+                       &pd8a_gmac_gmdc &pd9a_gmac_gmdio>;
+
+        This property must be used with phy-connection-type.
diff --git a/dts/bindings/ethernet/atmel,sam-gmac.yaml b/dts/bindings/ethernet/atmel,sam-gmac.yaml
new file mode 100644
index 0000000000..598a99107a
--- /dev/null
+++ b/dts/bindings/ethernet/atmel,sam-gmac.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM-family GMAC Ethernet
+
+compatible: "atmel,sam-gmac"
+
+include: atmel,gmac-common.yaml
+
+properties:
+    peripheral-id:
+      type: int
+      required: true
+      description: |
+        The peripheral identifier is required for Atmel SAMs MCUs to indicate
+        which is the clock line associated with a specific peripheral.  This
+        clock line is defined at Power Management Controller (PMC) and it
+        enables the peripheral.
diff --git a/dts/bindings/ethernet/atmel,sam0-gmac.yaml b/dts/bindings/ethernet/atmel,sam0-gmac.yaml
new file mode 100644
index 0000000000..9c2ed91d75
--- /dev/null
+++ b/dts/bindings/ethernet/atmel,sam0-gmac.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0-family GMAC Ethernet
+
+compatible: "atmel,sam0-gmac"
+
+include: atmel,gmac-common.yaml
diff --git a/dts/bindings/ethernet/ethernet,fixed-link.yaml b/dts/bindings/ethernet/ethernet,fixed-link.yaml
new file mode 100644
index 0000000000..363309bba8
--- /dev/null
+++ b/dts/bindings/ethernet/ethernet,fixed-link.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020, DENX Software Engineering GmbH
+#		      Lukasz Majewski <lukma@denx.de>
+# SPDX-License-Identifier: Apache-2.0
+
+child-binding:
+    description: Fixed link ethernet node
+    properties:
+       speed:
+          type: int
+          required: true
+          description: The speed of fixed link
+          enum:
+            - 100
+            - 10
+       full-duplex:
+          type: boolean
+          required: false
+          description: The fixed link operates in full duplex mode
diff --git a/dts/bindings/ethernet/ethernet-phy.yaml b/dts/bindings/ethernet/ethernet-phy.yaml
new file mode 100644
index 0000000000..5ba01e7b06
--- /dev/null
+++ b/dts/bindings/ethernet/ethernet-phy.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2021 IP-Logix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for MIIPHY devices
+
+description: Generic MII PHY
+
+compatible: "ethernet-phy"
+
+include: phy.yaml
+
+properties:
+    address:
+      type: int
+      required: true
+      description: PHY address
+    mdio:
+      type: phandle
+      required: true
+      description: MDIO driver node
+    no-reset:
+      type: boolean
+      required: false
+      description: Do not reset the PHY during initialization
+    fixed-link:
+      type: string
+      required: false
+      description: This link is fixed and does not require PHY configuration
+      enum:
+        - "10BASE-T Half-Duplex"
+        - "10BASE-T Full-Duplex"
+        - "100BASE-T Half-Duplex"
+        - "100BASE-T Full-Duplex"
diff --git a/dts/bindings/ethernet/ethernet.yaml b/dts/bindings/ethernet/ethernet.yaml
new file mode 100644
index 0000000000..ce5c957f96
--- /dev/null
+++ b/dts/bindings/ethernet/ethernet.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for Ethernet devices
+
+include: base.yaml
+
+properties:
+    local-mac-address:
+      type: uint8-array
+      required: false
+      description: Specifies the MAC address that was assigned to the network device
+    label:
+      required: true
+    zephyr,random-mac-address:
+      type: boolean
+      required: false
+      description: |
+        Use a random MAC address generated when the driver is initialized.
+        Note that using this choice and rebooting a board may leave stale
+        MAC address in peers' ARP caches and lead to issues and delays in
+        communication.  (Use "ip neigh flush all" on Linux peers to clear
+        ARP cache.)
+
+        It is driver specific how the OUI octets are handled.
+
+        If set we ignore any setting of the local-mac-address property.
diff --git a/dts/bindings/ethernet/intel,e1000.yaml b/dts/bindings/ethernet/intel,e1000.yaml
new file mode 100644
index 0000000000..d2f7dacce5
--- /dev/null
+++ b/dts/bindings/ethernet/intel,e1000.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Intel Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel E1000 Ethernet controller
+
+compatible: "intel,e1000"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/ethernet/litex,eth0.yaml b/dts/bindings/ethernet/litex,eth0.yaml
new file mode 100644
index 0000000000..866b40af81
--- /dev/null
+++ b/dts/bindings/ethernet/litex,eth0.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX Ethernet
+
+compatible: "litex,eth0"
+
+include: ethernet.yaml
+
+properties:
+    reg:
+        required: true
+
+    interrupts:
+        required: true
diff --git a/dts/bindings/ethernet/microchip,enc28j60.yaml b/dts/bindings/ethernet/microchip,enc28j60.yaml
new file mode 100644
index 0000000000..9e500e4b7d
--- /dev/null
+++ b/dts/bindings/ethernet/microchip,enc28j60.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: ENC28J60 standalone 10BASE-T Ethernet controller with SPI interface
+
+compatible: "microchip,enc28j60"
+
+include: [spi-device.yaml, ethernet.yaml]
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: true
+      description: Interrupt pin.
+
+        The interrupt pin of ENC28J60 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
diff --git a/dts/bindings/ethernet/microchip,enc424j600.yaml b/dts/bindings/ethernet/microchip,enc424j600.yaml
new file mode 100644
index 0000000000..db1d5d7cdc
--- /dev/null
+++ b/dts/bindings/ethernet/microchip,enc424j600.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2019, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ENC424J600 standalone 100BASE-T Ethernet controller with SPI interface
+
+compatible: "microchip,enc424j600"
+
+include: [spi-device.yaml, ethernet.yaml]
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: true
+      description: Interrupt pin.
+
+        The interrupt pin of ENC424J600 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
diff --git a/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml b/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml
new file mode 100644
index 0000000000..1bc97cd026
--- /dev/null
+++ b/dts/bindings/ethernet/nxp,kinetis-ethernet.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis Ethernet
+
+compatible: "nxp,kinetis-ethernet"
+
+include: ["ethernet.yaml", "ethernet,fixed-link.yaml"]
+
+properties:
+    reg:
+      required: true
+    interrupts:
+      required: true
diff --git a/dts/bindings/ethernet/nxp,kinetis-ptp.yaml b/dts/bindings/ethernet/nxp,kinetis-ptp.yaml
new file mode 100644
index 0000000000..0d8b56bbc5
--- /dev/null
+++ b/dts/bindings/ethernet/nxp,kinetis-ptp.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis Ethernet PTP (Precision Time Protocol)
+
+compatible: "nxp,kinetis-ptp"
+
+include: base.yaml
+
+properties:
+    interrupts:
+      required: true
diff --git a/dts/bindings/ethernet/phy.yaml b/dts/bindings/ethernet/phy.yaml
new file mode 100644
index 0000000000..8a66919cf2
--- /dev/null
+++ b/dts/bindings/ethernet/phy.yaml
@@ -0,0 +1,6 @@
+# Copyright (c) 2021 IP-Logix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for PHY devices
+
+include: base.yaml
diff --git a/dts/bindings/ethernet/silabs,gecko-ethernet.yaml b/dts/bindings/ethernet/silabs,gecko-ethernet.yaml
new file mode 100644
index 0000000000..40cb71d21a
--- /dev/null
+++ b/dts/bindings/ethernet/silabs,gecko-ethernet.yaml
@@ -0,0 +1,101 @@
+# Copyright (c) 2019 Interay Solutions B.V.
+# Copyright (c) 2019 Oane Kingma
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiLabs Gecko Ethernet
+
+compatible: "silabs,gecko-ethernet"
+
+include: ethernet.yaml
+
+properties:
+    reg:
+      required: true
+      description: mmio register space
+
+    interrupts:
+      required: true
+      description: required interrupts
+
+    # PHY address
+    phy-address:
+      type: int
+      required: true
+      description: address of the PHY on the MDIO bus
+
+    # RMII interface location
+    location-rmii:
+      type: int
+      required: true
+      description: location of RMII pins, configuration defined as <location>
+
+    # PHY management interface location
+    location-mdio:
+      type: int
+      required: true
+      description: location of MDC and MDIO pins, configuration defined as <location>
+
+    # PHY management pins
+    location-phy_mdc:
+      type: array
+      required: true
+      description: PHY MDC individual pin configuration defined as <location port pin>
+
+    location-phy_mdio:
+      type: array
+      required: true
+      description: PHY MDIO individual pin configuration defined as <location port pin>
+
+    # RMII interface pins
+    location-rmii_refclk:
+      type: array
+      required: true
+      description: Reference clock individual pin configuration defined as <location port pin>
+
+    location-rmii_crs_dv:
+      type: array
+      required: true
+      description: Receive data valid individual pin configuration defined as <location port pin>
+
+    location-rmii_txd0:
+      type: array
+      required: true
+      description: Transmit data 0 individual pin configuration defined as <location port pin>
+
+    location-rmii_txd1:
+      type: array
+      required: true
+      description: Transmit data 1 individual pin configuration defined as <location port pin>
+
+    location-rmii_tx_en:
+      type: array
+      required: true
+      description: Transmit enable individual pin configuration defined as <location port pin>
+
+    location-rmii_rxd0:
+      type: array
+      required: true
+      description: Receive data 0 individual pin configuration defined as <location port pin>
+
+    location-rmii_rxd1:
+      type: array
+      required: true
+      description: Receive data 1 individual pin configuration defined as <location port pin>
+
+    location-rmii_rx_er:
+      type: array
+      required: true
+      description: Receive error individual pin configuration defined as <location port pin>
+
+    # PHY control pins
+    location-phy_pwr_enable:
+      type: array
+      description: PHY power enable individual pin configuration defined as <port pin>
+
+    location-phy_reset:
+      type: array
+      description: PHY reset individual pin configuration defined as <port pin>
+
+    location-phy_interrupt:
+      type: array
+      description: PHY interrupt individual pin configuration defined as <port pin>
diff --git a/dts/bindings/ethernet/smsc,lan9220.yaml b/dts/bindings/ethernet/smsc,lan9220.yaml
new file mode 100644
index 0000000000..c6fef07ed5
--- /dev/null
+++ b/dts/bindings/ethernet/smsc,lan9220.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: SMSC (now Microchip) LAN9220 Ethernet controller
+
+compatible: "smsc,lan9220"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/ethernet/snps,designware-ethernet.yaml b/dts/bindings/ethernet/snps,designware-ethernet.yaml
new file mode 100644
index 0000000000..1113d4d5ba
--- /dev/null
+++ b/dts/bindings/ethernet/snps,designware-ethernet.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2021, BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys DesignWare Ethernet
+
+compatible: "snps,designware-ethernet"
+
+include: ethernet.yaml
+
+properties:
+    reg:
+      required: true
+    interrupts:
+      required: true
diff --git a/dts/bindings/ethernet/st,stm32-ethernet.yaml b/dts/bindings/ethernet/st,stm32-ethernet.yaml
new file mode 100644
index 0000000000..e7d5ae625f
--- /dev/null
+++ b/dts/bindings/ethernet/st,stm32-ethernet.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST STM32 Ethernet
+
+compatible: "st,stm32-ethernet"
+
+include: [ethernet.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+    interrupts:
+      required: true
+    clocks:
+      required: true
+    clock-names:
+      required: true
+    pinctrl-0:
+      required: true
+    pinctrl-names:
+      required: true
diff --git a/dts/bindings/ethernet/ti,stellaris-ethernet.yaml b/dts/bindings/ethernet/ti,stellaris-ethernet.yaml
new file mode 100644
index 0000000000..5ed96eaf8a
--- /dev/null
+++ b/dts/bindings/ethernet/ti,stellaris-ethernet.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018 Zilogic Systems
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI Stellaris Ethernet
+
+compatible: "ti,stellaris-ethernet"
+
+include: ethernet.yaml
+
+properties:
+    reg:
+      required: true
+    interrupts:
+      required: true
diff --git a/dts/bindings/ethernet/wiznet,w5500.yaml b/dts/bindings/ethernet/wiznet,w5500.yaml
new file mode 100644
index 0000000000..9e5c8a0fa5
--- /dev/null
+++ b/dts/bindings/ethernet/wiznet,w5500.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 Linumiz
+# SPDX-License-Identifier: Apache-2.0
+
+description: W5500 standalone 10/100BASE-T Ethernet controller with SPI interface
+
+compatible: "wiznet,w5500"
+
+include: [spi-device.yaml, ethernet.yaml]
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: true
+      description: Interrupt pin.
+
+        The interrupt pin of W5500 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: Reset pin.
+
+        The reset pin of W5500 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
diff --git a/dts/bindings/ethernet/xlnx,gem.yaml b/dts/bindings/ethernet/xlnx,gem.yaml
new file mode 100644
index 0000000000..f6dfd95c5e
--- /dev/null
+++ b/dts/bindings/ethernet/xlnx,gem.yaml
@@ -0,0 +1,378 @@
+#
+# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Xilinx GEM Ethernet controller
+
+compatible: "xlnx,gem"
+
+include: ethernet.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clock-frequency:
+      type: int
+      required: true
+      description: |
+        Specifies the base clock frequency from which the GEM's TX clock
+        frequency will be derived using two dividers in the respective GEM's
+        clock control register in the CRL_APB. The GEM's TX clock frequency
+        is determined by the current link speed reported by the PHY, to
+        which it will be adjusted at run-time. Therefore, the value of this
+        item must be set to the clock frequency of the PLL supplying the
+        respective GEM's TX clock - by default, this is the IO PLL.
+
+    mdc-divider:
+      type: int
+      required: true
+      description: |
+        The MDC clock divider for the respective GEM. This is the divider
+        applied to the LPD_LSBUS clock in order to derive MDIO interface
+        clock driving communications with the attached PHY. Refer to the
+        ZynqMP register documentation (ug1087), network_config (GEM) Register
+        Description, bits [20:18] to determine the appropriate divider for
+        the current target's LPD LSBUS clock frequency.
+
+    init-mdio-phy:
+      type: boolean
+      required: false
+      description: |
+        Activates the management of a PHY associated with the controller in-
+        stance. If this parameter is activated at the board level, the de-
+        fault values of the associated parameters mdio-phy-address, phy-poll-
+        interval, link-speed and advertise-lower-link-speeds should be checked
+        and overwritten at the board level if required.
+
+    mdio-phy-address:
+      type: int
+      required: true
+      description: |
+        The address on the MDIO bus of the PHY associated with the controller
+        instance. Set the address to 0 for auto-detection (first responding
+        PHY will be claimed by the driver, watch out in case of shared MDIO
+        use), or to a fixed address between 1 and 32.
+
+    phy-poll-interval:
+      type: int
+      required: true
+      description: |
+        PHY status polling interval in milliseconds for a driver instance
+        managing an associated PHY.
+
+    link-speed:
+      type: int
+      required: true
+      description: |
+        Nominal link speed. If no PHY is managed by an instance of this driver,
+        the respective controller will be configured to match the link speed
+        specified here. If a PHY is managed by the driver, advertisement of
+        the link speed specified here will be requested. If the optional pro-
+        perty advertise-lower-link-speeds is set, advertisement of the link
+        speed specified here plus any valid link speed below this value will
+        be requested.
+      enum:
+        - 1
+        - 2
+        - 3
+
+    advertise-lower-link-speeds:
+      type: boolean
+      required: false
+      description: |
+        Indicates to a driver instance which manages an associated PHY on
+        the MDIO bus to include link speeds lower than the nominal value
+        set in the link-speed property in the advertisement when requesting
+        link speed auto-negotiation with a peer system.
+
+    handle-rx-in-isr:
+      type: boolean
+      required: false
+      description: |
+        Moves the handling of the frame received interrupt including the
+        transfer of packet data from the DMA to network packet buffers and
+        the subsequent propagation of the received packets to the network
+        stack into the context of the ISR. Due to the unpredictability of
+        the runtime of the ISR whenever large amounts of data are received,
+        handling of the RX interrupt is normally deferred to the context
+        of the system work queue.
+
+    handle-tx-in-workq:
+      type: boolean
+      required: false
+      description: |
+        Moves the handling of the frame transmission done interrupt into the
+        context of the system work queue. By default, TX done handling is per-
+        formed in the context of the ISR, as it only involves a limited number
+        of memory accesses. This option CAN NOT be used if any component ex-
+        ists within the current system setup that triggers the transmission
+        of packets from within the context of the system work queue!
+
+    amba-ahb-dbus-width:
+      type: int
+      required: true
+      description: AMBA AHB data bus width.
+      enum:
+        - 0
+        - 1
+        - 2
+
+    amba-ahb-burst-length:
+      type: int
+      required: true
+      description: AMBA AHB burst length for DMA operations.
+      enum:
+        - 1
+        - 4
+        - 8
+        - 16
+
+    hw-rx-buffer-size:
+      type: int
+      required: true
+      description: |
+        Hardware RX buffer size, scalable between 1 kB and 8 kB, where the full
+        8 kB should be the default.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+
+    hw-rx-buffer-offset:
+      type: int
+      required: true
+      description: |
+        Data offset in the hardware RX packet buffer (in bytes). Valid range is
+        0-3 bytes.
+
+    hw-tx-buffer-size-full:
+      type: boolean
+      required: false
+      description: |
+        When set, the hardware TX data buffer will make use of the full 4 kB
+        that are available. If unset, the hardware TX data buffer will be
+        limited to 2 kB.
+
+    rx-buffer-descriptors:
+      type: int
+      required: true
+      description: |
+        The number of descriptors to be allocated in the RX buffer descriptor
+        ring. Must be <= 255.
+
+    rx-buffer-size:
+      type: int
+      required: true
+      description: |
+        The size of each receive data buffer, must be a multiple of 8, highest
+        valid value is 16320, values less than 64 are not really useful.
+
+    tx-buffer-descriptors:
+      type: int
+      required: true
+      description: |
+        The number of descriptors to be allocated in the TX buffer descriptor
+        ring. Must be <= 255.
+
+    tx-buffer-size:
+      type: int
+      required: true
+      description: |
+        The size of each transmit data buffer, highest valid value is 16380,
+        values less than 64 are not really useful.
+
+    ignore-ipg-rxer:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Ignore IPG rx_er. When set, rx_er has no
+        effect on the GEM's operation when rx_dv is low. Set this when using
+        the RGMII wrapper in half-duplex mode.
+
+    disable-reject-nsp:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Receive bad preamble. When set, frames with
+        non-standard preamble will not be rejected.
+
+    ipg-stretch:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable IPG stretch. When set, the transmit
+        IPG can be increased above 96 bit times depending on the previous
+        frame length using the IPG stretch register.
+
+    sgmii-mode:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable SGMII mode. Changes the behaviour of
+        the auto-negotiation advertisement and link partner ability registers
+        to meet the requirements of SGMII and reduces the duration of the link
+        timer from 10 ms to 1.6 ms.
+
+    disable-reject-fcs-crc-errors:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Disable rejection of FCS/CRC errors.
+        When set, frames with FCS/CRC errors will not be rejected. FCS error
+        statistics will still be collected for frames with bad FCS and FCS
+        status will be recorded in the frame's DMA descriptor. This option
+        should not be activated for normal operation.
+
+    rx-halfdup-while-tx:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable frames to be received in half-duplex
+        mode while transmitting.
+
+    rx-checksum-offload:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable RX IP/TCP/UDP checksum offload to
+        hardware. Frames with bad IP, TCP or UDP checksums will be discarded.
+        This option is NOT supported by the QEMU implementation of the GEM!
+
+    tx-checksum-offload:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable TX IP/TCP/UDP checksum offload to
+        hardware. This option is NOT supported by the QEMU implementation
+        of the GEM!
+
+    disable-pause-copy:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Do not copy received pause frames to memory.
+        Set this option in order to prevent valid pause frames from being
+        copied to memory. When set, pause frames are not copied to memory
+        regardless of the state of the copy all frames bit, whether a hash
+        match is found or whether a type ID match is identified. If a desti-
+        nation address match is found the pause frame will be copied to
+        memory. Note that valid pause frames received will still increment
+        pause statistics and pause the transmission of frames as required.
+
+    discard-rx-fcs:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Remove FCS of received frames.
+        When set, received frames will be written to memory without their
+        frame check sequence (last 4 bytes). The frame length indicated will
+        be reduced by four bytes in this mode.
+
+    discard-rx-length-errors:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Discard frames with length field errors.
+        When set, frames with a measured length shorter than the extracted
+        length field (as indicated by bytes 13 and 14 in a non-VLAN tagged
+        frame) will be discarded. This only applies to frames with a length
+        field less than 0x0600.
+
+    pause-frame:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable pause. When set, transmission will
+        pause if a non zero 802.3 classic pause frame is received and PFC
+        has not been negotiated.
+
+    tbi:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable TBI. When set, the TBI interface is en-
+        bled instead of the GMII/MII interface.
+
+    ext-address-match:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable external address match. When set, the
+        external address match interface can be used to copy frames to memory.
+
+    long-frame-rx-support:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable reception of 1536 byte frames.
+        Normally, the GEM rejects any frame above 1518 bytes.
+
+    unicast-hash:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable unicast hash. When set, unicast frames
+        will be accepted when the 6 bit hash function of the destination
+        address points to a bit that is set in the hash register.
+
+    multicast-hash:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable multicast hash. When set, mutlicast
+        frames will be accepted when the 6 bit hash function of the desti-
+        nation address points to a bit that is set in the hash register.
+
+    reject-broadcast:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Reject broadcast frames. When set, frames
+        addressed to the all-ones broadcast address will be rejected.
+
+    promiscuous-mode:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable promiscuous mode. When set, all valid
+        frames will be accepted.
+
+    discard-non-vlan:
+      type: boolean
+      required: false
+      description: Optional feature flag - Discard non-VLAN frames. When set,
+        only VLAN tagged frames will be passed to the address matching logic.
+
+    full-duplex:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enables full duplex reception and transmission.
+
+    discard-rx-frame-ahb-unavail:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Discard received packets when no AHB resource
+        is available.
+
+    ahb-packet-endian-swap:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable AHB packet data endianness swap to big
+        endian. If this flag is not set, data will be little endian.
+
+    ahb-md-endian-swap:
+      type: boolean
+      required: false
+      description: |
+        Optional feature flag - Enable AHB management descriptor data endian-
+        ness swap to big endian. If this flag is not set, data will be little
+        endian.
diff --git a/dts/bindings/flash_controller/atmel,sam-flash-controller.yaml b/dts/bindings/flash_controller/atmel,sam-flash-controller.yaml
new file mode 100644
index 0000000000..8c98742398
--- /dev/null
+++ b/dts/bindings/flash_controller/atmel,sam-flash-controller.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Enhanced Embedded Flash Controller (EEFC)
+
+compatible: "atmel,sam-flash-controller"
+
+include: flash-controller.yaml
+
+properties:
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
diff --git a/dts/bindings/flash_controller/atmel,sam0-nvmctrl.yaml b/dts/bindings/flash_controller/atmel,sam0-nvmctrl.yaml
new file mode 100644
index 0000000000..9e24ddadd5
--- /dev/null
+++ b/dts/bindings/flash_controller/atmel,sam0-nvmctrl.yaml
@@ -0,0 +1,11 @@
+description: Atmel SAM0 NVMC (Non-Volatile Memory Controller)
+
+compatible: "atmel,sam0-nvmctrl"
+
+include: flash-controller.yaml
+
+properties:
+    lock-regions:
+      type: int
+      required: true
+      description: Number of lock regions
diff --git a/dts/bindings/flash_controller/cypress,psoc6-flash-controller.yaml b/dts/bindings/flash_controller/cypress,psoc6-flash-controller.yaml
new file mode 100644
index 0000000000..6b06e93ede
--- /dev/null
+++ b/dts/bindings/flash_controller/cypress,psoc6-flash-controller.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, Cypress
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress flash controller
+
+compatible: "cypress,psoc6-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/espressif,esp32-flash-controller.yaml b/dts/bindings/flash_controller/espressif,esp32-flash-controller.yaml
new file mode 100644
index 0000000000..c1bfa3bf69
--- /dev/null
+++ b/dts/bindings/flash_controller/espressif,esp32-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: ESP32 Family flash controller
+
+compatible: "espressif,esp32-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/flash-controller.yaml b/dts/bindings/flash_controller/flash-controller.yaml
new file mode 100644
index 0000000000..92786e7a71
--- /dev/null
+++ b/dts/bindings/flash_controller/flash-controller.yaml
@@ -0,0 +1,10 @@
+# Common fields for flash controllers
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
diff --git a/dts/bindings/flash_controller/ite,it8xxx2-flash-controller.yaml b/dts/bindings/flash_controller/ite,it8xxx2-flash-controller.yaml
new file mode 100644
index 0000000000..16da0e5d96
--- /dev/null
+++ b/dts/bindings/flash_controller/ite,it8xxx2-flash-controller.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE IT8XXX2 flash memory
+
+compatible: "ite,it8xxx2-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/nordic,nrf-qspi.yaml b/dts/bindings/flash_controller/nordic,nrf-qspi.yaml
new file mode 100644
index 0000000000..63b410c9fe
--- /dev/null
+++ b/dts/bindings/flash_controller/nordic,nrf-qspi.yaml
@@ -0,0 +1,76 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Properties defining the interface for the Nordic QSPI peripheral.
+
+    The reg property describes two register blocks: one for the memory
+    corresponding to the QSPI peripheral registers, and another for
+    the memory mapped XIP area:
+
+        qspi: qspi@2b000 {
+                compatible = "nordic,nrf-qspi";
+                reg = <0x2b000 0x1000>, <0x10000000 0x10000000>;
+                reg-names = "qspi", "qspi_mm";
+                ...
+        };
+
+    Above, the register block with base address 0x2b000 and name
+    "qspi" are the QSPI peripheral registers. The register block with
+    base address 0x10000000 and name "qspi_mm" is the XIP area.
+
+compatible: "nordic,nrf-qspi"
+
+include: flash-controller.yaml
+
+bus: qspi
+
+properties:
+  "#address-cells":
+    required: true
+    const: 1
+
+  "#size-cells":
+    required: true
+    const: 0
+
+  interrupts:
+    required: true
+
+  sck-pin:
+    type: int
+    required: true
+    description: |
+      The SCK pin to use.
+
+      For pins P0.0 through P0.31, use the pin number. For example,
+      to use P0.16 for SCK, set:
+
+          sck-pin = <16>;
+
+      For pins P1.0 through P1.31, add 32 to the pin number. For
+      example, to use P1.2 for SCK, set:
+
+          sck-pin = <34>;  /* 32 + 2 */
+  io-pins:
+    type: array
+    required: true
+    description: |
+      Pin numbers associated with IO0 through IO3 signals.
+
+      Examples:
+
+          io-pins = <io0-pin io1-pin>; // two pins
+
+          io-pins = <io0-pin io1-pin io2-pin io3-pin>; // four pins
+
+      Either two or four pins must be configured using this property
+      as shown above. The pin numbering scheme is the same as the
+      sck-pin property's.
+  csn-pins:
+    type: array
+    required: true
+    description: |
+      Chip select signal pin number. Exactly one pin should be
+      given. The pin numbering scheme is the same as the
+      sck-pin property's.
diff --git a/dts/bindings/flash_controller/nordic,nrf51-flash-controller.yaml b/dts/bindings/flash_controller/nordic,nrf51-flash-controller.yaml
new file mode 100644
index 0000000000..c176c6073b
--- /dev/null
+++ b/dts/bindings/flash_controller/nordic,nrf51-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: Nordic NVMC (Non-Volatile Memory Controller)
+
+compatible: "nordic,nrf51-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/nordic,nrf52-flash-controller.yaml b/dts/bindings/flash_controller/nordic,nrf52-flash-controller.yaml
new file mode 100644
index 0000000000..d4c3d318e5
--- /dev/null
+++ b/dts/bindings/flash_controller/nordic,nrf52-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: Nordic NVMC (Non-Volatile Memory Controller)
+
+compatible: "nordic,nrf52-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/nordic,nrf53-flash-controller.yaml b/dts/bindings/flash_controller/nordic,nrf53-flash-controller.yaml
new file mode 100644
index 0000000000..857746bccd
--- /dev/null
+++ b/dts/bindings/flash_controller/nordic,nrf53-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: Nordic NVMC (Non-Volatile Memory Controller)
+
+compatible: "nordic,nrf53-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/nordic,nrf91-flash-controller.yaml b/dts/bindings/flash_controller/nordic,nrf91-flash-controller.yaml
new file mode 100644
index 0000000000..ac8aa24e4f
--- /dev/null
+++ b/dts/bindings/flash_controller/nordic,nrf91-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: Nordic NVMC (Non-Volatile Memory Controller)
+
+compatible: "nordic,nrf91-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/nxp,kinetis-ftfa.yaml b/dts/bindings/flash_controller/nxp,kinetis-ftfa.yaml
new file mode 100644
index 0000000000..46f1a0ead0
--- /dev/null
+++ b/dts/bindings/flash_controller/nxp,kinetis-ftfa.yaml
@@ -0,0 +1,5 @@
+description: NXP Kinetis Flash Memory Module A (FTFA)
+
+compatible: "nxp,kinetis-ftfa"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/nxp,kinetis-ftfe.yaml b/dts/bindings/flash_controller/nxp,kinetis-ftfe.yaml
new file mode 100644
index 0000000000..7c273d9809
--- /dev/null
+++ b/dts/bindings/flash_controller/nxp,kinetis-ftfe.yaml
@@ -0,0 +1,5 @@
+description: NXP Kinetis Flash Memory Module E (FTFE)
+
+compatible: "nxp,kinetis-ftfe"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/nxp,kinetis-ftfl.yaml b/dts/bindings/flash_controller/nxp,kinetis-ftfl.yaml
new file mode 100644
index 0000000000..de39bc46ac
--- /dev/null
+++ b/dts/bindings/flash_controller/nxp,kinetis-ftfl.yaml
@@ -0,0 +1,5 @@
+description: NXP Kinetis Flash Memory Module L (FTFL)
+
+compatible: "nxp,kinetis-ftfl"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/nxp,lpc-iap.yaml b/dts/bindings/flash_controller/nxp,lpc-iap.yaml
new file mode 100644
index 0000000000..505ab69161
--- /dev/null
+++ b/dts/bindings/flash_controller/nxp,lpc-iap.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC IAP (In-Application Programming) flash memory controller
+
+compatible: "nxp,lpc-iap"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/openisa,rv32m1-ftfe.yaml b/dts/bindings/flash_controller/openisa,rv32m1-ftfe.yaml
new file mode 100644
index 0000000000..49c2b24746
--- /dev/null
+++ b/dts/bindings/flash_controller/openisa,rv32m1-ftfe.yaml
@@ -0,0 +1,5 @@
+description: OpenISA Flash Memory Module E (FTFE)
+
+compatible: "openisa,rv32m1-ftfe"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/silabs,gecko-flash-controller.yaml b/dts/bindings/flash_controller/silabs,gecko-flash-controller.yaml
new file mode 100644
index 0000000000..0b73841856
--- /dev/null
+++ b/dts/bindings/flash_controller/silabs,gecko-flash-controller.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silicon Labs Gecko flash controller
+
+compatible: "silabs,gecko-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32-flash-controller.yaml
new file mode 100644
index 0000000000..5156f4be35
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 Family flash controller
+
+compatible: "st,stm32-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml b/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml
new file mode 100644
index 0000000000..1e8f5bd3db
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2020, Linaro limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STM32 QSPI Flash controller supporting the JEDEC CFI interface
+
+    Representation of a serial flash on a quadspi bus:
+
+        mx25r6435f: qspi-nor-flash@0 {
+                compatible = "st,stm32-qspi-nor";
+                label = "MX25R6435F";
+                reg = <0>;
+                qspi-max-frequency = <80000000>;
+                size = <0x4000000>;
+                status = "okay";
+        };
+
+compatible: "st,stm32-qspi-nor"
+
+include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
+
+on-bus: qspi
+
+properties:
+    reg:
+      required: true
+    qspi-max-frequency:
+      type: int
+      required: true
+      description: Maximum clock frequency of device's QSPI interface in Hz
+    label:
+      required: true
+    size:
+      required: true
+      description: Flash Memory size in bits
diff --git a/dts/bindings/flash_controller/st,stm32f0-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f0-flash-controller.yaml
new file mode 100644
index 0000000000..bb2248ded8
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32f0-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 F0 flash controller
+
+compatible: "st,stm32f0-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml
new file mode 100644
index 0000000000..1ba1208d90
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 F1 flash controller
+
+compatible: "st,stm32f1-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml
new file mode 100644
index 0000000000..65ab19a071
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 F2 flash controller
+
+compatible: "st,stm32f2-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32f3-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f3-flash-controller.yaml
new file mode 100644
index 0000000000..e23c3baef0
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32f3-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 F3 flash controller
+
+compatible: "st,stm32f3-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml
new file mode 100644
index 0000000000..cea824302a
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 F4 flash controller
+
+compatible: "st,stm32f4-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml
new file mode 100644
index 0000000000..cdeaa308df
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 F7 flash controller
+
+compatible: "st,stm32f7-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml
new file mode 100644
index 0000000000..226858e3e5
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 G0 flash controller
+
+compatible: "st,stm32g0-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml
new file mode 100644
index 0000000000..71df716072
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 G4 flash controller
+
+compatible: "st,stm32g4-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml
new file mode 100644
index 0000000000..305107cc1c
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 H7 flash controller
+
+compatible: "st,stm32h7-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32l0-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l0-flash-controller.yaml
new file mode 100644
index 0000000000..2b70035d0f
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32l0-flash-controller.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 L0 flash controller
+
+compatible: "st,stm32l0-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32l1-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l1-flash-controller.yaml
new file mode 100644
index 0000000000..2703eddfcf
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32l1-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 L1 flash controller
+
+compatible: "st,stm32l1-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml
new file mode 100644
index 0000000000..17e3e76fba
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 L4 flash controller
+
+compatible: "st,stm32l4-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml
new file mode 100644
index 0000000000..0f6edba9d9
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 L5 flash controller
+
+compatible: "st,stm32l5-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32u5-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32u5-flash-controller.yaml
new file mode 100644
index 0000000000..5a13de3b4d
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32u5-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: STM32 U5 flash controller
+
+compatible: "st,stm32u5-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml
new file mode 100644
index 0000000000..3610bd2723
--- /dev/null
+++ b/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml
@@ -0,0 +1,16 @@
+description: STM32 WB flash controller
+
+compatible: "st,stm32wb-flash-controller"
+
+include: flash-controller.yaml
+
+properties:
+    single-bank:
+      type: boolean
+      description: dual-bank mode not enabled (page erase 4096k)
+      required: false
+
+    dual-bank:
+      type: boolean
+      description: dual-bank mode enabled (page erase 2048k)
+      required: false
diff --git a/dts/bindings/flash_controller/telink,b91-flash-controller.yaml b/dts/bindings/flash_controller/telink,b91-flash-controller.yaml
new file mode 100644
index 0000000000..baf0de3829
--- /dev/null
+++ b/dts/bindings/flash_controller/telink,b91-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: Telink B91 Flash Controller
+
+compatible: "telink,b91-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/ti,stellaris-flash-controller.yaml b/dts/bindings/flash_controller/ti,stellaris-flash-controller.yaml
new file mode 100644
index 0000000000..964e489ff2
--- /dev/null
+++ b/dts/bindings/flash_controller/ti,stellaris-flash-controller.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI Stellaris flash controller
+
+compatible: "ti,stellaris-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/zephyr,sim-flash.yaml b/dts/bindings/flash_controller/zephyr,sim-flash.yaml
new file mode 100644
index 0000000000..6cc1239552
--- /dev/null
+++ b/dts/bindings/flash_controller/zephyr,sim-flash.yaml
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Simulated flash memory
+
+compatible: "zephyr,sim-flash"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    erase-value:
+      type: int
+      description: Value of erased flash cell
+      required: false
diff --git a/dts/bindings/fs/zephyr,fstab,littlefs.yaml b/dts/bindings/fs/zephyr,fstab,littlefs.yaml
new file mode 100644
index 0000000000..519c1271e0
--- /dev/null
+++ b/dts/bindings/fs/zephyr,fstab,littlefs.yaml
@@ -0,0 +1,78 @@
+# Copyright (C) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Description of pre-defined file systems.
+
+compatible: "zephyr,fstab,littlefs"
+
+include: "zephyr,fstab-common.yaml"
+
+properties:
+  # num-files and num-dirs are not filesystem-specific.
+
+  read-size:
+    type: int
+    required: true
+    description: |
+      The size of file system read operations, in bytes.
+
+      All read operations will be a multiple of this value.  A
+      reasonable default is 16.
+
+      This corresponds to CONFIG_FS_LITTLEFS_READ_SIZE.
+
+  prog-size:
+    type: int
+    required: true
+    description: |
+      The size of file system program (write) operations, in bytes.
+
+      All program operations will be a multiple of this value.  A
+      reasonable default is 16.
+
+      This corresponds to CONFIG_FS_LITTLEFS_PROG_SIZE.
+
+  cache-size:
+    type: int
+    required: true
+    description: |
+      The size of block caches, in bytes.
+
+      Each cache buffers a portion of a block in RAM.  The littlefs
+      needs a read cache, a program cache, and one additional cache per
+      file. Larger caches can improve performance by storing more data
+      and reducing the number of disk accesses. Must be a multiple of
+      the read and program sizes of the underlying flash device, and a
+      factor of the block size.
+
+      A reasonable default is 64.
+
+      This corresponds to CONFIG_FS_LITTLEFS_CACHE_SIZE.
+
+  lookahead-size:
+    type: int
+    required: true
+    description: |
+      The size of the lookahead buffer, in bytes.
+
+      A larger lookahead buffer increases the number of blocks found
+      during an allocation pass. The lookahead buffer is stored as a
+      compact bitmap, so each byte of RAM can track 8 blocks. Must be a
+      multiple of 8.
+
+      A reasonable default is 32.
+
+      This corresponds to CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE.
+
+  block-cycles:
+    type: int
+    required: true
+    description: |
+      The number of erase cycles before moving data to another block.
+
+      For dynamic wear leveling, the number of erase cycles before data
+      is moved to another block.  Set to a non-positive value to disable
+      leveling.
+
+      This corresponds to CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE.
diff --git a/dts/bindings/fs/zephyr,fstab-common.yaml b/dts/bindings/fs/zephyr,fstab-common.yaml
new file mode 100644
index 0000000000..e7e9fa3fe9
--- /dev/null
+++ b/dts/bindings/fs/zephyr,fstab-common.yaml
@@ -0,0 +1,51 @@
+# Copyright (C) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties for Zephyr filesystem compatibles
+
+include: base.yaml
+
+properties:
+  mount-point:
+    type: string
+    required: true
+    description: |
+      The absolute path used as the file system mount point.
+
+  partition:
+    type: phandle
+    required: true
+    description: |
+      A reference to the file system's partition.
+
+  automount:
+    type: boolean
+    description: |
+      Mount file system on boot if present.
+
+      During initialization the file system driver will attempt to mount
+      this partition.
+
+  read-only:
+    type: boolean
+    description: |
+      Mount file system read-only if present.
+
+      This adds the FS_MOUNT_FLAG_READ_ONLY option to be set in the
+      mount descriptor generated for the file system.
+
+  no-format:
+    type: boolean
+    description: |
+      Do not format file system if mount fails.
+
+      This causes the FS_MOUNT_FLAG_NO_FORMAT option to be set in the
+      mount descriptor generated for the file system.
+
+  disk-access:
+    type: boolean
+    description: |
+      Use disk-access for accessing storage media.
+
+      This causes the FS_MOUNT_FLAG_USE_DISK_ACCESS option to be set in
+      the mount descriptor generated for the file system.
diff --git a/dts/bindings/fs/zephyr,fstab.yaml b/dts/bindings/fs/zephyr,fstab.yaml
new file mode 100644
index 0000000000..4126305f1b
--- /dev/null
+++ b/dts/bindings/fs/zephyr,fstab.yaml
@@ -0,0 +1,12 @@
+# Copyright (C) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Description of pre-defined file systems.
+
+    This is a container for child nodes that provide at minimum the
+    properties described in zephyr,fstab-common.yaml.
+
+compatible: "zephyr,fstab"
+
+include: base.yaml
diff --git a/dts/bindings/gpio/adafruit-feather-header.yaml b/dts/bindings/gpio/adafruit-feather-header.yaml
new file mode 100644
index 0000000000..d545431fe0
--- /dev/null
+++ b/dts/bindings/gpio/adafruit-feather-header.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2020 Richard Osterloh
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GPIO pins exposed on Adafruit Feather headers.
+
+    The Feather layout provides two headers, one each along
+    opposite edges of the board.
+    Proceeding counter-clockwise:
+    * A 16-pin header.  12 pins on this header are exposed
+      by this binding.
+    * A 12-pin header.  9 pins on this header are exposed
+      by this binding.
+
+    This binding provides a nexus mapping for 21 pins where parent pins 0
+    through 5 correspond to A0 through A5, and parent pins 6 through 20
+    correspond as depicted below:
+
+        - RESET
+        - 3V3
+        - 3V3
+        - GND
+        0 A0                     - VBAT
+        1 A1                     - EN
+        2 A2                     - VBUS
+        3 A3                     D13  20
+        4 A4                     D12  19
+        5 A5                     D11  18
+        6 SCK                    D10  17
+        7 MOSI                   D9   16
+        8 MISO                   D6   15
+        9 RX                     D5   14
+       10 TX                     SCL  13
+       11 D4                     SDA  12
+
+
+compatible: "adafruit-feather-header"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/andestech,atcgpio100.yaml b/dts/bindings/gpio/andestech,atcgpio100.yaml
new file mode 100644
index 0000000000..93f88ebd85
--- /dev/null
+++ b/dts/bindings/gpio/andestech,atcgpio100.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2021, Andes Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description:
+    This is a representation of Andes Technology atcgpio100 GPIO node
+
+compatible: "andestech,atcgpio100"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/arduino-header-r3.yaml b/dts/bindings/gpio/arduino-header-r3.yaml
new file mode 100644
index 0000000000..1dae0b2575
--- /dev/null
+++ b/dts/bindings/gpio/arduino-header-r3.yaml
@@ -0,0 +1,50 @@
+# Copyright (c) 2019 Foundries.io
+# Copyright (C) 2019 Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GPIO pins exposed on Arduino Uno (R3) headers.
+
+    The Arduino Uno layout provides four headers, two each along
+    opposite edges of the board.
+
+    Proceeding counter-clockwise:
+    * An 8-pin Power Supply header.  No pins on this header are exposed
+      by this binding.
+    * A 6-pin Analog Input header.  This has analog input signals
+      labeled from A0 at the top through A5 at the bottom.
+    * An 8-pin header (opposite Analog Input).  This has digital input
+      signals labeled from D0 at the bottom D7 at the top;
+    * A 10-pin header (opposite Power Supply).  This has six additional
+      digital input signals labelled from D8 at the bottom through D13
+      towards the top, skipping two pins, then finishing with D14 and
+      D15 at the top.
+
+    This binding provides a nexus mapping for 20 pins where parent pins 0
+    through 5 correspond to A0 through A5, and parent pins 6 through 21
+    correspond to D0 through D15, as depicted below:
+
+                                 D15  21
+                                 D14  20
+                                 AREF -
+                                 GND  -
+        - N/C                    D13  19
+        - IOREF                  D12  18
+        - RESET                  D11  17
+        - 3V3                    D10  16
+        - 5V                     D9   15
+        - GND                    D8   14
+        - GND
+        - VIN                    D7   13
+                                 D6   12
+        0 A0                     D5   11
+        1 A1                     D4   10
+        2 A2                     D3    9
+        3 A3                     D2    8
+        4 A4                     D1    7
+        5 A5                     D0    6
+
+
+compatible: "arduino-header-r3"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/arm,cmsdk-gpio.yaml b/dts/bindings/gpio/arm,cmsdk-gpio.yaml
new file mode 100644
index 0000000000..cd971071c0
--- /dev/null
+++ b/dts/bindings/gpio/arm,cmsdk-gpio.yaml
@@ -0,0 +1,22 @@
+description: ARM CMSDK GPIO
+
+compatible: "arm,cmsdk-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml b/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml
new file mode 100644
index 0000000000..f4e9f50583
--- /dev/null
+++ b/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml
@@ -0,0 +1,18 @@
+description: GPIO controller on ARM MPS2 FPGA
+
+compatible: "arm,mps2-fpgaio-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    ngpios:
+      required: true
+
+    "#gpio-cells":
+      const: 1
+
+gpio-cells:
+  - pin
diff --git a/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml b/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml
new file mode 100644
index 0000000000..4d6db2f203
--- /dev/null
+++ b/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml
@@ -0,0 +1,18 @@
+description: GPIO controller on ARM MPS3 FPGA
+
+compatible: "arm,mps3-fpgaio-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    ngpios:
+      required: true
+
+    "#gpio-cells":
+      const: 1
+
+gpio-cells:
+  - pin
diff --git a/dts/bindings/gpio/atmel,sam-gpio.yaml b/dts/bindings/gpio/atmel,sam-gpio.yaml
new file mode 100644
index 0000000000..4d01557c0c
--- /dev/null
+++ b/dts/bindings/gpio/atmel,sam-gpio.yaml
@@ -0,0 +1,38 @@
+description: SAM GPIO PORT node
+
+compatible: "atmel,sam-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    "#atmel,pin-cells":
+      type: int
+      required: true
+      const: 2
+      description: Number of items to expect in a atmel,pins specifier
+
+
+gpio-cells:
+  - pin
+  - flags
+
+atmel,pin-cells:
+  - pin
+  - peripheral
diff --git a/dts/bindings/gpio/atmel,sam0-gpio.yaml b/dts/bindings/gpio/atmel,sam0-gpio.yaml
new file mode 100644
index 0000000000..7c4e02a200
--- /dev/null
+++ b/dts/bindings/gpio/atmel,sam0-gpio.yaml
@@ -0,0 +1,29 @@
+description: SAM0 GPIO PORT node
+
+compatible: "atmel,sam0-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    "#atmel,pin-cells":
+      type: int
+      required: true
+      const: 2
+      description: Number of items to expect in a atmel,pins specifier
+
+gpio-cells:
+  - pin
+  - flags
+
+atmel,pin-cells:
+  - pin
+  - peripheral
diff --git a/dts/bindings/gpio/atmel,sam4l-gpio.yaml b/dts/bindings/gpio/atmel,sam4l-gpio.yaml
new file mode 100644
index 0000000000..9e10bd6afa
--- /dev/null
+++ b/dts/bindings/gpio/atmel,sam4l-gpio.yaml
@@ -0,0 +1,5 @@
+description: SAM4L GPIO PORT node
+
+compatible: "atmel,sam4l-gpio"
+
+include: ["atmel,sam-gpio.yaml"]
diff --git a/dts/bindings/gpio/atmel-xplained-header.yaml b/dts/bindings/gpio/atmel-xplained-header.yaml
new file mode 100644
index 0000000000..ad3b559239
--- /dev/null
+++ b/dts/bindings/gpio/atmel-xplained-header.yaml
@@ -0,0 +1,45 @@
+# Copyright (C) 2020 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GPIO pins exposed on Atmel Xplained headers.
+
+    The Xplained layout provide a standard 10 pin header.  A board can have
+    one or more headers and can share pins.  This connector was developed to
+    match with Atmel AVR XMEGA devices GPIO port plus power signals.  The Atmel
+    Xplained Pro standard connector keep compatibility with this header and it
+    can be defined on every board with an Xplained Pro Connector extension and
+    every pin can be defined as general purpose GPIO.
+
+    The AVR XMEGA port was designed as:
+
+    Signal  Main Function
+       Px0  SDA
+       Px1  SCL
+       Px2  RX
+       Px3  TX
+       Px4  SS
+       Px5  MOSI
+       Px6  MISO
+       Px7  SCK
+       GND
+       VDD
+
+    Documentation:
+    * https://www.microchip.com/development-tools/xplained-boards
+    * http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Development-Kit_User%20Guide.pdf
+
+    This binding provides a nexus mapping for 10 pins where pins are disposed
+    to have a even and odd column:
+
+                           Connector
+    Bind      Pin Name     Pin   Pin  Pin Name        Bind
+      0          I2C(SDA)  1       2  I2C(SCL)         1
+      2          UART(RX)  3       4  UART(TX)         3
+      4          SPI(CS0)  5       6  SPI(MOSI)        5
+      6         SPI(MISO)  7       8  SPI(SCK)         7
+                      GND  9      10  VDD(+3.3V)
+
+compatible: "atmel-xplained-header"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/atmel-xplained-pro-header.yaml b/dts/bindings/gpio/atmel-xplained-pro-header.yaml
new file mode 100644
index 0000000000..173223e7b4
--- /dev/null
+++ b/dts/bindings/gpio/atmel-xplained-pro-header.yaml
@@ -0,0 +1,49 @@
+# Copyright (C) 2020 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GPIO pins exposed on Atmel Xplained Pro headers.
+
+    The Xplained Pro layout provide a standard 20 pin header.  A board can have
+    one or more headers and can share pins.  The extension headers are given
+    names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
+    to the embedded debugger.  A header with ID7 signal from the embedded
+    debugger connected should be called EXT7. PWR, EXT1, EXT2 and EXT3 are
+    standard extension headers that have a predefined position according to the
+    list below:
+      * PWR is right angled at the top right hand side of the board. This
+      header must always be implemented.
+      * EXT1 is right angled at the top right hand side of the board, located
+      below the PWR header. This header must always be present.
+      * EXT2 is right angled and at the bottom right hand side of the board.
+      This header is mandatory for medium and large boards and should not be
+      implemented on small boards.
+      * EXT3 is right angled pointing downwards
+    All MCU boards have to implement at least PWR, EXT1, EXT2 (on medium and
+    large boards), and EXT3. EXT4 to EXT7 can be placed differently depending
+    on the board design. EXT4 to EXT7 can either be standard extension headers
+    or application specific headers.
+
+    Documentation:
+    * https://www.microchip.com/development-tools/xplained-boards
+    * http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Development-Kit_User%20Guide.pdf
+
+    This binding provides a nexus mapping for 20 pins where pins are disposed
+    to have a even and odd column:
+
+                           Connector
+    Bind      Pin Name     Pin   Pin  Pin Name        Bind
+                       ID  1       2  GND
+      0            ADC(+)  3       4  ADC(-)           1
+      2   UART(RTS)/GPIO1  5       6  UART(CTS)/GPIO2  3
+      4            PWM(+)  7       8  PWM(-)           5
+      6         IRQ/GPIO3  9      10  SPI(CS1)/GPIO4   7
+      8          I2C(SDA)  11     12  I2C(SCL)         9
+     10          UART(RX)  13     14  UART(TX)         11
+     12          SPI(CS0)  15     16  SPI(MOSI)        13
+     14         SPI(MISO)  17     18  SPI(SCK)         15
+                      GND  19     20  VDD(+3.3V)
+
+compatible: "atmel-xplained-pro-header"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml b/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml
new file mode 100644
index 0000000000..c5238f99cd
--- /dev/null
+++ b/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2021 Synopsys
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress cy8c95xx GPIO port node
+
+compatible: "cypress,cy8c95xx-gpio-port"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    ngpios:
+      required: true
+      const: 8
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml b/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml
new file mode 100644
index 0000000000..cfe9ef2f03
--- /dev/null
+++ b/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021 Synopsys
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress cy8c95xx GPIO node
+
+compatible: "cypress,cy8c95xx-gpio"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/gpio/cypress,psoc6-gpio.yaml b/dts/bindings/gpio/cypress,psoc6-gpio.yaml
new file mode 100644
index 0000000000..fe27377e09
--- /dev/null
+++ b/dts/bindings/gpio/cypress,psoc6-gpio.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2020-2021 ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress GPIO PORT node
+
+compatible: "cypress,psoc6-gpio"
+
+include: ["gpio-controller.yaml", "base.yaml"]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    "#cypress,pin-cells":
+      type: int
+      required: true
+      const: 2
+      description: Number of items to expect in a cypress,pins specifier
+
+gpio-cells:
+  - pin
+  - flags
+
+cypress,pin-cells:
+  - pin
+  - hsiom
diff --git a/dts/bindings/gpio/cypress,psoc6-hsiom.yaml b/dts/bindings/gpio/cypress,psoc6-hsiom.yaml
new file mode 100644
index 0000000000..6c33f5e1e1
--- /dev/null
+++ b/dts/bindings/gpio/cypress,psoc6-hsiom.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020 ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress High Speed I/O Matrix
+
+compatible: "cypress,psoc6-hsiom"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/gpio/espressif,esp32-gpio.yaml b/dts/bindings/gpio/espressif,esp32-gpio.yaml
new file mode 100644
index 0000000000..e9a8c4b6a5
--- /dev/null
+++ b/dts/bindings/gpio/espressif,esp32-gpio.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2019, Yannis Damigos
+# SPDX-License-Identifier: Apache-2.0
+
+description: ESP32 GPIO controller
+
+compatible: "espressif,esp32-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+        required: true
+
+    label:
+        required: true
+
+    "#gpio-cells":
+        const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/fcs,fxl6408.yaml b/dts/bindings/gpio/fcs,fxl6408.yaml
new file mode 100644
index 0000000000..72cf18a15f
--- /dev/null
+++ b/dts/bindings/gpio/fcs,fxl6408.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021 Abel Sensors
+# SPDX-License-Identifier: Apache-2.0
+
+description: FXL6408 I2C-based GPIO expander
+
+compatible: "fcs,fxl6408"
+
+include: [gpio-controller.yaml, i2c-device.yaml]
+
+properties:
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/gd,gd32-gpio.yaml b/dts/bindings/gpio/gd,gd32-gpio.yaml
new file mode 100644
index 0000000000..36c9ef1e6b
--- /dev/null
+++ b/dts/bindings/gpio/gd,gd32-gpio.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2021 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: GD32 GPIO node
+
+compatible: "gd,gd32-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    rcu-periph-clock:
+      type: int
+      description: Reset Control Unit Peripheral Clock ID
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/gpio-controller.yaml b/dts/bindings/gpio/gpio-controller.yaml
new file mode 100644
index 0000000000..2edab42b69
--- /dev/null
+++ b/dts/bindings/gpio/gpio-controller.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for GPIO controllers
+
+properties:
+    "gpio-controller":
+      type: boolean
+      required: true
+      description: Convey's this node is a GPIO controller
+    "#gpio-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a GPIO specifier
+    ngpios:
+      type: int
+      required: false
+      default: 32
+      description: |
+          This property indicates the number of in-use slots of available slots
+          for GPIOs. The typical example is something like this: the hardware
+          register is 32 bits wide, but only 18 of the bits have a physical
+          counterpart. The driver is generally written so that all 32 bits can
+          be used, but the IP block is reused in a lot of designs, some using
+          all 32 bits, some using 18 and some using 12. In this case, setting
+          "ngpios = <18>;" informs the driver that only the first 18 GPIOs, at
+          local offset 0 .. 17, are in use.  For cases in which there might be
+          holes in the slot range, this value should be the max slot number-1.
+    gpio-reserved-ranges:
+      type: array
+      required: false
+      description: |
+          If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
+          this property contains an additional set of tuples which specify which GPIOs
+          are unusable. This property indicates the start and size of the GPIOs
+          that can't be used.
+
+          For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
+          GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>.
+    gpio-line-names:
+      type: string-array
+      required: false
+      description: |
+          This is an array of strings defining the names of the GPIO lines
+          going out of the GPIO controller
diff --git a/dts/bindings/gpio/gpio-keys.yaml b/dts/bindings/gpio/gpio-keys.yaml
new file mode 100644
index 0000000000..b40a07fe8e
--- /dev/null
+++ b/dts/bindings/gpio/gpio-keys.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: GPIO KEYS parent node
+
+compatible: "gpio-keys"
+
+child-binding:
+    description: GPIO KEYS child node
+    properties:
+       gpios:
+          type: phandle-array
+          required: true
+       label:
+          required: true
+          type: string
+          description: Human readable string describing the device (used as device_get_binding() argument)
diff --git a/dts/bindings/gpio/gpio-leds.yaml b/dts/bindings/gpio/gpio-leds.yaml
new file mode 100644
index 0000000000..32dbbde0a5
--- /dev/null
+++ b/dts/bindings/gpio/gpio-leds.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: GPIO LEDs parent node
+
+compatible: "gpio-leds"
+
+include:
+    - name: base.yaml
+      property-allowlist: [label]
+
+properties:
+    label:
+      description: |
+        Human readable string describing the device and used to set the device
+        name. It can be passed as argument to device_get_binding() to retrieve
+        the device. If this property is omitted, then the device name is set
+        from the node full name.
+
+child-binding:
+    description: GPIO LED child node
+    properties:
+       gpios:
+          type: phandle-array
+          required: true
+       label:
+          required: false
+          type: string
+          description: |
+            Human readable string describing the LED. It can be used by an
+            application to identify this LED or to retrieve its number/index
+            (i.e. child node number) on the parent device.
diff --git a/dts/bindings/gpio/gpio-nexus.yaml b/dts/bindings/gpio/gpio-nexus.yaml
new file mode 100644
index 0000000000..052fdd66af
--- /dev/null
+++ b/dts/bindings/gpio/gpio-nexus.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for GPIO nexus nodes
+
+properties:
+    gpio-map:
+      type: compound
+      required: true
+
+    gpio-map-mask:
+      type: compound
+      required: false
+
+    gpio-map-pass-thru:
+      type: compound
+      required: false
+
+    "#gpio-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a GPIO specifier
diff --git a/dts/bindings/gpio/intel,gpio.yaml b/dts/bindings/gpio/intel,gpio.yaml
new file mode 100644
index 0000000000..aeb5318ed7
--- /dev/null
+++ b/dts/bindings/gpio/intel,gpio.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2018-2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel GPIO node
+
+compatible: "intel,gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    group-index:
+      type: int
+      description: Group number for this GPIO entry
+
+    interrupts:
+      required: true
+
+    ngpios:
+      required: true
+      description: Number of pins for this GPIO entry
+
+    pin-offset:
+      type: int
+      required: true
+      description: Pin offset of this GPIO entry
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ite,it8xxx2-gpio.yaml b/dts/bindings/gpio/ite,it8xxx2-gpio.yaml
new file mode 100644
index 0000000000..b2c11325fc
--- /dev/null
+++ b/dts/bindings/gpio/ite,it8xxx2-gpio.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: This binding gives a base representation of the ITE gpio
+
+compatible: "ite,it8xxx2-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/linaro,96b-lscon-1v8.yaml b/dts/bindings/gpio/linaro,96b-lscon-1v8.yaml
new file mode 100644
index 0000000000..56e43a9587
--- /dev/null
+++ b/dts/bindings/gpio/linaro,96b-lscon-1v8.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Represents GPIO pin nodes exposed on the 96Boards 1.8v low-speed header
+
+compatible: "linaro,96b-lscon-1v8"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/linaro,96b-lscon-3v3.yaml b/dts/bindings/gpio/linaro,96b-lscon-3v3.yaml
new file mode 100644
index 0000000000..2fe7a49988
--- /dev/null
+++ b/dts/bindings/gpio/linaro,96b-lscon-3v3.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2019 Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Represents GPIO pin nodes exposed on the 96Boards 3.3v low-speed header
+
+compatible: "linaro,96b-lscon-3v3"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/litex,gpio.yaml b/dts/bindings/gpio/litex,gpio.yaml
new file mode 100644
index 0000000000..487ca378d1
--- /dev/null
+++ b/dts/bindings/gpio/litex,gpio.yaml
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Litex GPIO
+
+compatible: "litex,gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    port-is-output:
+      type: boolean
+      description: Indicates if the port is an output port
+
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    ngpios:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/microbit,edge-connector.yaml b/dts/bindings/gpio/microbit,edge-connector.yaml
new file mode 100644
index 0000000000..63a3794ece
--- /dev/null
+++ b/dts/bindings/gpio/microbit,edge-connector.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2020 Micro:bit Educational Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GPIO pins exposed on BBC MicroBit headers.
+
+    The edge connector on the micro:bit is used to connect to external
+    circuits and components.
+
+    There are 25 strips/pins including 5 rings for using with 4mm banana
+    plugs or crocodile clips. 3 of these rings are for general purpose
+    input and output (GPIO) and are also capable of analog, PWM and touch
+    sensing, and two are connected to the micro:bit power supply.
+
+    The smaller strips spaced at 1.27mm on the edge connector have additional
+    signals, some of which are used by the micro:bit, and others that are free
+    for you to use. There are a number of external PCB connectors for purchase
+    with an 80w 1.27mm pitch that can be used to easily access these extra pins.
+
+    Only the pins on the front are connected to signals. The back rings are
+    connected to the front rings, but the back small strips are unconnected.
+
+compatible: "microbit,edge-connector"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/microchip,mcp230xx.yaml b/dts/bindings/gpio/microchip,mcp230xx.yaml
new file mode 100644
index 0000000000..3e08cdf840
--- /dev/null
+++ b/dts/bindings/gpio/microchip,mcp230xx.yaml
@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2021 metraTec GmbH
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: |
+    This is a representation of the Microchip MCP230xx I2C Gpio Expander.
+
+compatible: "microchip,mcp230xx"
+
+include: [gpio-controller.yaml, i2c-device.yaml]
+
+properties:
+    label:
+      required: true
+
+    ngpios:
+      type: int
+      enum:
+        - 8
+        - 16
+      required: true
+      description: |
+        Number of gpios supported by the chip.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/microchip,mcp23s17.yaml b/dts/bindings/gpio/microchip,mcp23s17.yaml
new file mode 100644
index 0000000000..4f4bd3700d
--- /dev/null
+++ b/dts/bindings/gpio/microchip,mcp23s17.yaml
@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2020 Geanix ApS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: |
+    This is a representation of the Microchip MCP23S17 SPI Gpio Expander.
+
+compatible: "microchip,mcp23s17"
+
+include: [gpio-controller.yaml, spi-device.yaml]
+
+properties:
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    ngpios:
+      type: int
+      required: true
+      const: 16
+      description: Number of gpios supported
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/microchip,mcp23sxx.yaml b/dts/bindings/gpio/microchip,mcp23sxx.yaml
new file mode 100644
index 0000000000..bef0afd1f3
--- /dev/null
+++ b/dts/bindings/gpio/microchip,mcp23sxx.yaml
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2020 Geanix ApS
+# Copyright (c) 2021 Peter Johanson
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: |
+    This is a representation of the Microchip MCP23SXX SPI Gpio Expander.
+
+compatible: "microchip,mcp23sxx"
+
+include: [gpio-controller.yaml, spi-device.yaml]
+
+properties:
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    ngpios:
+      type: int
+      required: true
+      enum:
+        - 8
+        - 16
+      description: Number of gpios supported
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/microchip,xec-gpio-v2.yaml b/dts/bindings/gpio/microchip,xec-gpio-v2.yaml
new file mode 100644
index 0000000000..97a9a70590
--- /dev/null
+++ b/dts/bindings/gpio/microchip,xec-gpio-v2.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip CEC/MEC GPIO V2 node
+
+compatible: "microchip,xec-gpio-v2"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    label:
+      required: true
+
+    port-id:
+      type: int
+      required: true
+      description: Zero based GPIO port number
+
+    girq-id:
+      type: int
+      required: true
+      description: Aggregated GIRQ number for this bank of 32 GPIO pins.
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/microchip,xec-gpio.yaml b/dts/bindings/gpio/microchip,xec-gpio.yaml
new file mode 100644
index 0000000000..b46add5847
--- /dev/null
+++ b/dts/bindings/gpio/microchip,xec-gpio.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip CEC/MEC GPIO node
+
+compatible: "microchip,xec-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/mikro-bus.yaml b/dts/bindings/gpio/mikro-bus.yaml
new file mode 100644
index 0000000000..526bc11200
--- /dev/null
+++ b/dts/bindings/gpio/mikro-bus.yaml
@@ -0,0 +1,33 @@
+# Copyright (C) 2020 Linaro
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GPIO pins exposed on Mikro BUS headers.
+
+    The Mikro BUS layout provides two headers, aligned on the opposite
+    edges of the board.
+
+    Documentation:
+    * https://www.mikroe.com/mikrobus
+    * https://download.mikroe.com/documents/standards/mikrobus/mikrobus-standard-specification-v200.pdf
+
+    This binding provides a nexus mapping for 10 pins, left side pins are
+    numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
+    (PWM - SDA). The bottom 2 pins on each side are used for input voltage
+    and ground, they are not mapped in the nexus.
+
+                           Analog - AN     PWM - PWM output
+                            Reset - RST    INT - Hardware Interrupt
+                  SPI Chip Select - CS      RX - UART Receive
+                        SPI Clock - SCK     TX - UART Transmit
+    SPI Master Input Slave Output - MISO   SCL - I2C Clock
+    SPI Master Output Slave Input - MOSI   SDA - I2C Data
+                   VCC-3.3V power - +3.3V  +5V - VCC-5V power
+                 Reference Ground - GND    GND - Reference Ground
+
+    Board's silkscreen may vary depending you board, but coherent with
+    the description above as it's according to the standard's specification.
+
+compatible: "mikro-bus"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/neorv32-gpio.yaml b/dts/bindings/gpio/neorv32-gpio.yaml
new file mode 100644
index 0000000000..1cb175d740
--- /dev/null
+++ b/dts/bindings/gpio/neorv32-gpio.yaml
@@ -0,0 +1,25 @@
+description: NEORV32 GPIO
+
+compatible: "neorv32-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    reg-names:
+      required: true
+
+    syscon:
+      type: phandle
+      required: true
+      description: |
+        phandle to syscon (NEORV32 SYSINFO) node.
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nordic,nrf-gpio.yaml b/dts/bindings/gpio/nordic,nrf-gpio.yaml
new file mode 100644
index 0000000000..be586752ae
--- /dev/null
+++ b/dts/bindings/gpio/nordic,nrf-gpio.yaml
@@ -0,0 +1,41 @@
+# Copyright (c) 2018, marc-cpdesign
+# SPDX-License-Identifier: Apache-2.0
+
+description: NRF5 GPIO node
+
+compatible: "nordic,nrf-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    sense-edge-mask:
+      required: false
+      type: int
+      description: |
+        Mask of pins that use the GPIO sense mechanism for edge detection.
+        Pins not included in the mask use GPIOTE channels in the event mode.
+
+    port:
+      type: int
+      required: true
+      description: |
+        The GPIO port number. GPIO port P0 has:
+
+          port = <0>;
+
+        And P1 has:
+
+          port = <1>;
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nordic,nrf-gpiote.yaml b/dts/bindings/gpio/nordic,nrf-gpiote.yaml
new file mode 100644
index 0000000000..a774105091
--- /dev/null
+++ b/dts/bindings/gpio/nordic,nrf-gpiote.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, marc-cpdesign
+# SPDX-License-Identifier: Apache-2.0
+
+description: NRF5 GPIOTE node
+
+compatible: "nordic,nrf-gpiote"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/gpio/nuvoton,nct38xx-gpio-alert.yaml b/dts/bindings/gpio/nuvoton,nct38xx-gpio-alert.yaml
new file mode 100644
index 0000000000..01a4c0e720
--- /dev/null
+++ b/dts/bindings/gpio/nuvoton,nct38xx-gpio-alert.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Nuvoton NCT38XX series I2C-based GPIO expander alert handler
+
+    Example:
+      nct3807_alert_1 {
+        compatible = "nuvoton,nct38xx-gpio-alert";
+        irq-gpios = <&gpiod 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+        nct38xx-dev = <&nct3808_0_P1 &nct3808_0_P2>;
+        label = "NCT3808_ALERT_0";
+      };
+
+compatible: "nuvoton,nct38xx-gpio-alert"
+
+include: [base.yaml]
+
+properties:
+    label:
+      required: true
+
+    irq-gpios:
+      type: phandle-array
+      required: true
+      description: Interrupt GPIO pin
+
+    nct38xx-dev:
+      type: phandles
+      required: true
+      description: |
+        NCT38XX devices which alert are handled by this alert handler.
diff --git a/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml b/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml
new file mode 100644
index 0000000000..13b9c46279
--- /dev/null
+++ b/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml
@@ -0,0 +1,44 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton NCT38XX series I2C-based GPIO expander port
+
+compatible: "nuvoton,nct38xx-gpio-port"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    pin_mask:
+      type: int
+      required: true
+      description: |
+        Not every GPIOs are usable for different NCT38XX series. This property
+        indicates the usable GPIO mask.
+
+        NCT3808: <0xdc>
+        others: <0xff>
+
+    pinmux_mask:
+      type: int
+      required: false
+      description: |
+        NCT38XX series port 0 has Pin Multiplexing functionality. However, not
+        every GPIOs have pinmux controller functionality. This property
+        indicates the usable GPIO pinmux mask. For port 1, this property is
+        ignored.
+
+        NCT3807 port 0: <0xf7>
+        others: <0xff>
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nuvoton,nct38xx-gpio.yaml b/dts/bindings/gpio/nuvoton,nct38xx-gpio.yaml
new file mode 100644
index 0000000000..9e5aae27fa
--- /dev/null
+++ b/dts/bindings/gpio/nuvoton,nct38xx-gpio.yaml
@@ -0,0 +1,83 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Nuvoton NCT38XX series I2C-based GPIO expander
+
+    Example:
+      &i2c0_0 {
+        nct3807@70 {
+          #address-cells = <1>;
+          #size-cells = <0>;
+          compatible = "nuvoton,nct38xx-gpio";
+          reg = <0x70>;
+          label = "NCT3807_0";
+
+          gpio@0 {
+            compatible = "nuvoton,nct38xx-gpio-port";
+            reg = <0x0>;
+            label = "NCT3807_0_GPIO0";
+            gpio-controller;
+            #gpio-cells = <2>;
+            ngpios = <8>;
+            pin_mask = <0xff>;
+            pinmux_mask = <0xf7>;
+          };
+
+          gpio@1 {
+            compatible = "nuvoton,nct38xx-gpio-port";
+            reg = <0x1>;
+            label = "NCT3807_0_GPIO1";
+            gpio-controller;
+            #gpio-cells = <2>;
+            ngpios = <8>;
+            pin_mask = <0xff>;
+          };
+        };
+
+        nct3808_0_P1@71 {
+          #address-cells = <1>;
+          #size-cells = <0>;
+          compatible = "nuvoton,nct38xx-gpio";
+          reg = <0x71>;
+          label = "NCT3808_0_P1";
+
+          gpio@0 {
+            compatible = "nuvoton,nct38xx-gpio-port";
+            reg = <0x0>;
+            label = "NCT3808_0_P1_GPIO0";
+            gpio-controller;
+            #gpio-cells = <2>;
+            ngpios = <8>;
+            pin_mask = <0xdc>;
+            pinmux_mask = <0xff>;
+          };
+        };
+
+        nct3808_0_P2@75 {
+          #address-cells = <1>;
+          #size-cells = <0>;
+          compatible = "nuvoton,nct38xx-gpio";
+          reg = <0x75>;
+          label = "NCT3808_0_P2";
+
+          gpio@0 {
+            compatible = "nuvoton,nct38xx-gpio-port";
+            reg = <0x0>;
+            label = "NCT3808_0_P2_GPIO0";
+            gpio-controller;
+            #gpio-cells = <2>;
+            ngpios = <8>;
+            pin_mask = <0xdc>;
+            pinmux_mask = <0xff>;
+          };
+        };
+      };
+
+compatible: "nuvoton,nct38xx-gpio"
+
+include: [i2c-device.yaml]
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/gpio/nuvoton,npcx-gpio.yaml b/dts/bindings/gpio/nuvoton,npcx-gpio.yaml
new file mode 100644
index 0000000000..ca084505b4
--- /dev/null
+++ b/dts/bindings/gpio/nuvoton,npcx-gpio.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-GPIO node
+
+compatible: "nuvoton,npcx-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+        required: true
+
+    label:
+        required: true
+
+    index:
+        type: int
+        required: true
+        description: index of gpio device
+
+    wui-maps:
+        type: phandles
+        required: true
+        description: |
+            Mapping table between Wake-Up Input (WUI) and 8 IOs belong to this device.
+            Please notice not all IOs connect to WUIs.
+            In this case, it will be presented by wui_none.
+
+            For example the WUI mapping on NPCX7 GPIO8 would be
+               wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
+                           &wui_none &wui_none &wui_io86 &wui_io87>;
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nuvoton,npcx-psl-out.yaml b/dts/bindings/gpio/nuvoton,npcx-psl-out.yaml
new file mode 100644
index 0000000000..f220e72c27
--- /dev/null
+++ b/dts/bindings/gpio/nuvoton,npcx-psl-out.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-PSL (Power Switch Logic) Output node
+
+compatible: "nuvoton,npcx-psl-out"
+
+include: [base.yaml]
+
+properties:
+    controller:
+        type: phandle
+        required: true
+        description: gpio controller to handle PSL output pad.
+
+    pin:
+        type: int
+        required: true
+        description: pin in gpio controller for PSL output.
diff --git a/dts/bindings/gpio/nxp,imx-gpio.yaml b/dts/bindings/gpio/nxp,imx-gpio.yaml
new file mode 100644
index 0000000000..38a8e0c555
--- /dev/null
+++ b/dts/bindings/gpio/nxp,imx-gpio.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX GPIO node
+
+compatible: "nxp,imx-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    label:
+      required: true
+
+    rdc:
+     type: int
+     required: false
+     description: Set the RDC permission for this peripheral
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nxp,kinetis-gpio.yaml b/dts/bindings/gpio/nxp,kinetis-gpio.yaml
new file mode 100644
index 0000000000..d6ef88e2cc
--- /dev/null
+++ b/dts/bindings/gpio/nxp,kinetis-gpio.yaml
@@ -0,0 +1,26 @@
+description: Kinetis GPIO node
+
+compatible: "nxp,kinetis-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    nxp,kinetis-port:
+      required: true
+      type: phandle
+      description: |
+        A phandle reference to the device tree node that contains the pinmux
+        port associated with this GPIO controller.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nxp,lpc-gpio.yaml b/dts/bindings/gpio/nxp,lpc-gpio.yaml
new file mode 100644
index 0000000000..6f161fa920
--- /dev/null
+++ b/dts/bindings/gpio/nxp,lpc-gpio.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC GPIO node
+
+compatible: "nxp,lpc-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    port:
+      type: int
+      required: true
+      description: The GPIO port this node describes
+      enum:
+        - 0
+        - 1
+        - 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml b/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml
new file mode 100644
index 0000000000..a6f8ff3282
--- /dev/null
+++ b/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml
@@ -0,0 +1,41 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC11U6X GPIO node
+
+compatible: "nxp,lpc11u6x-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    base:
+      type: int
+      required: false
+      default: 0
+      description: index of the first GPIO for this port.
+
+    clocks:
+      required: true
+
+    pinmux-port:
+      required: true
+      type: phandle
+      description: |
+        a phandle reference to the device tree node that contains the pinmux
+        port associated with this GPIO controller.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nxp,pca95xx.yaml b/dts/bindings/gpio/nxp,pca95xx.yaml
new file mode 100644
index 0000000000..4039f82316
--- /dev/null
+++ b/dts/bindings/gpio/nxp,pca95xx.yaml
@@ -0,0 +1,29 @@
+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: PCA95xx series I2C-based GPIO expander
+
+compatible: "nxp,pca95xx"
+
+include: [gpio-controller.yaml, i2c-device.yaml]
+
+properties:
+    label:
+      required: true
+
+    has-pud:
+      type: boolean
+      required: false
+      description: Supports pull-up/pull-down
+
+    interrupt-gpios:
+      type: phandle-array
+      required: false
+      description: Interrupt GPIO pin (active-low open-drain)
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nxp,pcal6408a.yaml b/dts/bindings/gpio/nxp,pcal6408a.yaml
new file mode 100644
index 0000000000..857b2c4b9f
--- /dev/null
+++ b/dts/bindings/gpio/nxp,pcal6408a.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: PCAL6408A 8-bit I2C-based I/O expander
+
+compatible: "nxp,pcal6408a"
+
+include: [i2c-device.yaml, gpio-controller.yaml]
+
+properties:
+    label:
+      required: true
+
+    ngpios:
+      required: true
+      const: 8
+
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        GPIO connected to the controller INT pin. This pin is active-low.
+
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        GPIO connected to the controller RESET pin. This pin is active-low.
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/openisa,rv32m1-gpio.yaml b/dts/bindings/gpio/openisa,rv32m1-gpio.yaml
new file mode 100644
index 0000000000..e54606bf13
--- /dev/null
+++ b/dts/bindings/gpio/openisa,rv32m1-gpio.yaml
@@ -0,0 +1,29 @@
+description: OpenISA GPIO node
+
+compatible: "openisa,rv32m1-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    openisa,rv32m1-port:
+      required: true
+      type: phandle
+      description: |
+        A phandle reference to the device tree node that contains the pinmux
+        port associated with this GPIO controller.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/particle-gen3-header.yaml b/dts/bindings/gpio/particle-gen3-header.yaml
new file mode 100644
index 0000000000..d80e5c2f55
--- /dev/null
+++ b/dts/bindings/gpio/particle-gen3-header.yaml
@@ -0,0 +1,43 @@
+# Copyright (C) 2020 Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GPIO pins exposed on Particle Gen3 (Feather) headers.
+
+    The Particle Gen3 boards are compatible with the Adafruit Feather
+    "shields" but use a different orientation and pin numbering scheme.
+
+    With the board oriented with the micro USB at the top:
+    * A 12-pin header on the right.  9 pins on this header are exposed
+      by this binding
+    * A 16-pin header.  13 pins on this header are exposed by this
+      binding.
+
+    This binding provides a nexus mapping for 22 pins where parent pins
+    0 through 8 correspond to the pins on the 12-pin header, starting
+    from the bottom; and pins 9 through 21 correspond to pins on the
+    16-pin header, skipping the bottom pin then assigning 9 through 19,
+    skipping over GND, and replacing the lower 3V3 with pin 20.  The
+    physical layout is depicted below.
+
+        21 RESETn
+        -  3V3
+        20 MODEn
+        -  GND
+        19 ADC0                  LiPo+   -
+        18 ADC1                  ENABLE  -
+        17 ADC2                  VBUS    -
+        16 ADC3                  PWM1    8
+        15 ADC4                  PWM0    7
+        14 SS                    PWM1    6
+        13 SCK                   PWM1    5
+        12 MOSI                  PWM1    4
+        11 MISO                  PWM3    3
+        10 RX                    PWM3    2
+         9 TX                    SCL     1
+        -  n/c                   SDA     0
+
+
+compatible: "particle-gen3-header"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml b/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml
new file mode 100644
index 0000000000..1a17abed23
--- /dev/null
+++ b/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml
@@ -0,0 +1,39 @@
+description: EOS S3 GPIO node
+
+compatible: "quicklogic,eos-s3-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    pin-secondary-config:
+      type: int
+      required: true
+      description: |
+          This property is used to preconfigure the GPIOs and connect them to
+          a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs
+          which can be configured as follows
+          "GPIO_NUM : primary_pin_num / secondary_pin_num"
+          "0 : 6 / 24"
+          "1 : 9 / 26"
+          "2 : 11 / 28"
+          "3 : 14 / 30"
+          "4 : 18 / 31"
+          "5 : 21 / 36"
+          "6 : 22 / 38"
+          "7 : 23 / 45"
+          E.g. configuring GPIO 2 as secondary results in controlling pin 28,
+          to do so set the bit on the 2nd index of this property
+          "pin-secondary-config = <0x04>;"
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/renesas,rcar-gpio.yaml b/dts/bindings/gpio/renesas,rcar-gpio.yaml
new file mode 100644
index 0000000000..413ab0c1a4
--- /dev/null
+++ b/dts/bindings/gpio/renesas,rcar-gpio.yaml
@@ -0,0 +1,28 @@
+#
+# Copyright (c) 2020 IoT.bzh
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Renesas RCAR GPIO
+
+compatible: "renesas,rcar-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/seeed-xiao-header.yaml b/dts/bindings/gpio/seeed-xiao-header.yaml
new file mode 100644
index 0000000000..f605184bb0
--- /dev/null
+++ b/dts/bindings/gpio/seeed-xiao-header.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2019 Foundries.io
+# Copyright (C) 2019 Peter Bigot Consulting, LLC
+# Copyright (C) 2021 Peter Johanson
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GPIO pins exposed on Seeeduino Xiao (and compatible devices) headers.
+
+    The Seeeeduino Xiao layout provides two headers, along opposite
+    edges of the board.
+
+    Proceeding counter-clockwise:
+    * A 7-pin Digital/Analog Input header.  This has input signals
+      labeled from 0 at the top through 6 at the bottom.
+    * An 7-pin header Power and Digital/Analog Input header.  This
+      has three power pins, followed by four inputs labeled 10 at the
+      top through 7 at the bottom.
+
+    This binding provides a nexus mapping for 10 pins where parent pins 0
+    through 10 correspond to D0 through D10, as depicted below:
+
+        0 D0                     5V   -
+        1 D1                     GND  -
+        2 D2                     3V3  -
+        3 D3                     D10 10
+        4 A4                     D9   9
+        5 D5                     D8   8
+        6 D6                     D7   7
+
+
+compatible: "seeed,xiao-gpio"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/semtech,sx1509b.yaml b/dts/bindings/gpio/semtech,sx1509b.yaml
new file mode 100644
index 0000000000..8d88e5af63
--- /dev/null
+++ b/dts/bindings/gpio/semtech,sx1509b.yaml
@@ -0,0 +1,46 @@
+# Copyright (c) 2018, Aapo Vienamo
+# SPDX-License-Identifier: Apache-2.0
+
+description: SX1509B GPIO node
+
+compatible: "semtech,sx1509b"
+
+include: [i2c-device.yaml, gpio-controller.yaml]
+
+properties:
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    ngpios:
+      required: true
+      const: 16
+
+    nint-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Connection for the NINT signal. This signal is active-low when
+        produced by sx1509b GPIO node.
+
+    init-out-low:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Bit mask identifying pins that should be initialized as outputs
+        driven low.
+
+    init-out-high:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Bit mask identifying pins that should be initialized as outputs
+        driven high.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/sifive,gpio0.yaml b/dts/bindings/gpio/sifive,gpio0.yaml
new file mode 100644
index 0000000000..d30d26af26
--- /dev/null
+++ b/dts/bindings/gpio/sifive,gpio0.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2018, SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive GPIO node
+
+compatible: "sifive,gpio0"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/silabs,gecko-gpio-port.yaml b/dts/bindings/gpio/silabs,gecko-gpio-port.yaml
new file mode 100644
index 0000000000..ed78f6a47a
--- /dev/null
+++ b/dts/bindings/gpio/silabs,gecko-gpio-port.yaml
@@ -0,0 +1,24 @@
+description: SiLabs Gecko GPIO port node
+
+compatible: "silabs,gecko-gpio-port"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: peripheral ID
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/silabs,gecko-gpio.yaml b/dts/bindings/gpio/silabs,gecko-gpio.yaml
new file mode 100644
index 0000000000..7cf803ed3a
--- /dev/null
+++ b/dts/bindings/gpio/silabs,gecko-gpio.yaml
@@ -0,0 +1,20 @@
+description: SiLabs Gecko GPIO node
+
+compatible: "silabs,gecko-gpio"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    location-swo:
+      type: int
+      required: false
+      description: Serial Wire Output (SWO) PIN location
diff --git a/dts/bindings/gpio/snps,creg-gpio.yaml b/dts/bindings/gpio/snps,creg-gpio.yaml
new file mode 100644
index 0000000000..0bf9b713e7
--- /dev/null
+++ b/dts/bindings/gpio/snps,creg-gpio.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2021 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys CREG GPIO node
+
+compatible: "snps,creg-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    bit_per_gpio:
+      type: int
+      required: true
+
+    off_val:
+      type: int
+      required: true
+
+    on_val:
+      type: int
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/snps,designware-gpio.yaml b/dts/bindings/gpio/snps,designware-gpio.yaml
new file mode 100644
index 0000000000..40db115d22
--- /dev/null
+++ b/dts/bindings/gpio/snps,designware-gpio.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys DesignWare GPIO node
+
+compatible: "snps,designware-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/st,stm32-gpio.yaml b/dts/bindings/gpio/st,stm32-gpio.yaml
new file mode 100644
index 0000000000..62bf1fac09
--- /dev/null
+++ b/dts/bindings/gpio/st,stm32-gpio.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 GPIO node
+
+compatible: "st,stm32-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    clocks:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/st,stmpe1600.yaml b/dts/bindings/gpio/st,stmpe1600.yaml
new file mode 100644
index 0000000000..60249d2368
--- /dev/null
+++ b/dts/bindings/gpio/st,stmpe1600.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021 Titouan Christophe
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMPE1600 I2C-based GPIO expander
+
+compatible: "st,stmpe1600"
+
+include: [gpio-controller.yaml, i2c-device.yaml]
+
+properties:
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/telink,b91-gpio.yaml b/dts/bindings/gpio/telink,b91-gpio.yaml
new file mode 100644
index 0000000000..902be6ebb7
--- /dev/null
+++ b/dts/bindings/gpio/telink,b91-gpio.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2021, Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink B91 GPIO node
+
+compatible: "telink,b91-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ti,boosterpack-header.yaml b/dts/bindings/gpio/ti,boosterpack-header.yaml
new file mode 100644
index 0000000000..af7f0e5c4a
--- /dev/null
+++ b/dts/bindings/gpio/ti,boosterpack-header.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2019 Brett Witherspoon
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    TI BoosterPack GPIO header
+
+    GPIO pins exposed as BoosterPack headers on TI LaunchPads.
+
+    BoosterPack plug-in modules are available in 20 and 40 pin variants. The
+    20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
+    10 x 2 pin headers. Both variants are compatible and stackable.
+
+    The pins of the 20 pin variant and the outer row of the 40 pin variant are
+    numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
+    through 40. The BoosterPack pinout is depicted below:
+
+    1  3.3V     21 5V                    40 GPIO 20 GND
+    2  Analog   22 GND                   39 GPIO 19 GPIO / SPI CS
+    3  UART RXD 23 Analog                38 GPIO 18 GPIO
+    4  UART TXD 24 Analog                37 GPIO 17 GPIO
+    5  GPIO     25 Analog                36 GPIO 16 RESET
+    6  Analog   26 Analog                35 GPIO 15 SPI MOSI
+    7  SPI CLK  27 Analog                34 GPIO 14 SPI MISO
+    8  GPIO     28 Analog                33 GPIO 13 GPIO / SPI CS
+    9  I2C SCL  29                       32 GPIO 12 GPIO / SPI CS
+    10 I2C SDA  30                       31 GPIO 11 GPIO
+
+    Additional information about the BoosterPack pinout can be found at
+    http://processors.wiki.ti.com/index.php/BYOB or in the documentation for
+    a TI LaunchPad development kit,
+
+compatible: "ti,boosterpack-header"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml b/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml
new file mode 100644
index 0000000000..b0e5e02ca4
--- /dev/null
+++ b/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2019 Brett Witherspoon
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC13xx / CC26xx GPIO node
+
+compatible: "ti,cc13xx-cc26xx-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ti,cc32xx-gpio.yaml b/dts/bindings/gpio/ti,cc32xx-gpio.yaml
new file mode 100644
index 0000000000..63ea566138
--- /dev/null
+++ b/dts/bindings/gpio/ti,cc32xx-gpio.yaml
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+description: TI CC32XX GPIO node
+
+compatible: "ti,cc32xx-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml b/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml
new file mode 100644
index 0000000000..13dd416c62
--- /dev/null
+++ b/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml
@@ -0,0 +1,18 @@
+description: TI LMP90xxx GPIO controller binding
+
+compatible: "ti,lmp90xxx-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+on-bus: lmp90xxx
+
+properties:
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ti,stellaris-gpio.yaml b/dts/bindings/gpio/ti,stellaris-gpio.yaml
new file mode 100644
index 0000000000..2d22961bac
--- /dev/null
+++ b/dts/bindings/gpio/ti,stellaris-gpio.yaml
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI Stellaris GPIO node
+
+compatible: "ti,stellaris-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ti,tca9538.yaml b/dts/bindings/gpio/ti,tca9538.yaml
new file mode 100644
index 0000000000..c5c9127f96
--- /dev/null
+++ b/dts/bindings/gpio/ti,tca9538.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2018, Aapo Vienamo
+# Copyright (c) 2021, Laird Connectivity
+# SPDX-License-Identifier: Apache-2.0
+
+description: TCA9538 GPIO node
+
+compatible: "ti,tca9538"
+
+include: [i2c-device.yaml, gpio-controller.yaml]
+
+properties:
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+    ngpios:
+      required: true
+      const: 8
+      description: |
+        Number of GPIOs available on port expander.
+
+    nint-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Connection for the NINT signal. This signal is active-low when
+        produced by tca9538 GPIO node.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml
new file mode 100644
index 0000000000..eb579cb9cb
--- /dev/null
+++ b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml
@@ -0,0 +1,18 @@
+description: Xilinx AXI GPIO IP GPIO2 node
+
+compatible: "xlnx,xps-gpio-1.00.a-gpio2"
+
+include: [gpio-controller.yaml, base.yaml]
+
+on-bus: xlnx,xps-gpio-1.00.a
+
+properties:
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml
new file mode 100644
index 0000000000..3d55d5f690
--- /dev/null
+++ b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml
@@ -0,0 +1,79 @@
+description: Xilinx AXI GPIO IP node
+
+compatible: "xlnx,xps-gpio-1.00.a"
+
+include: [gpio-controller.yaml, base.yaml]
+
+bus: xlnx,xps-gpio-1.00.a
+
+# Property names correspond to a subset of those generated by
+# https://github.com/Xilinx/device-tree-xlnx
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    xlnx,all-inputs:
+      type: int
+      description: |
+        1 if all GPIOs are inputs, 0 otherwise
+
+    xlnx,all-outputs:
+      type: int
+      description: |
+        1 if all GPIOs are outputs, 0 otherwise
+
+    xlnx,dout-default:
+      type: int
+      description: |
+        Default output value. If n-th bit is 1, GPIO-n default value is 1.
+
+    xlnx,gpio-width:
+      type: int
+      description: |
+        Number of GPIOs supported
+
+    xlnx,tri-default:
+      type: int
+      description: |
+        Default tristate register value. If n-th bit is 1, GPIO-n is an input.
+
+    xlnx,is-dual:
+      type: int
+      description: |
+        1 if controller has GPIO2 enabled, 0 otherwise
+
+    xlnx,all-inputs-2:
+      type: int
+      description: |
+        1 if all GPIO2s are inputs, 0 otherwise
+
+    xlnx,all-outputs-2:
+      type: int
+      description: |
+        1 if all GPIO2s are outputs, 0 otherwise
+
+    xlnx,dout-default-2:
+      type: int
+      description: |
+        Default output value. If n-th bit is 1, GPIO2-n default value is 1.
+
+    xlnx,gpio2-width:
+      type: int
+      description: |
+        Number of GPIO2s supported
+
+    xlnx,tri-default-2:
+      type: int
+      description: |
+        Default tristate register value. If n-th bit is 1, GPIO2-n is an input.
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/zephyr,gpio-emul.yaml b/dts/bindings/gpio/zephyr,gpio-emul.yaml
new file mode 100644
index 0000000000..69ac5a7148
--- /dev/null
+++ b/dts/bindings/gpio/zephyr,gpio-emul.yaml
@@ -0,0 +1,38 @@
+# Copyright 2020, Friedt Professional Engineering Services, Inc
+# SPDX-License-Identifier: Apache-2.0
+
+description: GPIO Emulator
+
+compatible: "zephyr,gpio-emul"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    rising-edge:
+      description: Enables support for rising edge interrupt detection
+      type: boolean
+
+    falling-edge:
+      description: Enables support for falling edge interrupt detection
+      type: boolean
+
+    high-level:
+      description: Enables support for high level interrupt detection
+      type: boolean
+
+    low-level:
+      description: Enables support for low level interrupt detection
+      type: boolean
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/hwinfo/atmel,sam4l-uid.yaml b/dts/bindings/hwinfo/atmel,sam4l-uid.yaml
new file mode 100644
index 0000000000..a8a76aa134
--- /dev/null
+++ b/dts/bindings/hwinfo/atmel,sam4l-uid.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ATMEL SAM4L Unique 120-bit Serial Number
+
+compatible: "atmel,sam4l-uid"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
diff --git a/dts/bindings/hwinfo/cypress,psoc6-uid.yaml b/dts/bindings/hwinfo/cypress,psoc6-uid.yaml
new file mode 100644
index 0000000000..d713960dd2
--- /dev/null
+++ b/dts/bindings/hwinfo/cypress,psoc6-uid.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2020 ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress PSoC-6 Unique 88-bit Serial Number
+
+compatible: "cypress,psoc6-uid"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
diff --git a/dts/bindings/hwinfo/litex,dna0.yaml b/dts/bindings/hwinfo/litex,dna0.yaml
new file mode 100644
index 0000000000..64e4f4e206
--- /dev/null
+++ b/dts/bindings/hwinfo/litex,dna0.yaml
@@ -0,0 +1,12 @@
+# Copyright (c)  2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX DNA ID reader
+
+compatible: "litex,dna0"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
diff --git a/dts/bindings/hwinfo/nxp,lpc-uid.yaml b/dts/bindings/hwinfo/nxp,lpc-uid.yaml
new file mode 100644
index 0000000000..9d47c3b715
--- /dev/null
+++ b/dts/bindings/hwinfo/nxp,lpc-uid.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC 128-bit Unique identifier
+
+compatible: "nxp,lpc-uid"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
diff --git a/dts/bindings/i2c/altr,nios2-i2c.yaml b/dts/bindings/i2c/altr,nios2-i2c.yaml
new file mode 100644
index 0000000000..87a87504e2
--- /dev/null
+++ b/dts/bindings/i2c/altr,nios2-i2c.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Altera NIOS2 I2C
+
+compatible: "altr,nios2-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/i2c/arm,versatile-i2c.yaml b/dts/bindings/i2c/arm,versatile-i2c.yaml
new file mode 100644
index 0000000000..2f7c145cb1
--- /dev/null
+++ b/dts/bindings/i2c/arm,versatile-i2c.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM SBCon two-wire serial bus interface
+
+compatible: "arm,versatile-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/i2c/asmedia,asm2364.yaml b/dts/bindings/i2c/asmedia,asm2364.yaml
new file mode 100644
index 0000000000..312becb7bf
--- /dev/null
+++ b/dts/bindings/i2c/asmedia,asm2364.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: ASMedia ASM2364 USB-to-PCIe bridge controller
+
+compatible: "asmedia,asm2364"
+
+include: base.yaml
+
+on-bus: i2c
+
+properties:
+  int-gpios:
+    type: phandle-array
+    required: true
+    description: Interrupt GPIO for read requests
diff --git a/dts/bindings/i2c/atmel,sam-i2c-twi.yaml b/dts/bindings/i2c/atmel,sam-i2c-twi.yaml
new file mode 100644
index 0000000000..800f0e6a8e
--- /dev/null
+++ b/dts/bindings/i2c/atmel,sam-i2c-twi.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2017 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Family I2C (TWI) node
+
+compatible: "atmel,sam-i2c-twi"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
+      description: |
+        PIO pin configuration for TWCK & TWD signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the I2C on SAM3x would be
+           pinctrl-0 = <&pa18a_twi0_twck0 &pa17a_twi0_twd0>;
diff --git a/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml b/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml
new file mode 100644
index 0000000000..85e76d6593
--- /dev/null
+++ b/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2017 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Family I2C (TWIHS) node
+
+compatible: "atmel,sam-i2c-twihs"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
+      description: |
+        PIO pin configuration for TWCK & TWD signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the I2C on SAME7x would be
+           pinctrl-0 = <&pa4a_twihs0_twck0 &pa3a_twihs0_twd0>;
diff --git a/dts/bindings/i2c/atmel,sam-i2c-twim.yaml b/dts/bindings/i2c/atmel,sam-i2c-twim.yaml
new file mode 100644
index 0000000000..c373f5d5ee
--- /dev/null
+++ b/dts/bindings/i2c/atmel,sam-i2c-twim.yaml
@@ -0,0 +1,215 @@
+# Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Atmel SAM4L Family I2C (TWIM) node
+
+  The Atmel Two-wire Master Interface (TWIM) interconnects components on a
+  unique two-wire bus, made up of one clock line and one data line with speeds
+  of up to 3.4 Mbit/s, based on a byte-oriented transfer format.  The TWIM is
+  always a bus master and can transfer sequential or single bytes.  Multiple
+  master capability is supported.  Arbitration of the bus is performed
+  internally and relinquishes the bus automatically if the bus arbitration is
+  lost.
+
+  When using speeds above standard mode, user may need adjust clock and data
+  lines slew and strength parameters.  In general, slew 0 and minimal strength
+  is enougth for short buses and light loads.  As reference, the below
+  is the lowest power configuration:
+
+    std-clk-slew-lim = <0>;
+    std-clk-strength-low = "0.5";
+    std-data-slew-lim = <0>;
+    std-data-strength-low = "0.5";
+
+    hs-clk-slew-lim = <0>;
+    hs-clk-strength-high = "0.5";
+    hs-clk-strength-low = "0.5";
+    hs-data-slew-lim = <0>;
+    hs-data-strength-low = "0.5";
+
+  For best performances, user can tune the slope curves using an osciloscope.
+  The tuning should be performed by groups defined <mode>-<line>.  The prefix
+  std-<line> configures fast/fast-plus mode speeds and hs-<line> selects the
+  high speed mode.  The tune should be performed for both clock and data lines
+  on both speed modes.
+
+
+compatible: "atmel,sam-i2c-twim"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: peripheral ID
+
+    std-clk-slew-lim:
+      type: int
+      required: true
+      description: |
+        Slew limit of the TWCK output buffer.  This should be adjusted with
+        std-clk-strength-low to fine tune the TWCK slope.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+
+    std-clk-strength-low:
+      type: string
+      required: true
+      description: |
+        Pull-down drive strength of the TWCK output buffer in fast/fast plus
+        mode.  This should be adjusted to provide proper TWCK line fall time.
+        The value represents the port output current in mA when signal on
+        low level.
+      enum:
+        - "0.5"
+        - "1.0"
+        - "1.6"
+        - "3.1"
+        - "6.2"
+        - "9.3"
+        - "15.5"
+        - "21.8"
+
+    std-data-slew-lim:
+      type: int
+      required: true
+      description: |
+        Slew limit of the TWD output buffer.  This should be adjusted with
+        std-data-strength-low to fine tune the TWD slope.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+
+    std-data-strength-low:
+      type: string
+      required: true
+      description: |
+        Pull-down drive strength of the TWD output buffer in fast/fast plus
+        mode.  This should be adjusted to provide proper TWD line fall time.
+        The value represents the port output current in mA when signal on
+        low level.
+      enum:
+        - "0.5"
+        - "1.0"
+        - "1.6"
+        - "3.1"
+        - "6.2"
+        - "9.3"
+        - "15.5"
+        - "21.8"
+
+    hs-clk-slew-lim:
+      type: int
+      required: true
+      description: |
+        Slew limit of the TWCK output buffer in high speed mode.  This
+        should be adjusted with both hs-clk-strength-high and
+        hs-clk-strength-low to fine tune the TWCK slope.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+
+    hs-clk-strength-high:
+      type: string
+      required: true
+      description: |
+        Pull-up drive strength of the TWCK output buffer in high speed
+        mode.  This should be adjusted to provide proper TWCK line rise time.
+        The value represents the port output current in mA when signal on
+        high level.
+      enum:
+        - "0.5"
+        - "1.0"
+        - "1.5"
+        - "3.0"
+
+    hs-clk-strength-low:
+      type: string
+      required: true
+      description: |
+        Pull-down drive strength of the TWCK output buffer in high speed
+        mode.  This should be adjusted to provide proper TWCK line fall time.
+        The value represents the port output current in mA when signal on
+        low level.
+      enum:
+        - "0.5"
+        - "1.0"
+        - "1.6"
+        - "3.1"
+        - "6.2"
+        - "9.3"
+        - "15.5"
+        - "21.8"
+
+    hs-data-slew-lim:
+      type: int
+      required: true
+      description: |
+        Slew limit of the TWD output buffer in high speed mode.  This
+        should be adjusted with hs-data-strength-low to fine tune the TWD
+        slope.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+
+    hs-data-strength-low:
+      type: string
+      description: |
+        Pull-down drive strength of the TWD output buffer in high speed
+        mode.  This should be adjusted to provide proper TWD line fall time.
+        The value represents the port output current in mA when signal on
+        low level.
+      enum:
+        - "0.5"
+        - "1.0"
+        - "1.6"
+        - "3.1"
+        - "6.2"
+        - "9.3"
+        - "15.5"
+        - "21.8"
+
+    hs-master-code:
+      type: int
+      required: true
+      description: |
+        3-bit code to be prefixed with 0b00001 to form a unique
+        8-bit HS-mode master code (0000 1XXX)
+      enum:
+        - 0   # 000
+        - 1   # 001
+        - 2   # 010
+        - 3   # 011
+        - 4   # 100
+        - 5   # 101
+        - 6   # 110
+        - 7   # 111
+
+    pinctrl-0:
+      type: phandles
+      required: true
+      description: |
+        GPIO pin configuration for TWCK & TWD signals. We expect that
+        the phandles will reference pinctrl nodes. These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the I2C on SAM4L would be
+           pinctrl-0 = <&pb0a_twi1_twd1 &pb1a_twi1_twck1>;
diff --git a/dts/bindings/i2c/atmel,sam0-i2c.yaml b/dts/bindings/i2c/atmel,sam0-i2c.yaml
new file mode 100644
index 0000000000..aacf61f3e2
--- /dev/null
+++ b/dts/bindings/i2c/atmel,sam0-i2c.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 series SERCOM I2C node
+
+compatible: "atmel,sam0-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    clock-names:
+      required: true
+
+    dmas:
+      description: |
+        Optional TX & RX dma specifiers.  Each specifier will have a phandle
+        reference to the dmac controller, the channel number, and peripheral
+        trigger source.
+
+        For example dmas for TX, RX on SERCOM3
+           dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
+
+    dma-names:
+      description: |
+        Required if the dmas property exists.  This should be "tx" and "rx"
+        to match the dmas property.
+
+        For example
+           dma-names = "tx", "rx";
diff --git a/dts/bindings/i2c/espressif,esp32-i2c.yaml b/dts/bindings/i2c/espressif,esp32-i2c.yaml
new file mode 100644
index 0000000000..31b149fac0
--- /dev/null
+++ b/dts/bindings/i2c/espressif,esp32-i2c.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2019 Mohamed ElShahawi (ExtremeGTX@hotmail.com)
+# SPDX-License-Identifier: Apache-2.0
+
+description: ESP32 I2C
+
+compatible: "espressif,esp32-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    sda-pin:
+      type: int
+      description: SDA pin
+      required: true
+
+    scl-pin:
+      type: int
+      description: SCL pin
+      required: true
+
+    tx-lsb:
+      type: boolean
+      required: false
+      description: Set I2C TX data as LSB
+
+    rx-lsb:
+      type: boolean
+      required: false
+      description: Set I2C RX data as LSB
diff --git a/dts/bindings/i2c/fsl,imx21-i2c.yaml b/dts/bindings/i2c/fsl,imx21-i2c.yaml
new file mode 100644
index 0000000000..e16480604d
--- /dev/null
+++ b/dts/bindings/i2c/fsl,imx21-i2c.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2018 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX I2C node
+
+compatible: "fsl,imx21-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    rdc:
+     type: int
+     required: true
+     description: Set the RDC permission for this peripheral
diff --git a/dts/bindings/i2c/gpio-i2c.yaml b/dts/bindings/i2c/gpio-i2c.yaml
new file mode 100644
index 0000000000..45319d693b
--- /dev/null
+++ b/dts/bindings/i2c/gpio-i2c.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: GPIO bitbanging I2C support
+
+compatible: "gpio-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    scl-gpios:
+      type: phandle-array
+      required: true
+      description: GPIO to which the SCL pin of the I2C bus is connected.
+    sda-gpios:
+      type: phandle-array
+      required: true
+      description: GPIO to which the SDA pin of the I2C bus is connected.
diff --git a/dts/bindings/i2c/i2c-controller.yaml b/dts/bindings/i2c/i2c-controller.yaml
new file mode 100644
index 0000000000..77adf899a9
--- /dev/null
+++ b/dts/bindings/i2c/i2c-controller.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2017 I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for I2C controllers
+
+include: base.yaml
+
+bus: i2c
+
+properties:
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      required: true
+      const: 0
+    clock-frequency:
+      type: int
+      required: false
+      description: Initial clock frequency in Hz
+    label:
+      required: true
diff --git a/dts/bindings/i2c/i2c-device.yaml b/dts/bindings/i2c/i2c-device.yaml
new file mode 100644
index 0000000000..34fafa29e0
--- /dev/null
+++ b/dts/bindings/i2c/i2c-device.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2017, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for I2C devices
+
+include: [base.yaml, power.yaml]
+
+on-bus: i2c
+
+properties:
+    reg:
+      required: true
+      description: device address on i2c bus
+    label:
+      required: true
diff --git a/dts/bindings/i2c/ite,it8xxx2-i2c.yaml b/dts/bindings/i2c/ite,it8xxx2-i2c.yaml
new file mode 100644
index 0000000000..adbd71443c
--- /dev/null
+++ b/dts/bindings/i2c/ite,it8xxx2-i2c.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it8xxx2 I2C
+
+compatible: "ite,it8xxx2-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    port-num:
+      type: int
+      required: true
+      description: Ordinal identifying the port
+
+    gpio-dev:
+        type: phandle
+        required: true
+        description: Get the handle of the GPIO device
+
+    pinctrl-0:
+      type: phandles
+      required: true
+      description: Configuration of I2C SCL and SDA pinmux controller.
+                   The SCL pin must be specified first and the SDA pin
+                   second in the pinctrl-0 array.
diff --git a/dts/bindings/i2c/litex,i2c.yaml b/dts/bindings/i2c/litex,i2c.yaml
new file mode 100644
index 0000000000..d243b26949
--- /dev/null
+++ b/dts/bindings/i2c/litex,i2c.yaml
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: LiteX I2C controller
+
+compatible: "litex,i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/i2c/microchip,xec-i2c-v2.yaml b/dts/bindings/i2c/microchip,xec-i2c-v2.yaml
new file mode 100644
index 0000000000..1934fe2dbb
--- /dev/null
+++ b/dts/bindings/i2c/microchip,xec-i2c-v2.yaml
@@ -0,0 +1,43 @@
+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip I2C/SMB V2 controller
+
+compatible: "microchip,xec-i2c-v2"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    port_sel:
+      type: int
+      description: soc block mapping to pin
+      required: true
+
+    girqs:
+      type: array
+      required: true
+      description: array of GIRQ numbers [8:26] and bit positions [0:31]
+
+    pcrs:
+      type: array
+      required: true
+      description: PCR sleep register index and bit position
+
+    "#girq-cells":
+      type: int
+      const: 2
+
+    "pcr-cells":
+      type: int
+      const: 2
+
+girq-cells:
+    - girq_num
+    - bitpos
+
+pcr-cells:
+    - regidx
+    - bitpos
diff --git a/dts/bindings/i2c/microchip,xec-i2c.yaml b/dts/bindings/i2c/microchip,xec-i2c.yaml
new file mode 100644
index 0000000000..dcd22bd468
--- /dev/null
+++ b/dts/bindings/i2c/microchip,xec-i2c.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip I2C/SMB controller
+
+compatible: "microchip,xec-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    port_sel:
+      type: int
+      description: soc block mapping to pin
+      required: true
+
+    girq:
+      type: int
+      required: true
+      description: GIRQ for this device
+
+    girq-bit:
+      type: int
+      required: true
+      description: Bit position in GIRQ for this device
diff --git a/dts/bindings/i2c/nordic,nrf-twi-common.yaml b/dts/bindings/i2c/nordic,nrf-twi-common.yaml
new file mode 100644
index 0000000000..01faf8d323
--- /dev/null
+++ b/dts/bindings/i2c/nordic,nrf-twi-common.yaml
@@ -0,0 +1,37 @@
+# Copyright (c) 2018 Aapo Vienamo
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for Nordic nRF family TWI peripherals
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    sda-pin:
+      type: int
+      required: true
+      description: |
+        The SDA pin to use.
+
+        For pins P0.0 through P0.31, use the pin number. For example,
+        to use P0.16 for SDA, set:
+
+            sda-pin = <16>;
+
+        For pins P1.0 through P1.31, add 32 to the pin number. For
+        example, to use P1.2 for SDA, set:
+
+            sda-pin = <34>;  /* 32 + 2 */
+
+    scl-pin:
+      type: int
+      required: true
+      description: |
+        The SCL pin to use. The pin numbering scheme is the same as
+        the sda-pin property's.
diff --git a/dts/bindings/i2c/nordic,nrf-twi.yaml b/dts/bindings/i2c/nordic,nrf-twi.yaml
new file mode 100644
index 0000000000..c83dddfbfe
--- /dev/null
+++ b/dts/bindings/i2c/nordic,nrf-twi.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nordic nRF family TWI (TWI master).
+
+  This binding can be used for nodes which can represent TWI
+  peripherals. When a single SoC peripheral ID corresponds to multiple
+  I2C peripherals (like TWI or TWIM), the corresponding devicetree
+  nodes must be set up to select TWI before use.
+
+  To select TWI, set the node's "compatible" to "nordic,nrf-twi" and
+  its "status" to "okay", e.g. using an overlay file like this:
+
+      /* This is for TWI0 -- change to "i2c1" for TWI1. */
+      &i2c0 {
+              compatible = "nordic,nrf-twi";
+              status = "okay";
+              /* other property settings can go here */
+      };
+
+  You can use either of these options to check TWI availability on
+  your SoC:
+
+      1. Check the peripheral Instantiation table in the Memory
+         section of your SoC's Product Specification document.
+         A "TWI0" instance in the table means "i2c0" in the devicetree
+         can be used with this binding, and similarly for "TWI1".
+
+      2. Open your SoC's .dtsi file and look for a node definition that
+         documents TWI support, like this:
+
+             i2c0: i2c@40003000 {
+                     /*
+                      * This i2c node can be TWI, [...].
+                      */
+                     ...
+             };
+
+   If your SoC only has TWIM and TWIS I2C peripherals, you cannot use
+   this binding. See the "nordic,nrf-twim" binding instead.
+
+compatible: "nordic,nrf-twi"
+
+include: nordic,nrf-twi-common.yaml
diff --git a/dts/bindings/i2c/nordic,nrf-twim.yaml b/dts/bindings/i2c/nordic,nrf-twim.yaml
new file mode 100644
index 0000000000..bad6959972
--- /dev/null
+++ b/dts/bindings/i2c/nordic,nrf-twim.yaml
@@ -0,0 +1,63 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nordic nRF family TWIM (TWI master with EasyDMA).
+
+  This binding can be used for nodes which can represent TWIM
+  peripherals. A single SoC peripheral ID is often associated with
+  multiple I2C peripherals, like a TWIM and a TWIS. You can choose
+  TWIM by setting the node's "compatible" to "nordic,nrf-twim"
+  and "status" to "okay", e.g. using an overlay file like this one:
+
+      /* This is for TWIM0 -- change to "i2c1" for TWIM1, etc. */
+      &i2c0 {
+              compatible = "nordic,nrf-twim";
+              status = "okay";
+              /* other property settings can go here */
+      };
+
+  This works on any supported SoC, for all TWIM instances.
+
+  Note: on nRF51 SoCs, use the "nordic,nrf-twi" binding instead.
+
+compatible: "nordic,nrf-twim"
+
+include: nordic,nrf-twi-common.yaml
+
+properties:
+    zephyr,concat-buf-size:
+        type: int
+        required: false
+        default: 16
+        description: |
+            Size of a concatenation buffer that the driver is to use for merging
+            multiple same direction I2C messages that have no RESTART or STOP
+            flag between them (see e.g. the i2c_burst_write() function) into one
+            transfer on the bus.
+
+            This property must be provided when interacting with devices like
+            the SSD1306 display that cannot tolerate a repeated start and
+            address appearing on the bus between message fragments. For many
+            devices a concatenation buffer is not necessary.
+
+    zephyr,flash-buf-max-size:
+        type: int
+        required: false
+        default: 16
+        description: |
+            TWIM peripherals cannot perform write transactions from buffers
+            located in flash. If such buffers are expected to be used with
+            a given instance of the TWIM peripheral, this property must be
+            set to the maximum possible size of those buffers, so that the
+            driver can reserve enough space in RAM to copy there the contents
+            of particular buffers before requesting the actual transfers.
+
+            If this property is not set to a value adequate for a given
+            application, write transactions may fail for buffers that are
+            located in flash, what in turn may cause certain components,
+            like the DPS310 sensor driver, to not work.
+
+            It is recommended to use the same value for this property and for
+            the zephyr,concat-buf-size one, as both these buffering mechanisms
+            can utilize the same space in RAM.
diff --git a/dts/bindings/i2c/nordic,nrf-twis.yaml b/dts/bindings/i2c/nordic,nrf-twis.yaml
new file mode 100644
index 0000000000..fe29d7c19e
--- /dev/null
+++ b/dts/bindings/i2c/nordic,nrf-twis.yaml
@@ -0,0 +1,41 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nordic nRF family TWIS (TWI slave with EasyDMA).
+
+  Note: for Zephyr users, the I2C slave API is not available for
+  these devices. See this issue for more details and a HAL-based
+  workaround:
+
+      https://github.com/zephyrproject-rtos/zephyr/issues/21445
+
+  This binding can be used for nodes which can represent TWIS
+  peripherals. A single SoC peripheral ID is often associated with
+  multiple I2C peripherals, like a TWIM and a TWIS. You can choose
+  TWIS by setting the node's "compatible" to "nordic,nrf-twis"
+  and its "status" to "okay", e.g. using an overlay file like this:
+
+      /* This is for TWIS0 -- change to "i2c1" for TWIS1, etc. */
+      &i2c0 {
+              compatible = "nordic,nrf-twis";
+              status = "okay";
+              /* other property settings can go here */
+      };
+
+  This works on any supported SoC, for all TWIS instances.
+
+compatible: "nordic,nrf-twis"
+
+include: nordic,nrf-twi-common.yaml
+
+properties:
+    address-0:
+      type: int
+      required: false
+      description: TWI slave address 0
+
+    address-1:
+      type: int
+      required: false
+      description: TWI slave address 1
diff --git a/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml b/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml
new file mode 100644
index 0000000000..83e4c01f9d
--- /dev/null
+++ b/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-I2C controller node
+
+compatible: "nuvoton,npcx-i2c-ctrl"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
+    clocks:
+        required: true
+    label:
+        required: true
diff --git a/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml b/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml
new file mode 100644
index 0000000000..1047f021df
--- /dev/null
+++ b/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-I2C port pads node
+
+compatible: "nuvoton,npcx-i2c-port"
+
+include: i2c-controller.yaml
+
+properties:
+    port:
+        type: int
+        required: true
+        description: index of i2c port
+
+    controller:
+        type: phandle
+        required: true
+        description: i2c controller to handle signals from port pads
+
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of pinmux controllers
+
+    clock-frequency:
+        required: true
diff --git a/dts/bindings/i2c/nxp,imx-lpi2c.yaml b/dts/bindings/i2c/nxp,imx-lpi2c.yaml
new file mode 100644
index 0000000000..adcd1d8ff1
--- /dev/null
+++ b/dts/bindings/i2c/nxp,imx-lpi2c.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP i.MX LPI2C controller
+
+compatible: "nxp,imx-lpi2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    bus-idle-timeout:
+      required: false
+      type: int
+      description: Bus idle timeout in nanoseconds
diff --git a/dts/bindings/i2c/nxp,kinetis-i2c.yaml b/dts/bindings/i2c/nxp,kinetis-i2c.yaml
new file mode 100644
index 0000000000..21f642321f
--- /dev/null
+++ b/dts/bindings/i2c/nxp,kinetis-i2c.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2017 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis I2C node
+
+compatible: "nxp,kinetis-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
diff --git a/dts/bindings/i2c/nxp,lpc-i2c.yaml b/dts/bindings/i2c/nxp,lpc-i2c.yaml
new file mode 100644
index 0000000000..4c2ceb77a8
--- /dev/null
+++ b/dts/bindings/i2c/nxp,lpc-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC I2C node
+
+compatible: "nxp,lpc-i2c"
+
+include: [i2c-controller.yaml, "nxp,lpc-flexcomm.yaml"]
diff --git a/dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml b/dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml
new file mode 100644
index 0000000000..653a77c129
--- /dev/null
+++ b/dts/bindings/i2c/nxp,lpc11u6x-i2c.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC11U6X I2C Controller
+
+compatible: "nxp,lpc11u6x-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    pinmuxs:
+      type: phandle-array
+      required: true
+      description: SDA and SCL pins
+
+    pinmux-names:
+      type: string-array
+      required: true
+      description: Pin names for SDA and SCL
diff --git a/dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml b/dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml
new file mode 100644
index 0000000000..53fbf75ffa
--- /dev/null
+++ b/dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: OpenISA LPI2C controller
+
+compatible: "openisa,rv32m1-lpi2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/i2c/renesas,rcar-i2c.yaml b/dts/bindings/i2c/renesas,rcar-i2c.yaml
new file mode 100644
index 0000000000..620b33cce7
--- /dev/null
+++ b/dts/bindings/i2c/renesas,rcar-i2c.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021, IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas R-Car I2C controller
+
+compatible: "renesas,rcar-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+    interrupts:
+      required: true
+    clocks:
+      required: true
diff --git a/dts/bindings/i2c/sifive,i2c0.yaml b/dts/bindings/i2c/sifive,i2c0.yaml
new file mode 100644
index 0000000000..5f74df571e
--- /dev/null
+++ b/dts/bindings/i2c/sifive,i2c0.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2018 SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive Freedom I2C interface
+
+compatible: "sifive,i2c0"
+
+include: i2c-controller.yaml
+
+properties:
+    input-frequency:
+      type: int
+      required: false
+      description: Frequency of the peripheral input clock.
+
+    reg:
+      required: true
diff --git a/dts/bindings/i2c/silabs,gecko-i2c.yaml b/dts/bindings/i2c/silabs,gecko-i2c.yaml
new file mode 100644
index 0000000000..84d1b76008
--- /dev/null
+++ b/dts/bindings/i2c/silabs,gecko-i2c.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2018 Diego Sueiro <diego.sueiro@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silabs Gecko I2C node
+
+compatible: "silabs,gecko-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    # Note: Not all SoC series support setting individual pin location. If this
+    # is a case all location-* properties need to have identical value.
+
+    location-sda:
+      type: array
+      required: true
+      description: SDA pin configuration defined as <location port pin>
+
+    location-scl:
+      type: array
+      required: true
+      description: SCL pin configuration defined as <location port pin>
diff --git a/dts/bindings/i2c/snps,designware-i2c.yaml b/dts/bindings/i2c/snps,designware-i2c.yaml
new file mode 100644
index 0000000000..36970b355d
--- /dev/null
+++ b/dts/bindings/i2c/snps,designware-i2c.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys DesignWare I2C node
+
+compatible: "snps,designware-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/i2c/st,stm32-i2c-v1.yaml b/dts/bindings/i2c/st,stm32-i2c-v1.yaml
new file mode 100644
index 0000000000..d86cdb8aed
--- /dev/null
+++ b/dts/bindings/i2c/st,stm32-i2c-v1.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2017 I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 I2C V1 controller
+
+compatible: "st,stm32-i2c-v1"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
diff --git a/dts/bindings/i2c/st,stm32-i2c-v2.yaml b/dts/bindings/i2c/st,stm32-i2c-v2.yaml
new file mode 100644
index 0000000000..dad8205f4a
--- /dev/null
+++ b/dts/bindings/i2c/st,stm32-i2c-v2.yaml
@@ -0,0 +1,46 @@
+# Copyright (c) 2017 I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 I2C V2 controller
+
+compatible: "st,stm32-i2c-v2"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
+    timings:
+        type: array
+        required: false
+        description: |
+            An optional table of pre-computed i2c timing values with the
+            matching clock configuration.
+
+            Precise timings values for a given Hardware can be pre-computed
+            with a tool like STM32CubeMX or directly from I2C_TIMINGR register
+            description.
+
+            Because timing value is valid for a given I2C peripheral clock
+            frequency and target I2C bus clock, each timing value must be
+            provided with the matching configuration.
+
+            The resulting table entries should look like <periph_clock
+            clock-frequency timing>
+
+            For example timings could be defined as
+
+                timings = <64000000 I2C_BITRATE_STANDARD 0x10707DBC>,
+                          <64000000 I2C_BITRATE_FAST 0x00603D56>,
+                          <56000000 I2C_BITRATE_STANDARD 0x10606DA4>,
+                          <56000000 I2C_BITRATE_FAST 0x00501D63>;
diff --git a/dts/bindings/i2c/telink,b91-i2c.yaml b/dts/bindings/i2c/telink,b91-i2c.yaml
new file mode 100644
index 0000000000..a0efe7f8ff
--- /dev/null
+++ b/dts/bindings/i2c/telink,b91-i2c.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021, Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink B91 I2C
+
+include: i2c-controller.yaml
+
+compatible: "telink,b91-i2c"
+
+properties:
+    reg:
+        required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
diff --git a/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml b/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml
new file mode 100644
index 0000000000..49f62771da
--- /dev/null
+++ b/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2019 Brett Witherspoon
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI CC13xx / CC26xx I2C node
+
+compatible: "ti,cc13xx-cc26xx-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    sda-pin:
+      type: int
+      required: true
+      description: SDA pin
+
+    scl-pin:
+      type: int
+      required: true
+      description: SCL pin
diff --git a/dts/bindings/i2c/ti,cc32xx-i2c.yaml b/dts/bindings/i2c/ti,cc32xx-i2c.yaml
new file mode 100644
index 0000000000..00d6a8f489
--- /dev/null
+++ b/dts/bindings/i2c/ti,cc32xx-i2c.yaml
@@ -0,0 +1,12 @@
+description: TI CC32XX I2C controller
+
+compatible: "ti,cc32xx-i2c"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/i2c/ti,tca9546a.yaml b/dts/bindings/i2c/ti,tca9546a.yaml
new file mode 100644
index 0000000000..1e0bb69d5f
--- /dev/null
+++ b/dts/bindings/i2c/ti,tca9546a.yaml
@@ -0,0 +1,10 @@
+#Binding for TI TCA9546A, compatible with NXP PCA9546A
+
+description: Texas Instruments TCA9546A binding
+
+compatible: "ti,tca9546a"
+
+include: ti,tca954x-base.yaml
+
+child-binding:
+  compatible: "ti,tca9546a-channel"
diff --git a/dts/bindings/i2c/ti,tca9548a.yaml b/dts/bindings/i2c/ti,tca9548a.yaml
new file mode 100644
index 0000000000..f894881b8c
--- /dev/null
+++ b/dts/bindings/i2c/ti,tca9548a.yaml
@@ -0,0 +1,10 @@
+#Binding for TI TCA9548A, compatible with NXP PCA9548A
+
+description: Texas Instruments TCA9548A binding
+
+compatible: "ti,tca9548a"
+
+include: ti,tca954x-base.yaml
+
+child-binding:
+  compatible: "ti,tca9548a-channel"
diff --git a/dts/bindings/i2c/ti,tca954x-base.yaml b/dts/bindings/i2c/ti,tca954x-base.yaml
new file mode 100644
index 0000000000..f7f481260b
--- /dev/null
+++ b/dts/bindings/i2c/ti,tca954x-base.yaml
@@ -0,0 +1,60 @@
+# Copyright (c) 2020, Innoseis BV
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for TI TCA954X I2C mux family
+
+description: |
+  TCA954x I2C switch
+
+  Each channel is represented by a separate devicetree child node.
+  The channel node can then be used as a standard i2c bus controller
+  like in the following simplified example:
+
+      /* The tca954x node must be a child of an i2c controller */
+      mux: tca9546a@77 {
+          compatible = "ti,tca9546a";
+          reg = <0x77>;
+          status = "okay";
+          label = "i2c_mux";
+          #address-cells = <1>;
+          #size-cells = <0>;
+          reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+
+          mux_i2c@0 {
+              compatible: "ti,tca9546a-channel"
+              reg = <0>;
+              #address-cells = <1>;
+              #size-cells = <0>;
+
+              temp_sens_0: tmp116@49 {
+                  compatible = "ti,tmp116";
+                  reg = <0x49>;
+              };
+          };
+
+          mux_i2c@1 {
+            compatible: "ti,tca9546a-channel"
+              reg = <1>;
+              #address-cells = <1>;
+              #size-cells = <0>;
+
+              temp_sens_1: tmp116@49 {
+                  compatible = "ti,tmp116";
+                  reg = <0x49>;
+              };
+          };
+      };
+
+include: [i2c-device.yaml]
+
+properties:
+  reset-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      GPIO connected to the controller RESET pin. This pin is active-low.
+
+child-binding:
+  description: TCA954x I2C switch channel node
+  include: [i2c-controller.yaml]
+  on-bus: i2c
diff --git a/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml b/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml
new file mode 100644
index 0000000000..7bd4f58acb
--- /dev/null
+++ b/dts/bindings/i2c/zephyr,i2c-emul-controller.yaml
@@ -0,0 +1,12 @@
+# Copyright 2020 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr I2C Emulation controller
+
+compatible: "zephyr,i2c-emul-controller"
+
+include: i2c-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/i2s/i2s-controller.yaml b/dts/bindings/i2s/i2s-controller.yaml
new file mode 100644
index 0000000000..3000542b13
--- /dev/null
+++ b/dts/bindings/i2s/i2s-controller.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for I2S controllers
+
+include: base.yaml
+
+bus: i2s
+
+properties:
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      required: true
+      const: 0
+    label:
+      required: true
diff --git a/dts/bindings/i2s/i2s-device.yaml b/dts/bindings/i2s/i2s-device.yaml
new file mode 100644
index 0000000000..4e31032ee6
--- /dev/null
+++ b/dts/bindings/i2s/i2s-device.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for I2S devices
+
+include: base.yaml
+
+on-bus: i2s
+
+properties:
+    reg:
+      required: true
+    label:
+      required: true
diff --git a/dts/bindings/i2s/intel,cavs-i2s.yaml b/dts/bindings/i2s/intel,cavs-i2s.yaml
new file mode 100644
index 0000000000..3350704605
--- /dev/null
+++ b/dts/bindings/i2s/intel,cavs-i2s.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2020 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel CAVS I2S controller
+
+compatible: "intel,cavs-i2s"
+
+include: [i2s-controller.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    interrupt-parent:
+      required: true
+
+    dmas:
+      required: true
+
+    dma-names:
+      required: true
diff --git a/dts/bindings/i2s/litex,i2s.yaml b/dts/bindings/i2s/litex,i2s.yaml
new file mode 100644
index 0000000000..3d1bcbc6b3
--- /dev/null
+++ b/dts/bindings/i2s/litex,i2s.yaml
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: LiteX I2S controller
+
+compatible: "litex,i2s"
+include: i2s-controller.yaml
+
+properties:
+    reg:
+        required: true
+
+    fifo_depth:
+        type: int
+        required: true
diff --git a/dts/bindings/i2s/nordic,nrf-i2s.yaml b/dts/bindings/i2s/nordic,nrf-i2s.yaml
new file mode 100644
index 0000000000..f3e866d3fd
--- /dev/null
+++ b/dts/bindings/i2s/nordic,nrf-i2s.yaml
@@ -0,0 +1,60 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic I2S (Inter-IC sound interface)
+
+compatible: "nordic,nrf-i2s"
+
+include: i2s-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    sck-pin:
+      type: int
+      required: true
+      description: SCK pin
+
+    lrck-pin:
+      type: int
+      required: true
+      description: LRCK pin
+
+    sdout-pin:
+      type: int
+      required: false
+      description: SDOUT pin
+
+    sdin-pin:
+      type: int
+      required: false
+      description: SDIN pin
+
+    mck-pin:
+      type: int
+      required: false
+      description: MCK pin
+
+    clock-source:
+      type: string
+      required: false
+      default: "PCLK32M_HFXO"
+      description: |
+        Clock source to be used by the I2S peripheral for the master clock
+        (MCK) generator. The generator is only needed when the I2S peripheral
+        is operating in Master mode. The following options are available:
+        - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
+        - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
+          (HFXO) for better clock accuracy and jitter performance
+        - "ACLK": Audio PLL clock with configurable frequency (frequency for
+          this clock must be set via the "hfclkaudio-frequency" property
+          in the "nordic,nrf-clock" node); this clock source is only available
+          in the nRF53 Series SoCs and it requires the use of HFXO
+      enum:
+        - "PCLK32M"
+        - "PCLK32M_HFXO"
+        - "ACLK"
diff --git a/dts/bindings/i2s/nxp,lpc-i2s.yaml b/dts/bindings/i2s/nxp,lpc-i2s.yaml
new file mode 100644
index 0000000000..332eea3bf2
--- /dev/null
+++ b/dts/bindings/i2s/nxp,lpc-i2s.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC I2S node
+
+compatible: "nxp,lpc-i2s"
+
+include: [i2s-controller.yaml, "nxp,lpc-flexcomm.yaml"]
diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml
new file mode 100644
index 0000000000..c68cd9f41b
--- /dev/null
+++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml
@@ -0,0 +1,70 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP mcux SAI-I2S controller
+
+compatible: "nxp,mcux-i2s"
+
+include: [i2s-controller.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    dma-names:
+      required: true
+
+    nxp,tx-dma-channel:
+      type: int
+      required: true
+      description: tx dma channel number
+
+    nxp,rx-dma-channel:
+      type: int
+      required: true
+      description: rx dma channel number
+
+    nxp,tx-sync-mode:
+      type: boolean
+      required: false
+      description: tx sync mode
+
+    nxp,rx-sync-mode:
+      type: boolean
+      required: false
+      description: rx sync mode
+
+    pre-div:
+      type: int
+      required: false
+      description: pre divider
+
+    podf:
+      type: int
+      required: false
+      description: post-divider fraction
+
+    pll-clocks:
+      type: phandle-array
+      required: false
+      description: pll settings
+      specifier-space: pll-clock
+
+    pll-clock-names:
+      required: false
+      type: string-array
+      description: Provided names of pll-clock specifiers
+
+    pinmuxes:
+      type: phandle-array
+      required: false
+      specifier-space: pinmux
+      description: iomux settings
+
+    nxp,tx-channel:
+      type: int
+      required: false
+      description: tx channel the maximum number is SOC dependent
diff --git a/dts/bindings/i2s/st,stm32-i2s.yaml b/dts/bindings/i2s/st,stm32-i2s.yaml
new file mode 100644
index 0000000000..d66a6c8d43
--- /dev/null
+++ b/dts/bindings/i2s/st,stm32-i2s.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2018, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 I2S controller
+
+compatible: "st,stm32-i2s"
+
+include: [i2s-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    dmas:
+      required: true
+
+    dma-names:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
diff --git a/dts/bindings/ieee802154/atmel,rf2xx.yaml b/dts/bindings/ieee802154/atmel,rf2xx.yaml
new file mode 100644
index 0000000000..2e3cff87c6
--- /dev/null
+++ b/dts/bindings/ieee802154/atmel,rf2xx.yaml
@@ -0,0 +1,40 @@
+# Copyright (c) 2019-2020 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ATMEL AT86RF2xx 802.15.4 wireless transceiver
+
+compatible: "atmel,rf2xx"
+
+include: spi-device.yaml
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: true
+
+    reset-gpios:
+      type: phandle-array
+      required: true
+
+    slptr-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        Multi-functional pin that controls sleep, deep sleep, transmit
+        start and receive states
+
+    dig2-gpios:
+      type: phandle-array
+      required: false
+      description: RX and TX Frame Time Stamping(TX_ARET)
+
+    clkm-gpios:
+      type: phandle-array
+      required: false
+      description: Master clock signal output
+
+    local-mac-address:
+      type: uint8-array
+      description: |
+        Specifies the MAC address that was assigned to the network
+        device
diff --git a/dts/bindings/ieee802154/decawave,dw1000.yaml b/dts/bindings/ieee802154/decawave,dw1000.yaml
new file mode 100644
index 0000000000..908d8041bf
--- /dev/null
+++ b/dts/bindings/ieee802154/decawave,dw1000.yaml
@@ -0,0 +1,37 @@
+# Copyright (c) 2019, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: Decawave DW1000 802.15.4 UWB transceiver
+
+compatible: "decawave,dw1000"
+
+include: spi-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: true
+      description: Interrupt pin.
+
+        The interrupt pin IRQ of DW1000 is active high output.
+        If connected directly the MCU pin should be configured
+        as active high.
+
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: RESET pin.
+
+        The RESET pin of DW1000 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    tx-ant-delay:
+      type: int
+      required: false
+      description: Transmitter antenna delay.
+
+    rx-ant-delay:
+      type: int
+      required: false
+      description: Receiver antenna delay.
diff --git a/dts/bindings/ieee802154/nxp,mcr20a.yaml b/dts/bindings/ieee802154/nxp,mcr20a.yaml
new file mode 100644
index 0000000000..b7f9f63776
--- /dev/null
+++ b/dts/bindings/ieee802154/nxp,mcr20a.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCR20A 802.15.4 wireless transceiver
+
+compatible: "nxp,mcr20a"
+
+include: spi-device.yaml
+
+properties:
+    irqb-gpios:
+      type: phandle-array
+      required: true
+      description: Interrupt pin.
+
+        The interrupt pin of MCR20A is open-drain, active low.
+        If connected directly the MCU pin should be configured
+        as pull-up, active low.
+
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: RESET pin.
+
+        The RESET pin of MCR20A is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
diff --git a/dts/bindings/ieee802154/telink,b91-zb.yaml b/dts/bindings/ieee802154/telink,b91-zb.yaml
new file mode 100644
index 0000000000..8c776232e0
--- /dev/null
+++ b/dts/bindings/ieee802154/telink,b91-zb.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021, Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink B91 IEEE802154 node
+
+compatible: "telink,b91-zb"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/ieee802154/ti,cc1200.yaml b/dts/bindings/ieee802154/ti,cc1200.yaml
new file mode 100644
index 0000000000..492d82dda3
--- /dev/null
+++ b/dts/bindings/ieee802154/ti,cc1200.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments CC1200 802.15.4 wireless transceiver
+
+compatible: "ti,cc1200"
+
+include: spi-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: true
diff --git a/dts/bindings/ieee802154/ti,cc2520.yaml b/dts/bindings/ieee802154/ti,cc2520.yaml
new file mode 100644
index 0000000000..c310add544
--- /dev/null
+++ b/dts/bindings/ieee802154/ti,cc2520.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2018, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments CC2520 802.15.4 wireless transceiver
+
+compatible: "ti,cc2520"
+
+include: spi-device.yaml
+
+properties:
+    vreg-en-gpios:
+      type: phandle-array
+      required: true
+
+    reset-gpios:
+      type: phandle-array
+      required: true
+
+    fifo-gpios:
+      type: phandle-array
+      required: true
+
+    cca-gpios:
+      type: phandle-array
+      required: true
+
+    sfd-gpios:
+      type: phandle-array
+      required: true
+
+    fifop-gpios:
+      type: phandle-array
+      required: true
diff --git a/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml b/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml
new file mode 100644
index 0000000000..96a3c23c3c
--- /dev/null
+++ b/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-ADC node
+
+compatible: "nuvoton,npcx-adc"
+
+include: [adc-controller.yaml]
+
+properties:
+    reg:
+        required: true
+    clocks:
+        required: true
+    label:
+        required: true
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of pinmux controllers
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/iio/adc/nxp,lpc-lpadc.yaml b/dts/bindings/iio/adc/nxp,lpc-lpadc.yaml
new file mode 100644
index 0000000000..2996b4a0c7
--- /dev/null
+++ b/dts/bindings/iio/adc/nxp,lpc-lpadc.yaml
@@ -0,0 +1,56 @@
+# Copyright (c) 2020, Toby Firth
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC LPADC
+
+compatible: "nxp,lpc-lpadc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clk-divider:
+      type: int
+      required: true
+      description: clock divider for the converter
+
+    clk-source:
+      type: int
+      required: true
+      description: source to attach the ADC clock to
+
+    voltage-ref:
+      type: int
+      required: true
+      description: reference voltage source
+
+    calibration-average:
+      type: int
+      required: true
+      description: conversion average number for auto-calibration
+
+    power-level:
+      type: int
+      required: true
+      description: power level for the ADC
+
+    offset-value-a:
+      type: int
+      required: true
+      description: Offset value A to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false
+
+    offset-value-b:
+      type: int
+      required: true
+      description: Offset value B to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/interrupt-controller/arm,gic-v3-its.yaml b/dts/bindings/interrupt-controller/arm,gic-v3-its.yaml
new file mode 100644
index 0000000000..16fe057e5e
--- /dev/null
+++ b/dts/bindings/interrupt-controller/arm,gic-v3-its.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: GIC v3 Interrupt Translation Service
+
+compatible: "arm,gic-v3-its"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/interrupt-controller/arm,gic.yaml b/dts/bindings/interrupt-controller/arm,gic.yaml
new file mode 100644
index 0000000000..8752a53685
--- /dev/null
+++ b/dts/bindings/interrupt-controller/arm,gic.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2018 Marvell
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARMv7-R Generic Interrupt Controller
+
+compatible: "arm,gic"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+interrupt-cells:
+  - type
+  - irq
+  - flags
+  - priority
diff --git a/dts/bindings/interrupt-controller/arm,v6m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v6m-nvic.yaml
new file mode 100644
index 0000000000..1fc581fa1a
--- /dev/null
+++ b/dts/bindings/interrupt-controller/arm,v6m-nvic.yaml
@@ -0,0 +1,21 @@
+description: ARMv6-M NVIC (Nested Vectored Interrupt Controller) controller
+
+compatible: "arm,v6m-nvic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    arm,num-irq-priority-bits:
+      required: true
+      type: int
+      description: number of bits of IRQ priorities
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml
new file mode 100644
index 0000000000..43847c4420
--- /dev/null
+++ b/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml
@@ -0,0 +1,21 @@
+description: ARMv7-M NVIC (Nested Vectored Interrupt Controller)
+
+compatible: "arm,v7m-nvic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    arm,num-irq-priority-bits:
+      required: true
+      type: int
+      description: number of bits of IRQ priorities
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml
new file mode 100644
index 0000000000..cb1e26e742
--- /dev/null
+++ b/dts/bindings/interrupt-controller/arm,v8.1m-nvic.yaml
@@ -0,0 +1,21 @@
+description: ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)
+
+compatible: "arm,v8.1m-nvic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    arm,num-irq-priority-bits:
+      required: true
+      type: int
+      description: number of bits of IRQ priorities
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml b/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml
new file mode 100644
index 0000000000..6aadc1b687
--- /dev/null
+++ b/dts/bindings/interrupt-controller/arm,v8m-nvic.yaml
@@ -0,0 +1,21 @@
+description: ARMv8-M NVIC (Nested Vectored Interrupt Controller)
+
+compatible: "arm,v8m-nvic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    arm,num-irq-priority-bits:
+      required: true
+      type: int
+      description: number of bits of IRQ priorities
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/atmel,sam0-eic.yaml b/dts/bindings/interrupt-controller/atmel,sam0-eic.yaml
new file mode 100644
index 0000000000..6c5a50f374
--- /dev/null
+++ b/dts/bindings/interrupt-controller/atmel,sam0-eic.yaml
@@ -0,0 +1,15 @@
+description: Atmel SAM0 series External Interrupt Controller
+
+compatible: "atmel,sam0-eic"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  label:
+    required: true
diff --git a/dts/bindings/interrupt-controller/cdns,xtensa-core-intc.yaml b/dts/bindings/interrupt-controller/cdns,xtensa-core-intc.yaml
new file mode 100644
index 0000000000..5c52526218
--- /dev/null
+++ b/dts/bindings/interrupt-controller/cdns,xtensa-core-intc.yaml
@@ -0,0 +1,17 @@
+description: Xtensa Core interrupt controller
+
+compatible: "cdns,xtensa-core-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 3
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
diff --git a/dts/bindings/interrupt-controller/cypress,psoc6-intmux-ch.yaml b/dts/bindings/interrupt-controller/cypress,psoc6-intmux-ch.yaml
new file mode 100644
index 0000000000..c443183078
--- /dev/null
+++ b/dts/bindings/interrupt-controller/cypress,psoc6-intmux-ch.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2019, Linaro Limited
+# Copyright (c) 2020, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Cypress Interrupt Multiplex Channel
+
+  see cypress,psoc6-intmux
+
+compatible: "cypress,psoc6-intmux-ch"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  label:
+      required: true
+
+  interrupts:
+      required: true
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml b/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml
new file mode 100644
index 0000000000..d4e68259c3
--- /dev/null
+++ b/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml
@@ -0,0 +1,79 @@
+# Copyright (c) 2018 Foundries.io
+# Copyright (c) 2020 ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Cypress Interrupt Multiplex
+
+  The PSoC-6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
+  user can select up to 32 interrupts sources from the 240 possible vectors
+  to be processed in the Cortex-M0+ CPU.
+
+  At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to
+  configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
+  4 interrupt sources by grouping intmux channels. These means that each byte
+  from intmux[0~7] store a 'vector number' which selects the peripheral
+  interrupt source in the multiplexer. The multiplexer is placed before
+  Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
+  directly connected to NVIC and doesn't require any special configuration.
+
+  On a general view, the below represents the Interrupt Multiplexer
+  configuration and how the Cortex-M0+ NVIC sources are organized. Each
+  channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
+  The vector number selects the PSoC-6 peripheral interrupt source for the
+  Cortex-M0+ NVIC controller line.
+
+  intmux[0] = {ch03, ch02, ch01, ch00}
+  intmux[1] = {ch07, ch06, ch05, ch04}
+  ...
+  intmux[7] = {ch31, ch30, ch29, ch28}
+
+  In pratical terms, the Cortex-M0+ requires user to define all NVIC interrupt
+  sources and the proper NVIC interrupt order. With that, the system configures
+  the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
+  More information about it at PSoC-6 Architecture Technical Reference Manual,
+  section CPU Sub System (CPUSS) Registers.
+
+
+  The below fragment configure the GPIO Port 0 to generate an interrupt at
+  Cortex-M0+ NVIC:
+
+  At psoc6.dtsi file the gpio_prt0 peripheral had the interrupt source 2:
+
+  gpio_prt0: gpio@40320100 {
+    interrupts = <2 1>;
+  };
+
+  In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
+  must be defined at gpio_prt0 node selecting the Interrupt Multiplex Channel.
+  This can be defined at <board>_m0.dts file:
+
+  &gpio_prt0 {
+    interrupt-parent = <&intmux_ch20>;
+  };
+
+  The translation of these two definitions is:
+         CH   REGS  INT NUM    CH   CH/REG
+  intmux[20 mod 8] |= 0x02 << (20 mod 4);
+
+  These results in Cortex-M0+ NVIC line 20 handling PSoC-6 interrupt source 2.
+  The interrupt can be enabled/disable at NVIC at line 20 as usual.
+
+  Notes:
+  1) Multiple definitions will generate multiple interrutps
+  2) The interrupt sources are shared between Cortex-M0+/M4. These means, can
+     trigger action in parallel in both processors.
+  3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
+     at interrupt-parent properties.
+  4) Only the peripherals used by Cortex-M0+ should be configured.
+
+compatible: "cypress,psoc6-intmux"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  label:
+      required: true
diff --git a/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml b/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml
new file mode 100644
index 0000000000..60561db1bc
--- /dev/null
+++ b/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ESP32 Interrupt controller
+compatible: "espressif,esp32-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+interrupt-cells:
+  - irq
diff --git a/dts/bindings/interrupt-controller/gaisler,irqmp.yaml b/dts/bindings/interrupt-controller/gaisler,irqmp.yaml
new file mode 100644
index 0000000000..b5734c9a04
--- /dev/null
+++ b/dts/bindings/interrupt-controller/gaisler,irqmp.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2020 Cobham Gaisler AB
+# SPDX-License-Identifier: Apache-2.0
+
+description: GRLIB Multiprocessor Interrupt Controller
+
+compatible: "gaisler,irqmp"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    eirq:
+      type: int
+      description: Extended interrupt number (or 0 for none)
+
+    "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
diff --git a/dts/bindings/interrupt-controller/intel,cavs-intc.yaml b/dts/bindings/interrupt-controller/intel,cavs-intc.yaml
new file mode 100644
index 0000000000..530ffd6908
--- /dev/null
+++ b/dts/bindings/interrupt-controller/intel,cavs-intc.yaml
@@ -0,0 +1,23 @@
+description: CAVS interrupt controller
+
+compatible: "intel,cavs-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  label:
+      required: true
+
+  "#interrupt-cells":
+      const: 3
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
diff --git a/dts/bindings/interrupt-controller/intel,ioapic.yaml b/dts/bindings/interrupt-controller/intel,ioapic.yaml
new file mode 100644
index 0000000000..3d8f9fb679
--- /dev/null
+++ b/dts/bindings/interrupt-controller/intel,ioapic.yaml
@@ -0,0 +1,17 @@
+description: Intel I/O Advanced Programmable Interrupt Controller (APIC)
+
+compatible: "intel,ioapic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 3
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
diff --git a/dts/bindings/interrupt-controller/intel,vt-d.yaml b/dts/bindings/interrupt-controller/intel,vt-d.yaml
new file mode 100644
index 0000000000..5b89c84364
--- /dev/null
+++ b/dts/bindings/interrupt-controller/intel,vt-d.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel VT-D Interrupt Remapping Controller
+
+compatible: "intel,vt-d"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/interrupt-controller/interrupt-controller.yaml b/dts/bindings/interrupt-controller/interrupt-controller.yaml
new file mode 100644
index 0000000000..93e1a433be
--- /dev/null
+++ b/dts/bindings/interrupt-controller/interrupt-controller.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for interrupt controllers
+
+properties:
+    "interrupt-controller":
+      type: boolean
+      required: true
+      description: Convey's this node is an interrupt controller
+    "#interrupt-cells":
+      type: int
+      required: true
+      description: Number of items to expect in an interrupt specifier
diff --git a/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml b/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml
new file mode 100644
index 0000000000..54c932d893
--- /dev/null
+++ b/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE Interrupt controller
+compatible: "ite,it8xxx2-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+interrupt-cells:
+  - irq
+  - flags
diff --git a/dts/bindings/interrupt-controller/microchip,xec-ecia-girq.yaml b/dts/bindings/interrupt-controller/microchip,xec-ecia-girq.yaml
new file mode 100644
index 0000000000..387317638e
--- /dev/null
+++ b/dts/bindings/interrupt-controller/microchip,xec-ecia-girq.yaml
@@ -0,0 +1,26 @@
+description: Microchip XEC series External Interrupt Aggregator GIRQ
+
+compatible: "microchip,xec-ecia-girq"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    girq-id:
+       type: int
+       required: true
+       description: GIRQ ID number [0, 18]
+
+    sources:
+      type: array
+      required: true
+      description: |
+        Bit positions of each source implemented by this GIRQ.
diff --git a/dts/bindings/interrupt-controller/microchip,xec-ecia.yaml b/dts/bindings/interrupt-controller/microchip,xec-ecia.yaml
new file mode 100644
index 0000000000..c033f99b54
--- /dev/null
+++ b/dts/bindings/interrupt-controller/microchip,xec-ecia.yaml
@@ -0,0 +1,22 @@
+description: Microchip XEC series External Interrupt Aggregator Controller
+
+compatible: "microchip,xec-ecia"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    clocks:
+      required: true
+
+    direct-capable-girqs:
+      type: array
+      required: true
+      description: |
+        Array of GIRQ numbers in [8, 26] whose result bits can be connected
+        directly to the ARM NVIC.
diff --git a/dts/bindings/interrupt-controller/nuclei,eclic.yaml b/dts/bindings/interrupt-controller/nuclei,eclic.yaml
new file mode 100644
index 0000000000..47aee3157d
--- /dev/null
+++ b/dts/bindings/interrupt-controller/nuclei,eclic.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021, Tokita, Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuclei ECLIC interrupt controller
+
+compatible: "nuclei,eclic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-int-map.yaml b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-int-map.yaml
new file mode 100644
index 0000000000..56646e0dcf
--- /dev/null
+++ b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-int-map.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: NPCX-MIWU group-interrupt mapping child node
+
+compatible: "nuvoton,npcx-miwu-int-map"
+
+properties:
+    parent:
+        type: phandle
+        required: true
+        description: parent device node of miwu groups
+
+child-binding:
+    description: Child node to present the mapping between MIWU group and interrupt
+    properties:
+       irq:
+          type: int
+          required: true
+          description: irq for miwu group
+       irq-prio:
+          type: int
+          required: true
+          description: irq's priority for miwu group. The valid number is from 0 to 7.
+       group-mask:
+          type: int
+          required: true
+          description: group bit-mask for miwu interrupts
+       groups:
+          type: array
+          required: false
+          description: groups shared the same interrupt
diff --git a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-wui-map.yaml b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-wui-map.yaml
new file mode 100644
index 0000000000..6711820ee0
--- /dev/null
+++ b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu-wui-map.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: NPCX-MIWU Wake-Up Unit Input (WUI) mapping child node
+
+compatible: "nuvoton,npcx-miwu-wui-map"
+
+child-binding:
+    description: Child node to present the mapping between input of MIWU and its source device
+    properties:
+       miwus:
+            type: phandle-array
+            required: true
diff --git a/dts/bindings/interrupt-controller/nuvoton,npcx-miwu.yaml b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu.yaml
new file mode 100644
index 0000000000..89a2f817be
--- /dev/null
+++ b/dts/bindings/interrupt-controller/nuvoton,npcx-miwu.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Multi-Input Wake-Up Unit (MIWU) node
+
+compatible: "nuvoton,npcx-miwu"
+
+include: [base.yaml]
+
+properties:
+    label:
+        required: true
+
+    index:
+        type: int
+        required: true
+        description: index of miwu device
+
+    "#miwu-cells":
+        type: int
+        required: true
+        description: Number of items to present a MIWU input souce specifier
+
+miwu-cells:
+  - group
+  - bit
diff --git a/dts/bindings/interrupt-controller/openisa,rv32m1-event-unit.yaml b/dts/bindings/interrupt-controller/openisa,rv32m1-event-unit.yaml
new file mode 100644
index 0000000000..e08fe1d0bb
--- /dev/null
+++ b/dts/bindings/interrupt-controller/openisa,rv32m1-event-unit.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2018, Linaro Inc.
+# Copyright (c) 2018, Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 Event Unit
+
+compatible: "openisa,rv32m1-event-unit"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
diff --git a/dts/bindings/interrupt-controller/openisa,rv32m1-intmux-ch.yaml b/dts/bindings/interrupt-controller/openisa,rv32m1-intmux-ch.yaml
new file mode 100644
index 0000000000..78f0114bcf
--- /dev/null
+++ b/dts/bindings/interrupt-controller/openisa,rv32m1-intmux-ch.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 INTMUX channel
+
+compatible: "openisa,rv32m1-intmux-ch"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  label:
+      required: true
+
+  interrupts:
+      required: true
+
+interrupt-cells:
+  - irq
diff --git a/dts/bindings/interrupt-controller/openisa,rv32m1-intmux.yaml b/dts/bindings/interrupt-controller/openisa,rv32m1-intmux.yaml
new file mode 100644
index 0000000000..038b080241
--- /dev/null
+++ b/dts/bindings/interrupt-controller/openisa,rv32m1-intmux.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 INTMUX IP
+
+compatible: "openisa,rv32m1-intmux"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  label:
+      required: true
diff --git a/dts/bindings/interrupt-controller/riscv,clint0.yaml b/dts/bindings/interrupt-controller/riscv,clint0.yaml
new file mode 100644
index 0000000000..82a48d04d8
--- /dev/null
+++ b/dts/bindings/interrupt-controller/riscv,clint0.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020, Katsuhiro Suzuki.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Common fields for the RISC-V Core-Local interruptor.
+
+include: [interrupt-controller.yaml, base.yaml]
+
+compatible: "riscv,clint0"
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
diff --git a/dts/bindings/interrupt-controller/riscv,cpu-intc.yaml b/dts/bindings/interrupt-controller/riscv,cpu-intc.yaml
new file mode 100644
index 0000000000..b5592e0c53
--- /dev/null
+++ b/dts/bindings/interrupt-controller/riscv,cpu-intc.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: RISC-V CPU interrupt controller
+
+compatible: "riscv,cpu-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
diff --git a/dts/bindings/interrupt-controller/riscv,plic0.yaml b/dts/bindings/interrupt-controller/riscv,plic0.yaml
new file mode 100644
index 0000000000..f662b6258f
--- /dev/null
+++ b/dts/bindings/interrupt-controller/riscv,plic0.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2018, SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for the RISC-V platform-local interrupt controller
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  riscv,max-priority:
+      type: int
+      description: maximum interrupt priority
+      required: true
+
+  "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/shared-irq.yaml b/dts/bindings/interrupt-controller/shared-irq.yaml
new file mode 100644
index 0000000000..3dfc64b1d2
--- /dev/null
+++ b/dts/bindings/interrupt-controller/shared-irq.yaml
@@ -0,0 +1,12 @@
+description: Shared IRQ interrupt dispatcher
+
+compatible: "shared-irq"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  interrupts:
+      required: true
+
+  label:
+      required: true
diff --git a/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
new file mode 100644
index 0000000000..45d004ed8c
--- /dev/null
+++ b/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018, SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive RISCV-V platform-local interrupt controller
+
+compatible: "sifive,plic-1.0.0"
+
+include: riscv,plic0.yaml
+
+properties:
+    riscv,ndev:
+        type: int
+        description: Number of external interrupts supported
+        required: true
diff --git a/dts/bindings/interrupt-controller/snps,archs-idu-intc.yaml b/dts/bindings/interrupt-controller/snps,archs-idu-intc.yaml
new file mode 100644
index 0000000000..1c89703958
--- /dev/null
+++ b/dts/bindings/interrupt-controller/snps,archs-idu-intc.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, synopsys
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ARC-HS Interrupt Distribution Unit 2nd-level interrupt controller. Can be
+    used in SMP configurations for dynamic IRQ routing and load balancing of
+    common/external IRQs towards the core interrupt controller.
+
+compatible: "snps,archs-idu-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/snps,arcv2-intc.yaml b/dts/bindings/interrupt-controller/snps,arcv2-intc.yaml
new file mode 100644
index 0000000000..09f1a029d5
--- /dev/null
+++ b/dts/bindings/interrupt-controller/snps,arcv2-intc.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2018, synopsys
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARCV2 interrupt controller
+
+compatible: "snps,arcv2-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/snps,designware-intc.yaml b/dts/bindings/interrupt-controller/snps,designware-intc.yaml
new file mode 100644
index 0000000000..957aa90d48
--- /dev/null
+++ b/dts/bindings/interrupt-controller/snps,designware-intc.yaml
@@ -0,0 +1,25 @@
+description: DesignWare programmable interrupt controller
+
+compatible: "snps,designware-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  "#interrupt-cells":
+      const: 3
+
+  num-irqs:
+      type: int
+      required: true
+      description: Number of irq the controller manages
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
diff --git a/dts/bindings/interrupt-controller/st,stm32-exti.yaml b/dts/bindings/interrupt-controller/st,stm32-exti.yaml
new file mode 100644
index 0000000000..25851b7563
--- /dev/null
+++ b/dts/bindings/interrupt-controller/st,stm32-exti.yaml
@@ -0,0 +1,9 @@
+description: STMicroelectronics STM32 family External Interrupt Controller
+
+compatible: "st,stm32-exti"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/interrupt-controller/swerv,pic.yaml b/dts/bindings/interrupt-controller/swerv,pic.yaml
new file mode 100644
index 0000000000..f71f2676e4
--- /dev/null
+++ b/dts/bindings/interrupt-controller/swerv,pic.yaml
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: SweRV EH1 PIC (Programmable Interrupt Controller)
+
+compatible: "swerv,pic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  riscv,max-priority:
+      type: int
+      description: maximum interrupt priority
+      required: true
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/interrupt-controller/vexriscv-intc0.yaml b/dts/bindings/interrupt-controller/vexriscv-intc0.yaml
new file mode 100644
index 0000000000..a99c8a297e
--- /dev/null
+++ b/dts/bindings/interrupt-controller/vexriscv-intc0.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX VexRiscV interrupt controller
+
+compatible: "vexriscv-intc0"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  riscv,max-priority:
+      type: int
+      description: maximum interrupt priority
+      required: true
+
+  "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/ipc/zephyr,ipc-openamp-static-vrings.yaml b/dts/bindings/ipc/zephyr,ipc-openamp-static-vrings.yaml
new file mode 100644
index 0000000000..4a4d0524f0
--- /dev/null
+++ b/dts/bindings/ipc/zephyr,ipc-openamp-static-vrings.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: OpenAMP (RPMsg with static VRINGs) backend
+
+compatible: "zephyr,ipc-openamp-static-vrings"
+
+include: base.yaml
+
+properties:
+  role:
+    description: OpenAMP roles
+    required: true
+    type: string
+    enum:
+      - host
+      - remote
+
+  memory-region:
+    description: phandle to the shared memory region
+    required: true
+    type: phandle
+
+  mboxes:
+    description: phandle to the MBOX controller (TX and RX are required)
+    required: true
+
+  mbox-names:
+    description: MBOX channel names (must be called "tx" and "rx")
+    required: true
diff --git a/dts/bindings/ipm/intel,adsp-mailbox.yaml b/dts/bindings/ipm/intel,adsp-mailbox.yaml
new file mode 100644
index 0000000000..e566f238eb
--- /dev/null
+++ b/dts/bindings/ipm/intel,adsp-mailbox.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: INTEL ADSP MAILBOX
+
+compatible: "intel,adsp-mailbox"
+
+include: base.yaml
+
+properties:
+  interrupts:
+    required: true
+
+  interrupt-parent:
+    required: true
diff --git a/dts/bindings/ipm/intel,cavs-idc.yaml b/dts/bindings/ipm/intel,cavs-idc.yaml
new file mode 100644
index 0000000000..30551ea342
--- /dev/null
+++ b/dts/bindings/ipm/intel,cavs-idc.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: CAVS Intra-DSP Communication (IDC) on Intel SoC
+
+compatible: "intel,cavs-idc"
+
+include: base.yaml
+
+properties:
+    interrupts:
+      required: true
+
+    interrupt-parent:
+      required: true
diff --git a/dts/bindings/ipm/nordic,nrf-ipc.yaml b/dts/bindings/ipm/nordic,nrf-ipc.yaml
new file mode 100644
index 0000000000..11b0cc4f5b
--- /dev/null
+++ b/dts/bindings/ipm/nordic,nrf-ipc.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF family IPC (Interprocessor Communication)
+
+compatible: "nordic,nrf-ipc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/ipm/nxp,lpc-mailbox.yaml b/dts/bindings/ipm/nxp,lpc-mailbox.yaml
new file mode 100644
index 0000000000..13d75cf874
--- /dev/null
+++ b/dts/bindings/ipm/nxp,lpc-mailbox.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC MAILBOX
+
+compatible: "nxp,lpc-mailbox"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  label:
+      required: true
diff --git a/dts/bindings/ipm/st,stm32-hsem-mailbox.yaml b/dts/bindings/ipm/st,stm32-hsem-mailbox.yaml
new file mode 100644
index 0000000000..813ca865f9
--- /dev/null
+++ b/dts/bindings/ipm/st,stm32-hsem-mailbox.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 HSEM MAILBOX
+
+compatible: "st,stm32-hsem-mailbox"
+
+include: base.yaml
+
+properties:
+  clocks:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/ipm/st,stm32-ipcc-mailbox.yaml b/dts/bindings/ipm/st,stm32-ipcc-mailbox.yaml
new file mode 100644
index 0000000000..39ea08d4a2
--- /dev/null
+++ b/dts/bindings/ipm/st,stm32-ipcc-mailbox.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 IPCC MAILBOX
+
+compatible: "st,stm32-ipcc-mailbox"
+
+include: base.yaml
+
+properties:
+  clocks:
+    required: true
diff --git a/dts/bindings/ipm/zephyr,ipm-console.yaml b/dts/bindings/ipm/zephyr,ipm-console.yaml
new file mode 100644
index 0000000000..8159b089f5
--- /dev/null
+++ b/dts/bindings/ipm/zephyr,ipm-console.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: IPM console
+
+compatible: "zephyr,ipm-console"
+
+include: uart-device.yaml
+
+properties:
+  label:
+    required: true
diff --git a/dts/bindings/kscan/focaltech,ft5336.yaml b/dts/bindings/kscan/focaltech,ft5336.yaml
new file mode 100644
index 0000000000..77cf707493
--- /dev/null
+++ b/dts/bindings/kscan/focaltech,ft5336.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: FT5XX6/FT6XX6 capacitive touch panels
+
+compatible: "focaltech,ft5336"
+
+include: [kscan.yaml, i2c-device.yaml]
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/kscan/holtek,ht16k33-keyscan.yaml b/dts/bindings/kscan/holtek,ht16k33-keyscan.yaml
new file mode 100644
index 0000000000..5ab63b1b0e
--- /dev/null
+++ b/dts/bindings/kscan/holtek,ht16k33-keyscan.yaml
@@ -0,0 +1,11 @@
+description: Holtek HT16K33 keyscan
+
+compatible: "holtek,ht16k33-keyscan"
+
+include: base.yaml
+
+on-bus: ht16k33
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/kscan/ite,it8xxx2-kscan.yaml b/dts/bindings/kscan/ite,it8xxx2-kscan.yaml
new file mode 100644
index 0000000000..7994301611
--- /dev/null
+++ b/dts/bindings/kscan/ite,it8xxx2-kscan.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it8xxx2 keyboard matrix controller
+
+compatible: "ite,it8xxx2-kscan"
+
+include: kscan.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    gpio-dev:
+        type: phandle
+        required: true
+        description: configure GPIO controller
+
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configure KSO pinmux controller
diff --git a/dts/bindings/kscan/kscan.yaml b/dts/bindings/kscan/kscan.yaml
new file mode 100644
index 0000000000..74fe974d95
--- /dev/null
+++ b/dts/bindings/kscan/kscan.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties for keyboard matrix devices
+
+include: base.yaml
+
+bus: kscan
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/kscan/microchip,xec-kscan.yaml b/dts/bindings/kscan/microchip,xec-kscan.yaml
new file mode 100644
index 0000000000..318d70a036
--- /dev/null
+++ b/dts/bindings/kscan/microchip,xec-kscan.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC keyboard matrix controller
+
+compatible: "microchip,xec-kscan"
+
+include: kscan.yaml
+
+properties:
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      type: int
+      const: 0
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/led/holtek,ht16k33.yaml b/dts/bindings/led/holtek,ht16k33.yaml
new file mode 100644
index 0000000000..4c373a1fc5
--- /dev/null
+++ b/dts/bindings/led/holtek,ht16k33.yaml
@@ -0,0 +1,15 @@
+description: Holtek HT16K33 LEDs
+
+compatible: "holtek,ht16k33"
+
+include: i2c-device.yaml
+
+bus: ht16k33
+
+properties:
+    label:
+      required: true
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: IRQ pin
diff --git a/dts/bindings/led/led-controller.yaml b/dts/bindings/led/led-controller.yaml
new file mode 100644
index 0000000000..d96cc654d5
--- /dev/null
+++ b/dts/bindings/led/led-controller.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for LED controllers and child LEDs
+
+properties:
+    label:
+      required: true
+
+child-binding:
+    description: LED child node
+    properties:
+        label:
+          required: false
+          type: string
+          description: Human readable string describing the LED
+        index:
+          required: false
+          type: int
+          description: |
+            Index of the LED on a controller. It can be used by drivers or
+            applications to map a logical LED to its real position on the
+            controller. For example, this allows to handle boards where the
+            LEDs in an array/strip are not wired following the LED order of
+            the controller.
+        color-mapping:
+          type: array
+          required: false
+          description: |
+            Channel to color mapping of a multicolor LED. If a LED supports
+            several colors, then the color-mapping property can be used to
+            describe how the hardware channels and the colors are mapped.
+
+            For example the channel to color mapping of RGB LEDs would be
+
+               color-mapping =
+                    <LED_COLOR_ID_RED>,
+                    <LED_COLOR_ID_GREEN>,
+                    <LED_COLOR_ID_BLUE>;
diff --git a/dts/bindings/led/nxp,pca9633.yaml b/dts/bindings/led/nxp,pca9633.yaml
new file mode 100644
index 0000000000..ec82d69457
--- /dev/null
+++ b/dts/bindings/led/nxp,pca9633.yaml
@@ -0,0 +1,5 @@
+description: NXP PCA9633 LED
+
+compatible: "nxp,pca9633"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/led/pwm-leds.yaml b/dts/bindings/led/pwm-leds.yaml
new file mode 100644
index 0000000000..9f32946c2d
--- /dev/null
+++ b/dts/bindings/led/pwm-leds.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: PWM LEDs parent node
+
+compatible: "pwm-leds"
+
+include:
+    - name: base.yaml
+      property-allowlist: [label]
+
+properties:
+    label:
+      description: |
+        Human readable string describing the device and used to set the device
+        name. It can be passed as argument to device_get_binding() to retrieve
+        the device. If this property is omitted, then the device name is set
+        from the node full name.
+
+child-binding:
+    description: PWM LED child node
+    properties:
+        pwms:
+          required: true
+          type: phandle-array
+
+        label:
+          required: false
+          type: string
+          description: |
+            Human readable string describing the LED. It can be used by an
+            application to identify this LED or to retrieve its number/index
+            (i.e. child node number) on the parent device.
diff --git a/dts/bindings/led/ti,lp3943.yaml b/dts/bindings/led/ti,lp3943.yaml
new file mode 100644
index 0000000000..402d64779d
--- /dev/null
+++ b/dts/bindings/led/ti,lp3943.yaml
@@ -0,0 +1,5 @@
+description: TI LP3943 LED
+
+compatible: "ti,lp3943"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/led/ti,lp503x.yaml b/dts/bindings/led/ti,lp503x.yaml
new file mode 100644
index 0000000000..fe9928ff02
--- /dev/null
+++ b/dts/bindings/led/ti,lp503x.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI LP503x LED controller node
+
+compatible: "ti,lp503x"
+
+include: ["i2c-device.yaml", "led-controller.yaml"]
+
+properties:
+    max_curr_opt:
+      type: boolean
+      required: false
+      description: |
+        If enabled the maximum current output is set to 35 mA (25.5 mA else).
+    log_scale_en:
+      type: boolean
+      required: false
+      description: |
+        If enabled a logarithmic dimming scale curve is used for LED brightness
+        control. A linear dimming scale curve is used else.
+
+child-binding:
+    properties:
+        label:
+          required: true
+        index:
+          required: true
+        color-mapping:
+          required: true
diff --git a/dts/bindings/led/ti,lp5562.yaml b/dts/bindings/led/ti,lp5562.yaml
new file mode 100644
index 0000000000..3264d3e9a5
--- /dev/null
+++ b/dts/bindings/led/ti,lp5562.yaml
@@ -0,0 +1,5 @@
+description: TI LP5562 LED
+
+compatible: "ti,lp5562"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/led/ti,tlc59108.yaml b/dts/bindings/led/ti,tlc59108.yaml
new file mode 100644
index 0000000000..7aa9a1dda8
--- /dev/null
+++ b/dts/bindings/led/ti,tlc59108.yaml
@@ -0,0 +1,5 @@
+description: TI TLC59108 LED
+
+compatible: "ti,tlc59108"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/led_strip/apa,apa102.yaml b/dts/bindings/led_strip/apa,apa102.yaml
new file mode 100644
index 0000000000..0a6e6a00a0
--- /dev/null
+++ b/dts/bindings/led_strip/apa,apa102.yaml
@@ -0,0 +1,5 @@
+description: APA102 SPI LED strip
+
+compatible: "apa,apa102"
+
+include: spi-device.yaml
diff --git a/dts/bindings/led_strip/greeled,lpd8803.yaml b/dts/bindings/led_strip/greeled,lpd8803.yaml
new file mode 100644
index 0000000000..6baca4898d
--- /dev/null
+++ b/dts/bindings/led_strip/greeled,lpd8803.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: GreeLed LPD8803 SPI LED strip
+
+compatible: "greeled,lpd8803"
+
+include: spi-device.yaml
diff --git a/dts/bindings/led_strip/greeled,lpd8806.yaml b/dts/bindings/led_strip/greeled,lpd8806.yaml
new file mode 100644
index 0000000000..0a0f0e9f6e
--- /dev/null
+++ b/dts/bindings/led_strip/greeled,lpd8806.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: GreeLed LPD8806 SPI LED strip
+
+compatible: "greeled,lpd8806"
+
+include: spi-device.yaml
diff --git a/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml b/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml
new file mode 100644
index 0000000000..c8ae12276e
--- /dev/null
+++ b/dts/bindings/led_strip/worldsemi,ws2812-gpio.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2019, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Worldsemi WS2812 LED strip, GPIO binding
+
+  Driver bindings for bit-banging a WS2812 or compatible LED strip.
+
+  The GPIO driver uses inline assembly, and isn't available for all
+  boards.
+
+compatible: "worldsemi,ws2812-gpio"
+
+include: [base.yaml, ws2812.yaml]
+
+properties:
+  label:
+    required: true
+
+  in-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      GPIO phandle and specifier for the pin connected to the daisy
+      chain's input pin. Exactly one pin should be given.
diff --git a/dts/bindings/led_strip/worldsemi,ws2812-spi.yaml b/dts/bindings/led_strip/worldsemi,ws2812-spi.yaml
new file mode 100644
index 0000000000..3c8626c1ec
--- /dev/null
+++ b/dts/bindings/led_strip/worldsemi,ws2812-spi.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2019, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Worldsemi WS2812 LED strip, SPI binding
+
+  Driver bindings for controlling a WS2812 or compatible LED
+  strip with a SPI master.
+
+  The SPI driver should be usable as long as a zephyr SPI API driver
+  is available for your board. Hardware specific tuning is required
+  using these properties:
+
+    - spi-max-frequency
+    - spi-zero-frame
+    - spi-one-frame.
+
+  Use of this driver implies an 8x internal memory overhead (1 byte of
+  driver RAM overhead per bit of pixel data).
+
+compatible: "worldsemi,ws2812-spi"
+
+include: [spi-device.yaml, ws2812.yaml]
+
+properties:
+
+  spi-one-frame:
+    type: int
+    required: true
+    description: 8-bit SPI frame to shift out for a 1 pulse.
+
+  spi-zero-frame:
+    type: int
+    required: true
+    description: 8-bit SPI frame to shift out for a 0 pulse.
diff --git a/dts/bindings/led_strip/ws2812.yaml b/dts/bindings/led_strip/ws2812.yaml
new file mode 100644
index 0000000000..c5e126c7df
--- /dev/null
+++ b/dts/bindings/led_strip/ws2812.yaml
@@ -0,0 +1,66 @@
+# Copyright (c) 2019, Linaro Limited
+# Copyright (c) 2019, Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Worldsemi WS2812 (and compatible) LED controller
+
+  Driver bindings for daisy chains of WS2812 (and compatible devices
+  like SK6812, or Everlight B1414) LED controllers.
+
+  The PWM protocol is described here:
+  https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
+
+  A 0 bit's pulse width is between 200 and 500 ns. A 1 bit's is
+  at least 550 ns, with 700 ns or so typical. Pixel order is GRB.
+
+  You can connect the device to either a GPIO on your SoC, or a SPI
+  MOSI line. Use the worldsemi,ws2812-spi.yaml or
+  worldsemi,ws2812-gpio.yaml bindings instead of this file after
+  making your choice.
+
+  Everlight B1414:
+
+  The specification of the Everlight B1414 LED controller is slightly different.
+  For the control signal (waveform) each bit is described with a 1.2 us pulse:
+
+    0 bit: 300 ns high and 900 ns low.
+    1 bit: 900 ns high and 300 ns low.
+
+  There is a a +/- 80 ns tolerance for each timing.
+
+  The latch/reset delay is 250 us and it must be set using the reset-delay
+  property. The pixel order depends on the model and it can be configured
+  using the color-mapping property.
+
+properties:
+  chain-length:
+    type: int
+    required: true
+    description: |
+      The number of devices in the daisy-chain.
+
+  color-mapping:
+    type: array
+    required: true
+    description: |
+      Channel to color mapping (or pixel order).
+
+      For example a GRB channel to color mapping would be
+
+         color-mapping = <LED_COLOR_ID_GREEN
+                          LED_COLOR_ID_RED
+                          LED_COLOR_ID_BLUE>;
+
+  reset-delay:
+    type: int
+    required: false
+    default: 8
+    description: |
+      Minimum delay to wait (in microseconds) to make sure that the strip has
+      latched the signal. If omitted, a default value of 8 microseconds is used.
+      This default is good for the WS2812 controllers. Note that despite the
+      WS2812 datasheet states that a 50 microseconds delay is required, it seems
+      6 microseconds is enough. The default is set to 8 microseconds just to be
+      safe.
diff --git a/dts/bindings/lora/semtech,sx1261.yaml b/dts/bindings/lora/semtech,sx1261.yaml
new file mode 100644
index 0000000000..8e637a16f8
--- /dev/null
+++ b/dts/bindings/lora/semtech,sx1261.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 Andreas Sandberg
+# SPDX-License-Identifier: Apache-2.0
+
+description: Semtech SX1261 LoRa Modem
+
+compatible: "semtech,sx1261"
+
+include: semtech,sx126x-base.yaml
+
+properties:
+    reset-gpios:
+      required: true
+    busy-gpios:
+      required: true
+    dio1-gpios:
+      required: true
diff --git a/dts/bindings/lora/semtech,sx1262.yaml b/dts/bindings/lora/semtech,sx1262.yaml
new file mode 100644
index 0000000000..c6d04a23be
--- /dev/null
+++ b/dts/bindings/lora/semtech,sx1262.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 Andreas Sandberg
+# SPDX-License-Identifier: Apache-2.0
+
+description: Semtech SX1262 LoRa Modem
+
+compatible: "semtech,sx1262"
+
+include: semtech,sx126x-base.yaml
+
+properties:
+    reset-gpios:
+      required: true
+    busy-gpios:
+      required: true
+    dio1-gpios:
+      required: true
diff --git a/dts/bindings/lora/semtech,sx126x-base.yaml b/dts/bindings/lora/semtech,sx126x-base.yaml
new file mode 100644
index 0000000000..02bf5e9bd6
--- /dev/null
+++ b/dts/bindings/lora/semtech,sx126x-base.yaml
@@ -0,0 +1,70 @@
+# Copyright (c) 2019 Manivannan Sadhasivam
+# Copyright (c) 2020 Andreas Sandberg
+# SPDX-License-Identifier: Apache-2.0
+
+include: spi-device.yaml
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        GPIO connected to the modem's NRESET signal.
+
+        This signal is open-drain, active-low as interpreted by the
+        modem.
+
+    busy-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        GPIO connected to the modem's BUSY signal.
+
+    antenna-enable-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Antenna power enable pin.
+
+    tx-enable-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Antenna switch TX enable GPIO. If set, the driver tracks the
+        state of the radio and controls the RF switch.
+
+    rx-enable-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Antenna switch RX enable GPIO. If set, the driver tracks the
+        state of the radio and controls the RF switch.
+
+    dio1-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        GPIO connected to DIO1. This GPIO will be used as a generic
+        IRQ line from the chip.
+
+    dio2-tx-enable:
+      type: boolean
+      required: false
+      description: |
+        Use DIO2 to drive an RF switch selecting between the TX and RX
+        paths. When enabled, DIO2 goes high when the chip is
+        transmitting.
+
+    dio3-tcxo-voltage:
+      type: int
+      required: false
+      description: |
+        TCXO supply voltage controlled by DIO3 if present.
+
+        See constants in dt-bindings/lora/sx126x.h.
+
+    tcxo-power-startup-delay-ms:
+      type: int
+      required: false
+      description: |
+        Startup delay to let the TCXO stabilize after TCXO power on.
diff --git a/dts/bindings/lora/semtech,sx1272.yaml b/dts/bindings/lora/semtech,sx1272.yaml
new file mode 100644
index 0000000000..c75b30ef8e
--- /dev/null
+++ b/dts/bindings/lora/semtech,sx1272.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Ilya Tagunov
+# SPDX-License-Identifier: Apache-2.0
+
+description: Semtech SX1272 LoRa Modem
+
+compatible: "semtech,sx1272"
+
+include: semtech,sx127x-base.yaml
diff --git a/dts/bindings/lora/semtech,sx1276.yaml b/dts/bindings/lora/semtech,sx1276.yaml
new file mode 100644
index 0000000000..ef35e3780e
--- /dev/null
+++ b/dts/bindings/lora/semtech,sx1276.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Ilya Tagunov
+# SPDX-License-Identifier: Apache-2.0
+
+description: Semtech SX1276 LoRa Modem
+
+compatible: "semtech,sx1276"
+
+include: semtech,sx127x-base.yaml
diff --git a/dts/bindings/lora/semtech,sx127x-base.yaml b/dts/bindings/lora/semtech,sx127x-base.yaml
new file mode 100644
index 0000000000..19adb36fd3
--- /dev/null
+++ b/dts/bindings/lora/semtech,sx127x-base.yaml
@@ -0,0 +1,70 @@
+# Copyright (c) 2019, Manivannan Sadhasivam
+# Copyright (c) 2020, Grinn
+# SPDX-License-Identifier: Apache-2.0
+
+include: spi-device.yaml
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        GPIO connected to the modem's RESET/NRESET signal.
+
+        This signal is open-drain, active-high (SX1272/3) or
+        active-low (SX1276/7/8/9) as interpreted by the modem.
+
+    dio-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        Up to six pins that produce service interrupts from the modem.
+
+        These signals are normally active-high.
+
+    power-amplifier-output:
+      type: string
+      required: false
+      description: |
+        Selects power amplifier output pin. This is required when neither
+        'rfo-enable-gpios' nor 'pa-boost-enable-gpios' is specified. In other
+        case this property is simply ignored.
+      enum:
+         - "rfo"
+         - "pa-boost"
+
+    antenna-enable-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Antenna power enable pin.
+
+    rfi-enable-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        RFI antenna input enable pin.
+
+    rfo-enable-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        RFO antenna output enable pin.
+
+    pa-boost-enable-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        PA_BOOST antenna output enable pin.
+
+    tcxo-power-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        TCXO power enable pin.
+
+    tcxo-power-startup-delay-ms:
+      type: int
+      required: false
+      description: |
+        Delay which has to be applied after enabling TCXO power.
diff --git a/dts/bindings/lora/st,stm32wl-subghz-radio.yaml b/dts/bindings/lora/st,stm32wl-subghz-radio.yaml
new file mode 100644
index 0000000000..3060703e5a
--- /dev/null
+++ b/dts/bindings/lora/st,stm32wl-subghz-radio.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Fabio Baltieri
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32WL SUBGHZ Radio
+
+compatible: "st,stm32wl-subghz-radio"
+
+include: semtech,sx126x-base.yaml
+
+properties:
+    interrupts:
+      required: true
+      description: |
+        Position of the "Radio IRQ, Busy" interrupt line.
diff --git a/dts/bindings/mailbox/mailbox-controller.yaml b/dts/bindings/mailbox/mailbox-controller.yaml
new file mode 100644
index 0000000000..ff9f80e55e
--- /dev/null
+++ b/dts/bindings/mailbox/mailbox-controller.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for mailbox / IPM controllers
+
+properties:
+    "#mbox-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a Mailbox specifier
diff --git a/dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml b/dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml
new file mode 100644
index 0000000000..07f79aeed9
--- /dev/null
+++ b/dts/bindings/mbox/nordic,mbox-nrf-ipc.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF family IPC (MBOX Interprocessor Communication)
+
+compatible: "nordic,mbox-nrf-ipc"
+
+include: [base.yaml, mailbox-controller.yaml]
+
+properties:
+    tx-mask:
+      type: int
+      required: true
+      description: TX supported channels mask
+
+    rx-mask:
+      type: int
+      required: true
+      description: RX supported channels mask
+
+    interrupts:
+      required: true
+
+mbox-cells:
+  - channel
diff --git a/dts/bindings/mdio/atmel,sam-mdio.yaml b/dts/bindings/mdio/atmel,sam-mdio.yaml
new file mode 100644
index 0000000000..9e4f8b605f
--- /dev/null
+++ b/dts/bindings/mdio/atmel,sam-mdio.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 IP-Logix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Family MDIO Driver node
+
+compatible: "atmel,sam-mdio"
+
+include: mdio-controller.yaml
+
+properties:
+    pinctrl-0:
+      type: phandles
+      required: false
+      description: |
+        PIO pin configuration for MDC, and MDIO signals.
+
+        For example the GMAC on SAME7x would be
+          pinctrl-0 = <&pd8a_gmac_gmdc &pd9a_gmac_gmdio>;
diff --git a/dts/bindings/mdio/mdio-controller.yaml b/dts/bindings/mdio/mdio-controller.yaml
new file mode 100644
index 0000000000..28fda48755
--- /dev/null
+++ b/dts/bindings/mdio/mdio-controller.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2021 IP-Logix Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for MDIO controllers
+
+include: base.yaml
+
+bus: mdio
+
+properties:
+    label:
+      required: true
+    protocol:
+      required: false
+      type: string
+      description: |
+        MDIO bus framing protocol to use for communication. Most devices
+        support clause 22.
+
+        - clause 22: IEEE802.3 clause 22 frame format
+        - clause 45: IEEE802.3 clause 45 frame format
+        - micrel SMI: Micrel Serial Management Interface frame format
+      enum:
+        - "clause 22"
+        - "clause 45"
+        - "micrel SMI"
+      default: "clause 22"
diff --git a/dts/bindings/memory-controllers/ite,it8xxx2-bbram.yaml b/dts/bindings/memory-controllers/ite,it8xxx2-bbram.yaml
new file mode 100644
index 0000000000..0104f892be
--- /dev/null
+++ b/dts/bindings/memory-controllers/ite,it8xxx2-bbram.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021 Google Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE, IT8XXX2 Battery Backed RAM node
+
+compatible: "ite,it8xxx2-bbram"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
+
+    label:
+        required: true
diff --git a/dts/bindings/memory-controllers/nuvoton,npcx-bbram.yaml b/dts/bindings/memory-controllers/nuvoton,npcx-bbram.yaml
new file mode 100644
index 0000000000..2d95874923
--- /dev/null
+++ b/dts/bindings/memory-controllers/nuvoton,npcx-bbram.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021 Google Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Battery Backed RAM node
+
+compatible: "nuvoton,npcx-bbram"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
+
+    label:
+        required: true
diff --git a/dts/bindings/memory-controllers/nxp,imx-semc.yaml b/dts/bindings/memory-controllers/nxp,imx-semc.yaml
new file mode 100644
index 0000000000..d7716e94d2
--- /dev/null
+++ b/dts/bindings/memory-controllers/nxp,imx-semc.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Smart External Memory Controller (SEMC)
+
+compatible: "nxp,imx-semc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/memory-controllers/st,stm32-backup-sram.yaml b/dts/bindings/memory-controllers/st,stm32-backup-sram.yaml
new file mode 100644
index 0000000000..04bcab041b
--- /dev/null
+++ b/dts/bindings/memory-controllers/st,stm32-backup-sram.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 Backup SRAM.
+
+  With a battery connected to the VBAT pin, the backup SRAM can be used to
+  retain data during low-power mode (Standby and VBAT mode).
+
+compatible: "st,stm32-backup-sram"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+  label:
+    required: true
+
+  reg:
+    required: true
+
+  clocks:
+    required: true
diff --git a/dts/bindings/memory-controllers/st,stm32-fmc-sdram.yaml b/dts/bindings/memory-controllers/st,stm32-fmc-sdram.yaml
new file mode 100644
index 0000000000..c925b0deb2
--- /dev/null
+++ b/dts/bindings/memory-controllers/st,stm32-fmc-sdram.yaml
@@ -0,0 +1,169 @@
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 Flexible Memory Controller (SDRAM controller).
+
+  The FMC SDRAM controller can be used to interface with external SDRAM
+  memories. Up to 2 SDRAM banks are supported with independent configuration. It
+  is worth to note that while settings are independent, some are shared or are
+  required to be set according to the most constraining device. Refer to the
+  properties description or the datasheet for more details.
+
+  The FMC SDRAM controller is defined below the FMC node and SDRAM banks are
+  defined as child nodes of the FMC SDRAM node. You can either have bank 1 (@0),
+  bank 2 (@1) or both. You can enable the FMC SDRAM controller in your board
+  DeviceTree file like this:
+
+  &fmc {
+      status = "okay";
+      pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
+
+      sdram {
+          status = "okay";
+
+          power-up-delay = <100>;
+          num-auto-refresh = <8>;
+          mode-register = <0x220>;
+          refresh-rate = <603>;
+
+          bank@0 {
+              reg = <0>;
+
+              st,sdram-control = <STM32_FMC_SDRAM_NC_9
+                                  STM32_FMC_SDRAM_NR_12
+                                  STM32_FMC_SDRAM_MWID_32
+                                  STM32_FMC_SDRAM_NB_4
+                                  STM32_FMC_SDRAM_CAS_2
+                                  STM32_FMC_SDRAM_SDCLK_PERIOD_2
+                                  STM32_FMC_SDRAM_RBURST_ENABLE
+                                  STM32_FMC_SDRAM_RPIPE_0>;
+              st,sdram-timing = <2 6 4 6 2 2 2>;
+          };
+
+          bank@1 {
+              reg = <1>;
+              ...
+          };
+      };
+  };
+
+  Note that you will find definitions for the st,sdram-control field at
+  dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
+  in the SoC DeviceTree files.
+
+  Finally, in order to make the memory available you will need to define new
+  memory device/s in DeviceTree:
+
+  sdram1: sdram@c0000000 {
+      compatible = "mmio-sram";
+      device_type = "memory";
+      reg = <0xc000000 DT_SIZE_M(X)>;
+      zephyr,memory-region = "SDRAM1";
+  };
+
+  sdram2: sdram@d0000000 {
+      compatible = "mmio-sram";
+      device_type = "memory";
+      reg = <0xd000000 DT_SIZE_M(X)>;
+      zephyr,memory-region = "SDRAM2";
+  };
+
+  It is important to use sdram1 and sdram2 node labels for bank 1 and bank 2
+  respectively. Memory addresses are 0xc0000000 and 0xd0000000 for bank 1 and
+  bank 2 respectively.
+
+compatible: "st,stm32-fmc-sdram"
+
+include: base.yaml
+
+properties:
+  label:
+    required: true
+
+  "#address-cells":
+    required: true
+    const: 1
+
+  "#size-cells":
+    required: true
+    const: 0
+
+  power-up-delay:
+    type: int
+    default: 100
+    description: Power-up delay in microseconds.
+
+  num-auto-refresh:
+    type: int
+    default: 8
+    description: Number of auto-refresh commands issued.
+
+  mode-register:
+    type: int
+    required: true
+    description:
+      A 14-bit field that defines the SDRAM Mode Register content. The mode
+      register bits are also used to program the extended mode register for
+      mobile SDRAM.
+
+  refresh-rate:
+    type: int
+    required: true
+    description:
+      A 13-bit field defines the refresh rate of the SDRAM device. It is
+      expressed in number of memory clock cycles. It must be set at least to
+      41 SDRAM clock cycles.
+
+child-binding:
+  description: SDRAM bank.
+
+  properties:
+    reg:
+      type: int
+      required: true
+
+    st,sdram-control:
+      type: array
+      required: true
+      description: |
+        SDRAM control configuration. Expected fields, in order, are,
+
+        - NC: Number of bits of a column address.
+        - NR: Number of bits of a row address.
+        - MWID: Memory device width.
+        - NB: Number of internal banks.
+        - CAS: SDRAM CAS latency in number of memory clock cycles.
+        - SDCLK: SDRAM clock period. If two SDRAM devices are used both should
+          have the same value.
+        - RBURST: Enable burst read mode. If two SDRAM devices are used both
+          should have the same value.
+        - RPIPE: Delay, in fmc_ker_ck clock cycles, for reading data after CAS
+          latency. If two SDRAM devices are used both should have the same
+          value.
+
+    st,sdram-timing:
+      type: array
+      required: true
+      description: |
+        SDRAM timing configuration. Expected fields, in order, are,
+
+        - TMRD: Delay between a Load Mode Register command and an Active or
+          Refresh command in number of memory clock cycles.
+        - TXSR: Delay from releasing the Self-refresh command to issuing the
+          Activate command in number of memory clock cycles. If two SDRAM
+          devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with
+          the same TXSR timing corresponding to the slowest SDRAM device
+        - TRAS: Minimum Self-refresh period in number of memory clock cycles.
+        - TRC: Delay between the Refresh command and the Activate command, as
+          well as the delay between two consecutive Refresh commands. It is
+          expressed in number of memory clock cycles. If two SDRAM devices are
+          used, the TRC must be programmed with the timings of the slowest
+          device in both banks.
+        - TWP: Delay between a Write and a Precharge command in number of memory
+          clock cycles
+        - TRP: Delay between a Precharge command and another command in number
+          of memory clock cycles. If two SDRAM devices are used, the TRP must be
+          programmed with the timing of the slowest device in both banks.
+        - TRCD: Delay between the Activate command and a Read/Write command in
+          number of memory clock cycles.
diff --git a/dts/bindings/memory-controllers/st,stm32-fmc.yaml b/dts/bindings/memory-controllers/st,stm32-fmc.yaml
new file mode 100644
index 0000000000..f958bd2c19
--- /dev/null
+++ b/dts/bindings/memory-controllers/st,stm32-fmc.yaml
@@ -0,0 +1,48 @@
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 Flexible Memory Controller (FMC).
+
+  The FMC allows to interface with static-memory mapped external devices such as
+  SRAM, NOR Flash, NAND Flash, SDRAM...
+
+  All external memories share the addresses, data and control signals with the
+  controller. Each external device is accessed by means of a unique chip select.
+  The FMC performs only one access at a time to an external device.
+
+  The flexible memory controller includes three memory controllers:
+
+    - NOR/PSRAM memory controller
+    - NAND memory controller (some devices also support PC Card)
+    - Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
+
+  Each memory controller is defined below the FMC DeviceTree node and is managed
+  by a separate Zephyr device. However, because signals are shared the FMC
+  device handles the signals and the peripheral clocks. FMC can be enabled
+  in your board DeviceTree file like this:
+
+  &fmc {
+      status = "okay";
+      pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
+  };
+
+compatible: "st,stm32-fmc"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    clocks:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
diff --git a/dts/bindings/memory-controllers/zephyr,bbram-emul.yaml b/dts/bindings/memory-controllers/zephyr,bbram-emul.yaml
new file mode 100644
index 0000000000..7581d6913b
--- /dev/null
+++ b/dts/bindings/memory-controllers/zephyr,bbram-emul.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2021 Google Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr, Battery Backed RAM emulator node
+
+compatible: "zephyr,bbram-emul"
+
+include: base.yaml
+
+properties:
+    size:
+        type: int
+        required: true
+        description: Size of the BBRAM region in bytes.
+
+    label:
+        required: true
diff --git a/dts/bindings/mhu/arm,mhu.yaml b/dts/bindings/mhu/arm,mhu.yaml
new file mode 100644
index 0000000000..af6c0d5cb8
--- /dev/null
+++ b/dts/bindings/mhu/arm,mhu.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM MHU (Message Handling Unit)
+
+compatible: "arm,mhu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/misc/nuvoton,npcx-booter-variant.yaml b/dts/bindings/misc/nuvoton,npcx-booter-variant.yaml
new file mode 100644
index 0000000000..4a6866d17c
--- /dev/null
+++ b/dts/bindings/misc/nuvoton,npcx-booter-variant.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX booter variant options
+
+compatible: "nuvoton,npcx-booter-variant"
+
+properties:
+    hif-type-auto:
+        type: boolean
+        required: false
+        description: |
+            The host interface type (LPC/eSPI/SHI) is configured by booter
+            if true; otherwise, it should be configured by the firmware.
diff --git a/dts/bindings/misc/nuvoton,npcx-soc-id.yaml b/dts/bindings/misc/nuvoton,npcx-soc-id.yaml
new file mode 100644
index 0000000000..e65a5473fa
--- /dev/null
+++ b/dts/bindings/misc/nuvoton,npcx-soc-id.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX soc ID node
+
+compatible: "nuvoton,npcx-soc-id"
+
+properties:
+    family-id:
+        type: int
+        required: true
+        description: NPCX family ID
+
+    chip-id:
+        type: int
+        required: true
+        description: NPCX chip ID
+
+    device-id:
+        type: int
+        required: true
+        description: NPCX device ID
+
+    revision-reg:
+        type: array
+        required: true
+        description: NPCX revision register address & length in byte
diff --git a/dts/bindings/misc/skyworks,sky13351.yaml b/dts/bindings/misc/skyworks,sky13351.yaml
new file mode 100644
index 0000000000..f4e3152881
--- /dev/null
+++ b/dts/bindings/misc/skyworks,sky13351.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019, Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Output selectors on the SKY13351 GaAs SPDT FET I/C switch
+
+compatible: "skyworks,sky13351"
+
+include: base.yaml
+
+properties:
+    vctl1-gpios:
+        type: phandle-array
+        required: true
+        description: VCTL1 pin
+    vctl2-gpios:
+        type: phandle-array
+        required: true
+        description: VCTL2 pin
diff --git a/dts/bindings/misc/zephyr,modbus-serial.yaml b/dts/bindings/misc/zephyr,modbus-serial.yaml
new file mode 100644
index 0000000000..a79736b3b1
--- /dev/null
+++ b/dts/bindings/misc/zephyr,modbus-serial.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2020 PHYTEC Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: Modbus over serial line device
+
+compatible: "zephyr,modbus-serial"
+
+include: uart-device.yaml
+
+properties:
+    de-gpios:
+      type: phandle-array
+      required: false
+      description: Driver enable pin.
+
+        Driver enable pin (DE) of the RS-485 transceiver.
+        If connected directly the MCU pin should be configured
+        as active high.
+
+    re-gpios:
+      type: phandle-array
+      required: false
+      description: Receiver enable pin.
+
+        Receiver enable pin (nRE) of the RS-485 transceiver.
+        If connected directly the MCU pin should be configured
+        as active low.
diff --git a/dts/bindings/mmc/mmc.yaml b/dts/bindings/mmc/mmc.yaml
new file mode 100644
index 0000000000..ba5b527398
--- /dev/null
+++ b/dts/bindings/mmc/mmc.yaml
@@ -0,0 +1,6 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+# Specifies the MMC/SDHC module
+
+include: base.yaml
diff --git a/dts/bindings/mmc/nxp,imx-usdhc.yaml b/dts/bindings/mmc/nxp,imx-usdhc.yaml
new file mode 100644
index 0000000000..9bc1a0f14d
--- /dev/null
+++ b/dts/bindings/mmc/nxp,imx-usdhc.yaml
@@ -0,0 +1,48 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP i.MXRT USDHC module
+
+compatible: "nxp,imx-usdhc"
+
+include: mmc.yaml
+
+properties:
+    clocks:
+      required: true
+
+    pwr-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Power pin
+        This pin defaults to active high when consumed by the SD card. The
+        property value should ensure the flags properly describe the signal
+        that is presented to the driver.
+
+    cd-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Detect pin
+        This pin defaults to active low when produced by the SD card. The
+        property value should ensure the flags properly describe the signal
+        that is presented to the driver.
+
+    no-1-8-v:
+      type: boolean
+      required: false
+      description: |
+        When the external SD card circuit does not support 1.8V, add this
+        property to disable 1.8v card voltage of SD card controller.
+
+    detect-dat3:
+      type: boolean
+      required: false
+      description: |
+        Enable the host to detect an SD card via the DAT3 line of the SD card
+        connection. Requires the board to define a function to pull DAT3 low or
+        high using pullup/pulldown resistors.
+
+    label:
+      required: true
diff --git a/dts/bindings/mmc/st,stm32-sdmmc.yaml b/dts/bindings/mmc/st,stm32-sdmmc.yaml
new file mode 100644
index 0000000000..d83faf9a8e
--- /dev/null
+++ b/dts/bindings/mmc/st,stm32-sdmmc.yaml
@@ -0,0 +1,31 @@
+description: stm32 sdmmc disk access
+
+compatible: "st,stm32-sdmmc"
+
+include: [mmc.yaml, pinctrl-device.yaml]
+
+properties:
+    clocks:
+        required: true
+
+    label:
+        required: true
+
+    reg:
+        required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
+    cd-gpios:
+        type: phandle-array
+        required: false
+        description: Card Detect pin
+
+    pwr-gpios:
+        type: phandle-array
+        required: false
+        description: Power pin
diff --git a/dts/bindings/mmc/zephyr,mmc-spi-slot.yaml b/dts/bindings/mmc/zephyr,mmc-spi-slot.yaml
new file mode 100644
index 0000000000..d6a743b14b
--- /dev/null
+++ b/dts/bindings/mmc/zephyr,mmc-spi-slot.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+description: MMC/SD/SDIO slot connected via SPI
+
+compatible: "zephyr,mmc-spi-slot"
+
+include: spi-device.yaml
diff --git a/dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml
new file mode 100644
index 0000000000..e44a04a50b
--- /dev/null
+++ b/dts/bindings/mmu_mpu/arm,armv6m-mpu.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARMv6-M Memory Protection Unit (MPU)
+
+compatible: "arm,armv6m-mpu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    arm,num-mpu-regions:
+      required: true
+      type: int
+      const: 8
+      description: number of MPU regions supported by hardware
diff --git a/dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml
new file mode 100644
index 0000000000..4225b6aaf6
--- /dev/null
+++ b/dts/bindings/mmu_mpu/arm,armv7m-mpu.yaml
@@ -0,0 +1,14 @@
+description: ARMv7-M Memory Protection Unit (MPU)
+
+compatible: "arm,armv7m-mpu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    arm,num-mpu-regions:
+      required: true
+      type: int
+      description: number of MPU regions supported by hardware
diff --git a/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml
new file mode 100644
index 0000000000..610ec29daa
--- /dev/null
+++ b/dts/bindings/mmu_mpu/arm,armv8.1m-mpu.yaml
@@ -0,0 +1,14 @@
+description: ARMv8.1-M MPU (Memory Protection Unit)
+
+compatible: "arm,armv8.1m-mpu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    arm,num-mpu-regions:
+      required: true
+      type: int
+      description: number of MPU regions supported by hardware
diff --git a/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml b/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml
new file mode 100644
index 0000000000..662b504371
--- /dev/null
+++ b/dts/bindings/mmu_mpu/arm,armv8m-mpu.yaml
@@ -0,0 +1,14 @@
+description: ARMv8-M MPU (Memory Protection Unit)
+
+compatible: "arm,armv8m-mpu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    arm,num-mpu-regions:
+      required: true
+      type: int
+      description: number of MPU regions supported by hardware
diff --git a/dts/bindings/modem/openisa,rv32m1-genfsk.yaml b/dts/bindings/modem/openisa,rv32m1-genfsk.yaml
new file mode 100644
index 0000000000..37416f084f
--- /dev/null
+++ b/dts/bindings/modem/openisa,rv32m1-genfsk.yaml
@@ -0,0 +1,15 @@
+# Copyright 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 Generic FSK programmable modem node
+
+compatible: "openisa,rv32m1-genfsk"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/modem/quectel,bg9x.yaml b/dts/bindings/modem/quectel,bg9x.yaml
new file mode 100644
index 0000000000..516161c522
--- /dev/null
+++ b/dts/bindings/modem/quectel,bg9x.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2020 Analog Life LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: quectel BG9x modem
+
+compatible: "quectel,bg9x"
+
+include: uart-device.yaml
+
+properties:
+    label:
+      required: true
+
+    mdm-power-gpios:
+      type: phandle-array
+      required: true
+
+    mdm-reset-gpios:
+      type: phandle-array
+      required: true
+
+    mdm-dtr-gpios:
+      type: phandle-array
+      required: false
+
+    mdm-wdisable-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/modem/simcom,sim7080.yaml b/dts/bindings/modem/simcom,sim7080.yaml
new file mode 100644
index 0000000000..f66cee254c
--- /dev/null
+++ b/dts/bindings/modem/simcom,sim7080.yaml
@@ -0,0 +1,16 @@
+# Copyright (C) 2021 metraTec GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: Simcom Sim7080 modem
+
+compatible: "simcom,sim7080"
+
+include: uart-device.yaml
+
+properties:
+  label:
+    required: true
+
+  mdm-power-gpios:
+    type: phandle-array
+    required: true
diff --git a/dts/bindings/modem/swir,hl7800.yaml b/dts/bindings/modem/swir,hl7800.yaml
new file mode 100644
index 0000000000..7ee2389f4f
--- /dev/null
+++ b/dts/bindings/modem/swir,hl7800.yaml
@@ -0,0 +1,51 @@
+#
+# Copyright (c) 2020, Laird Connectivity
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Sierra Wireless HL7800 Modem
+
+compatible: "swir,hl7800"
+
+include: uart-device.yaml
+
+properties:
+    label:
+      required: true
+
+    mdm-wake-gpios:
+        type: phandle-array
+        required: true
+
+    mdm-reset-gpios:
+        type: phandle-array
+        required: true
+
+    mdm-pwr-on-gpios:
+        type: phandle-array
+        required: true
+
+    mdm-fast-shutd-gpios:
+        type: phandle-array
+        required: true
+
+    mdm-vgpio-gpios:
+        type: phandle-array
+        required: true
+
+    mdm-uart-dsr-gpios:
+        type: phandle-array
+        required: true
+
+    mdm-uart-cts-gpios:
+        type: phandle-array
+        required: true
+
+    mdm-gpio2-gpios:
+        type: phandle-array
+        required: false
+
+    mdm-gpio6-gpios:
+        type: phandle-array
+        required: true
diff --git a/dts/bindings/modem/u-blox,sara-r4.yaml b/dts/bindings/modem/u-blox,sara-r4.yaml
new file mode 100644
index 0000000000..87e9a1e74e
--- /dev/null
+++ b/dts/bindings/modem/u-blox,sara-r4.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2019, Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: u-blox SARA-R4 modem
+
+compatible: "u-blox,sara-r4"
+
+include: uart-device.yaml
+
+properties:
+    label:
+      required: true
+
+    mdm-power-gpios:
+      type: phandle-array
+      required: true
+
+    mdm-reset-gpios:
+      type: phandle-array
+      required: false
+
+    mdm-vint-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/modem/wnc,m14a2a.yaml b/dts/bindings/modem/wnc,m14a2a.yaml
new file mode 100644
index 0000000000..8df975c3f4
--- /dev/null
+++ b/dts/bindings/modem/wnc,m14a2a.yaml
@@ -0,0 +1,37 @@
+# Copyright (c) 2018, Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: WNC-M14A2A LTE-M modem
+
+compatible: "wnc,m14a2a"
+
+include: uart-device.yaml
+
+properties:
+    label:
+      required: true
+
+    mdm-boot-mode-sel-gpios:
+      type: phandle-array
+      required: true
+
+    mdm-power-gpios:
+      type: phandle-array
+      required: true
+
+    mdm-keep-awake-gpios:
+      type: phandle-array
+      required: true
+
+    mdm-reset-gpios:
+      type: phandle-array
+      required: true
+
+    mdm-shld-trans-ena-gpios:
+      type: phandle-array
+      required: true
+
+    mdm-send-ok-gpios:
+      type: phandle-array
+      required: false
+      description: UART RTS pin if no HW flow control (set to always enabled)
diff --git a/dts/bindings/modem/zephyr,gsm-ppp.yaml b/dts/bindings/modem/zephyr,gsm-ppp.yaml
new file mode 100644
index 0000000000..768173d627
--- /dev/null
+++ b/dts/bindings/modem/zephyr,gsm-ppp.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 G-Technologies Sdn. Bhd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: GSM PPP modem
+
+compatible: "zephyr,gsm-ppp"
+
+include: uart-device.yaml
diff --git a/dts/bindings/mtd/atmel,at24.yaml b/dts/bindings/mtd/atmel,at24.yaml
new file mode 100644
index 0000000000..da3369ec62
--- /dev/null
+++ b/dts/bindings/mtd/atmel,at24.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# Copyright (c) 2018, Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel AT24 (or compatible) I2C EEPROM
+
+compatible: "atmel,at24"
+
+include: ["atmel,at2x-base.yaml", i2c-device.yaml]
diff --git a/dts/bindings/mtd/atmel,at25.yaml b/dts/bindings/mtd/atmel,at25.yaml
new file mode 100644
index 0000000000..9b1977e8dc
--- /dev/null
+++ b/dts/bindings/mtd/atmel,at25.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel AT25 (or compatible) SPI EEPROM
+
+compatible: "atmel,at25"
+
+include: ["atmel,at2x-base.yaml", spi-device.yaml]
diff --git a/dts/bindings/mtd/atmel,at2x-base.yaml b/dts/bindings/mtd/atmel,at2x-base.yaml
new file mode 100644
index 0000000000..7ba8b4677e
--- /dev/null
+++ b/dts/bindings/mtd/atmel,at2x-base.yaml
@@ -0,0 +1,29 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for AT24 (I2C) and AT25 (SPI) EEPROM devices
+
+include: eeprom-base.yaml
+
+properties:
+    size:
+      required: true
+    pagesize:
+      type: int
+      required: true
+      description: EEPROM page size in bytes
+    address-width:
+      type: int
+      required: true
+      description: EEPROM address width in bits
+    timeout:
+      type: int
+      required: true
+      description: EEPROM write cycle timeout in milliseconds
+    wp-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        GPIO to which the write-protect pin of the chip is connected.
+
+        The device will interpret this signal as active-low.
diff --git a/dts/bindings/mtd/atmel,at45.yaml b/dts/bindings/mtd/atmel,at45.yaml
new file mode 100644
index 0000000000..4f8bd45dca
--- /dev/null
+++ b/dts/bindings/mtd/atmel,at45.yaml
@@ -0,0 +1,80 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel AT45 (or compatible) SPI flash
+
+compatible: "atmel,at45"
+
+include: [spi-device.yaml]
+
+properties:
+  jedec-id:
+    type: uint8-array
+    required: true
+    description: JEDEC ID as manufacturer ID (1 byte) and device ID (2 bytes).
+
+  size:
+    type: int
+    required: true
+    description: Flash capacity in bits.
+
+  sector-size:
+    type: int
+    required: true
+    description: Flash sector size in bytes.
+
+  block-size:
+    type: int
+    required: true
+    description: Flash block size in bytes.
+
+  page-size:
+    type: int
+    required: true
+    description: Flash page size in bytes.
+
+  use-udpd:
+    type: boolean
+    required: false
+    description: |
+      When set, the driver will use the Ultra-Deep Power-Down command instead
+      of the default Deep Power-Down one to put the chip into low power mode.
+
+      From the driver perspective, as it does not rely on the contents of the
+      SRAM buffers in the chip, the difference between the Deep and Ultra-Deep
+      Power-Down modes is that the chip consumes far less power in the latter
+      but needs some more time to enter this mode and to exit from it.
+
+  enter-dpd-delay:
+    type: int
+    required: false
+    default: 0
+    description: |
+      Time, in nanoseconds, needed by the chip to enter the Deep Power-Down
+      mode (or Ultra-Deep Power-Down mode when the "use-udpd" property is set)
+      after the corresponding command is issued.
+
+  exit-dpd-delay:
+    type: int
+    required: false
+    default: 0
+    description: |
+      Time, in nanoseconds, needed by the chip to exit from the Deep Power-Down
+      mode (or Ultra-Deep Power-Down mode when the "use-udpd" property is set)
+      after the corresponding command is issued.
+
+  reset-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      The RESET pin of AT45 is active low.
+      If connected directly the MCU pin should be configured
+      as active low.
+
+  wp-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      The WP pin of AT45 is active low.
+      If connected directly the MCU pin should be configured
+      as active low.
diff --git a/dts/bindings/mtd/eeprom-base.yaml b/dts/bindings/mtd/eeprom-base.yaml
new file mode 100644
index 0000000000..d984970137
--- /dev/null
+++ b/dts/bindings/mtd/eeprom-base.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for EEPROM devices
+
+include: base.yaml
+
+properties:
+    size:
+      type: int
+      required: false
+      description: Total EEPROM size in bytes
+    read-only:
+      type: boolean
+      required: false
+      description: Disable writes to the EEPROM
+    label:
+      required: true
diff --git a/dts/bindings/mtd/fixed-partitions.yaml b/dts/bindings/mtd/fixed-partitions.yaml
new file mode 100644
index 0000000000..8c086a0304
--- /dev/null
+++ b/dts/bindings/mtd/fixed-partitions.yaml
@@ -0,0 +1,39 @@
+description: Flash partitions parent node
+
+compatible: "fixed-partitions"
+
+properties:
+    "#address-cells":
+        type: int
+        required: false
+        description: number of address cells in reg property
+
+    "#size-cells":
+        type: int
+        required: false
+        description: number of size cells in reg property
+
+child-binding:
+    description: Flash partition child node
+    properties:
+       label:
+          type: string
+          required: false
+          description: Human readable string describing the device (used as device_get_binding() argument)
+       read-only:
+          type: boolean
+          required: false
+          description: if the partition is read-only or not
+       reg:
+          type: array
+          description: register space
+          required: true
+       zephyr,memory-region:
+          type: string
+          required: false
+          description: |
+            Signify that this node should result in a dedicated linker script
+            memory region in the final executable. The region address and size
+            is taken from the <reg> property, while the name is the value of
+            this property. This must only be added to memory-mapped partitions,
+            not partitions on external flash.
diff --git a/dts/bindings/mtd/jedec,jesd216.yaml b/dts/bindings/mtd/jedec,jesd216.yaml
new file mode 100644
index 0000000000..5346ab433b
--- /dev/null
+++ b/dts/bindings/mtd/jedec,jesd216.yaml
@@ -0,0 +1,75 @@
+# Copyright (c) 2018 Peter Bigot Consulting, LLC
+# Copyright (c) 2019-2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties used by nodes describing serial flash devices that
+# are compatible with the JESD216 Serial Flash Discoverable Parameters
+# specification.
+#
+# This allows encoding the entire BFP block in devicetree to avoid
+# reading at runtime, while still allowing the driver to pull out extra
+# data of interest, such as erase sizes.
+#
+# Alternatively the BFP block can be absent, but critical fields like
+# size can be provided directly along with the JEDEC ID of the expected
+# device to verify its presence at runtime.
+#
+# Only properties supported by parameter tables documented in the
+# JESD216 standards should be listed in this binding include file.
+
+properties:
+  jedec-id:
+    type: uint8-array
+    required: false
+    description: JEDEC ID as manufacturer ID, memory type, memory density
+
+  size:
+    type: int
+    required: false
+    description: flash capacity in bits
+
+  sfdp-bfp:
+    type: uint8-array
+    required: false
+    description: |
+      Contains the 32-bit words in little-endian byte order from the
+      JESD216 Serial Flash Discoverable Parameters Basic Flash
+      Parameters table.  This provides flash-specific configuration
+      information in cases were runtime retrieval of SFDP data
+      is not desired.
+
+  quad-enable-requirements:
+    type: string
+    enum:
+      - "NONE"
+      - "S2B1v1"
+      - "S1B6"
+      - "S2B7"
+      - "S2B1v4"
+      - "S2B1v5"
+      - "S2B1v6"
+    required: false
+    description: |
+      Quad Enable Requirements value from JESD216 BFP DW15.
+
+      Use NONE if the device detects 1-1-4 and 1-4-4 modes by the
+      instruction.  Use S1B6 if QE is bit 6 of the first status register
+      byte, and can be configured by reading then writing one byte with
+      RDSR and WRSR.  For other fields see the specification.
+
+  enter-4byte-addr:
+    type: int
+    required: false
+    description: |
+      Enter 4-Byte Addressing value from JESD216 BFP DW16
+
+      This property is ignored if the device is configured to use SFDP data
+      from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read
+      SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).
+
+      For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24
+      of DW16 identifying ways a device can be placed into 4-byte addressing
+      mode.  If provided as a non-zero value the driver assumes that 4-byte
+      addressing is require to access the full address range, and
+      automatically puts the device into 4-byte address mode when the device
+      is initialized.
diff --git a/dts/bindings/mtd/jedec,spi-nor-common.yaml b/dts/bindings/mtd/jedec,spi-nor-common.yaml
new file mode 100644
index 0000000000..0a9d5ef9b2
--- /dev/null
+++ b/dts/bindings/mtd/jedec,spi-nor-common.yaml
@@ -0,0 +1,97 @@
+# Copyright (c) 2018 Peter Bigot Consulting, LLC
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties used by nodes describing M25P80-compatible SPI NOR
+# serial flash devices, regardless of which Zephyr driver is being used.
+#
+# This extends JESD216-defined features with additional functionality
+# that may be specific to the vendor of a M25P80-compatible device and
+# only supported in certain drivers.  Any information that can be
+# obtained from standardized SFDP parameter blocks should be in
+# jedec,jesd216.yaml instead.
+
+include: "jedec,jesd216.yaml"
+
+properties:
+  requires-ulbpr:
+    type: boolean
+    required: false
+    description: |
+      Indicates the device requires the ULBPR (0x98) command.
+
+      Some flash chips such as the Microchip SST26VF series have a block
+      protection register that initializes to write-protected.  Use this
+      property to indicate that the BPR must be unlocked before write
+      operations can proceed.
+
+  has-dpd:
+    type: boolean
+    required: false
+    description: |
+      Indicates the device supports the DPD (0xB9) command.
+
+      Use this property to indicate the flash chip supports the Deep
+      Power-Down mode that is entered by command 0xB9 to reduce power
+      consumption below normal standby levels.  Use of this property
+      implies that the RDPD (0xAB) Release from Deep Power Down command
+      is also supported.  (On some chips this command functions as Read
+      Electronic Signature; see t-enter-dpd).
+
+  dpd-wakeup-sequence:
+    type: array
+    required: false
+    description: |
+      Specifies wakeup durations for devices without RDPD.
+
+      Some devices (Macronix MX25R in particular) wake from deep power
+      down by a timed sequence of CSn toggles rather than the RDPD
+      command.  This property specifies three durations measured in
+      nanoseconds, in this order:
+      (1) tDPDD (Delay Time for Release from Deep Power-Down Mode)
+      (2) tCDRP (CSn Toggling Time before Release from Deep Power-Down Mode)
+      (3) tRDP (Recovery Time for Release from Deep Power-Down Mode)
+
+      Absence of this property indicates that the RDPD command should be
+      used to wake the chip from Deep Power-Down mode.
+
+  t-enter-dpd:
+    type: int
+    required: false
+    description: |
+      Duration required to complete the DPD command.
+
+      This provides the duration, in nanoseconds, that CSn must be
+      remain deasserted after issuing DPD before the chip will enter
+      deep power down.
+
+      If not provided the driver does not enforce a delay.
+
+  t-exit-dpd:
+    type: int
+    required: false
+    description: |
+      Duration required to complete the RDPD command.
+
+      This provides the duration, in nanoseconds, that CSn must be
+      remain deasserted after issuing RDPD before the chip will exit
+      deep power down and be ready to receive additional commands.
+
+      If not provided the driver does not enforce a delay.
+
+  has-lock:
+    type: int
+    required: false
+    description: |
+      Bit mask of bits of the status register that should be cleared on
+      startup.
+
+      Some devices from certain vendors power-up with block protect bits
+      set in the status register, which prevent any erase or program
+      operation from working.  Devices that have this behavior need to
+      clear those bits on startup.  However, other devices have
+      non-volatile bits in the status register that should not be
+      cleared.
+
+      This value, when present, identifies bits in the status register
+      that should be cleared when the device is initialized.
diff --git a/dts/bindings/mtd/jedec,spi-nor.yaml b/dts/bindings/mtd/jedec,spi-nor.yaml
new file mode 100644
index 0000000000..cb7ad618de
--- /dev/null
+++ b/dts/bindings/mtd/jedec,spi-nor.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2018 Peter Bigot Consulting, LLC
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Properties supporting Zephyr spi-nor flash driver (over the Zephyr SPI
+  API) control of serial flash memories using the standard M25P80-based
+  command set.
+
+compatible: "jedec,spi-nor"
+
+include: [spi-device.yaml, "jedec,spi-nor-common.yaml"]
+
+properties:
+  wp-gpios:
+    type: phandle-array
+    required: false
+    description: WPn pin
+  hold-gpios:
+    type: phandle-array
+    required: false
+    description: HOLDn pin
+  reset-gpios:
+    type: phandle-array
+    required: false
+    description: RESETn pin
diff --git a/dts/bindings/mtd/nordic,qspi-nor.yaml b/dts/bindings/mtd/nordic,qspi-nor.yaml
new file mode 100644
index 0000000000..613effb573
--- /dev/null
+++ b/dts/bindings/mtd/nordic,qspi-nor.yaml
@@ -0,0 +1,102 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  QSPI NOR flash supporting the JEDEC CFI interface.
+
+compatible: "nordic,qspi-nor"
+
+include: [base.yaml, "jedec,spi-nor-common.yaml"]
+
+on-bus: qspi
+
+properties:
+  reg:
+    required: true
+
+  label:
+    required: true
+
+  jedec-id:
+    required: true
+
+  size:
+    required: true
+
+  # Match original driver NORDIC_QSPI_NOR_QE_BIT Kconfig default.
+  quad-enable-requirements:
+    default: "S1B6"
+
+  readoc:
+    type: string
+    required: false
+    enum:
+      - "fastread"        # Single data line SPI, FAST_READ (0x0B)
+      - "read2o"          # Dual data line SPI, READ2O (0x3B)
+      - "read2io"         # Dual data line SPI, READ2IO (0xBB)
+      - "read4o"          # Quad data line SPI, READ4O (0x6B)
+      - "read4io"         # Quad data line SPI, READ4IO (0xEB)
+    description: |
+      Specify the number of data lines and opcode used for reading.
+      If not provided fastread will be selected.
+
+  writeoc:
+    type: string
+    required: false
+    enum:
+      - "pp"            # Single data line SPI, PP (0x02)
+      - "pp2o"          # Dual data line SPI, PP2O (0xA2)
+      - "pp4o"          # Quad data line SPI, PP4O (0x32)
+      - "pp4io"         # Quad data line SPI, PP4IO (0x38)
+    description: |
+      Specify the number of data lines and opcode used for writing.
+      If not provided pp will be selected.
+
+  address-size-32:
+    type: boolean
+    required: false
+    description: |
+      Set to indicate that 32-bit addressing is to be used.
+      If not specified 24-bit addressing will be used.
+
+  ppsize-512:
+    type: boolean
+    required: false
+    description: |
+      Set to indicate that the write opcode operates on 512-byte pages.
+      If not specified the write opcode operates on 256-byte pages.
+
+  sck-delay:
+    type: int
+    required: false
+    default: 0
+    description: |
+      Number of clock cycles CSn must be asserted before it can go low
+      again, specified in nanoseconds.
+
+  rx-delay:
+    type: int
+    required: false
+    description: |
+      Number of clock cycles from the rising edge of the SPI clock
+      until the input serial data is sampled.
+
+  cpha:
+    type: boolean
+    required: false
+    description: |
+      Set to indicate phase starts with asserted half-phase (CPHA=1).
+      For this driver using this property requires also using cpol.
+
+  cpol:
+    type: boolean
+    required: false
+    description: |
+      Set to indicate clock leading edge is falling (CPOL=1).
+      For this driver using this property requires also using cpha.
+
+  sck-frequency:
+    type: int
+    required: true
+    description: |
+      Maximum clock speed supported by the device, in Hz.
diff --git a/dts/bindings/mtd/nxp,imx-flexspi-device.yaml b/dts/bindings/mtd/nxp,imx-flexspi-device.yaml
new file mode 100644
index 0000000000..f084e447de
--- /dev/null
+++ b/dts/bindings/mtd/nxp,imx-flexspi-device.yaml
@@ -0,0 +1,101 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI device
+
+compatible: "nxp,imx-flexspi-device"
+
+include: [spi-device.yaml, "jedec,jesd216.yaml"]
+
+properties:
+    cs-interval-unit:
+      type: int
+      required: false
+      default: 1
+      enum:
+        - 1
+        - 256
+      description: |
+        Chip select interval units, in serial clock cycles. See the
+        CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
+        default corresponds to the reset value of the register field.
+
+    cs-interval:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Minimum interval between chip select deassertion and assertion. See the
+        CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
+        default corresponds to the reset value of the register field.
+
+    cs-setup-time:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Chip select setup time, in serial clock cycles. See the TCSS field in
+        registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
+        reset value of the register field.
+
+    cs-hold-time:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Chip select hold time, in serial clock cycles. See the TCSH field in
+        registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
+        reset value of the register field.
+
+    data-valid-time:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Data valid time, in nanoseconds. See the registers DLLACR through
+        DLLBCR.
+
+    column-space:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Column address bit width. Set to zero if the flash does not support
+        column address. See the CAS field in registers FLASHA1CR0 through
+        FLASHB2CR0. The default corresponds to the reset value of the register
+        field.
+
+    word-addressable:
+      type: boolean
+      required: false
+      description: |
+        Don't transmit the least significant address bit when the flash is word
+        addressable. See the WA field in registers FLASHA1CR0 through
+        FLASHB2CR0.
+
+    ahb-write-wait-unit:
+      type: int
+      required: false
+      default: 2
+      enum:
+        - 2
+        - 8
+        - 32
+        - 128
+        - 512
+        - 2048
+        - 8192
+        - 32768
+      description: |
+        AHB write wait interval units, in AHB clock cycles. See the AWRWAITUNIT
+        field in registers FLASHA1CR2 through FLASHB2CR2. The default
+        corresponds to the reset value of the register field.
+
+    ahb-write-wait-interval:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Time to wait between AHB triggered command sequences. See the AWRWAIT
+        field in registers FLASHA1CR2 through FLASHB2CR2. The default
+        corresponds to the reset value of the register field.
diff --git a/dts/bindings/mtd/nxp,imx-flexspi-hyperflash.yaml b/dts/bindings/mtd/nxp,imx-flexspi-hyperflash.yaml
new file mode 100644
index 0000000000..e60450a6e8
--- /dev/null
+++ b/dts/bindings/mtd/nxp,imx-flexspi-hyperflash.yaml
@@ -0,0 +1,8 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI HyperFlash
+
+compatible: "nxp,imx-flexspi-hyperflash"
+
+include: nxp,imx-flexspi-device.yaml
diff --git a/dts/bindings/mtd/nxp,imx-flexspi-hyperram.yaml b/dts/bindings/mtd/nxp,imx-flexspi-hyperram.yaml
new file mode 100644
index 0000000000..12069da611
--- /dev/null
+++ b/dts/bindings/mtd/nxp,imx-flexspi-hyperram.yaml
@@ -0,0 +1,8 @@
+# Copyright 2021 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI HyperRAM
+
+compatible: "nxp,imx-flexspi-hyperram"
+
+include: nxp,imx-flexspi-device.yaml
diff --git a/dts/bindings/mtd/nxp,imx-flexspi-mx25um51345g.yaml b/dts/bindings/mtd/nxp,imx-flexspi-mx25um51345g.yaml
new file mode 100644
index 0000000000..a7cea2d55a
--- /dev/null
+++ b/dts/bindings/mtd/nxp,imx-flexspi-mx25um51345g.yaml
@@ -0,0 +1,8 @@
+# Copyright 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI MX25UM51345G
+
+compatible: "nxp,imx-flexspi-mx25um51345g"
+
+include: ["nxp,imx-flexspi-device.yaml", soc-nv-flash.yaml]
diff --git a/dts/bindings/mtd/nxp,imx-flexspi-nor.yaml b/dts/bindings/mtd/nxp,imx-flexspi-nor.yaml
new file mode 100644
index 0000000000..8bde7df0af
--- /dev/null
+++ b/dts/bindings/mtd/nxp,imx-flexspi-nor.yaml
@@ -0,0 +1,8 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI NOR
+
+compatible: "nxp,imx-flexspi-nor"
+
+include: ["nxp,imx-flexspi-device.yaml", soc-nv-flash.yaml]
diff --git a/dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml b/dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml
new file mode 100644
index 0000000000..ddca97882a
--- /dev/null
+++ b/dts/bindings/mtd/nxp,lpc11u6x-eeprom.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC11U6X on-chip EEPROM node
+
+compatible: "nxp,lpc11u6x-eeprom"
+
+include: eeprom-base.yaml
diff --git a/dts/bindings/mtd/soc-nv-flash.yaml b/dts/bindings/mtd/soc-nv-flash.yaml
new file mode 100644
index 0000000000..1fd67b339f
--- /dev/null
+++ b/dts/bindings/mtd/soc-nv-flash.yaml
@@ -0,0 +1,19 @@
+description: Flash node
+
+compatible: "soc-nv-flash"
+
+include: base.yaml
+
+properties:
+    label:
+      required: false
+
+    erase-block-size:
+     type: int
+     description: address alignment required by flash erase operations
+     required: false
+
+    write-block-size:
+     type: int
+     description: address alignment required by flash write operations
+     required: false
diff --git a/dts/bindings/mtd/st,stm32-eeprom.yaml b/dts/bindings/mtd/st,stm32-eeprom.yaml
new file mode 100644
index 0000000000..6f2c0040a3
--- /dev/null
+++ b/dts/bindings/mtd/st,stm32-eeprom.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Kwon Tae-young <tykwon@m2i.co.kr>
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 on-chip EEPROM
+
+compatible: "st,stm32-eeprom"
+
+include: eeprom-base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/mtd/st,stm32-nv-flash.yaml b/dts/bindings/mtd/st,stm32-nv-flash.yaml
new file mode 100644
index 0000000000..08e89ef724
--- /dev/null
+++ b/dts/bindings/mtd/st,stm32-nv-flash.yaml
@@ -0,0 +1,14 @@
+description: |
+  STM32 flash memory. This binding is for the flash memory itself, not
+  the flash controller peripheral. For that, see the
+  "st,stm32-flash-controller" binding.
+
+include: soc-nv-flash.yaml
+
+compatible: st,stm32-nv-flash
+
+properties:
+    max-erase-time:
+     type: int
+     description: max erase time(millisecond) of a flash sector or page or half-page
+     required: true
diff --git a/dts/bindings/mtd/ti,tmp116-eeprom.yaml b/dts/bindings/mtd/ti,tmp116-eeprom.yaml
new file mode 100644
index 0000000000..4c4188b0c7
--- /dev/null
+++ b/dts/bindings/mtd/ti,tmp116-eeprom.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 Innoseis B.V
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI TMP116 EEPROM controller binding
+
+compatible: "ti,tmp116-eeprom"
+
+include: eeprom-base.yaml
+
+on-bus: tmp116
diff --git a/dts/bindings/mtd/zephyr,emu-eeprom.yaml b/dts/bindings/mtd/zephyr,emu-eeprom.yaml
new file mode 100644
index 0000000000..c64bf363b7
--- /dev/null
+++ b/dts/bindings/mtd/zephyr,emu-eeprom.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2019 Laczen
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr Emulated EEPROM device
+
+compatible: "zephyr,emu-eeprom"
+
+include: eeprom-base.yaml
+
+properties:
+    size:
+      required: true
+    pagesize:
+      type: int
+      required: true
+      description: Size of a page used to emulate EEPROM in flash
+    partition:
+      type: phandle
+      required: true
+      description: Flash partition used to store the emulated EEPROM data
+    rambuf:
+      type: boolean
+      required: false
+      description: Enable a ram buffer of EEPROM size for improved read speed
+    partition-erase:
+      type: boolean
+      required: false
+      description: |
+        Delay erase until complete partition is used. This enables a
+        ram buffer to allow data to be copied during the partition erase. If
+        power is lost during the partition erase the data will be lost.
diff --git a/dts/bindings/mtd/zephyr,sim-eeprom.yaml b/dts/bindings/mtd/zephyr,sim-eeprom.yaml
new file mode 100644
index 0000000000..c7c7cb7b4f
--- /dev/null
+++ b/dts/bindings/mtd/zephyr,sim-eeprom.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Laczen
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr Simulated EEPROM device
+
+compatible: "zephyr,sim-eeprom"
+
+include: eeprom-base.yaml
+
+properties:
+    size:
+      required: true
diff --git a/dts/bindings/multi_heap_manager/shared-multi-heap.yaml b/dts/bindings/multi_heap_manager/shared-multi-heap.yaml
new file mode 100644
index 0000000000..fdf735c97e
--- /dev/null
+++ b/dts/bindings/multi_heap_manager/shared-multi-heap.yaml
@@ -0,0 +1,20 @@
+description: Shared multi-heap memory pool manager
+
+compatible: "shared-multi-heap"
+
+include:
+  - name: base.yaml
+    property-allowlist: ['reg', 'label']
+
+properties:
+    # Keep this is sync with shared_multi_heap.h
+    capability:
+      type: string
+      required: false
+      description: memory region capability
+      enum:
+        - "cacheable"
+        - "non-cacheable"
+
+    label:
+      required: true
diff --git a/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml b/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml
new file mode 100644
index 0000000000..0b802e15ae
--- /dev/null
+++ b/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml
@@ -0,0 +1,57 @@
+# Copyright (c) 2020-2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    This is a representation of generic radio Front-End Module (FEM)
+    that has a two-pin control interface (CTX, CRX).
+
+    The CTX control pin is used to enable the Power Amplifier (PA) in
+    the transmit path. This is therefore sometimes referred to as
+    the "PA pin" in other contexts.
+
+    The CRX control pin is used to enable the Low Noise Amplifier
+    (LNA) in the receive path, and is sometimes referred to as
+    the "LNA pin" in other contexts.
+
+    Each of these pins is optional, and may be omitted if not present.
+    (Though if you do specify a pin, you must also specify its
+    corresponding settle-time-us property.)
+
+compatible: "generic-fem-two-ctrl-pins"
+
+include: base.yaml
+
+properties:
+    ctx-gpios:
+        type: phandle-array
+        required: false
+        description: |
+            SoC GPIO connected to the CTX input pin on the FEM device.
+
+    crx-gpios:
+        type: phandle-array
+        required: false
+        description: |
+            SoC GPIO connected to the CRX input pin on the FEM device.
+
+    ctx-settle-time-us:
+        type: int
+        description: |
+            Desired minimum settling time, in microseconds, from
+            assertion of the CTX pin to beginning of transmission.
+
+    crx-settle-time-us:
+        type: int
+        description: |
+            Desired minimum settling time, in microseconds, from
+            assertion of the CRX pin to beginning of reception.
+
+    tx-gain-db:
+        type: int
+        description: |
+            TX gain of the PA of the FEM device, in dB.
+
+    rx-gain-db:
+        type: int
+        description: |
+            RX gain of the LNA of the FEM device, in dB.
diff --git a/dts/bindings/net/wireless/nordic,nrf-radio.yaml b/dts/bindings/net/wireless/nordic,nrf-radio.yaml
new file mode 100644
index 0000000000..a3166bac75
--- /dev/null
+++ b/dts/bindings/net/wireless/nordic,nrf-radio.yaml
@@ -0,0 +1,217 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Nordic nRF family RADIO peripheral.
+
+    This controls the 2.4 GHz radio transceiver on nRF5x
+    SoCs, which is available for use with Bluetooth, 802.15.4,
+    and proprietary wireless protocols (not all of these
+    protocols are available on all SoCs; consult the product
+    specifications for details).
+
+    This binding is not relevant to the nRF91x baseband radio.
+
+    Front-End Module (FEM) support
+    ------------------------------
+
+    External front-end modules are range extenders used for boosting
+    the link robustness and link budget of wireless SoCs. If your
+    system includes an external FEM, set it up in the devicetree using
+    this binding's 'fem' property, like this example:
+
+      &radio {
+              fem = <&nrf_radio_fem>;
+      };
+
+      nrf_radio_fem: my-fem {
+              compatible = "...";
+              ....
+      };
+
+    Currently supported "compatible" properties for the FEM node are:
+
+      - generic-fem-two-ctrl-pins
+      - nordic,nrf21540-fem
+
+    Refer to the bindings for these compatibles for more information
+    about how to configure the FEM.
+
+    Direction Finding Extension
+    ---------------------------
+
+    Some radios support the Bluetooth Direction Finding Extension (DFE).
+    The 'dfe-supported' property will be set when it is available.
+    In this case, the 'dfegpio[n]-gpios' properties configure GPIO pins
+    to use to drive antenna switching.
+
+    Each dfegpio[n]-gpios property which is set is used to initialize the
+    corresponding PSEL.DFEGPIO[n] register.
+
+    None of the dfegpio[n]-gpios properties are marked 'required',
+    since which PSEL.DFEGPIO[n] registers will be used to drive
+    antenna switches depends on the use case. Nevertheless, at least two
+    antennas must be available to use DFE.
+
+    That in turn means that at least one dfegpio[n]-gpios
+    property must be provided if DFE is used, to give the radio the
+    possibility to switch between two antennas. To use 12 antennas,
+    4 GPIOs must be provided (since 4 GPIO pins support switching up to
+    16 antennas).
+
+    GPIOs are used in order, following the indices of the dfegpio[n]-gpios
+    properties. The order is important because it affects the mapping of
+    antenna switch patterns to GPIOs.
+
+    Antenna switching patterns
+    --------------------------
+
+    An antenna switching pattern is a binary number where each bit is
+    applied to a particular antenna GPIO pin. For example, the pattern
+    0x3 means that antenna GPIOs at indexes 0 and 1 will be set, while
+    the following are left unset.
+
+    The number of GPIOs specified with dfegpio[n]-gpios properties
+    affects the allowed pattern values. For example, when using four
+    GPIOs, the pattern count cannot be greater than 16, and the
+    maximum allowed value is 15.
+
+    Antenna switch patterns are stored in DFE internal memory by
+    writes to the SWITCHPATTERN register. DFE handling code applies
+    antenna switch patterns during Constant Tone Extension (CTE)
+    receive (Angle of Arrival mode) or transmission (Angle of
+    Departure mode) procedure.
+
+    DFE States
+    ----------
+
+    There are four states of DFE operation:
+
+    * Idle: in this state, PDU transmission happens.
+      DFE uses SWITCHPATTERN[0] to select the antenna in this state.
+      (The 'dfe-pdu-antenna' property value described below is stored
+      in SWITCHPATTERN[0] by the radio controller code.)
+
+    * Guard: in this state, DFE prepares for reception or transmission
+      of CTE. For this state, DFE selects the antenna by applying
+      SWITCHPATTERN[1].
+
+    * Reference: in this state, DFE starts to receive or transmit CTE.
+      In AoA mode, DFE collects reference IQ samples. The selected
+      antenna is the same as in the guard state.
+
+    * Switch-sample: in this state, actual antenna switching happens.
+      DFE selects antennas by applying SWITCHPATTERN[2..N]. If the
+      number of switch-sample periods is greater than the number of
+      stored switching patterns, DFE loops back to SWITCHPATTERN[2].
+
+
+compatible: "nordic,nrf-radio"
+
+include: [base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    fem:
+      type: phandle
+      description: |
+        Phandle linking the RADIO node to its external front-end module.
+
+    coex:
+      type: phandle
+      description: |
+        Phandle linking the RADIO node to the external radio coexistence arbitrator.
+
+    dfe-supported:
+      type: boolean
+      description: |
+        If set, the radio hardware supports the Direction Finding Extension.
+        This property should be treated as read-only and should not be overridden;
+        the correct value is provided for your target's SoC already.
+
+    dfe-antenna-num:
+      type: int
+      required: false
+      description: |
+        Number of available antennas for the Direction Finding Extension.
+
+        This should only be set if dfe-supported is true. If you set this
+        property, the value must be at least two.
+
+    dfe-pdu-antenna:
+      type: int
+      required: false
+      description: |
+        Antenna switch pattern to be used for transmission of PDU before start
+        of transmission of Constant Tone Extension.
+
+        This should only be set if dfe-supported is true.
+
+        This pattern is stored in SWITCHPATTERN[0] before actual antenna
+        switching patterns. This pattern will also be used to drive GPIOs
+        when the radio releases control of GPIOs used to switch antennas.
+
+    dfegpio0-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Pin select for DFE pin 0. This should only be set if dfe-supported
+        is true.
+
+        For example, to use P0.2 on an nRF5x SoC:
+
+          dfegpio1-gpios = <&gpio0 2 0>;
+
+        To use P1.4:
+
+          dfegpio1-gpios = <&gpio1 4 0>;
+
+        Note the last 'flags' cell in the property is not used,
+        and should be set to 0 as shown.
+
+    dfegpio1-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Pin select for DFE pin 1. See description for dfegpio0-gpios.
+
+    dfegpio2-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Pin select for DFE pin 2. See description for dfegpio0-gpios.
+
+    dfegpio3-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Pin select for DFE pin 3. See description for dfegpio0-gpios.
+
+    dfegpio4-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Pin select for DFE pin 4. See description for dfegpio0-gpios.
+
+    dfegpio5-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Pin select for DFE pin 5. See description for dfegpio0-gpios.
+
+    dfegpio6-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Pin select for DFE pin 6. See description for dfegpio0-gpios.
+
+    dfegpio7-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Pin select for DFE pin 7. See description for dfegpio0-gpios.
diff --git a/dts/bindings/net/wireless/nordic,nrf21540-fem-spi.yaml b/dts/bindings/net/wireless/nordic,nrf21540-fem-spi.yaml
new file mode 100644
index 0000000000..e745c76546
--- /dev/null
+++ b/dts/bindings/net/wireless/nordic,nrf21540-fem-spi.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+
+description: |
+    This is a SPI device interface to the nRF21540 Radio Front-End module
+
+compatible: "nordic,nrf21540-fem-spi"
+
+include: spi-device.yaml
diff --git a/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml b/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml
new file mode 100644
index 0000000000..1babc0d060
--- /dev/null
+++ b/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml
@@ -0,0 +1,137 @@
+# Copyright (c) 2020, 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+
+description: |
+    This is a representation of the nRF21540 Radio Front-End module.
+
+    See the "nordic,nrf21540-fem-spi" binding to configure the SPI
+    interface. The SPI interface should be configured as a child node
+    of the SPI bus you have connected to the FEM. Then you "connect"
+    the FEM and SPI configurations using the spi-if property.
+
+    Here is an example nRF21540 configuration with a SPI interface
+    selected, using the SPIM0 peripheral found on several nRF5 SoCs:
+
+      &spi0 {
+              compatible = "nordic,nrf-spim";
+              status = "okay";
+              cs-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+              /* ... MISO/MOSI/SCK pin configuration goes here ... */
+
+              my_spi_if: nrf21540-spi@0 {
+                      compatible = "nordic,nrf21540-fem-spi";
+                      reg = <0>;
+                      spi-max-frequency = <8000000>;
+              };
+      };
+
+      nrf_radio_fem: nrf21540 {
+              compatible = "nordic,nrf21540-fem";
+              tx-en-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+              rx-en-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+              spi-if = <&my_spi_if>;
+              pdn-gpios = <...>;
+              ant-sel-gpios = <...>;
+              mode-gpios = <...>;
+              /* ... other nRF21540 properties go here ... */
+      };
+
+      &radio {
+              fem = <&nrf_radio_fem>;
+      };
+
+    In the above example, the nRF21540 is configured for use with:
+
+      - TX_EN on P0.2 (from 'tx-en-gpios')
+      - RX_EN on P0.5 (from 'rx-en-gpios')
+      - SPI communication via SPIM0 (the bus, or parent node, of
+        the 'my_spi_if' node
+      - CSN on P1.3 (from index 0 in the bus node's 'cs-gpios' property)
+
+    You must perform any additional required SPI pin configuration
+    (nRF21540 MISO, MOSI, and SCK pins) within the SPI bus node
+    ('spi0' in the above example). See your SPI node's binding for
+    details on these pin mux properties. You can use any SPI node
+    available in your SoC's devicetree.
+
+    Configure any other nRF21540 pins as needed using 'pdn-gpios',
+    'ant-sel-gpios', and 'mode-gpios' properties. If unsure about the
+    format, use 'tx-en-gpios' as an example.
+
+    Finally, the nRF5 SoC's radio peripheral is set up for use with
+    the nRF21540 via the 'fem' property in the 'radio' node.
+
+compatible: "nordic,nrf21540-fem"
+
+include: base.yaml
+
+properties:
+    tx-en-gpios:
+        type: phandle-array
+        required: false
+        description: |
+            GPIO of the SOC controlling TX_EN pin of the nRF21540
+    rx-en-gpios:
+        type: phandle-array
+        required: false
+        description: |
+            GPIO of the SOC controlling RX_EN pin of the nRF21540
+    pdn-gpios:
+        type: phandle-array
+        required: false
+        description: |
+            GPIO of the SOC controlling PDN pin of the nRF21540
+    ant-sel-gpios:
+        type: phandle-array
+        required: false
+        description: |
+            GPIO of the SOC controlling ANT-SEL pin of the nRF21540
+    mode-gpios:
+        type: phandle-array
+        required: false
+        description: |
+            GPIO of the SOC controlling MODE pin of the nRF21540
+    spi-if:
+        type: phandle
+        required: false
+        description: |
+            Reference to the nordic,nrf21540-fem-spi SPI bus interface.
+
+            This must be present to support SPI control of the FEM.
+    tx-en-settle-time-us:
+        type: int
+        default: 11
+        description: |
+            Settling time in microseconds from state PG to TX.
+
+            Default value is based on Table 6 of the nRF21540 Product
+            Specification (v1.0), and can be overridden for tuned
+            configurations.
+    rx-en-settle-time-us:
+        type: int
+        default: 11
+        description: |
+            Settling time in microseconds from state PG to RX.
+
+            Default value is based on Table 6 of the nRF21540 Product
+            Specification (v1.0), and can be overridden for tuned
+            configurations.
+    pdn-settle-time-us:
+        type: int
+        default: 18
+        description: |
+            Settling time in microseconds from state PD to PG.
+
+            Default value is based on Table 6 of the nRF21540 Product
+            Specification (v1.0), and can be overridden for tuned
+            configurations.
+    trx-hold-time-us:
+        type: int
+        default: 3
+        description: |
+            Power-off time in microseconds when changing from RX or TX to PG.
+
+            Default value is based on Table 6 of the nRF21540 Product
+            Specification (v1.0), and can be overridden for tuned
+            configurations.
diff --git a/dts/bindings/neural_net/intel,gna.yaml b/dts/bindings/neural_net/intel,gna.yaml
new file mode 100644
index 0000000000..f62f6f9a9a
--- /dev/null
+++ b/dts/bindings/neural_net/intel,gna.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Gaussian Mixture Model and Neural Network Accelerator (GNA)
+
+compatible: "intel,gna"
+
+include: [base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    interrupt-parent:
+      required: true
diff --git a/dts/bindings/pcie/endpoint/brcm,iproc-pcie-ep.yaml b/dts/bindings/pcie/endpoint/brcm,iproc-pcie-ep.yaml
new file mode 100644
index 0000000000..2568bfdcb3
--- /dev/null
+++ b/dts/bindings/pcie/endpoint/brcm,iproc-pcie-ep.yaml
@@ -0,0 +1,19 @@
+# Copyright 2020 Broadcom.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Broadcom iProc PCIe EP node
+
+compatible: "brcm,iproc-pcie-ep"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+      description: |
+        Register space for the memory mapped PAX(PCIe to AXI bridge) registers,
+        It includes registers to access EP configuration space
+        and to map Host PCIe address to PCIe Outbound memory.
+
+    label:
+      required: true
diff --git a/dts/bindings/pcie/host/intel,pcie.yaml b/dts/bindings/pcie/host/intel,pcie.yaml
new file mode 100644
index 0000000000..991f44af05
--- /dev/null
+++ b/dts/bindings/pcie/host/intel,pcie.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel PCIe host controller
+
+compatible: "intel,pcie"
+
+include: pcie-controller.yaml
diff --git a/dts/bindings/pcie/host/pci-host-ecam-generic.yaml b/dts/bindings/pcie/host/pci-host-ecam-generic.yaml
new file mode 100644
index 0000000000..111bceef84
--- /dev/null
+++ b/dts/bindings/pcie/host/pci-host-ecam-generic.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2020 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: PCIe Controller in ECAM mode
+
+compatible: "pci-host-ecam-generic"
+
+include: pcie-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    msi-parent:
+      type: phandle
+
+    ranges:
+      type: array
+      required: true
+      description: |
+        As described in IEEE Std 1275-1994, but must provide at least a
+        definition of non-prefetchable memory. One or both of prefetchable Memory
+        and IO Space may also be provided.
diff --git a/dts/bindings/pcie/host/pcie-controller.yaml b/dts/bindings/pcie/host/pcie-controller.yaml
new file mode 100644
index 0000000000..fb8ab644c9
--- /dev/null
+++ b/dts/bindings/pcie/host/pcie-controller.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for PCIe bus controllers
+
+include: base.yaml
+
+bus: pcie
+
+properties:
+    "#address-cells":
+      required: true
+    "#size-cells":
+      required: true
diff --git a/dts/bindings/pcie/host/ptm-root.yaml b/dts/bindings/pcie/host/ptm-root.yaml
new file mode 100644
index 0000000000..5fe5160e00
--- /dev/null
+++ b/dts/bindings/pcie/host/ptm-root.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for PCIe PTM root
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/peci/microchip,xec-peci.yaml b/dts/bindings/peci/microchip,xec-peci.yaml
new file mode 100644
index 0000000000..69b95fae52
--- /dev/null
+++ b/dts/bindings/peci/microchip,xec-peci.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC PECI controller
+
+compatible: "microchip,xec-peci"
+
+include: peci.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/peci/peci.yaml b/dts/bindings/peci/peci.yaml
new file mode 100644
index 0000000000..9808ed6409
--- /dev/null
+++ b/dts/bindings/peci/peci.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties for PS/2 devices
+
+include: base.yaml
+
+bus: peci
+
+properties:
+    "#address-cells":
+      type: int
+      required: true
+      const: 1
+    "#size-cells":
+      type: int
+      required: true
+      const: 0
+    label:
+      required: true
diff --git a/dts/bindings/phy/phy-controller.yaml b/dts/bindings/phy/phy-controller.yaml
new file mode 100644
index 0000000000..cd0b830734
--- /dev/null
+++ b/dts/bindings/phy/phy-controller.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018, Yannis Damigos
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for PHY providers
+
+include: base.yaml
+
+properties:
+    "#phy-cells":
+        type: int
+        required: true
+        description: |
+          Number of cells in a PHY provider. The meaning those
+          cells is defined by the binding for the phy node.
diff --git a/dts/bindings/phy/st,stm32-usbphyc.yaml b/dts/bindings/phy/st,stm32-usbphyc.yaml
new file mode 100644
index 0000000000..019a997e5b
--- /dev/null
+++ b/dts/bindings/phy/st,stm32-usbphyc.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018, Yannis Damigos
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 USB HS PHY controller
+
+compatible: "st,stm32-usbphyc"
+
+include: phy-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    "#phy-cells":
+      const: 0
diff --git a/dts/bindings/phy/usb-nop-xceiv.yaml b/dts/bindings/phy/usb-nop-xceiv.yaml
new file mode 100644
index 0000000000..3e1a631a64
--- /dev/null
+++ b/dts/bindings/phy/usb-nop-xceiv.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2018, Yannis Damigos
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    This binding is to be used by all the usb transceivers which are built-in
+    with USB IP
+
+compatible: "usb-nop-xceiv"
+
+include: phy-controller.yaml
+
+properties:
+    "#phy-cells":
+      const: 0
diff --git a/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml b/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml
new file mode 100644
index 0000000000..73fa06398c
--- /dev/null
+++ b/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2020, Linaro Limited
+# Copyright (c) 2021, Gerson Fernando Budke
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Atmel SAM Pinctrl container node
+
+  The Atmel SAM pins implements following pin configuration option:
+
+    * bias-pull-up
+    * bias-pull-down
+    * drive-open-drain
+
+  These options define devicetree flags that are converted to SoC flags at
+  ATMEL_SAM_PIN_FLAGS().
+
+compatible: "atmel,sam-pinctrl"
+
+include: [base.yaml, pincfg-node.yaml]
+
+properties:
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      required: true
+      const: 1
+
+child-binding:
+    description: Atmel pins
+    properties:
+      "atmel,pins":
+        type: phandle-array
diff --git a/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml b/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml
new file mode 100644
index 0000000000..8a1081feb2
--- /dev/null
+++ b/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml
@@ -0,0 +1,55 @@
+# Copyright (c) 2020, Linaro Limited
+# Copyright (c) 2021, Gerson Fernando Budke
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Atmel SAM0 Pinctrl container node
+
+  The Atmel SAM0 pins implements following pin configuration option:
+
+    * bias-pull-up
+    * bias-pull-down
+    * drive-strength
+    * input-enable
+    * output-enable
+    * pinmux-enable
+
+  These options define devicetree flags that are converted to SoC flags at
+  ATMEL_SAM0_PIN_FLAGS().
+
+compatible: "atmel,sam0-pinctrl"
+
+include:
+    - name: base.yaml
+    - name: pincfg-node.yaml
+      child-binding:
+        property-allowlist:
+          - bias-pull-up
+          - bias-pull-down
+          - drive-strength
+          - input-enable
+          - output-enable
+
+properties:
+    reg:
+      required: true
+
+properties:
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      required: true
+      const: 1
+
+child-binding:
+    description: Atmel pins
+    properties:
+      "atmel,pins":
+        type: phandle-array
+
+      pinmux-enable:
+        required: false
+        type: boolean
+        description: |
+          Assign pin to an embedded device peripheral
diff --git a/dts/bindings/pinctrl/atmel,sam0-pinmux.yaml b/dts/bindings/pinctrl/atmel,sam0-pinmux.yaml
new file mode 100644
index 0000000000..3caf6c2eea
--- /dev/null
+++ b/dts/bindings/pinctrl/atmel,sam0-pinmux.yaml
@@ -0,0 +1,13 @@
+description: Atmel SAM0 PINMUX
+
+compatible: "atmel,sam0-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+pinmux-cells:
+  - pin
+  - function
diff --git a/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml b/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml
new file mode 100644
index 0000000000..0ed794bd74
--- /dev/null
+++ b/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml
@@ -0,0 +1,36 @@
+# Copyright (c) 2020, Linaro Limited
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Cypress PSoC-6 Pinctrl container node
+
+  The Cypress PSoC-6 pins implements following pin configuration option:
+
+    * bias-pull-up
+    * bias-pull-down
+    * drive-open-drain
+    * drive-open-source
+    * drive-push-pull   (strong)
+    * input-enable      (input-buffer)
+
+  These options define devicetree flags that are converted to SoC flags at
+  CY_PSOC6_PIN_FLAGS().
+
+compatible: "cypress,psoc6-pinctrl"
+
+include: [base.yaml, pincfg-node.yaml]
+
+properties:
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      required: true
+      const: 1
+
+child-binding:
+    description: cypress pins
+    properties:
+      "cypress,pins":
+        type: phandle-array
diff --git a/dts/bindings/pinctrl/espressif,esp32-pinmux.yaml b/dts/bindings/pinctrl/espressif,esp32-pinmux.yaml
new file mode 100644
index 0000000000..6938f2d2b0
--- /dev/null
+++ b/dts/bindings/pinctrl/espressif,esp32-pinmux.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Mohamed ElShahawi
+# SPDX-License-Identifier: Apache-2.0
+
+description: ESP32 PINMUX
+
+compatible: "espressif,esp32-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/pinctrl/gd,gd32-afio.yaml b/dts/bindings/pinctrl/gd,gd32-afio.yaml
new file mode 100644
index 0000000000..f47b541c89
--- /dev/null
+++ b/dts/bindings/pinctrl/gd,gd32-afio.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2021 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  The AFIO peripheral is used to configure pin remapping, EXTI sources and,
+  when available, enable the I/O compensation cell.
+
+compatible: "gd,gd32-afio"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  label:
+    required: true
+
+  rcu-periph-clock:
+    type: int
+    description: Reset Control Unit Peripheral Clock ID
+    required: true
+
+  enable-cps:
+    required: false
+    type: boolean
+    description: |
+      Enable the I/O compensation cell. This option should be enabled when the
+      output speed is greater than 50MHz to reduce the I/O noise effects on
+      the power supply. This option is only available on certain GD32 series.
diff --git a/dts/bindings/pinctrl/gd,gd32-pinctrl-af.yaml b/dts/bindings/pinctrl/gd,gd32-pinctrl-af.yaml
new file mode 100644
index 0000000000..2089e72b26
--- /dev/null
+++ b/dts/bindings/pinctrl/gd,gd32-pinctrl-af.yaml
@@ -0,0 +1,111 @@
+# Copyright (c) 2021 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The GD32 pin controller (AF model) is a singleton node responsible for
+    controlling pin function selection and pin properties. For example, you can
+    use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
+    on the pin.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      /* You can put this in places like a board-pinctrl.dtsi file in
+       * your board directory, or a devicetree overlay in your application.
+       */
+
+      /* include pre-defined combinations for the SoC variant used by the board */
+      #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
+
+      &pinctrl {
+        /* configuration for the usart0 "default" state */
+        usart0_default: usart0_default {
+          /* group 1 */
+          group1 {
+            /* configure PA9 as USART0 TX and PA11 as USART0 CTS */
+            pinmux = <USART0_TX_PA9>, <USART0_CTS_PA11>;
+          };
+          /* group 2 */
+          group2 {
+            /* configure PA10 as USART0 RX and PA12 as USART0 RTS */
+            pinmux = <USART0_RX_PA10>, <USART0_RTS_PA12>;
+            /* both PA10 and PA12 have pull-up enabled */
+            bias-pull-up;
+          };
+
+        /* configuration for the usart0 "sleep" state */
+        usart0_sleep: usart0_sleep {
+          /* group 1 */
+          group1 {
+            /* configure PA9, PA10, PA11 and PA12 in analog mode */
+            pinmux = <ANALOG_PA9>, <ANALOG_PA10>, <ANALOG_PA12>, <ANALOG_PA11>;
+          };
+        };
+
+    The 'usart0_default' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state. Similarly, 'usart0_sleep' child node encodes the pin configurations
+    for the sleep state (used in device low power mode). Note that analog mode
+    is used for low power states because it disconnects the pin pull-up/down
+    resistor, schmitt trigger, and output buffer.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'pinmux'
+    property.
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'bias-pull-up' property in group 2. Here is a list of
+    supported standard pin properties:
+
+    - drive-push-pull: Push-pull drive mode (default, not required).
+    - drive-open-drain: Open-drain drive mode.
+    - bias-disable: Disable pull-up/down (default, not required).
+    - bias-pull-up: Enable pull-up resistor.
+    - bias-pull-down: Enable pull-down resistor.
+    - slew-rate: Set the maximum speed (and so the slew-rate) of the output
+      signal (default: 2MHz).
+
+    Note that drive and bias options are mutually exclusive.
+
+    To link pin configurations with a device, use a pinctrl-N property for some
+    number N, like this example you could place in your board's DTS file:
+
+       #include "board-pinctrl.dtsi"
+
+       &usart0 {
+             pinctrl-0 = <&usart0_default>;
+             pinctrl-1 = <&usart0_sleep>;
+             pinctrl-names = "default", "sleep";
+       };
+
+compatible: "gd,gd32-pinctrl-af"
+
+include: gd,gd32-pinctrl-common.yaml
+
+child-binding:
+  description: |
+    Each child node defines the configuration for a particular state.
+  child-binding:
+    description: |
+      The grandchild nodes group pins that share the same pin configuration.
+    properties:
+      slew-rate:
+        required: false
+        type: string
+        default: "max-speed-2mhz"
+        enum:
+          - "max-speed-2mhz"
+          - "max-speed-25mhz"
+          - "max-speed-50mhz"
+          - "max-speed-200mhz"
+        description: |
+          Set the maximum speed of a pin. This setting effectively limits the
+          slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC
+          default.
diff --git a/dts/bindings/pinctrl/gd,gd32-pinctrl-afio.yaml b/dts/bindings/pinctrl/gd,gd32-pinctrl-afio.yaml
new file mode 100644
index 0000000000..265db61127
--- /dev/null
+++ b/dts/bindings/pinctrl/gd,gd32-pinctrl-afio.yaml
@@ -0,0 +1,137 @@
+# Copyright (c) 2021 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The GD32 pin controller (AFIO model) is a singleton node responsible for
+    controlling pin function selection and pin properties. For example, you can
+    use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
+    on the pin. Remapping is also supported.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      /* You can put this in places like a board-pinctrl.dtsi file in
+       * your board directory, or a devicetree overlay in your application.
+       */
+
+      /* include pre-defined combinations for the SoC variant used by the board */
+      #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
+
+      &pinctrl {
+        /* configuration for the usart0 "default" state */
+        usart0_default: usart0_default {
+          /* group 1 */
+          group1 {
+            /* configure PA9 as USART0 TX and PA11 as USART0 CTS (no remap) */
+            pinmux = <USART0_TX_PA9_NORMP>, <USART0_CTS_PA11_NORMP>;
+          };
+          /* group 2 */
+          group2 {
+            /* configure PA10 as USART0 RX and PA12 as USART0 RTS (no remap) */
+            pinmux = <USART0_RX_PA10_NORMP>, <USART0_RTS_PA12_NORMP>;
+            /* both PA10 and PA12 have pull-up enabled */
+            bias-pull-up;
+          };
+
+        /* configuration for the usart0 "sleep" state */
+        usart0_sleep: usart0_sleep {
+          /* group 1 */
+          group1 {
+            /* configure PA9, PA10, PA11 and PA12 in analog mode */
+            pinmux = <ANALOG_PA9>, <ANALOG_PA10>, <ANALOG_PA12>, <ANALOG_PA11>;
+          };
+        };
+
+    The 'usart0_default' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state. Similarly, 'usart0_sleep' child node encodes the pin configurations
+    for the sleep state (used in device low power mode). Note that analog mode
+    is used for low power states because it disconnects the pin pull-up/down
+    resistor, schmitt trigger, and output buffer.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'pinmux'
+    property.
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'bias-pull-up' property in group 2. Here is a list of
+    supported standard pin properties:
+
+    - drive-push-pull: Push-pull drive mode (default, not required). Only
+      applies for GPIO_IN mode.
+    - drive-open-drain: Open-drain drive mode. Only applies for GPIO_IN mode.
+    - bias-disable: Disable pull-up/down (default, not required). Only applies
+      for GPIO_IN mode.
+    - bias-pull-up: Enable pull-up resistor. Only applies for GPIO_IN mode.
+    - bias-pull-down: Enable pull-down resistor. Only applies for GPIO_IN mode.
+    - slew-rate: Set the maximum speed (and so the slew-rate) of the output
+      signal (default: 2MHz). Only applies for ALTERNATE mode.
+
+    Note that drive and bias options are mutually exclusive.
+
+    Peripherals that are remappable will have their pre-defined macros suffixed
+    with the remap option being selected, for example:
+
+      - CAN0_RX_PA11_NORMP: No remap
+      - CAN0_RX_PB8_PRMP: Partial remap
+      - CAN0_RX_PD0_FRMP: Full remap
+
+    It is important that **ALL** pinmux entries share the same remap. For
+    example:
+
+      &pinctrl {
+        can0_default: can0_default {
+          group1 {
+            pinmux = <CAN0_RX_PD0_FRMP>, <CAN0_TX_PD1_FRMP>;
+            /*                    ^^^^                ^^^^           */
+            /* CAN0 pins are remapped choosing the full remap option */
+          };
+        };
+      };
+
+    To link pin configurations with a device, use a pinctrl-N property for some
+    number N, like this example you could place in your board's DTS file:
+
+       #include "board-pinctrl.dtsi"
+
+       &usart0 {
+             pinctrl-0 = <&usart0_default>;
+             pinctrl-1 = <&usart0_sleep>;
+             pinctrl-names = "default", "sleep";
+       };
+
+compatible: "gd,gd32-pinctrl-afio"
+
+include: gd,gd32-pinctrl-common.yaml
+
+child-binding:
+  description: |
+    Each child node defines the configuration for a particular state.
+  child-binding:
+    description: |
+      The grandchild nodes group pins that share the same pin configuration.
+    properties:
+      slew-rate:
+        required: false
+        type: string
+        default: "max-speed-2mhz"
+        enum:
+          - "max-speed-10mhz"
+          - "max-speed-2mhz"
+          - "max-speed-50mhz"
+          - "max-speed-highest"
+        description: |
+          Set the maximum speed of a pin. This setting effectively limits the
+          slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC
+          default. The max-speed-highest option may not be available on all SoC
+          variants. If selected and not available the 50 MHz maximum speed will
+          be used instead. Note that usage of max-speed-highest may require
+          enabling the I/O compensation cell (refer to the gd,gd32-afio binding
+          for more details).
diff --git a/dts/bindings/pinctrl/gd,gd32-pinctrl-common.yaml b/dts/bindings/pinctrl/gd,gd32-pinctrl-common.yaml
new file mode 100644
index 0000000000..c8f1dfbba0
--- /dev/null
+++ b/dts/bindings/pinctrl/gd,gd32-pinctrl-common.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2021 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+include:
+    - name: base.yaml
+    - name: pincfg-node-group.yaml
+      child-binding:
+        child-binding:
+          property-allowlist:
+            - drive-push-pull
+            - drive-open-drain
+            - bias-disable
+            - bias-pull-down
+            - bias-pull-up
+
+child-binding:
+  child-binding:
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins should
+          be defined using pre-defined macros or, alternatively, using the
+          GD32_PINMUX_AF or GD32_PINMUX_AFIO utility macros depending on the
+          pinmux model used by the SoC series.
diff --git a/dts/bindings/pinctrl/intel,s1000-pinmux.yaml b/dts/bindings/pinctrl/intel,s1000-pinmux.yaml
new file mode 100644
index 0000000000..e3fbdd7a45
--- /dev/null
+++ b/dts/bindings/pinctrl/intel,s1000-pinmux.yaml
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+description: Intel S1000 pinmux
+
+compatible: "intel,s1000-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+pinmux-cells:
+  - pin
+  - function
diff --git a/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-conf.yaml b/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-conf.yaml
new file mode 100644
index 0000000000..1d0faac628
--- /dev/null
+++ b/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-conf.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE IT8XXX2 Pin-Mux Configuration
+
+compatible: "ite,it8xxx2-pinctrl-conf"
+child-binding:
+    description: ITE Pinmux configuration child node
+    properties:
+        pinctrls:
+            type: phandle-array
+            required: true
+            description: Pin alternate function selection
diff --git a/dts/bindings/pinctrl/ite,it8xxx2-pinmux.yaml b/dts/bindings/pinctrl/ite,it8xxx2-pinmux.yaml
new file mode 100644
index 0000000000..02956f87e9
--- /dev/null
+++ b/dts/bindings/pinctrl/ite,it8xxx2-pinmux.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE IT8XXX2 pinmux node
+
+compatible: "ite,it8xxx2-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    func3_gcr:
+        type: array
+        required: true
+
+    func3_en_mask:
+        type: array
+        required: true
+
+    func4_gcr:
+        type: array
+        required: true
+
+    func4_en_mask:
+        type: array
+        required: true
+
+pinctrl-cells:
+  - pin
+  - alt_func
diff --git a/dts/bindings/pinctrl/microchip,xec-pinmux.yaml b/dts/bindings/pinctrl/microchip,xec-pinmux.yaml
new file mode 100644
index 0000000000..b1c72e48b7
--- /dev/null
+++ b/dts/bindings/pinctrl/microchip,xec-pinmux.yaml
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC Pinmux node
+
+compatible: "microchip,xec-pinmux"
+
+include: base.yaml
+
+child-binding:
+    description: pinmux child node
+    properties:
+       ph-reg:
+          type: phandle
+          required: true
+
+       port-num:
+         type: int
+         required: true
+         description: |
+           Zero based GPIO port number. Pin group 000 - 036 is port 0,
+           040 - 076 is port 1, etc.
diff --git a/dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml b/dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml
new file mode 100644
index 0000000000..c3daa63cf8
--- /dev/null
+++ b/dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml
@@ -0,0 +1,110 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The nRF pin controller is a singleton node responsible for controlling
+    pin function selection and pin properties. For example, you can use this
+    node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
+    pin.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      /* You can put this in places like a board-pinctrl.dtsi file in
+       * your board directory, or a devicetree overlay in your application.
+       */
+      &pinctrl {
+        /* configuration for uart0 device, default state */
+        uart0_default: uart0_default {
+          /* group 1 ('group1' name is arbitrary) */
+          group1 {
+            /* configure P0.1 as UART_TX and P0.2 as UART_RTS */
+            psels = <NRF_PSEL(UART_TX, 0, 1)>, <NRF_PSEL(UART_RTS, 0, 2)>;
+          };
+          /* group 2 */
+          group2 {
+            /* configure P0.3 as UART_RX and P0.4 as UART_CTS */
+            psels = <NRF_PSEL(UART_RX, 0, 3)>, <NRF_PSEL(UART_CTS, 0, 4)>;
+            /* both P0.3 and P0.4 are configured with pull-up */
+            bias-pull-up;
+          };
+        };
+      };
+
+    The 'uart0_default' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state. You would specify the low-power configuration for the same device
+    in a separate child node.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'psels'
+    property. The NRF_PSEL macro is used to specify a pin function selection.
+    Available pin functions can be found in the
+    include/dt-bindings/pinctrl/nrf-pinctrl.h header file.
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'bias-pull-up' property in group 2. Here is a list of
+    supported standard pin properties:
+
+    - bias-disable: Disable pull-up/down (default behavior, not required).
+    - bias-pull-up: Enable pull-up resistor.
+    - bias-pull-down: Enable pull-down resistor.
+    - low-power-enable: Configure pin as an input with input buffer
+      disconnected.
+
+    Note that bias options are mutually exclusive.
+
+    To link this pin configuration with a device, use a pinctrl-N property
+    for some number N, like this example you could place in your board's DTS
+    file:
+
+       #include "board-pinctrl.dtsi"
+
+       &uart0 {
+             pinctrl-0 = <&uart0_default>;
+             pinctrl-names = "default";
+       };
+
+compatible: "nordic,nrf-pinctrl"
+
+include:
+    - name: base.yaml
+    - name: pincfg-node-group.yaml
+      child-binding:
+        child-binding:
+          property-allowlist:
+            - bias-disable
+            - bias-pull-down
+            - bias-pull-up
+            - low-power-enable
+
+child-binding:
+  description: |
+    nRF pin controller pin configuration state nodes.
+  child-binding:
+    description: |
+      nRF pin controller pin configuration group.
+    properties:
+      psels:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins should
+          be defined using the NRF_PSEL utility macro that encodes the port,
+          pin and function.
+
+      drive-mode:
+        type: int
+        default: 0
+        description: |
+          Pin output drive mode. Available drive modes are pre-defined in
+          nrf-pinctrl.h. Note that extra modes may not be available on certain
+          devices. Defaults to standard mode for 0 and 1 (NRF_DRIVE_S0S1), the
+          SoC default.
diff --git a/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-conf.yaml b/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-conf.yaml
new file mode 100644
index 0000000000..ed1cd709dd
--- /dev/null
+++ b/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-conf.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nuvoton NPCX7 Low-Voltage level detection configuration map
+  between Nuvoton NPCX GPIO and low-voltage controller (LV_GPIO_CTL)
+  driver instances.
+
+compatible: "nuvoton,npcx-lvolctrl-conf"
+
+child-binding:
+    description: Child node to present the mapping between GPIO pad and its low-voltage support
+    properties:
+       lvols:
+          type: phandle-array
+          required: true
+          description: list of configurations map between io and low-voltage controllers
diff --git a/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-def.yaml b/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-def.yaml
new file mode 100644
index 0000000000..14d879004d
--- /dev/null
+++ b/dts/bindings/pinctrl/nuvoton,npcx-lvolctrl-def.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Default Low-Voltage Configurations
+
+compatible: "nuvoton,npcx-lvolctrl-def"
+
+include: [base.yaml]
+
+properties:
+    lvol-io-pads:
+        type: phandles
+        required: false
+        description: list of low-voltage configurations that need to set by default
diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml
new file mode 100644
index 0000000000..ff319f509e
--- /dev/null
+++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-conf.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nuvoton NPCX7 Pin-Mux Configuration
+  Configuration map from Nuvoton NPCX GPIO to pinmux controller
+  (SCFG) driver instances.
+
+compatible: "nuvoton,npcx-pinctrl-conf"
+child-binding:
+    description: NPCX Pinmux configuration child node
+    properties:
+        alts:
+            type: phandle-array
+            required: true
+            description: A SCFG ALT (Alternative controllers) specifier for pinmuxing of npcx ec
diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml
new file mode 100644
index 0000000000..4253352138
--- /dev/null
+++ b/dts/bindings/pinctrl/nuvoton,npcx-pinctrl-def.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Default Pins Configurations
+
+compatible: "nuvoton,npcx-pinctrl-def"
+
+include: [base.yaml]
+
+properties:
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: list of configurations of pinmux controllers need to set
diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pslctrl-conf.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pslctrl-conf.yaml
new file mode 100644
index 0000000000..59690352ae
--- /dev/null
+++ b/dts/bindings/pinctrl/nuvoton,npcx-pslctrl-conf.yaml
@@ -0,0 +1,44 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nuvoton NPCX pads configuration map between Pin Mux controller and
+  Power Switch Logic (PSL) controller driver instances.
+
+compatible: "nuvoton,npcx-pslctrl-conf"
+
+child-binding:
+   description: |
+     Child node to present the mapping between pin-mux controller
+     and its power switch logic (PSL) support
+
+   properties:
+      offset:
+         type: int
+         required: true
+         description: Offset in PSL_CTS for status and detection mode.
+
+      pinctrl-0:
+         type: phandles
+         required: true
+         description: Pinmux controller configuration for PSL io pads.
+
+      polarity-0:
+         type: phandles
+         required: true
+         description: Active polarity configuration for PSL io pads.
+
+      flag:
+         type: int
+         required: false
+         description: |
+            Detection mode and type for wake-up event detection.
+            5 = Configures PSL input in detecting rising edge.
+            6 = Configures PSL input in in detecting level high state.
+            9 = Configures PSL input in detecting falling edge.
+            10 = Configures PSL input in detecting level low state.
+         enum:
+            - 5
+            - 6
+            - 9
+            - 10
diff --git a/dts/bindings/pinctrl/nuvoton,npcx-pslctrl-def.yaml b/dts/bindings/pinctrl/nuvoton,npcx-pslctrl-def.yaml
new file mode 100644
index 0000000000..d6729bf594
--- /dev/null
+++ b/dts/bindings/pinctrl/nuvoton,npcx-pslctrl-def.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Default Power Switch Logic (PSL) input pads configurations
+
+compatible: "nuvoton,npcx-pslctrl-def"
+
+include: [base.yaml]
+
+properties:
+    psl-in-pads:
+        type: phandles
+        required: true
+        description: |
+            list of PSL input pads that are in charge of detecting the wake-up
+            signals and the related circuit will turn on core power supply
+            (VCC1) from standby power state (ultra-low-power mode) later.
diff --git a/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml b/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml
new file mode 100644
index 0000000000..97aa33ca55
--- /dev/null
+++ b/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX System Configuration (Pinmux, 1.8V support and so on) node
+
+compatible: "nuvoton,npcx-scfg"
+
+include: [base.yaml]
+
+properties:
+    reg:
+        required: true
+
+    "#alt-cells":
+        type: int
+        required: true
+        description: Number of items to expect in a SCFG ALT (Alternative controllers) specifier
+
+    "#lvol-cells":
+        type: int
+        required: true
+        description: Number of items to expect in a SCFG LV_GPIO_CTL (Low level IO controllers) specifier
+
+alt-cells:
+    - group
+    - bit
+    - inv
+
+lvol-cells:
+    - io_port
+    - io_bit
+    - ctrl
+    - bit
diff --git a/dts/bindings/pinctrl/nxp,imx-pinmux.yaml b/dts/bindings/pinctrl/nxp,imx-pinmux.yaml
new file mode 100644
index 0000000000..66c1ed3a0d
--- /dev/null
+++ b/dts/bindings/pinctrl/nxp,imx-pinmux.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX IOMUXC node
+
+compatible: "nxp,imx-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+pinmux-cells:
+  - pin
+  - function
diff --git a/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml b/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml
new file mode 100644
index 0000000000..fc236da138
--- /dev/null
+++ b/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml
@@ -0,0 +1,39 @@
+description: Kinetis pinmux node
+
+compatible: "nxp,kinetis-pinmux"
+
+include:
+  - name: base.yaml
+  - name: pincfg-node.yaml
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+child-binding:
+    description: |
+      NXP Kinetis Pin data.  A series of child nodes that describe each pin
+      configuration supported by the SoC.  Each node is expected to named as
+      follows - <periph>_<signal>_pt<port><pin>
+
+      The node will have a matching node label that board dtsi files can
+      utilized to reference in pinctrl-<N> properties.
+
+      The following is an example for UART0 CTS signal on pin 0, with mux
+      value of 2.
+
+      uart0_cts_pta0: uart0_cts_pta0 {
+           nxp,kinetis-port-pins = < 0 2 >;
+      };
+
+    properties:
+      "nxp,kinetis-port-pins":
+        description: |
+          The array is expected to have two elements. The first element is the
+          pin number and the second element is the mux value (i.e. PCR[MUX]).
+
+        type: array
+        required: true
diff --git a/dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml b/dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml
new file mode 100644
index 0000000000..8570415325
--- /dev/null
+++ b/dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC I/O Pin Configuration (IOCON) Port I/O (PIO)
+
+compatible: "nxp,lpc-iocon-pio"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/pinctrl/nxp,lpc-iocon.yaml b/dts/bindings/pinctrl/nxp,lpc-iocon.yaml
new file mode 100644
index 0000000000..62d5a2bd56
--- /dev/null
+++ b/dts/bindings/pinctrl/nxp,lpc-iocon.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC I/O Pin Configuration (IOCON)
+
+compatible: "nxp,lpc-iocon"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml b/dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml
new file mode 100644
index 0000000000..312310b105
--- /dev/null
+++ b/dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC11U6X pinmux (aka IOCON) node
+
+compatible: "nxp,lpc11u6x-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    "#pinmux-cells":
+      type: int
+      required: true
+      const: 2
+      description: number of items in a pinmux specifier
+
+pinmux-cells:
+  - pin
+  - function
diff --git a/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml b/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml
new file mode 100644
index 0000000000..87f49b6d5f
--- /dev/null
+++ b/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml
@@ -0,0 +1,16 @@
+description: RV32M1 pinmux node
+
+compatible: "openisa,rv32m1-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+pinmux-cells:
+  - pin
+  - function
diff --git a/dts/bindings/pinctrl/pincfg-node-group.yaml b/dts/bindings/pinctrl/pincfg-node-group.yaml
new file mode 100644
index 0000000000..09ec77d307
--- /dev/null
+++ b/dts/bindings/pinctrl/pincfg-node-group.yaml
@@ -0,0 +1,165 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Generic pin configuration schema.
+
+  This file is equivalent to pincfg-node.yaml but inserts properties at a
+  grandchildren level, useful for group based representation.
+
+child-binding:
+  child-binding:
+    description: |
+      Many data items that are represented in a pin configuration node are
+      common and generic. Pin control bindings should use the properties
+      defined below where they are applicable; not all of these properties are
+      relevant or useful for all hardware or binding structures. Each
+      individual binding document should state which of these generic
+      properties, if any, are used, and the structure of the DT nodes that
+      contain these properties.
+
+      This is based on Linux, documentation:
+        https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
+
+    properties:
+      bias-disable:
+        required: false
+        type: boolean
+        description: disable any pin bias
+
+      bias-high-impedance:
+        required: false
+        type: boolean
+        description: high impedance mode ("third-state", "floating")
+
+      bias-bus-hold:
+        required: false
+        type: boolean
+        description: latch weakly
+
+      bias-pull-up:
+        required: false
+        type: boolean
+        description: enable pull-up resistor
+
+      bias-pull-down:
+        required: false
+        type: boolean
+        description: enable pull-down resistor
+
+      bias-pull-pin-default:
+        required: false
+        type: boolean
+        description: use pin's default pull state
+
+      drive-push-pull:
+        required: false
+        type: boolean
+        description: drive actively high and low
+
+      drive-open-drain:
+        required: false
+        type: boolean
+        description: drive with open drain (hardware AND)
+
+      drive-open-source:
+        required: false
+        type: boolean
+        description: drive with open source (hardware OR)
+
+      drive-strength:
+        required: false
+        type: int
+        description: maximum sink or source current in mA
+
+      drive-strength-microamp:
+        required: false
+        type: int
+        description: maximum sink or source current in μA
+
+      input-enable:
+        required: false
+        type: boolean
+        description: |
+          enable input on pin (no effect on output, such as enabling an input
+          buffer)
+
+      input-disable:
+        required: false
+        type: boolean
+        description: |
+          disable input on pin (no effect on output, such as disabling an input
+          buffer)
+
+      input-schmitt-enable:
+        required: false
+        type: boolean
+        description: enable schmitt-trigger mode
+
+      input-schmitt-disable:
+        required: false
+        type: boolean
+        description: disable schmitt-trigger mode
+
+      input-debounce:
+        required: false
+        type: int
+        description: |
+          Takes the debounce time in μsec, as argument or 0 to disable debouncing
+
+      power-source:
+        required: false
+        type: int
+        description: select between different power supplies
+
+      low-power-enable:
+        required: false
+        type: boolean
+        description: enable low power mode
+
+      low-power-disable:
+        required: false
+        type: boolean
+        description: disable low power mode
+
+      output-disable:
+        required: false
+        type: boolean
+        description: disable output on a pin (such as disable an output buffer)
+
+      output-enable:
+        required: false
+        type: boolean
+        description: |
+          enable output on a pin without actively driving it (such as enabling
+          an output buffer)
+
+      output-low:
+        required: false
+        type: boolean
+        description: set the pin to output mode with low level
+
+      output-high:
+        required: false
+        type: boolean
+        description: set the pin to output mode with high level
+
+      sleep-hardware-state:
+        required: false
+        type: boolean
+        description: |
+          indicate this is sleep related state which will be programmed into
+          the registers for the sleep state
+
+      slew-rate:
+        required: false
+        type: int
+        description: set the slew rate
+
+      skew-delay:
+        required: false
+        type: int
+        description: |
+          This affects the expected clock skew on input pins and the delay
+          before latching a value to an output pin. Typically indicates how
+          many double-inverters are used to delay the signal.
diff --git a/dts/bindings/pinctrl/pincfg-node.yaml b/dts/bindings/pinctrl/pincfg-node.yaml
new file mode 100644
index 0000000000..449a0e7cfc
--- /dev/null
+++ b/dts/bindings/pinctrl/pincfg-node.yaml
@@ -0,0 +1,160 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic pin configuration schema
+
+child-binding:
+    description: |
+      Many data items that are represented in a pin configuration node are
+      common and generic. Pin control bindings should use the properties
+      defined below where they are applicable; not all of these properties are
+      relevant or useful for all hardware or binding structures. Each
+      individual binding document should state which of these generic
+      properties, if any, are used, and the structure of the DT nodes that
+      contain these properties.
+
+      This is based on Linux, documentation:
+        https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
+
+    properties:
+      bias-disable:
+        required: false
+        type: boolean
+        description: disable any pin bias
+
+      bias-high-impedance:
+        required: false
+        type: boolean
+        description: high impedance mode ("third-state", "floating")
+
+      bias-bus-hold:
+        required: false
+        type: boolean
+        description: latch weakly
+
+      bias-pull-up:
+        required: false
+        type: boolean
+        description: enable pull-up resistor
+
+      bias-pull-down:
+        required: false
+        type: boolean
+        description: enable pull-down resistor
+
+      bias-pull-pin-default:
+        required: false
+        type: boolean
+        description: use pin's default pull state
+
+      drive-push-pull:
+        required: false
+        type: boolean
+        description: drive actively high and low
+
+      drive-open-drain:
+        required: false
+        type: boolean
+        description: drive with open drain (hardware AND)
+
+      drive-open-source:
+        required: false
+        type: boolean
+        description: drive with open source (hardware OR)
+
+      drive-strength:
+        required: false
+        type: int
+        description: maximum sink or source current in mA
+
+      drive-strength-microamp:
+        required: false
+        type: int
+        description: maximum sink or source current in μA
+
+      input-enable:
+        required: false
+        type: boolean
+        description: |
+          enable input on pin (no effect on output, such as enabling an input
+          buffer)
+
+      input-disable:
+        required: false
+        type: boolean
+        description: |
+          disable input on pin (no effect on output, such as disabling an input
+          buffer)
+
+      input-schmitt-enable:
+        required: false
+        type: boolean
+        description: enable schmitt-trigger mode
+
+      input-schmitt-disable:
+        required: false
+        type: boolean
+        description: disable schmitt-trigger mode
+
+      input-debounce:
+        required: false
+        type: int
+        description: |
+          Takes the debounce time in μsec, as argument or 0 to disable debouncing
+
+      power-source:
+        required: false
+        type: int
+        description: select between different power supplies
+
+      low-power-enable:
+        required: false
+        type: boolean
+        description: enable low power mode
+
+      low-power-disable:
+        required: false
+        type: boolean
+        description: disable low power mode
+
+      output-disable:
+        required: false
+        type: boolean
+        description: disable output on a pin (such as disable an output buffer)
+
+      output-enable:
+        required: false
+        type: boolean
+        description: |
+          enable output on a pin without actively driving it (such as enabling
+          an output buffer)
+
+      output-low:
+        required: false
+        type: boolean
+        description: set the pin to output mode with low level
+
+      output-high:
+        required: false
+        type: boolean
+        description: set the pin to output mode with high level
+
+      sleep-hardware-state:
+        required: false
+        type: boolean
+        description: |
+          indicate this is sleep related state which will be programmed into
+          the registers for the sleep state
+
+      slew-rate:
+        required: false
+        type: int
+        description: set the slew rate
+
+      skew-delay:
+        required: false
+        type: int
+        description: |
+          This affects the expected clock skew on input pins and the delay
+          before latching a value to an output pin. Typically indicates how
+          many double-inverters are used to delay the signal.
diff --git a/dts/bindings/pinctrl/pinctrl-device.yaml b/dts/bindings/pinctrl/pinctrl-device.yaml
new file mode 100644
index 0000000000..40679dbac6
--- /dev/null
+++ b/dts/bindings/pinctrl/pinctrl-device.yaml
@@ -0,0 +1,43 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  This file needs to be included by devices that need to specify a set of pin
+  controller states. The maximum number of supported states is 5 (pinctrl-0 ...
+  pinctrl-4) but it can be incremented if required.
+
+  The bindings file for each pin controller driver implementation should provide
+  more information on what is the expected pin configuration format.
+
+properties:
+  pinctrl-0:
+    type: phandles
+    description: |
+      Pin configuration/s for the first state. Content is specific to the
+      selected pin controller driver implementation.
+
+  pinctrl-1:
+    type: phandles
+    description: |
+      Pin configuration/s for the second state. See pinctrl-0.
+
+  pinctrl-2:
+    type: phandles
+    description: |
+      Pin configuration/s for the third state. See pinctrl-0.
+
+  pinctrl-3:
+    type: phandles
+    description: |
+      Pin configuration/s for the fourth state. See pinctrl-0.
+
+  pinctrl-4:
+    type: phandles
+    description: |
+      Pin configuration/s for the fifth state. See pinctrl-0.
+
+  pinctrl-names:
+    type: string-array
+    description: |
+      Names for the provided states. The number of names needs to match the
+      number of states.
diff --git a/dts/bindings/pinctrl/sifive,iof.yaml b/dts/bindings/pinctrl/sifive,iof.yaml
new file mode 100644
index 0000000000..6a6d202f92
--- /dev/null
+++ b/dts/bindings/pinctrl/sifive,iof.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  SiFive FE310 IO Function (iof)
+  Binding covers the IOF_EN/IOF_SEL registers that are a subset of the GPIO
+  controller.
+
+compatible: "sifive,iof"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+pinmux-cells:
+  - pin
+  - function
diff --git a/dts/bindings/pinctrl/snps,creg-gpio-mux-hsdk.yaml b/dts/bindings/pinctrl/snps,creg-gpio-mux-hsdk.yaml
new file mode 100644
index 0000000000..ce428a91db
--- /dev/null
+++ b/dts/bindings/pinctrl/snps,creg-gpio-mux-hsdk.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Synopsys CREG HSDK GPIO pin mux
+
+compatible: "snps,creg-gpio-mux-hsdk"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+pinmux-cells:
+  - pin
+  - function
diff --git a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml
new file mode 100644
index 0000000000..611b502e79
--- /dev/null
+++ b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -0,0 +1,94 @@
+# Copyright (c) 2020 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STM32 Pin controller Node
+    Based on pincfg-node.yaml binding.
+
+    Note: `bias-disable` and `drive-push-pull` are default pin configurations.
+           They will be applied in case no `bias-foo` or `driver-bar` properties
+           are set.
+
+compatible: "st,stm32-pinctrl"
+
+include:
+    - name: base.yaml
+    - name: pincfg-node.yaml
+      child-binding:
+        property-allowlist:
+          - bias-disable
+          - bias-pull-down
+          - bias-pull-up
+          - drive-push-pull
+          - drive-open-drain
+
+properties:
+    reg:
+      required: true
+
+    remap-pa11:
+      type: boolean
+      required: false
+      description: Remaps the PA11 pin to operate as PA9 pin.
+        Use of this property is restricted to STM32G0 SoCs.
+
+    remap-pa12:
+      type: boolean
+      required: false
+      description: Remaps the PA12 pin to operate as PA10 pin.
+        Use of this property is restricted to STM32G0 SoCs.
+
+    remap-pa11-pa12:
+      type: boolean
+      required: false
+      description: Remaps the PA11/PA12 pin to operate as PA9/PA10 pin.
+        Use of this property is restricted to STM32F070x SoCs.
+
+child-binding:
+    description: |
+        This binding gives a base representation of the STM32 pins configration
+
+    properties:
+        pinmux:
+          required: true
+          type: int
+          description: |
+            Reused from https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+            Integer array, represents gpio pin number and mux setting.
+            These defines are calculated as: ((port * 16 + line) << 8) | function
+            With:
+            - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
+            - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
+            - function: The function number, can be:
+            * 0 : Alternate Function 0
+            * 1 : Alternate Function 1
+            * 2 : Alternate Function 2
+            * ...
+            * 15 : Alternate Function 15
+            * 16 : Analog
+            To simplify the usage, macro is available to generate "pinmux" field.
+            This macro is available here:
+              -include/dt-bindings/pinctrl/stm32-pinctrl-common.h
+            Some examples of macro usage:
+               GPIO A9 set as alernate function 2
+            ... {
+                     pinmux = <STM32_PINMUX('A', 9, AF2)>;
+            };
+               GPIO A9 set as analog
+            ... {
+                     pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+            };
+
+        slew-rate:
+          required: false
+          type: string
+          default: "low-speed"
+          enum:
+          - "low-speed"           # Default value.
+          - "medium-speed"
+          - "high-speed"
+          - "very-high-speed"
+          description: |
+            Pin speed. Default to low-speed. For few pins (PA11 and
+            PB3 depending on SoCs)hardware reset value could differ
+            (very-high-speed). Carefully check reference manual for these pins.
diff --git a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml
new file mode 100644
index 0000000000..b36dce16aa
--- /dev/null
+++ b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml
@@ -0,0 +1,105 @@
+# Copyright (c) 2020 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 Pin controller Node
+
+compatible: "st,stm32f1-pinctrl"
+
+include: [base.yaml]
+
+properties:
+    reg:
+      required: true
+
+child-binding:
+    description: |
+        This binding gives a base representation of the STM32F1 pins
+        configration
+
+    properties:
+        pinmux:
+          required: true
+          type: int
+          description: |
+            Adapted from https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+            Integer array, represents gpio pin number and mux setting.
+            These defines are calculated as: ((port * 16 + line) << 8) | (function << 6) | remap)
+            With:
+            - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
+            - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
+            - function: The configuration mode, can be:
+            * 0 : Alternate function output
+            * 1 : Input
+            * 2 : Analog
+            - remap: The pin remapping configuration. It allows to assign the pin
+            function to a different peripheral. Remain configuration can be:
+            * 0 : No remap
+            * 1 : Partial remap 1
+            * 2 : Partial remap 2
+            * 3 : Partial remap 3
+            * 4 : Full remap
+            To simplify the usage, macro is available to generate "pinmux" field.
+            This macro is available here:
+              -include/dt-bindings/pinctrl/stm32f1-pinctrl.h
+            Some examples of macro usage:
+               GPIO A9 set as alernate with no remap
+            ... {
+                     pinmux = <STM32F1_PINMUX('A', 9, ALTERNATE, REMAP_NO)>;
+            };
+               GPIO A9 set as alernate with full remap
+            ... {
+                     pinmux = <STM32F1_PINMUX('A', 9, ALTERNATE, REMAP_FULL)>;
+            };
+               GPIO A9 set as input
+            ... {
+                     pinmux = <STM32F1_PINMUX('A', 9, GPIO_IN, REMAP_NO)>;
+            };
+
+        bias-disable:
+          required: false
+          type: boolean
+          description: |
+            Pin bias (push-pull) disabled. This is the default pin
+            configuration and will be applied if no bias- property is
+            specified. Only available in input mode ("floating" configuration).
+
+        bias-pull-down:
+          required: false
+          type: boolean
+          description: |
+            Weak pull down resistor enabled. Not compatible with
+            output configuration modes (atlernate or general purpose output).
+
+        bias-pull-up:
+          required: false
+          type: boolean
+          description: |
+            Weak pull up resistor enabled. Not compatible with
+            output configuration modes (atlernate or general purpose output).
+
+        drive-push-pull:
+          required: false
+          type: boolean
+          description: |
+            Pin driven actively high and low. This is the default pin
+            configueration and will be applied if no drive- property is
+            specified. Only valid for output configuration modes.
+
+        drive-open-drain:
+          required: false
+          type: boolean
+          description: |
+            Pin driven in open drain. Only valid for output
+            configuration modes.
+
+        slew-rate:
+          required: false
+          type: string
+          default: "max-speed-10mhz"
+          enum:
+          - "max-speed-10mhz"       # Default
+          - "max-speed-2mhz"
+          - "max-speed-50mhz"
+          description: |
+            Pin output mode, maximum achievable speed. Only applies to
+            output mode (alternate).
diff --git a/dts/bindings/pinctrl/telink,b91-pinmux.yaml b/dts/bindings/pinctrl/telink,b91-pinmux.yaml
new file mode 100644
index 0000000000..68419f09f3
--- /dev/null
+++ b/dts/bindings/pinctrl/telink,b91-pinmux.yaml
@@ -0,0 +1,29 @@
+# Copyright (c) 2021, Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink B91 PinMux
+
+compatible: "telink,b91-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    pad-mul-sel:
+      type: int
+      required: true
+      description: PinMux pad_mul_sel register values.
+
+child-binding:
+    description:
+        This binding gives a base representation of the Telink B91 pins configration.
+
+    properties:
+        pinmux:
+          required: true
+          type: int
diff --git a/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinmux.yaml b/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinmux.yaml
new file mode 100644
index 0000000000..a17a266795
--- /dev/null
+++ b/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinmux.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Brett Witherspoon
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC13xx / CC26xx pinmux node
+
+compatible: "ti,cc13xx-cc26xx-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml b/dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml
new file mode 100644
index 0000000000..3f82067466
--- /dev/null
+++ b/dts/bindings/pm_cpu_ops/arm,psci-0.2.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2020 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: PSCI
+
+compatible: "arm,psci-0.2"
+
+include: base.yaml
+
+properties:
+  label:
+    required: true
+
+  method:
+    type: string
+    required: true
+    description: The method of calling the PSCI firmware.
+    enum:
+      - smc
+      - hvc
diff --git a/dts/bindings/power/nordic,nrf-power.yaml b/dts/bindings/power/nordic,nrf-power.yaml
new file mode 100644
index 0000000000..fbc38c33ae
--- /dev/null
+++ b/dts/bindings/power/nordic,nrf-power.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF power control node
+
+compatible: "nordic,nrf-power"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/power/nordic,nrf-regulators.yaml b/dts/bindings/power/nordic,nrf-regulators.yaml
new file mode 100644
index 0000000000..ecfa6b1bef
--- /dev/null
+++ b/dts/bindings/power/nordic,nrf-regulators.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic REGULATORS (voltage regulators control module)
+
+compatible: "nordic,nrf-regulators"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/power/nordic,nrf-vmc.yaml b/dts/bindings/power/nordic,nrf-vmc.yaml
new file mode 100644
index 0000000000..9ed6fa584c
--- /dev/null
+++ b/dts/bindings/power/nordic,nrf-vmc.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic VMC (Volatile Memory Controller)
+
+compatible: "nordic,nrf-vmc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/power/telink,b91-power.yaml b/dts/bindings/power/telink,b91-power.yaml
new file mode 100644
index 0000000000..7132f9d027
--- /dev/null
+++ b/dts/bindings/power/telink,b91-power.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2021 Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink B91 power control node
+
+compatible: "telink,b91-power"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    power-mode:
+      type: string
+      required: true
+      enum:
+        - "LDO_1P4_LDO_1P8"
+        - "DCDC_1P4_LDO_1P8"
+        - "DCDC_1P4_DCDC_1P8"
+
+    vbat-type:
+      type: string
+      required: true
+      enum:
+        - "VBAT_MAX_VALUE_LESS_THAN_3V6"
+        - "VBAT_MAX_VALUE_GREATER_THAN_3V6"
diff --git a/dts/bindings/power/zephyr,power-state.yaml b/dts/bindings/power/zephyr,power-state.yaml
new file mode 100644
index 0000000000..c45d5e39a2
--- /dev/null
+++ b/dts/bindings/power/zephyr,power-state.yaml
@@ -0,0 +1,36 @@
+# Copyright (c) 2020, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Properties for power management state
+
+compatible: "zephyr,power-state"
+
+properties:
+    power-state-name:
+        type: string
+        required: true
+        description: indicates a power state
+        enum:
+            - "active"
+            - "runtime-idle"
+            - "suspend-to-idle"
+            - "standby"
+            - "suspend-to-ram"
+            - "suspend-to-disk"
+            - "soft-off"
+    substate-id:
+        type: int
+        required: false
+        description: Platform specific identification.
+    min-residency-us:
+        type: int
+        required: false
+        description: |
+            Minimum residency duration in microseconds. It is the minimum time for a
+            given idle state to be worthwhile energywise. It includes the time to enter
+            in this state.
+    exit-latency-us:
+        type: int
+        required: false
+        description: |
+            Worst case latency in microseconds required to exit the idle state.
diff --git a/dts/bindings/ps2/microchip,xec-ps2.yaml b/dts/bindings/ps2/microchip,xec-ps2.yaml
new file mode 100644
index 0000000000..ec1c50613c
--- /dev/null
+++ b/dts/bindings/ps2/microchip,xec-ps2.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC PS/2 controller
+
+compatible: "microchip,xec-ps2"
+
+include: ps2.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    girq:
+      type: int
+      required: true
+      description: GIRQ for this device
+
+    girq-bit:
+      type: int
+      required: true
+      description: Bit position in GIRQ for this device
diff --git a/dts/bindings/ps2/nuvoton,npcx-ps2-channel.yaml b/dts/bindings/ps2/nuvoton,npcx-ps2-channel.yaml
new file mode 100644
index 0000000000..f50f26c24e
--- /dev/null
+++ b/dts/bindings/ps2/nuvoton,npcx-ps2-channel.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-PS/2 channel pads node
+
+compatible: "nuvoton,npcx-ps2-channel"
+
+include: base.yaml
+
+properties:
+    channel:
+        type: int
+        required: true
+        description: index of i2c channel
+
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of pinmux controllers
diff --git a/dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml b/dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml
new file mode 100644
index 0000000000..f1571235f7
--- /dev/null
+++ b/dts/bindings/ps2/nuvoton,npcx-ps2-ctrl.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-PS/2 controller node
+
+compatible: "nuvoton,npcx-ps2-ctrl"
+
+include: base.yaml
+
+bus: ps2
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+        required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/ps2/ps2.yaml b/dts/bindings/ps2/ps2.yaml
new file mode 100644
index 0000000000..89402024e6
--- /dev/null
+++ b/dts/bindings/ps2/ps2.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties for PS/2 devices
+
+include: base.yaml
+
+bus: ps2
+
+properties:
+    "#address-cells":
+      type: int
+      required: true
+      const: 1
+    "#size-cells":
+      type: int
+      required: true
+      const: 0
+    label:
+      required: true
diff --git a/dts/bindings/pwm/atmel,sam-pwm.yaml b/dts/bindings/pwm/atmel,sam-pwm.yaml
new file mode 100644
index 0000000000..c2e71fe4bd
--- /dev/null
+++ b/dts/bindings/pwm/atmel,sam-pwm.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2019, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM PWM
+
+compatible: "atmel,sam-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    prescaler:
+      type: int
+      required: true
+      description: Clock prescaler at the input of the PWM (0 to 10)
+
+    divider:
+      type: int
+      required: true
+      description: Clock divider at the input of the PWM (1 to 255)
+
+    "#pwm-cells":
+      const: 2
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
diff --git a/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml b/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml
new file mode 100644
index 0000000000..0a080c6070
--- /dev/null
+++ b/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml
@@ -0,0 +1,62 @@
+# Copyright (c) 2020 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 TCC in PWM mode
+
+compatible: "atmel,sam0-tcc-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clocks:
+    required: true
+
+  clock-names:
+    required: true
+
+  label:
+    required: true
+
+  channels:
+    type: int
+    required: true
+    description: Number of channels this TCC has
+    enum:
+      - 2
+      - 3
+      - 4
+      - 6
+
+  counter-size:
+    type: int
+    required: true
+    description: Width of the TCC counter in bits
+    enum:
+      - 16
+      - 24
+
+  prescaler:
+    type: int
+    required: true
+    description: PWM prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 64
+      - 256
+      - 1024
+
+  "#pwm-cells":
+    const: 1
+
+pwm-cells:
+  - channel
diff --git a/dts/bindings/pwm/espressif,esp32-ledc.yaml b/dts/bindings/pwm/espressif,esp32-ledc.yaml
new file mode 100644
index 0000000000..dfa81bff8a
--- /dev/null
+++ b/dts/bindings/pwm/espressif,esp32-ledc.yaml
@@ -0,0 +1,17 @@
+description: ESP32 LEDC
+
+compatible: "espressif,esp32-ledc"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    label:
+      required: true
+
+    "#pwm-cells":
+      const: 3
+
+pwm-cells:
+  - channel
+  - period
+  - flags
diff --git a/dts/bindings/pwm/fsl,imx27-pwm.yaml b/dts/bindings/pwm/fsl,imx27-pwm.yaml
new file mode 100644
index 0000000000..87434435b8
--- /dev/null
+++ b/dts/bindings/pwm/fsl,imx27-pwm.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2018, Diego Sueiro <diego.sueiro@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    This driver supports both i.MX6SX and i.MX7D PWM.
+    The compatible string is named "imx27" because the hardware module is the
+    same module present starting from imx27 CPUs and this driver can potentially
+    support other CPUs with imx27 module. This is also the same string used
+    in the Linux kernel.
+
+compatible: "fsl,imx27-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    prescaler:
+     type: int
+     required: true
+     description: Set the PWM prescale between 0 and 4096
+
+    rdc:
+     type: int
+     required: true
+     description: Set the RDC permission for this peripheral
+
+    "#pwm-cells":
+     const: 2
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
diff --git a/dts/bindings/pwm/ite,it8xxx2-pwm.yaml b/dts/bindings/pwm/ite,it8xxx2-pwm.yaml
new file mode 100644
index 0000000000..e3e6331a05
--- /dev/null
+++ b/dts/bindings/pwm/ite,it8xxx2-pwm.yaml
@@ -0,0 +1,63 @@
+# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE, it8xxx2 Pulse Width Modulator (PWM) node
+
+compatible: "ite,it8xxx2-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: false
+
+    channel:
+      type: int
+      required: true
+      enum:
+            - 0
+            - 1
+            - 2
+            - 3
+            - 4
+            - 5
+            - 6
+            - 7
+      description: |
+        0 = PWM_CHANNEL_0, 1 = PWM_CHANNEL_1, 2 = PWM_CHANNEL_2,
+        3 = PWM_CHANNEL_3, 4 = PWM_CHANNEL_4, 5 = PWM_CHANNEL_5,
+        6 = PWM_CHANNEL_6, 7 = PWM_CHANNEL_7
+
+    pwmctrl:
+        type: phandle
+        required: true
+        description: PWM prescaler controller
+
+    pinctrl-0:
+        type: phandle
+        required: true
+        description: configuration of PWM pinmux controller
+
+    prescaler-cx:
+      type: int
+      required: true
+      enum:
+            - 1
+            - 2
+            - 3
+      description: 1 = PWM_PRESCALER_C4, 2 = PWM_PRESCALER_C6, 3 = PWM_PRESCALER_C7
+
+    pwm-output-frequency:
+      type: int
+      required: false
+      description: PWM output frequency for operation
+
+pwm-cells:
+  - channel
+  - flags
diff --git a/dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml b/dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml
new file mode 100644
index 0000000000..8fa46445e4
--- /dev/null
+++ b/dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE, it8xxx2 PWM prescaler node
+
+compatible: "ite,it8xxx2-pwmprs"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: false
diff --git a/dts/bindings/pwm/litex,pwm.yaml b/dts/bindings/pwm/litex,pwm.yaml
new file mode 100644
index 0000000000..92bef61888
--- /dev/null
+++ b/dts/bindings/pwm/litex,pwm.yaml
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: LiteX PWM controller
+
+include: [pwm-controller.yaml, base.yaml]
+
+compatible: "litex,pwm"
+properties:
+
+    reg:
+      required: true
diff --git a/dts/bindings/pwm/microchip,xec-pwm.yaml b/dts/bindings/pwm/microchip,xec-pwm.yaml
new file mode 100644
index 0000000000..630b4a3129
--- /dev/null
+++ b/dts/bindings/pwm/microchip,xec-pwm.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC PWM
+
+include: [pwm-controller.yaml, base.yaml]
+
+compatible: "microchip,xec-pwm"
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/pwm/nordic,nrf-pwm.yaml b/dts/bindings/pwm/nordic,nrf-pwm.yaml
new file mode 100644
index 0000000000..b2393c6055
--- /dev/null
+++ b/dts/bindings/pwm/nordic,nrf-pwm.yaml
@@ -0,0 +1,77 @@
+description: nRF PWM
+
+compatible: "nordic,nrf-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    center-aligned:
+      type: boolean
+      required: false
+      description: Set this to use center-aligned (up and down) counter mode.
+
+    ch0-pin:
+      type: int
+      required: false
+      description: |
+        The channel 0 pin to use.
+
+        For pins P0.0 through P0.31, use the pin number. For example,
+        to use P0.16 for channel 0, set:
+
+            ch0-pin = <16>;
+
+        For pins P1.0 through P1.31, add 32 to the pin number. For
+        example, to use P1.2 for channel 0, set:
+
+            ch0-pin = <34>;  /* 32 + 2 */
+
+    ch0-inverted:
+      type: boolean
+      required: false
+      description: Set this to invert channel 0.
+
+    ch1-pin:
+      type: int
+      required: false
+      description: |
+        The channel 1 pin to use. The pin numbering scheme is the same
+        as the ch0-pin property's.
+
+    ch1-inverted:
+      type: boolean
+      required: false
+      description: Set this to invert channel 1.
+
+    ch2-pin:
+      type: int
+      required: false
+      description: |
+        The channel 2 pin to use. The pin numbering scheme is the same
+        as the ch0-pin property's.
+
+    ch2-inverted:
+      type: boolean
+      required: false
+      description: Set this to invert channel 2.
+
+    ch3-pin:
+      type: int
+      required: false
+      description: |
+        The channel 3 pin to use. The pin numbering scheme is the same
+        as the ch0-pin property's.
+
+    ch3-inverted:
+      type: boolean
+      required: false
+      description: Set this to invert channel 3.
+
+    "#pwm-cells":
+      const: 1
+
+pwm-cells:
+  - channel
diff --git a/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml b/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml
new file mode 100644
index 0000000000..2eb15f86d4
--- /dev/null
+++ b/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml
@@ -0,0 +1,36 @@
+description: nRFx S/W PWM
+
+compatible: "nordic,nrf-sw-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    generator:
+      type: phandle
+      description: |
+        Reference to TIMER or RTC instance for generating PWM output signals
+      required: true
+
+    channel-count:
+      type: int
+      description: |
+        Number of PWM channels. Limited by RTC/TIMER instance compare registers
+        minus 1.
+      required: true
+
+    clock-prescaler:
+      type: int
+      description: |
+        Clock prescaler for RTC or TIMER used for generating PWM output signals.
+
+        RTC: needs to be set to 0, which gives 32768 Hz base clock for PWM
+        generation.
+
+        TIMER: 16 MHz / 2^prescaler base clock is used for PWM generation.
+      required: true
+
+    "#pwm-cells":
+      const: 1
+
+pwm-cells:
+  - channel
diff --git a/dts/bindings/pwm/nuvoton,npcx-pwm.yaml b/dts/bindings/pwm/nuvoton,npcx-pwm.yaml
new file mode 100644
index 0000000000..f049f2e473
--- /dev/null
+++ b/dts/bindings/pwm/nuvoton,npcx-pwm.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Pulse Width Modulator (PWM) node
+
+compatible: "nuvoton,npcx-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+        required: true
+    clocks:
+        required: true
+    label:
+        required: true
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of pinmux controllers
+    drive-open-drain:
+        type: boolean
+        description: |
+            The PWM output will be configured as open-drain. If not set,
+            defaults to push-pull.
+    clock-bus:
+        required: false
+        type: string
+        description: |
+            Select a specific input clock source for the PWM module. If this
+            property doesn't exist, fallback to default value in clocks property.
+        enum:
+            - NPCX_CLOCK_BUS_APB2
+            - NPCX_CLOCK_BUS_LFCLK
+
+pwm-cells:
+    - channel
+    - flags
diff --git a/dts/bindings/pwm/nxp,flexpwm.yaml b/dts/bindings/pwm/nxp,flexpwm.yaml
new file mode 100644
index 0000000000..ba6284926c
--- /dev/null
+++ b/dts/bindings/pwm/nxp,flexpwm.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP eFLEX PWM module with mcux-pwm submodules
+
+compatible: "nxp,flexpwm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/pwm/nxp,imx-pwm.yaml b/dts/bindings/pwm/nxp,imx-pwm.yaml
new file mode 100644
index 0000000000..49b67ce9b7
--- /dev/null
+++ b/dts/bindings/pwm/nxp,imx-pwm.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUX PWM
+
+compatible: "nxp,imx-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    index:
+      type: int
+      description: flexpwm submodule index
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    "#pwm-cells":
+      const: 1
+
+pwm-cells:
+  - channel
diff --git a/dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml b/dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml
new file mode 100644
index 0000000000..091cc430cc
--- /dev/null
+++ b/dts/bindings/pwm/nxp,kinetis-ftm-pwm.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis FTM PWM
+
+compatible: "nxp,kinetis-ftm-pwm"
+
+include: [pwm-controller.yaml, "nxp,kinetis-ftm.yaml"]
+
+properties:
+    "#pwm-cells":
+      const: 3
+
+    pinctrl-0:
+      type: phandles
+      required: true
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
+  - flags
diff --git a/dts/bindings/pwm/nxp,kinetis-pwt.yaml b/dts/bindings/pwm/nxp,kinetis-pwt.yaml
new file mode 100644
index 0000000000..02e9282988
--- /dev/null
+++ b/dts/bindings/pwm/nxp,kinetis-pwt.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2021 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis PWT PWM Capture
+
+compatible: "nxp,kinetis-pwt"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+      description: Input clock prescaler
+
+    "#pwm-cells":
+      const: 3
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
+  - flags
diff --git a/dts/bindings/pwm/nxp,kinetis-tpm.yaml b/dts/bindings/pwm/nxp,kinetis-tpm.yaml
new file mode 100644
index 0000000000..fa381b3cca
--- /dev/null
+++ b/dts/bindings/pwm/nxp,kinetis-tpm.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: MCUX Timer/PWM Module (TPM)
+
+compatible: "nxp,kinetis-tpm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
+
+    "#pwm-cells":
+      const: 3
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
+  - flags
diff --git a/dts/bindings/pwm/nxp,sctimer-pwm.yaml b/dts/bindings/pwm/nxp,sctimer-pwm.yaml
new file mode 100644
index 0000000000..ee054be66c
--- /dev/null
+++ b/dts/bindings/pwm/nxp,sctimer-pwm.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP SCTimer PWM
+
+compatible: "nxp,sctimer-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    prescaler:
+      type: int
+      required: false
+      default: 1
+      description: prescaling factor from the SCT clock. Default to 1 which is the reset value
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+
+    "#pwm-cells":
+      const: 2
+
+pwm-cells:
+  - channel
+  - flags
diff --git a/dts/bindings/pwm/openisa,rv32m1-tpm.yaml b/dts/bindings/pwm/openisa,rv32m1-tpm.yaml
new file mode 100644
index 0000000000..bfcbbca80b
--- /dev/null
+++ b/dts/bindings/pwm/openisa,rv32m1-tpm.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: OpenISA Timer/PWM Module (TPM)
+
+compatible: "openisa,rv32m1-tpm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#pwm-cells":
+      const: 3
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
+  - flags
diff --git a/dts/bindings/pwm/pwm-controller.yaml b/dts/bindings/pwm/pwm-controller.yaml
new file mode 100644
index 0000000000..1ad60ea7c9
--- /dev/null
+++ b/dts/bindings/pwm/pwm-controller.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for PWM controllers
+
+properties:
+    label:
+      required: true
+
+    "#pwm-cells":
+      type: int
+      required: true
+      description: Number of items to expect in a pwm specifier
diff --git a/dts/bindings/pwm/sifive,pwm0.yaml b/dts/bindings/pwm/sifive,pwm0.yaml
new file mode 100644
index 0000000000..d6f4b00a04
--- /dev/null
+++ b/dts/bindings/pwm/sifive,pwm0.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2018, SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive PWM
+
+compatible: "sifive,pwm0"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    clock-frequency:
+      type: int
+      required: false
+      description: Clock frequency information for PWM operation
+
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    sifive,compare-width:
+      type: int
+      required: true
+      description: Width of the PWM comparator in bits
+
+    "#pwm-cells":
+      const: 2
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
diff --git a/dts/bindings/pwm/silabs,gecko-pwm.yaml b/dts/bindings/pwm/silabs,gecko-pwm.yaml
new file mode 100644
index 0000000000..dccf95d232
--- /dev/null
+++ b/dts/bindings/pwm/silabs,gecko-pwm.yaml
@@ -0,0 +1,36 @@
+description: Silabs Gecko PWM port
+
+compatible: "silabs,gecko-pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    pin-location:
+      type: array
+      required: true
+      description: pwm pin configuration defined as <location port pin>
+
+    prescaler:
+      type: int
+      required: false
+      default: 1
+      description: prescaling factor from the HFPERCLK clock
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+        - 256
+        - 512
+        - 1024
+
+    "#pwm-cells":
+      const: 2
+
+pwm-cells:
+  - channel
+  - flags
diff --git a/dts/bindings/pwm/snps,designware-pwm.yaml b/dts/bindings/pwm/snps,designware-pwm.yaml
new file mode 100644
index 0000000000..715fee2484
--- /dev/null
+++ b/dts/bindings/pwm/snps,designware-pwm.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2020 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys DesignWare PWM node
+
+compatible: "snps,designware-pwm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    channels:
+      type: int
+      required: true
+      description: Number of PWM channels
diff --git a/dts/bindings/pwm/st,stm32-pwm.yaml b/dts/bindings/pwm/st,stm32-pwm.yaml
new file mode 100644
index 0000000000..5ad0300a53
--- /dev/null
+++ b/dts/bindings/pwm/st,stm32-pwm.yaml
@@ -0,0 +1,34 @@
+description: STM32 PWM
+
+compatible: "st,stm32-pwm"
+
+include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
+
+properties:
+    label:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
+    st,prescaler:
+      type: int
+      required: false
+      deprecated: true
+      description: |
+        Clock prescaler at the input of the timer
+        Note: This property is obsolete and was replaced by "st,prescaler"
+        binding of parent timer node. It is kept temporarily for compatibility
+        reasons.
+
+    "#pwm-cells":
+      const: 3
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
+  - flags
diff --git a/dts/bindings/pwm/telink,b91-pwm.yaml b/dts/bindings/pwm/telink,b91-pwm.yaml
new file mode 100644
index 0000000000..71ed095ba0
--- /dev/null
+++ b/dts/bindings/pwm/telink,b91-pwm.yaml
@@ -0,0 +1,66 @@
+# Copyright (c) 2021, Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+
+description: Telink B91 PWM
+
+include: [pwm-controller.yaml, base.yaml]
+
+compatible: "telink,b91-pwm"
+
+properties:
+
+    pinctrl-0:
+      type: phandles
+      required: true
+
+    clock-frequency:
+      type: int
+      required: true
+      description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
+
+    clk32k-ch0-enable:
+      type: boolean
+      required: false
+      description: Enable 32K Source Clock for PWM Channel 0
+
+    clk32k-ch1-enable:
+      type: boolean
+      required: false
+      description: Enable 32K Source Clock for PWM Channel 1
+
+    clk32k-ch2-enable:
+      type: boolean
+      required: false
+      description: Enable 32K Source Clock for PWM Channel 2
+
+    clk32k-ch3-enable:
+      type: boolean
+      required: false
+      description: Enable 32K Source Clock for PWM Channel 3
+
+    clk32k-ch4-enable:
+      type: boolean
+      required: false
+      description: Enable 32K Source Clock for PWM Channel 4
+
+    clk32k-ch5-enable:
+      type: boolean
+      required: false
+      description: Enable 32K Source Clock for PWM Channel 5
+
+    channels:
+      type: int
+      const: 6
+      required: true
+      description: Number of channels this PWM has
+
+    reg:
+      required: true
+
+    "#pwm-cells":
+      const: 2
+
+pwm-cells:
+  - channel
+  - flags
diff --git a/dts/bindings/pwm/xlnx,xps-timer-1.00.a-pwm.yaml b/dts/bindings/pwm/xlnx,xps-timer-1.00.a-pwm.yaml
new file mode 100644
index 0000000000..a5509c5845
--- /dev/null
+++ b/dts/bindings/pwm/xlnx,xps-timer-1.00.a-pwm.yaml
@@ -0,0 +1,24 @@
+description: Xilinx AXI Timer IP node (PWM controller)
+
+compatible: "xlnx,xps-timer-1.00.a-pwm"
+
+include: [ "xlnx,xps-timer-1.00.a.yaml", pwm-controller.yaml ]
+
+properties:
+    xlnx,gen0-assert:
+      required: true
+
+    xlnx,gen1-assert:
+      required: true
+
+    xlnx,trig0-assert:
+      required: true
+
+    xlnx,trig1-assert:
+      required: true
+
+pwm-cells:
+  - channel
+# period in terms of nanoseconds
+  - period
+  - flags
diff --git a/dts/bindings/qspi/st,stm32-qspi.yaml b/dts/bindings/qspi/st,stm32-qspi.yaml
new file mode 100644
index 0000000000..caf55428da
--- /dev/null
+++ b/dts/bindings/qspi/st,stm32-qspi.yaml
@@ -0,0 +1,52 @@
+# Copyright (c) 2020, Linaro limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STM32 QSPI device representation. A stm32 quadspi node would typically
+    looks to this:
+
+        &quadspi {
+            pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
+                         &quadspi_bk1_io0_pe12 &quadspi_bk1_io1_pe13
+                         &quadspi_bk1_io2_pe14 &quadspi_bk1_io3_pe15>;
+
+            dmas = <&dma1 5 5 0x0000 0x03>;
+            dma-names = "tx_rx";
+
+            status = "okay";
+        };
+
+compatible: "st,stm32-qspi"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+bus: qspi
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
+    dmas:
+      description: |
+        Optional DMA channel specifier. If DMA should be used, specifier should
+        hold a phandle reference to the dma controller, the channel number,
+        the slot number, channel configuration and finally features.
+
+        For example dmas for TX/RX on QSPI
+           dmas = <&dma1 5 5 0x0000 0x03>;
+
+    dma-names:
+      description: |
+        DMA channel name. If DMA should be used, expected value is "tx_rx".
+
+        For example
+           dma-names = "tx_rx";
diff --git a/dts/bindings/regulator/regulator-fixed.yaml b/dts/bindings/regulator/regulator-fixed.yaml
new file mode 100644
index 0000000000..73ceab820d
--- /dev/null
+++ b/dts/bindings/regulator/regulator-fixed.yaml
@@ -0,0 +1,50 @@
+# Copyright 2019-2020 Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: GPIO-controlled regulators
+
+include: regulator.yaml
+
+# NOTE: The driver supports "regulator-fixed-sync" as a specializing
+# variant when it's known that the GPIO state change operations are
+# isr-ok and not sleep, and both startup and off-on delays are zero.
+# This bypasses the asynchronous onoff manager which optimizes both time
+# and memory use.
+#
+# To enable this use both:
+#    compatible = "regulator-fixed-sync", "regulator-fixed";
+#
+
+compatible: "regulator-fixed"
+
+properties:
+  label:
+    required: true
+
+  regulator-name:
+    type: string
+    required: true
+    description: Descriptive name for regulator outputs.
+
+  enable-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      GPIO to use to enable/disable the regulator.
+
+      Unlike the gpio property in the Linux bindings this array must
+      provide the GPIO polarity and open-drain status in the phandle
+      selector.  The Linux enable-active-high and gpio-open-drain
+      properties are not valid for Zephyr devicetree files.
+
+  startup-delay-us:
+    type: int
+    required: false
+    default: 0
+    description: Startup time, in microseconds
+
+  off-on-delay-us:
+    type: int
+    required: false
+    default: 0
+    description: Off delay time, in microseconds
diff --git a/dts/bindings/regulator/regulator-pmic.yaml b/dts/bindings/regulator/regulator-pmic.yaml
new file mode 100644
index 0000000000..9a6e1a4211
--- /dev/null
+++ b/dts/bindings/regulator/regulator-pmic.yaml
@@ -0,0 +1,92 @@
+# Copyright (c), 2021 NXP
+# SPDX -License-Identifier: Apache-2.0
+
+description: PMIC controlled regulator
+
+include: regulator.yaml
+
+compatible: "regulator-pmic"
+
+properties:
+    label:
+        required: false
+    voltage-range:
+        type: array
+        required: true
+        description: |
+           array of voltage values in uV, followed by the register value that
+           must be written to enable the voltage. For example, [3300000, 0x3]
+           denotes a value of 0x3 must be written to the register to set 3.3V
+    num-voltages:
+        type: int
+        required: true
+        description: number of voltages present in the voltage-range array.
+    vsel-reg:
+        type: int
+        required: true
+        description: I2C register to write voltage selection value to
+    vsel-mask:
+        type: int
+        required: true
+        description: |
+          Mask to apply to the voltage range value when written to vsel
+          register
+    enable-reg:
+        type: int
+        required: true
+        description: I2C register to write enable value to
+    enable-mask:
+        type: int
+        required: true
+        description: |
+          Mask to apply to the enable bit (either 1 for enabled,
+          or 0 for disabled) when writing it to the I2C enable register.
+    enable-val:
+        type: int
+        required: true
+        description: |
+          value to apply enable-mask to, and write to enable-reg in order
+          to enable the regulator output.
+    min-uV:
+        type: int
+        required: true
+        description: |
+           Minimum voltage in microvolts that this regulator supports
+    max-uV:
+        type: int
+        required: true
+        description: |
+           Maximum voltage in microvolts that this regulator supports
+    enable-inverted:
+        type: boolean
+        required: false
+        description: |
+          If the enable bit should be zero to turn the regulator on, add this
+          property.
+    current-levels:
+        type: array
+        required: false
+        description: |
+          Array of current limit values in uA, followed by the register value
+          that must be written to enable the current limit. For example,
+          [800000, 0x3] denotes a value of 0x3 must be written to the register
+          to set a current limit of 800mA
+    num-current-levels:
+        type: int
+        required: false
+        default: 0
+        description: |
+          Number of current limit levels this regulator supports. If left as
+          default, regulator current support will be disabled.
+    ilim-reg:
+        type: int
+        required: false
+        description: |
+          Register to write the register value given in current-levels into
+          to set the current limit
+    ilim-mask:
+        type: int
+        required: false
+        description: |
+          Mask to apply to the current-levels value before writing it to the
+          ilim-reg value to set the current limit
diff --git a/dts/bindings/regulator/regulator.yaml b/dts/bindings/regulator/regulator.yaml
new file mode 100644
index 0000000000..cc610c0c3d
--- /dev/null
+++ b/dts/bindings/regulator/regulator.yaml
@@ -0,0 +1,17 @@
+# Copyright 2019-2020, Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Voltage/Current Regulators
+
+include: [base.yaml, power.yaml]
+
+# Linux defines several dozen properties.  We're providing only the ones
+# currently useful to Zephyr.
+properties:
+  regulator-always-on:
+    type: boolean
+    description: regulator should always be on
+
+  regulator-boot-on:
+    type: boolean
+    description: regulator should be turned on at startup
diff --git a/dts/bindings/reserved-memory/reserved-memory.yaml b/dts/bindings/reserved-memory/reserved-memory.yaml
new file mode 100644
index 0000000000..5b2d26aa0f
--- /dev/null
+++ b/dts/bindings/reserved-memory/reserved-memory.yaml
@@ -0,0 +1,23 @@
+description: |
+  Reserved memory - Each child of the reserved-memory node specifies one or
+  more regions of reserved memory. Regions in the /reserved-memory node may be
+  referenced by other device nodes by adding a memory-region property to the
+  device node.
+
+compatible: "reserved-memory"
+
+include:
+  - name: base.yaml
+    property-allowlist: ['#address-cells', '#size-cells']
+
+child-binding:
+    description: Regions
+    properties:
+       label:
+          type: string
+          required: false
+          description: Human readable string describing the device (used as device_get_binding() argument)
+       reg:
+          type: array
+          description: register space
+          required: true
diff --git a/dts/bindings/riscv/openisa,rv32m1-pcc.yaml b/dts/bindings/riscv/openisa,rv32m1-pcc.yaml
new file mode 100644
index 0000000000..040900a543
--- /dev/null
+++ b/dts/bindings/riscv/openisa,rv32m1-pcc.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2018 Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 PCC (Peripheral Clock Control) IP node
+
+compatible: "openisa,rv32m1-pcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - name
diff --git a/dts/bindings/riscv/riscv,cpus.yaml b/dts/bindings/riscv/riscv,cpus.yaml
new file mode 100644
index 0000000000..a9a39d9fb7
--- /dev/null
+++ b/dts/bindings/riscv/riscv,cpus.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+include: cpu.yaml
+
+properties:
+  mmu-type:
+    description: Memory Management Unit (MMU)
+    required: false
+    type: string
+    enum:
+      - riscv,sv32
+      - riscv,sv39
+      - riscv,sv48
+      - riscv,none
+
+  riscv,isa:
+    description: RISC-V instruction set architecture
+    required: true
+    type: string
+    enum:
+      - rv32imac
+      - rv32imafc
+      - rv32imafcb
+      - rv64imac
+      - rv64imafdc
+
+  riscv,pmpregions:
+    description: Physical Memory Protection (PMP)
+    required: true
+    type: int
diff --git a/dts/bindings/riscv/riscv,sifive-e24.yaml b/dts/bindings/riscv/riscv,sifive-e24.yaml
new file mode 100644
index 0000000000..187cebe3db
--- /dev/null
+++ b/dts/bindings/riscv/riscv,sifive-e24.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive E24 Standard Core CPU
+
+compatible: "riscv,sifive-e24"
+
+include: riscv,sifive.yaml
diff --git a/dts/bindings/riscv/riscv,sifive.yaml b/dts/bindings/riscv/riscv,sifive.yaml
new file mode 100644
index 0000000000..b5681d7a70
--- /dev/null
+++ b/dts/bindings/riscv/riscv,sifive.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for SiFive RISC-V CPUs
+
+include: riscv,cpus.yaml
+
+properties:
+    hardware-exec-breakpoint-count:
+      type: int
+      required: false
+      description: Number of hardware break points
diff --git a/dts/bindings/rng/atmel,sam-trng.yaml b/dts/bindings/rng/atmel,sam-trng.yaml
new file mode 100644
index 0000000000..e3c67f354f
--- /dev/null
+++ b/dts/bindings/rng/atmel,sam-trng.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2018, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM RNG
+
+compatible: "atmel,sam-trng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/espressif,esp32-trng.yaml b/dts/bindings/rng/espressif,esp32-trng.yaml
new file mode 100644
index 0000000000..bde8d92ee6
--- /dev/null
+++ b/dts/bindings/rng/espressif,esp32-trng.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2019, Mohamed ElShahawi <ExtremeGTX@hotmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Espressif ESP32 TRNG (True Random Number Generator).
+
+    The TRNG uses the noise in the Wi-Fi/BT RF system. When Wi-Fi and BT are
+    disabled, the random number generator will give out pseudo-random numbers.
+
+compatible: "espressif,esp32-trng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/litex,prbs.yaml b/dts/bindings/rng/litex,prbs.yaml
new file mode 100644
index 0000000000..051fc75a64
--- /dev/null
+++ b/dts/bindings/rng/litex,prbs.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX PRBS
+
+compatible: "litex,prbs"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
diff --git a/dts/bindings/rng/neorv32-trng.yaml b/dts/bindings/rng/neorv32-trng.yaml
new file mode 100644
index 0000000000..89d894fc37
--- /dev/null
+++ b/dts/bindings/rng/neorv32-trng.yaml
@@ -0,0 +1,15 @@
+description: NEORV32 True Random Number Generator (TRNG)
+
+compatible: "neorv32-trng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    syscon:
+      type: phandle
+      required: true
+      description: |
+        phandle to syscon (NEORV32 SYSINFO) node.
diff --git a/dts/bindings/rng/nordic,nrf-rng.yaml b/dts/bindings/rng/nordic,nrf-rng.yaml
new file mode 100644
index 0000000000..fabc6b60c1
--- /dev/null
+++ b/dts/bindings/rng/nordic,nrf-rng.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF family RNG (Random Number Generator)
+
+compatible: "nordic,nrf-rng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/rng/nxp,kinetis-rnga.yaml b/dts/bindings/rng/nxp,kinetis-rnga.yaml
new file mode 100644
index 0000000000..415d94dbbc
--- /dev/null
+++ b/dts/bindings/rng/nxp,kinetis-rnga.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis RNGA (Random Number Generator Accelerator)
+
+compatible: "nxp,kinetis-rnga"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/nxp,kinetis-trng.yaml b/dts/bindings/rng/nxp,kinetis-trng.yaml
new file mode 100644
index 0000000000..62bcd8ad4a
--- /dev/null
+++ b/dts/bindings/rng/nxp,kinetis-trng.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis TRNG (True Random Number Generator)
+
+compatible: "nxp,kinetis-trng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/nxp,lpc-rng.yaml b/dts/bindings/rng/nxp,lpc-rng.yaml
new file mode 100644
index 0000000000..7e95d0ffc6
--- /dev/null
+++ b/dts/bindings/rng/nxp,lpc-rng.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC RNG (Random Number Generator)
+
+compatible: "nxp,lpc-rng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/openisa,rv32m1-trng.yaml b/dts/bindings/rng/openisa,rv32m1-trng.yaml
new file mode 100644
index 0000000000..f5fc8feffd
--- /dev/null
+++ b/dts/bindings/rng/openisa,rv32m1-trng.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: OpenISA TRNG (True Random Number Generator)
+
+compatible: "openisa,rv32m1-trng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/silabs,gecko-trng.yaml b/dts/bindings/rng/silabs,gecko-trng.yaml
new file mode 100644
index 0000000000..f89d4bf606
--- /dev/null
+++ b/dts/bindings/rng/silabs,gecko-trng.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2020, Lemonbeat GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    GECKO TRNG (True Random Number Generator).
+
+    The TRNG module is a non-deterministic randomnumber generator based on a full hardware solution.
+
+compatible: "silabs,gecko-trng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/st,stm32-rng.yaml b/dts/bindings/rng/st,stm32-rng.yaml
new file mode 100644
index 0000000000..2d890d39ac
--- /dev/null
+++ b/dts/bindings/rng/st,stm32-rng.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 Random Number Generator
+
+compatible: "st,stm32-rng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    clocks:
+      required: true
+
+    health-test-magic:
+      type: int
+      required: false
+      description: |
+           Magic Number to be written to Health Test Configuration Register (HTCR)
+           prior to real configuration, if any.
+
+    health-test-config:
+      type: int
+      required: false
+      description: |
+           Heath Test Configuration, necessary to have proper RNG behavior,
+           when available.
diff --git a/dts/bindings/rng/telink,b91-trng.yaml b/dts/bindings/rng/telink,b91-trng.yaml
new file mode 100644
index 0000000000..44d850d45b
--- /dev/null
+++ b/dts/bindings/rng/telink,b91-trng.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021, Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink B91 RNG
+
+compatible: "telink,b91-trng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml b/dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml
new file mode 100644
index 0000000000..d4a4acffdd
--- /dev/null
+++ b/dts/bindings/rng/ti,cc13xx-cc26xx-trng.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019 Brett Witherspoon
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC13xx / CC26xx TRNG (True Random Number Generator)
+
+compatible: "ti,cc13xx-cc26xx-trng"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/rng/zephyr,native-posix-rng.yaml b/dts/bindings/rng/zephyr,native-posix-rng.yaml
new file mode 100644
index 0000000000..fca8692a6c
--- /dev/null
+++ b/dts/bindings/rng/zephyr,native-posix-rng.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Native POSIX RNG/Entropy
+
+compatible: "zephyr,native-posix-rng"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/rtc/atmel,sam0-rtc.yaml b/dts/bindings/rtc/atmel,sam0-rtc.yaml
new file mode 100644
index 0000000000..8e3d704739
--- /dev/null
+++ b/dts/bindings/rtc/atmel,sam0-rtc.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2018 omSquare s.r.o.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 RTC
+
+compatible: "atmel,sam0-rtc"
+
+include: rtc.yaml
+
+properties:
+    reg:
+      required: true
+
+    clock-generator:
+      type: int
+      description: clock generator index
+      required: true
diff --git a/dts/bindings/rtc/maxim,ds3231.yaml b/dts/bindings/rtc/maxim,ds3231.yaml
new file mode 100644
index 0000000000..25d2ef7f6c
--- /dev/null
+++ b/dts/bindings/rtc/maxim,ds3231.yaml
@@ -0,0 +1,39 @@
+#
+# Copyright (c) 2019 Peter Bigot Consulting, LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Maxim DS3231 I2C RTC/TCXO
+
+compatible: "maxim,ds3231"
+
+include: i2c-device.yaml
+
+properties:
+  reg:
+    required: true
+
+  32k-gpios:
+    type: phandle-array
+    required: false
+    description: |
+
+      32 KiHz open drain output
+
+      The DS3231 defaults to providing a 32 KiHz square wave on this
+      signal.  The driver does not make use of this, but applications
+      may want access.
+
+  isw-gpios:
+    type: phandle-array
+    required: false
+    description: |
+
+      interrupt/square wave open drain output
+
+      The DS3231 uses this signal to notify when an alarm has triggered,
+      and also to produce a square wave aligned to the countdown chain.
+      Both capabilities are used within the driver.  This signal must be
+      present to support time set and read operations that preserve
+      sub-second accuracy.
diff --git a/dts/bindings/rtc/microchip,mcp7940n.yaml b/dts/bindings/rtc/microchip,mcp7940n.yaml
new file mode 100644
index 0000000000..86750eae22
--- /dev/null
+++ b/dts/bindings/rtc/microchip,mcp7940n.yaml
@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2021 Laird Connectivity
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Microchip MCP7940N I2C RTC
+
+compatible: "microchip,mcp7940n"
+
+include: i2c-device.yaml
+
+properties:
+  reg:
+    required: true
+
+  int-gpios:
+    type: phandle-array
+    required: false
+    description: |
+
+      Host input connected to the MCP7940N MFP open drain output pin
+
+      Notifies when an alarm has triggered by asserting this line.
diff --git a/dts/bindings/rtc/microchip,xec-timer.yaml b/dts/bindings/rtc/microchip,xec-timer.yaml
new file mode 100644
index 0000000000..d391635b39
--- /dev/null
+++ b/dts/bindings/rtc/microchip,xec-timer.yaml
@@ -0,0 +1,54 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC basic timer
+
+compatible: "microchip,xec-timer"
+
+include: rtc.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clock-frequency:
+      required: true
+
+    prescaler:
+      type: int
+      required: true
+      description: Timer frequency equals clock-frequency divided by the prescaler value
+
+    max-value:
+      type: int
+      required: true
+      description: Maximum counter value the instance can handle
+
+    girqs:
+      type: array
+      required: true
+      description: Array of GIRQ numbers [8:26] and bit positions [0:31].
+
+    pcrs:
+      type: array
+      required: true
+      description: PCR sleep enable register index and bit position.
+
+    "#girq-cells":
+      type: int
+      const: 2
+
+    "#pcr-cells":
+      type: int
+      const: 2
+
+girq-cells:
+    - girq_num
+    - bitpos
+
+pcr-cells:
+    - reg_index
+    - bitpos
diff --git a/dts/bindings/rtc/nordic,nrf-rtc.yaml b/dts/bindings/rtc/nordic,nrf-rtc.yaml
new file mode 100644
index 0000000000..f039cb8414
--- /dev/null
+++ b/dts/bindings/rtc/nordic,nrf-rtc.yaml
@@ -0,0 +1,37 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF RTC (Real-Time Counter)
+
+compatible: "nordic,nrf-rtc"
+
+include: rtc.yaml
+
+properties:
+    reg:
+      required: true
+
+    cc-num:
+      type: int
+      required: true
+      description: |
+        Number of compare (CC) registers available.
+
+        On nRF53 these registers can also be used for capture.
+
+    # If enabled, overflow different than full range (24 bits) is handled
+    # through PPI channel which ensures precise timing. If disabled then
+    # counter is cleared in the interrupt which results in accumulative error
+    # of counter period if top value is different than maximal.
+    ppi-wrap:
+      type: boolean
+      description: Enable wrapping with PPI
+      required: false
+
+   # If enabled then counter based on nRF RTC peripheral supports only maximal
+   # top value. That results in code optimizations and availability of one more
+   # channel
+    fixed-top:
+      type: boolean
+      description: Enable fixed top value
+      required: false
diff --git a/dts/bindings/rtc/nxp,imx-snvs-rtc.yaml b/dts/bindings/rtc/nxp,imx-snvs-rtc.yaml
new file mode 100644
index 0000000000..7e0b24c723
--- /dev/null
+++ b/dts/bindings/rtc/nxp,imx-snvs-rtc.yaml
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2021 Basalte bv
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: NXP SNVS LP/HP RTC
+
+compatible: "nxp,imx-snvs-rtc"
+
+include: rtc.yaml
diff --git a/dts/bindings/rtc/nxp,kinetis-lptmr.yaml b/dts/bindings/rtc/nxp,kinetis-lptmr.yaml
new file mode 100644
index 0000000000..66fc275c8c
--- /dev/null
+++ b/dts/bindings/rtc/nxp,kinetis-lptmr.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2020 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis LPTMR
+
+compatible: "nxp,kinetis-lptmr"
+
+include: rtc.yaml
+
+properties:
+    reg:
+      required: true
+
+    clock-frequency:
+      required: true
+
+    prescaler:
+      required: true
+
+    clk-source:
+      type: int
+      required: true
+      description: Prescaler clock source (0 to 3)
+
+    input-pin:
+      type: int
+      required: false
+      description: Pulse counter input pin (0 to 3).
+
+    active-low:
+      type: boolean
+      required: false
+      description: Pulse counter input pin is active-low
diff --git a/dts/bindings/rtc/nxp,kinetis-pit.yaml b/dts/bindings/rtc/nxp,kinetis-pit.yaml
new file mode 100644
index 0000000000..0b8943c545
--- /dev/null
+++ b/dts/bindings/rtc/nxp,kinetis-pit.yaml
@@ -0,0 +1,22 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUX Periodic Interrupt Timer (PIT)
+
+compatible: "nxp,kinetis-pit"
+
+include: [rtc.yaml]
+
+properties:
+    reg:
+      required: true
+
+    pit-channel:
+      type: int
+      required: true
+      description: pit channel to active
+
+    pit-period:
+      type: int
+      required: true
+      description: pit default period in us
diff --git a/dts/bindings/rtc/nxp,kinetis-rtc.yaml b/dts/bindings/rtc/nxp,kinetis-rtc.yaml
new file mode 100644
index 0000000000..e9203f44f8
--- /dev/null
+++ b/dts/bindings/rtc/nxp,kinetis-rtc.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, blik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis RTC
+
+compatible: "nxp,kinetis-rtc"
+
+include: rtc.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/rtc/rtc.yaml b/dts/bindings/rtc/rtc.yaml
new file mode 100644
index 0000000000..e30ebed8cb
--- /dev/null
+++ b/dts/bindings/rtc/rtc.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2018, blik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for RTC devices
+
+include: base.yaml
+
+properties:
+    clock-frequency:
+      type: int
+      required: false
+      description: Clock frequency information for RTC operation
+    label:
+      required: true
+    interrupts:
+      required: true
+
+    prescaler:
+      type: int
+      required: false
+      description: RTC frequency equals clock-frequency divided by the prescaler value
diff --git a/dts/bindings/rtc/silabs,gecko-rtcc.yaml b/dts/bindings/rtc/silabs,gecko-rtcc.yaml
new file mode 100644
index 0000000000..014c92d60e
--- /dev/null
+++ b/dts/bindings/rtc/silabs,gecko-rtcc.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019, Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silabs Gecko RTCC (Real-Time Counter)
+
+compatible: "silabs,gecko-rtcc"
+
+include: rtc.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/rtc/st,stm32-rtc.yaml b/dts/bindings/rtc/st,stm32-rtc.yaml
new file mode 100644
index 0000000000..8498474f48
--- /dev/null
+++ b/dts/bindings/rtc/st,stm32-rtc.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Workaround GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 RTC
+
+compatible: "st,stm32-rtc"
+
+include: rtc.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml b/dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml
new file mode 100644
index 0000000000..f98544b4e4
--- /dev/null
+++ b/dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2019, Texas Instruments Incorporated
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: TI SimpleLink CC13xx/CC26xx RTC
+
+compatible: "ti,cc13xx-cc26xx-rtc"
+
+include: rtc.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml b/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml
new file mode 100644
index 0000000000..41c248d791
--- /dev/null
+++ b/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml
@@ -0,0 +1,71 @@
+description: Xilinx AXI Timer IP node
+
+compatible: "xlnx,xps-timer-1.00.a"
+
+include: rtc.yaml
+
+# Property names correspond to those used by Xilinx PetaLinux:
+# https://github.com/Xilinx/meta-xilinx
+
+properties:
+    clock-frequency:
+      required: true
+
+    xlnx,count-width:
+      type: int
+      required: true
+      enum:
+        - 8
+        - 16
+        - 32
+      description: |
+        Individual timer/counter width in bits.
+
+    xlnx,gen0-assert:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+      description: |
+        Active state of the generateout0 signal (0 for active-low, 1 for
+        active-high).
+
+    xlnx,gen1-assert:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+      description: |
+        Active state of the generateout1 signal (0 for active-low, 1 for
+        active-high).
+
+    xlnx,one-timer-only:
+      type: int
+      required: true
+      enum:
+        - 0
+        - 1
+      description: |
+        0 if both Timer 1 and Timer 2 are enabled, 1 if only Timer 1 is enabled.
+
+    xlnx,trig0-assert:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+      description: |
+        Active state of the capturetrig0 signal (0 for active-low, 1 for
+        active-high).
+
+    xlnx,trig1-assert:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+      description: |
+        Active state of the capturetrig1 signal (0 for active-low, 1 for
+        active-high).
diff --git a/dts/bindings/sensor/adi,adt7420.yaml b/dts/bindings/sensor/adi,adt7420.yaml
new file mode 100644
index 0000000000..0cd6293e0d
--- /dev/null
+++ b/dts/bindings/sensor/adi,adt7420.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2018 Analog Devices Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADT7420 16-Bit digital I2C temperature sensor
+
+compatible: "adi,adt7420"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT signal defaults to active low open drain, so requires a
+        pull-up on the board or in the flags cell of this entry.
diff --git a/dts/bindings/sensor/adi,adxl345.yaml b/dts/bindings/sensor/adi,adxl345.yaml
new file mode 100644
index 0000000000..63cb7efe48
--- /dev/null
+++ b/dts/bindings/sensor/adi,adxl345.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADXL345 3-axis I2C accelerometer
+
+compatible: "adi,adxl345"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/adi,adxl362.yaml b/dts/bindings/sensor/adi,adxl362.yaml
new file mode 100644
index 0000000000..59812e9dcb
--- /dev/null
+++ b/dts/bindings/sensor/adi,adxl362.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADXL362 3-axis SPI accelerometer
+
+compatible: "adi,adxl362"
+
+include: spi-device.yaml
+
+properties:
+    int1-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT1 signal defaults to active high as produced by the
+        sensor.  The property value should ensure the flags properly
+        describe the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/adi,adxl372-i2c.yaml b/dts/bindings/sensor/adi,adxl372-i2c.yaml
new file mode 100644
index 0000000000..f09cb41e9e
--- /dev/null
+++ b/dts/bindings/sensor/adi,adxl372-i2c.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2018 Analog Devices Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADXL372 3-axis high-g I2C/SPI accelerometer
+
+compatible: "adi,adxl372"
+
+include: i2c-device.yaml
+
+properties:
+    int1-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT1 signal defaults to active high as produced by the
+        sensor.  The property value should ensure the flags properly
+        describe the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/adi,adxl372-spi.yaml b/dts/bindings/sensor/adi,adxl372-spi.yaml
new file mode 100644
index 0000000000..008bb8b4b3
--- /dev/null
+++ b/dts/bindings/sensor/adi,adxl372-spi.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018 Analog Devices Inc.
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADXL372 3-axis high-g accelerometer, accessed through SPI bus
+
+compatible: "adi,adxl372"
+
+include: spi-device.yaml
+
+properties:
+    int1-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT1 signal defaults to active high as produced by the
+        sensor.  The property value should ensure the flags properly
+        describe the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/ams,ccs811.yaml b/dts/bindings/sensor/ams,ccs811.yaml
new file mode 100644
index 0000000000..4b5aa5d458
--- /dev/null
+++ b/dts/bindings/sensor/ams,ccs811.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: CCS811 digital air quality sensor
+
+compatible: "ams,ccs811"
+
+include: i2c-device.yaml
+
+properties:
+    wake-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The WAKEn pin is asserted to communicate with the sensor.  The
+        sensor receives this as an active-low signal.
+
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The RESETn pin is asserted to disable the sensor causing a hard
+        reset.  The sensor receives this as an active-low signal.
+
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INTn pin signals that a new reading is available.  The
+        sensor generates an active-low level signal which remains
+        asserted until the data is read.
diff --git a/dts/bindings/sensor/ams,ens210.yaml b/dts/bindings/sensor/ams,ens210.yaml
new file mode 100644
index 0000000000..cad33bc924
--- /dev/null
+++ b/dts/bindings/sensor/ams,ens210.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2018, Alexander Wachter
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    AMS (Austria Mikro Systeme) ens210 Relative Humidity and Temperature Sensor
+
+compatible: "ams,ens210"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/ams,iaqcore.yaml b/dts/bindings/sensor/ams,iaqcore.yaml
new file mode 100644
index 0000000000..0756a3e715
--- /dev/null
+++ b/dts/bindings/sensor/ams,iaqcore.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, Alexander Wachter
+# SPDX-License-Identifier: Apache-2.0
+
+description: iAQ-core indoor air quality sensor
+
+compatible: "ams,iaqcore"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/aosong,dht.yaml b/dts/bindings/sensor/aosong,dht.yaml
new file mode 100644
index 0000000000..916fb70c1e
--- /dev/null
+++ b/dts/bindings/sensor/aosong,dht.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Aosong DHT (Digital-output Humidity and Temperature Sensor)
+
+    The Aosong DHT family of sensors provide temperature and humidity
+    measurements through a bidirectional serial digital signal.  The
+    DHT11 uses a polymer humidity capacitor with NTC thermistor; the
+    DHT22 replaces the thermistor with a DS18B20 1-wire thermometer.
+
+    The DHT22 is also known as an AM2303.
+
+compatible: "aosong,dht"
+
+include: base.yaml
+
+properties:
+  dio-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      Pin on which sensor communication will be performed.
+
+      Control and data are encoded by the duration of active low
+      signals.  A pull up may be appropriate.
+
+  dht22:
+    type: boolean
+    description: |
+      Set to identify sensor as a DHT22/AM2303.  Leave unset to identify
+      sensor as a DHT11.
diff --git a/dts/bindings/sensor/asahi-kasei,ak8975.yaml b/dts/bindings/sensor/asahi-kasei,ak8975.yaml
new file mode 100644
index 0000000000..c7d283f446
--- /dev/null
+++ b/dts/bindings/sensor/asahi-kasei,ak8975.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Asahi Kasei AK8975 Magnetometer. See datasheet at
+    https://www.akm.com/akm/en/file/datasheet/AK8975.pdf
+
+compatible: "asahi-kasei,ak8975"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/atmel,sam-tc-qdec.yaml b/dts/bindings/sensor/atmel,sam-tc-qdec.yaml
new file mode 100644
index 0000000000..2884f0b6ae
--- /dev/null
+++ b/dts/bindings/sensor/atmel,sam-tc-qdec.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Timer Counter (TC) QDEC node
+
+compatible: "atmel,sam-tc-qdec"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    peripheral-id:
+      type: array
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: false
+      description: |
+        PIO pin configuration for Timer Counter signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        In Quadrature Decoder mode TIOA0 & TIOB0 signals are expected
+
+        For example the TC0 on SAME7x would be
+           pinctrl-0 = <&pa0b_tc0_tioa0 &pa1b_tc0_tiob0>;
diff --git a/dts/bindings/sensor/avago,apds9960.yaml b/dts/bindings/sensor/avago,apds9960.yaml
new file mode 100644
index 0000000000..fd25465758
--- /dev/null
+++ b/dts/bindings/sensor/avago,apds9960.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: APDS9960 digital proximity, ambient light, RGB, and gesture sensor
+
+compatible: "avago,apds9960"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: true
+      description: Interrupt pin.
+
+        The interrupt pin of APDS9960 is open-drain, active low.
+        If connected directly the MCU pin should be configured
+        as pull-up, active low.
diff --git a/dts/bindings/sensor/bosch,bma280.yaml b/dts/bindings/sensor/bosch,bma280.yaml
new file mode 100644
index 0000000000..4f8b5727db
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bma280.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Bosch BMA280 triaxial acceleration sensor.  See more info at:
+  https://www.bosch-sensortec.com/products/motion-sensors/accelerometers/bma280.html
+
+compatible: "bosch,bma280"
+
+include: i2c-device.yaml
+
+properties:
+  int1-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      Identifies pin for the INT1 signal on the sensor.  The sensor
+      INT2 signal is not supported by the driver.
+
+  is-bmc150:
+    type: boolean
+    required: false
+    description: |
+      Specifies that the driver should adapt to the accelerometer
+      capability provided by the BMC150 6-axis eCompass.  This affects
+      the chip ID and the resolution of the measurements.
diff --git a/dts/bindings/sensor/bosch,bmc150_magn.yaml b/dts/bindings/sensor/bosch,bmc150_magn.yaml
new file mode 100644
index 0000000000..59759137f1
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bmc150_magn.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Bosch BMC150 Magnetometer.  See more info at:
+    https://www.bosch-sensortec.com/bst/products/all_products/bmc150
+
+compatible: "bosch,bmc150_magn"
+
+include: i2c-device.yaml
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/sensor/bosch,bme280-i2c.yaml b/dts/bindings/sensor/bosch,bme280-i2c.yaml
new file mode 100644
index 0000000000..c259b841bb
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bme280-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: BME280 integrated environmental sensor
+
+compatible: "bosch,bme280"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/bosch,bme280-spi.yaml b/dts/bindings/sensor/bosch,bme280-spi.yaml
new file mode 100644
index 0000000000..6249c7b327
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bme280-spi.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: BME280 integrated environmental sensor
+
+compatible: "bosch,bme280"
+
+include: spi-device.yaml
diff --git a/dts/bindings/sensor/bosch,bme680-i2c.yaml b/dts/bindings/sensor/bosch,bme680-i2c.yaml
new file mode 100644
index 0000000000..23eb1846e4
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bme680-i2c.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2018, Bosch Sensortec GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The BME680 is an integrated environmental sensor that measures
+    temperature, pressure, humidity and air quality
+
+compatible: "bosch,bme680"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/bosch,bmg160.yaml b/dts/bindings/sensor/bosch,bmg160.yaml
new file mode 100644
index 0000000000..909f286377
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bmg160.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Bosch BMG160 gyroscope.  See more info at:
+    https://www.bosch-sensortec.com/bst/products/all_products/bmg160
+
+compatible: "bosch,bmg160"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/sensor/bosch,bmi160.yaml b/dts/bindings/sensor/bosch,bmi160.yaml
new file mode 100644
index 0000000000..d409f83e22
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bmi160.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: BMI160 inertial measurement unit
+
+compatible: "bosch,bmi160"
+
+include: spi-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        This property specifies the connection for INT1, because the
+        Zephyr driver maps all interrupts to INT1.  The signal defaults
+        to output low when produced by the sensor.
diff --git a/dts/bindings/sensor/bosch,bmi270-i2c.yaml b/dts/bindings/sensor/bosch,bmi270-i2c.yaml
new file mode 100644
index 0000000000..2e2ee307c0
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bmi270-i2c.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2021, Bosch Sensortec GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The BMI270 is an inertial measurment unit. See more info at:
+    https://www.bosch-sensortec.com/products/motion-sensors/imus/bmi270.html
+
+compatible: "bosch,bmi270"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/bosch,bmm150.yaml b/dts/bindings/sensor/bosch,bmm150.yaml
new file mode 100644
index 0000000000..937d8c59af
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bmm150.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Bosch BMM150 Geomagnetic sensor.  See more info at:
+    https://www.bosch-sensortec.com/bst/products/all_products/bmm150
+
+compatible: "bosch,bmm150"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/bosch,bmp388-i2c.yaml b/dts/bindings/sensor/bosch,bmp388-i2c.yaml
new file mode 100644
index 0000000000..8499e3cd25
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bmp388-i2c.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2020 Facebook, Inc. and its affiliates
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Bosch BMP388 pressure sensor accessed through I2C bus
+
+compatible: "bosch,bmp388"
+
+include: [i2c-device.yaml, "bosch,bmp388.yaml"]
diff --git a/dts/bindings/sensor/bosch,bmp388-spi.yaml b/dts/bindings/sensor/bosch,bmp388-spi.yaml
new file mode 100644
index 0000000000..90e29acc67
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bmp388-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2020 Facebook, Inc. and its affiliates
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Bosch BMP388 pressure sensor accessed through SPI bus
+
+compatible: "bosch,bmp388"
+
+include: [spi-device.yaml, "bosch,bmp388.yaml"]
diff --git a/dts/bindings/sensor/bosch,bmp388.yaml b/dts/bindings/sensor/bosch,bmp388.yaml
new file mode 100644
index 0000000000..618fb563f9
--- /dev/null
+++ b/dts/bindings/sensor/bosch,bmp388.yaml
@@ -0,0 +1,109 @@
+# Copyright (c) 2020 Facebook, Inc. and its affiliates
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for BMP388
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+
+    odr:
+      type: string
+      required: false
+      description: |
+        Default output data rate in Hz. Only the following values are allowed:
+          200   - 200     - 5ms  (default; chip reset value)
+          100   - 100     - 10ms
+          50    - 50      - 20ms
+          25    - 25      - 40ms
+          12.5  - 25/2    - 80ms
+          6.25  - 25/4    - 160ms
+          3.125 - 25/8    - 320ms
+          1.563 - 25/16   - 640ms
+          .781  - 25/32   - 1.28s
+          .391  - 25/64   - 2.56s
+          .195  - 25/128  - 5.12s
+          .098  - 25/256  - 10.24s
+          .049  - 25/512  - 20.48s
+          .024  - 25/1024 - 40.96s
+          .012  - 25/2048 - 81.92s
+          .006  - 25/4096 - 163.84s
+          .003  - 25/8192 - 327.68s
+      default: "200"
+      enum:
+        - "200"
+        - "100"
+        - "50"
+        - "25"
+        - "12.5"
+        - "6.25"
+        - "3.125"
+        - "1.563"
+        - ".781"
+        - ".391"
+        - ".195"
+        - ".098"
+        - ".049"
+        - ".024"
+        - ".012"
+        - ".006"
+        - ".003"
+
+    osr-press:
+      type: int
+      required: false
+      description: |
+        Default pressure oversampling rate. Only the following values are
+        allowed:
+          1 sample, 16-bit, 2.64 Pa
+          2 samples, 17-bit, 1.32 Pa
+          4 samples, 18-bit, 0.66 Pa (default; chip reset value)
+          8 samples, 19-bit, 0.33 Pa
+          16 samples, 20-bit, 0.17 Pa
+          32 Samples, 21-bit, 0.085 Pa
+      default: 4
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+
+    osr-temp:
+      type: int
+      required: false
+      description: |
+        Default temperature oversampling rate. Only the following values are
+        allowed:
+          1 sample, 16-bit, .0050 C (default; chip reset value)
+          2 samples, 17-bit, .0025 C
+          4 samples, 18-bit, .0012 C
+          8 samples, 19-bit, .0006 C
+          16 samples, 20-bit, .0003 C
+          32 Samples, 21-bit, .00015 C
+      default: 1
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+
+    iir-filter:
+      type: int
+      required: false
+      description: |
+        Default IIR filter coefficient. The default 0 is the chip reset value.
+      default: 0
+      enum:
+        - 0
+        - 1
+        - 3
+        - 7
+        - 15
+        - 31
+        - 63
+        - 127
diff --git a/dts/bindings/sensor/honeywell,hmc5883l.yaml b/dts/bindings/sensor/honeywell,hmc5883l.yaml
new file mode 100644
index 0000000000..68c1fa4e1f
--- /dev/null
+++ b/dts/bindings/sensor/honeywell,hmc5883l.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Honeywell HMC5883L 3-axis magnetometer sensor
+
+compatible: "honeywell,hmc5883l"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin is active low, with an internal pullup in the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/honeywell,mpr.yaml b/dts/bindings/sensor/honeywell,mpr.yaml
new file mode 100644
index 0000000000..c618ad2263
--- /dev/null
+++ b/dts/bindings/sensor/honeywell,mpr.yaml
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Honeywell Digital Pressure Sensor. For details see here:
+    https://sensing.honeywell.com/micropressure-mpr-series
+
+compatible: "honeywell,mpr"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/honeywell,sm351lt.yaml b/dts/bindings/sensor/honeywell,sm351lt.yaml
new file mode 100644
index 0000000000..56143b77b7
--- /dev/null
+++ b/dts/bindings/sensor/honeywell,sm351lt.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020, Laird Connectivity
+# SPDX-License-Identifier: Apache-2.0
+
+description: SM351LT magnetoresistive sensor
+
+compatible: "honeywell,sm351lt"
+
+include: base.yaml
+
+properties:
+   gpios:
+      type: phandle-array
+      required: true
+      description: GPIO connected to the sensor
+   label:
+      required: true
+      type: string
+      description: Driver label
diff --git a/dts/bindings/sensor/hoperf,hp206c.yaml b/dts/bindings/sensor/hoperf,hp206c.yaml
new file mode 100644
index 0000000000..ef19ea51aa
--- /dev/null
+++ b/dts/bindings/sensor/hoperf,hp206c.yaml
@@ -0,0 +1,11 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    HopeRF Electronic HP206C precision barometer and altimeter.
+    See more info at:
+    https://www.hoperf.com/sensor/pressure_sensor/HP206C.html
+
+compatible: "hoperf,hp206c"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/hoperf,th02.yaml b/dts/bindings/sensor/hoperf,th02.yaml
new file mode 100644
index 0000000000..12f092fb3e
--- /dev/null
+++ b/dts/bindings/sensor/hoperf,th02.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    TH02 Temperature and Humidity sensor. See datasheet at
+    http://www.datasheetspdf.com/mobile/748107/TH02.html
+
+compatible: "hoperf,th02"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/infineon,dps310.yaml b/dts/bindings/sensor/infineon,dps310.yaml
new file mode 100644
index 0000000000..96cb2c5d73
--- /dev/null
+++ b/dts/bindings/sensor/infineon,dps310.yaml
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2019 Infineon Technologies AG
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Infineon DPS310 temperature and pressure sensor
+
+include: i2c-device.yaml
+
+compatible: "infineon,dps310"
diff --git a/dts/bindings/sensor/invensense,icm42605.yaml b/dts/bindings/sensor/invensense,icm42605.yaml
new file mode 100644
index 0000000000..8d55510e6a
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm42605.yaml
@@ -0,0 +1,89 @@
+# Copyright (c) 2020 TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICM-42605 motion tracking device
+
+# ICM-42605 is SPI.
+compatible: "invensense,icm42605"
+
+include: spi-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        The INT signal default configuration is active-high.  The
+        property value should ensure the flags properly describe the
+        signal that is presented to the driver.
+
+    accel-hz:
+      type: int
+      required: false
+      default: 12
+      description: |
+        Default frequency of accelerometer. (Unit - Hz)
+        Maps to ACCEL_ODR field in ACCEL_CONFIG0 setting
+      enum:
+        - 1
+        - 3
+        - 6
+        - 12
+        - 25
+        - 50
+        - 100
+        - 200
+        - 500
+        - 1000
+        - 2000
+        - 4000
+        - 8000
+
+    gyro-hz:
+      type: int
+      required: false
+      default: 12
+      description: |
+        Default frequency of gyroscope. (Unit - Hz)
+        Maps to GYRO_ODR field in GYRO_CONFIG0 setting
+      enum:
+        - 12
+        - 25
+        - 50
+        - 100
+        - 200
+        - 500
+        - 1000
+        - 2000
+        - 4000
+        - 8000
+
+    accel-fs:
+      type: int
+      required: false
+      default: 16
+      description: |
+        Default full scale of accelerometer. (Unit - g)
+        Maps to ACCEL_FS_SEL field in ACCEL_CONFIG0 setting
+      enum:
+        - 16
+        - 8
+        - 4
+        - 2
+
+    gyro-fs:
+      type: int
+      required: false
+      default: 2000
+      description: |
+        Default full scale of gyroscope. (Unit - DPS)
+        Maps to GYRO_FS_SEL field in GYRO_CONFIG0 setting
+      enum:
+        - 2000
+        - 1000
+        - 500
+        - 250
+        - 125
+        - 62.5
+        - 31.25
+        - 15.625
diff --git a/dts/bindings/sensor/invensense,mpu6050.yaml b/dts/bindings/sensor/invensense,mpu6050.yaml
new file mode 100644
index 0000000000..9f87d3a0c0
--- /dev/null
+++ b/dts/bindings/sensor/invensense,mpu6050.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: MPU-6000 motion tracking device
+
+# MPU-6000 is SPI or I2C.  MPU-6050 is I2C-only.  Driver does not
+# support SPI so stick with I2C variant.
+compatible: "invensense,mpu6050"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT signal default configuration is active-high.  The
+        property value should ensure the flags properly describe the
+        signal that is presented to the driver.
diff --git a/dts/bindings/sensor/invensense,mpu9150.yaml b/dts/bindings/sensor/invensense,mpu9150.yaml
new file mode 100644
index 0000000000..df287000d0
--- /dev/null
+++ b/dts/bindings/sensor/invensense,mpu9150.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    InvenSense MPU-9150 Nine-Axis (Gyro + Accelerometer + Compass). See more
+    info at https://www.invensense.com/products/motion-tracking/9-axis/mpu-9150/
+
+compatible: "invensense,mpu9150"
+
+include: i2c-device.yaml
+
+child-binding:
+    description: Embedded AK8975 Magnetometer
+    compatible: "asahi-kasei,ak8975"
+    properties:
+       "#address-cells":
+           type: int
+           required: true
+           const: 1
+       "#size-cells":
+           type: int
+           required: true
+           const: 0
diff --git a/dts/bindings/sensor/isil,isl29035.yaml b/dts/bindings/sensor/isil,isl29035.yaml
new file mode 100644
index 0000000000..511d2c8281
--- /dev/null
+++ b/dts/bindings/sensor/isil,isl29035.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Intersil ISL29035 Light Sensor. See datasheet at
+    https://www.renesas.com/us/en/www/doc/datasheet/isl29035.pdf
+
+compatible: "isil,isl29035"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT pin defaults to active low when produced by the sensor.
+        The property value should ensure the flags properly describe the
+        signal that is presented to the driver.
diff --git a/dts/bindings/sensor/lm75.yaml b/dts/bindings/sensor/lm75.yaml
new file mode 100644
index 0000000000..09b5b3491d
--- /dev/null
+++ b/dts/bindings/sensor/lm75.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Leica Geosystems AG
+# SPDX-License-Identifier: Apache-2.0
+
+description: LM75 Digital Temperature Sensor with 2-Wire Interface.
+
+compatible: "lm75"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/lm77.yaml b/dts/bindings/sensor/lm77.yaml
new file mode 100644
index 0000000000..b6ec88ad75
--- /dev/null
+++ b/dts/bindings/sensor/lm77.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2021 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  LM77 digital temperature sensor
+
+compatible: "lm77"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Identifies the INT signal, which is active-low open drain by default
+        when produced by the sensor.
+
+    int-inverted:
+      type: boolean
+      description: |
+        When present, the polarity on the INT signal is inverted (active-high).
+
+    tcrita-inverted:
+      type: boolean
+      description: |
+        When present, the polarity on the T_CRIT_A signal is inverted
+        (active-high).
+
+    enable-fault-queue:
+      type: boolean
+      description: |
+        When present, the fault queue is enabled. The fault queue allows up to 4
+        faults to prevent false INT/T_CRIT_A tripping when the LM77 is used in
+        noisy environments.
diff --git a/dts/bindings/sensor/maxim,max17055.yaml b/dts/bindings/sensor/maxim,max17055.yaml
new file mode 100644
index 0000000000..fc4103094c
--- /dev/null
+++ b/dts/bindings/sensor/maxim,max17055.yaml
@@ -0,0 +1,48 @@
+#
+# Copyright 2020 Google LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Maxim MAX17055 Fuel Gauge
+
+compatible: "maxim,max17055"
+
+include: i2c-device.yaml
+
+properties:
+    design-capacity:
+      type: int
+      required: true
+      description: The design capacity (aka label capacity) of the cell in mAh
+
+    design-voltage:
+      type: int
+      required: true
+      description: Battery Design Voltage in mV (3300 to 4400)
+
+    desired-voltage:
+      type: int
+      required: true
+      description: Battery Desired Voltage in mV (3300 to 4400)
+
+    desired-charging-current:
+      type: int
+      required: true
+      description: Battery Design Charging Current in mA (e.g. 2000)
+
+    i-chg-term:
+      type: int
+      required: true
+      description: The charge termination current in mA
+
+    rsense-mohms:
+      type: int
+      required: true
+      description: |
+        Value of Rsense resistor in milliohms (e.g. 5). It cannot be 0.
+
+    v-empty:
+      type: int
+      required: true
+      description: The empty voltage of the cell in mV
diff --git a/dts/bindings/sensor/maxim,max17262.yaml b/dts/bindings/sensor/maxim,max17262.yaml
new file mode 100644
index 0000000000..ddfd3e7d3d
--- /dev/null
+++ b/dts/bindings/sensor/maxim,max17262.yaml
@@ -0,0 +1,47 @@
+#
+# Copyright 2020 Matija Tudan
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Maxim MAX17262 Fuel Gauge
+
+compatible: "maxim,max17262"
+
+include: i2c-device.yaml
+
+properties:
+    design-voltage:
+      type: int
+      required: true
+      description: Battery Design Voltage in mV (3300 to 4400)
+
+    desired-voltage:
+      type: int
+      required: true
+      description: Battery Desired Voltage in mV (3300 to 4400)
+
+    desired-charging-current:
+      type: int
+      required: true
+      description: Battery Design Charging Current in mA (e.g. 2000)
+
+    design-cap:
+      type: int
+      required: true
+      description: Battery Capacity in mAh (default 3000)
+
+    empty-voltage:
+      type: int
+      required: true
+      description: Empty voltage target during load in mV (default 3300)
+
+    recovery-voltage:
+      type: int
+      required: true
+      description: The voltage level for clearing empty detection in mV (default 3880)
+
+    charge-voltage:
+      type: int
+      required: true
+      description: Charge voltage in mV
diff --git a/dts/bindings/sensor/maxim,max30101.yaml b/dts/bindings/sensor/maxim,max30101.yaml
new file mode 100644
index 0000000000..32e42999f1
--- /dev/null
+++ b/dts/bindings/sensor/maxim,max30101.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: MAX30101 heart rate sensor
+
+compatible: "maxim,max30101"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/maxim,max44009.yaml b/dts/bindings/sensor/maxim,max44009.yaml
new file mode 100644
index 0000000000..367768cbad
--- /dev/null
+++ b/dts/bindings/sensor/maxim,max44009.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Maxim MAX44009 Ambient Light Sensor. See datasheet at
+    https://datasheets.maximintegrated.com/en/ds/MAX44009.pdf
+
+compatible: "maxim,max44009"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/sensor/maxim,max6675.yaml b/dts/bindings/sensor/maxim,max6675.yaml
new file mode 100644
index 0000000000..b7b5d6113a
--- /dev/null
+++ b/dts/bindings/sensor/maxim,max6675.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: MAX6675 K-thermocouple to digital converter
+
+compatible: "maxim,max6675"
+
+include: spi-device.yaml
diff --git a/dts/bindings/sensor/meas,ms5607-i2c.yaml b/dts/bindings/sensor/meas,ms5607-i2c.yaml
new file mode 100644
index 0000000000..8c8cb45066
--- /dev/null
+++ b/dts/bindings/sensor/meas,ms5607-i2c.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2021, Aurelien Jarno <aurel32@aurel32.net>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    TE Connectivity MS5607 digital pressure and temperature sensor.
+    The Datasheet is at https://www.te.com/usa-en/product-CAT-BLPS0035.html
+
+compatible: "meas,ms5607"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/meas,ms5607-spi.yaml b/dts/bindings/sensor/meas,ms5607-spi.yaml
new file mode 100644
index 0000000000..2908cc15d5
--- /dev/null
+++ b/dts/bindings/sensor/meas,ms5607-spi.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019, Thomas Schmid <tom@lfence.de>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    TE Connectivity MS5607 digital pressure and temperature sensor.
+    The Datasheet is at https://www.te.com/usa-en/product-CAT-BLPS0035.html
+
+compatible: "meas,ms5607"
+
+include: spi-device.yaml
diff --git a/dts/bindings/sensor/meas,ms5837.yaml b/dts/bindings/sensor/meas,ms5837.yaml
new file mode 100644
index 0000000000..47aa51bd49
--- /dev/null
+++ b/dts/bindings/sensor/meas,ms5837.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, Jan Van Winkel <jan.van_winkel@dxplore.eu>
+# SPDX-License-Identifier: Apache-2.0
+
+description: TE Connectivity MS5837 digital pressure sensor
+
+compatible: "meas,ms5837"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/microchip,mcp9808.yaml b/dts/bindings/sensor/microchip,mcp9808.yaml
new file mode 100644
index 0000000000..66848db28c
--- /dev/null
+++ b/dts/bindings/sensor/microchip,mcp9808.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Microchip MCP9808 Digital Temperature Sensor. See
+    http://ww1.microchip.com/downloads/en/DeviceDoc/25095A.pdf.
+
+compatible: "microchip,mcp9808"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The alert pin defaults to active low when produced by the
+        sensor, and is open-drain.  A pull-up may be appropriate.  The
+        property value should ensure the flags properly describe the
+        signal that is presented to the driver.
+
+    resolution:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Sensor resolution. Default is 0.0625C (0b11),
+        which is the power-up default.
+      enum:
+        - 0 # 0.5C
+        - 1 # 0.25C
+        - 2 # 0.125C
+        - 3 # 0.0625C
diff --git a/dts/bindings/sensor/nordic,nrf-qdec.yaml b/dts/bindings/sensor/nordic,nrf-qdec.yaml
new file mode 100644
index 0000000000..e589751606
--- /dev/null
+++ b/dts/bindings/sensor/nordic,nrf-qdec.yaml
@@ -0,0 +1,65 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF quadrature decoder (QDEC) node
+
+compatible: "nordic,nrf-qdec"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    a-pin:
+      type: int
+      required: true
+      description: |
+        The A pin to use.
+
+        For pins P0.0 through P0.31, use the pin number. For example,
+        to use P0.16 for the A pin, set:
+
+            a-pin = <16>;
+
+        For pins P1.0 through P1.31, add 32 to the pin number. For
+        example, to use P1.2 for the A pin, set:
+
+            a-pin = <34>;  /* 32 + 2 */
+
+    b-pin:
+      type: int
+      required: true
+      description: |
+        The B pin to use. The pin numbering scheme is the same as
+        the a-pin property's.
+
+    led-pin:
+      type: int
+      required: false
+      description: |
+        The LED pin to use for a light based QDEC device. The pin
+        numbering scheme is the same as the a-pin property's.
+
+    enable-pin:
+      type: int
+      required: false
+      description: |
+        The enable pin to use, to enable a connected QDEC device. The
+        pin numbering scheme is the same as the a-pin property's.
+
+    led-pre:
+      type: int
+      description: Time LED is enabled prior to sampling event (in us)
+      required: true
+
+    steps:
+      type: int
+      description: Number of steps on the rotating wheel
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/sensor/nordic,nrf-temp.yaml b/dts/bindings/sensor/nordic,nrf-temp.yaml
new file mode 100644
index 0000000000..0497cd9f6b
--- /dev/null
+++ b/dts/bindings/sensor/nordic,nrf-temp.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF family TEMP node
+
+compatible: "nordic,nrf-temp"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/sensor/nxp,fxas21002.yaml b/dts/bindings/sensor/nxp,fxas21002.yaml
new file mode 100644
index 0000000000..fe048b812a
--- /dev/null
+++ b/dts/bindings/sensor/nxp,fxas21002.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: FXAS21002 3-axis gyroscope sensor
+
+compatible: "nxp,fxas21002"
+
+include: i2c-device.yaml
+
+properties:
+    int1-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        INT1 pin
+        This pin defaults to active low when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    int2-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        INT2 pin
+        This pin defaults to active low when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/nxp,fxos8700.yaml b/dts/bindings/sensor/nxp,fxos8700.yaml
new file mode 100644
index 0000000000..acd475b6c2
--- /dev/null
+++ b/dts/bindings/sensor/nxp,fxos8700.yaml
@@ -0,0 +1,159 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: FXOS8700 6-axis accelerometer/magnetometer sensor
+
+compatible: "nxp,fxos8700"
+
+include: i2c-device.yaml
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        RST pin
+        This pin defaults to active high when consumed by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    int1-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        INT1 pin
+        This pin defaults to active low when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    int2-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        INT2 pin
+        This pin defaults to active low when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    range:
+      type: int
+      required: false
+      default: 8
+      description: Range in g
+      enum:
+        - 8 # 8g (0.976 mg/LSB)
+        - 4 # 4g (0.488 mg/LSB)
+        - 2 # 2g (0.244 mg/LSB)
+
+    power-mode:
+      type: int
+      required: false
+      default: 0
+      description: Power mode
+      enum:
+        - 0 # Normal
+        - 1 # Low noise, low power
+        - 2 # High resolution
+        - 3 # Low power
+
+    pulse-cfg:
+      type: int
+      required: false
+      default: 0x3f
+      description: Pulse configuration register
+
+    pulse-thsx:
+      type: int
+      required: false
+      default: 0x20
+      description: |
+        Pulse X-axis threshold
+        Threshold to start the pulse-event detection procedure on the X-axis.
+        Threshold values for each axis are unsigned 7-bit numbers with a fixed
+        resolution of 0.063 g/LSB, corresponding to an 8g acceleration
+        full-scale range.
+
+    pulse-thsy:
+      type: int
+      required: false
+      default: 0x20
+      description: |
+        Pulse Y-axis threshold
+        Threshold to start the pulse-event detection procedure on the Y-axis.
+        Threshold values for each axis are unsigned 7-bit numbers with a fixed
+        resolution of 0.063 g/LSB, corresponding to an 8g acceleration
+        full-scale range.
+
+    pulse-thsz:
+      type: int
+      required: false
+      default: 0x40
+      description: |
+        Pulse Z-axis threshold
+        Threshold to start the pulse-event detection procedure on the Z-axis.
+        Threshold values for each axis are unsigned 7-bit numbers with a fixed
+        resolution of 0.063 g/LSB, corresponding to an 8g acceleration
+        full-scale range.
+
+    pulse-tmlt:
+      type: int
+      required: false
+      default: 0x18
+      description: |
+        Pulse time limit
+        The maximum time interval that can elapse between the start of the
+        acceleration on the selected channel exceeding the specified threshold
+        and the end when the channel acceleration goes back below the specified
+        threshold. The resolution depends upon the sample rate (ODR) and the
+        high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For
+        ODR=800 Hz and pls_hpf_en=0, the resolution is 0.625 ms/LSB.
+
+    pulse-ltcy:
+      type: int
+      required: false
+      default: 0x28
+      description: |
+        Pulse latency
+        The time interval that starts after the first pulse detection where the
+        pulse-detection function ignores the start of a new pulse. The
+        resolution depends upon the sample rate (ODR) and the high-pass filter
+        configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and
+        pls_hpf_en=0, the resolution is 1.25 ms/LSB.
+
+    pulse-wind:
+      type: int
+      required: false
+      default: 0x3c
+      description: |
+        Pulse window
+        The maximum interval of time that can elapse after the end of the
+        latency interval in which the start of the second pulse event must be
+        detected provided the device has been configured for double pulse
+        detection. The detected second pulse width must be shorter than the
+        time limit constraint specified by the PULSE_TMLT register, but the end
+        of the double pulse need not finish within the time specified by the
+        PULSE_WIND register. The resolution depends upon the sample rate (ODR)
+        and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]).
+        For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB.
+
+    mag-vecm-cfg:
+      type: int
+      required: false
+      default: 0x4e
+      description: Magnetic vector-magnitude configuration register
+
+    mag-vecm-ths-msb:
+      type: int
+      required: false
+      default: 0x00
+      description: |
+        Magnetic vector-magnitude threshold most significant byte.
+        Resolution is 0.1 uT/LSB.
+
+    mag-vecm-ths-lsb:
+      type: int
+      required: false
+      default: 0x5a
+      description: |
+        Magnetic vector-magnitude threshold least significant byte.
+        Resolution is 0.1 uT/LSB.
diff --git a/dts/bindings/sensor/nxp,kinetis-acmp.yaml b/dts/bindings/sensor/nxp,kinetis-acmp.yaml
new file mode 100644
index 0000000000..5789d858ba
--- /dev/null
+++ b/dts/bindings/sensor/nxp,kinetis-acmp.yaml
@@ -0,0 +1,68 @@
+# Copyright (c) 2020 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis Analog Comparator (ACMP)
+
+compatible: "nxp,kinetis-acmp"
+
+include: base.yaml
+
+properties:
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    nxp,enable-output-pin:
+      type: boolean
+      required: false
+      description: |
+        Make the comparator output (CMP0) available on a packaged pin.
+
+    nxp,use-unfiltered-output:
+      type: boolean
+      required: false
+      description: |
+        Use the unfiltered comparator output for CMP0.
+
+    nxp,high-speed-mode:
+      type: boolean
+      required: false
+      description: |
+        Enable high speed comparison mode.
+
+    nxp,enable-sample:
+      type: boolean
+      required: false
+      description: |
+        Enable external sample signal as clock input.
+
+    nxp,filter-count:
+      type: int
+      required: false
+      description: |
+        Filter sample count (0 to 7).
+
+    nxp,filter-period:
+      type: int
+      required: false
+      description: |
+        Filter sample period in bus clock cycles (0 to 255).
+
+    nxp,window-mode:
+      type: boolean
+      required: false
+      description: |
+        Enable windowing mode.
+
+    "#io-channel-cells":
+      type: int
+      const: 2
+
+io-channel-cells:
+    - positive
+    - negative
diff --git a/dts/bindings/sensor/nxp,kinetis-temperature.yaml b/dts/bindings/sensor/nxp,kinetis-temperature.yaml
new file mode 100644
index 0000000000..f272d0ed32
--- /dev/null
+++ b/dts/bindings/sensor/nxp,kinetis-temperature.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2020 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis temperature sensor
+
+compatible: "nxp,kinetis-temperature"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    io-channels:
+      required: true
+      description: ADC channels for temperature sensor and bandgap voltage
+
+    io-channel-names:
+      required: true
+      description: name of each ADC channel (SENSOR or BANDGAP)
+
+    bandgap-voltage:
+      type: int
+      required: true
+      description: Bandgap voltage in microvolts
+
+    vtemp25:
+      type: int
+      required: true
+      description: |
+          Temperature sensor voltage at 25 degrees Celcius in microvolts
+
+    sensor-slope-cold:
+      type: int
+      required: true
+      description: |
+          Temperature sensor slope in microvolts per degree Celsius for
+          temperatures below 25 degrees Celsius
+
+    sensor-slope-hot:
+      type: int
+      required: true
+      description: |
+          Temperature sensor slope in microvolts per degree Celsius for
+          temperatures above or equal to 25 degrees Celsius
diff --git a/dts/bindings/sensor/panasonic,amg88xx.yaml b/dts/bindings/sensor/panasonic,amg88xx.yaml
new file mode 100644
index 0000000000..44c4212808
--- /dev/null
+++ b/dts/bindings/sensor/panasonic,amg88xx.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: Panasonic AMG88XX 8x8 (64) pixel infrared array sensor
+
+compatible: "panasonic,amg88xx"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: true
+      description: Interrupt pin.
+
+        The interrupt pin of AMG88XX is open-drain, active low.
+        If connected directly the MCU pin should be configured
+        as pull-up, active low.
diff --git a/dts/bindings/sensor/plantower,pms7003.yaml b/dts/bindings/sensor/plantower,pms7003.yaml
new file mode 100644
index 0000000000..970675d019
--- /dev/null
+++ b/dts/bindings/sensor/plantower,pms7003.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Plantower PMS7003 air pollution sensor.
+  Air pollution sensor capable of measuring mass concentration of dust.  See
+  more info at:
+  https://www.espruino.com/datasheets/PMS7003.pdf
+
+compatible: "plantower,pms7003"
+
+include: uart-device.yaml
diff --git a/dts/bindings/sensor/sbs,sbs-gauge.yaml b/dts/bindings/sensor/sbs,sbs-gauge.yaml
new file mode 100644
index 0000000000..9134f28c9a
--- /dev/null
+++ b/dts/bindings/sensor/sbs,sbs-gauge.yaml
@@ -0,0 +1,5 @@
+description: SBS 1.1 compliant fuel gauge (http://www.sbs-forum.org/specs)
+
+compatible: "sbs,sbs-gauge"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/seeed,grove-light.yaml b/dts/bindings/sensor/seeed,grove-light.yaml
new file mode 100644
index 0000000000..0d6fad632a
--- /dev/null
+++ b/dts/bindings/sensor/seeed,grove-light.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Grove Photo-Resistor Light Sensor
+
+compatible: "seeed,grove-light"
+
+include: base.yaml
+
+properties:
+  io-channels:
+    required: true
+    description: |
+      IO channel associated with the resistor voltage divider.
diff --git a/dts/bindings/sensor/seeed,grove-temperature.yaml b/dts/bindings/sensor/seeed,grove-temperature.yaml
new file mode 100644
index 0000000000..0fe2ba82fc
--- /dev/null
+++ b/dts/bindings/sensor/seeed,grove-temperature.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Grove NTC Temperature Sensor
+
+compatible: "seeed,grove-temperature"
+
+include: base.yaml
+
+properties:
+  io-channels:
+    required: true
+    description: |
+      IO channel associated with the NTC voltage
+
+  v1p0:
+    type: boolean
+    description: |
+      Set to indicate a v1.0 sensor.  Leave unset for v1.1 or v1.2.
diff --git a/dts/bindings/sensor/semtech,sx9500.yaml b/dts/bindings/sensor/semtech,sx9500.yaml
new file mode 100644
index 0000000000..7763e2eb86
--- /dev/null
+++ b/dts/bindings/sensor/semtech,sx9500.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Semtech SX9500 capacitive proximity/button. See more info at
+    https://www.semtech.com/products/smart-sensing/touch-proximity-devices/sx9500
+
+compatible: "semtech,sx9500"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Connection for the NIRQ signal.  This signal is active-low when
+        produced by the sensor.
diff --git a/dts/bindings/sensor/sensirion,sgp40.yaml b/dts/bindings/sensor/sensirion,sgp40.yaml
new file mode 100644
index 0000000000..7c0a268557
--- /dev/null
+++ b/dts/bindings/sensor/sensirion,sgp40.yaml
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2021, Leonard Pollak
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sensirion SGP40 Multipixel Gas Sensor
+
+compatible: "sensirion,sgp40"
+
+include: i2c-device.yaml
+
+properties:
+    enable-selftest:
+      type: boolean
+      description: |
+        Enabling this will run a selftest when the driver initializes.
+        The selftest takes ~250ms.
diff --git a/dts/bindings/sensor/sensirion,sht3xd.yaml b/dts/bindings/sensor/sensirion,sht3xd.yaml
new file mode 100644
index 0000000000..ebf3ea7213
--- /dev/null
+++ b/dts/bindings/sensor/sensirion,sht3xd.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2018, Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sensirion Humidity SHT3x-DIS humidity and temperature sensor
+
+compatible: "sensirion,sht3xd"
+
+include: i2c-device.yaml
+
+properties:
+    alert-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        ALERT pin.
+
+        This pin signals active high when produced by the sensor.  The
+        property value should ensure the flags properly describe the
+        signal that is presented to the driver.
diff --git a/dts/bindings/sensor/sensirion,sht4x.yaml b/dts/bindings/sensor/sensirion,sht4x.yaml
new file mode 100644
index 0000000000..b90b5d6f7b
--- /dev/null
+++ b/dts/bindings/sensor/sensirion,sht4x.yaml
@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2021, Leonard Pollak
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sensirion SHT4x humidity and temperature sensor
+
+compatible: "sensirion,sht4x"
+
+include: i2c-device.yaml
+
+properties:
+    repeatability:
+      type: int
+      required: true
+      description: |
+        Repeatability of the T/RH Measurement
+        0 = low -> 1.7 ms
+        1 = med -> 4.5 ms
+        2 = high -> 8.2 ms
+      enum:
+        - 0
+        - 1
+        - 2
diff --git a/dts/bindings/sensor/sensirion,shtcx.yaml b/dts/bindings/sensor/sensirion,shtcx.yaml
new file mode 100644
index 0000000000..4c81c80c6e
--- /dev/null
+++ b/dts/bindings/sensor/sensirion,shtcx.yaml
@@ -0,0 +1,37 @@
+# Copyright (c) 2021, Thomas Stranger
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sensirion SHTCx humidity and temperature sensor
+
+compatible: "sensirion,shtcx"
+
+include: i2c-device.yaml
+
+properties:
+  chip:
+    type: string
+    required: true
+    description: |
+      Specifies which chip exactly is used. This is necessary to get exact
+      timing information and supported command set.
+      SHTC3 has an additional sleep mode that is entered between measurements.
+    enum:
+        - "shtc1"
+        - "shtc3"
+
+  measure-mode:
+    type: string
+    required: true
+    description: |
+      Specifies which measurement mode is used.
+      SHTC1 sensor only supports the normal measuremnt mode.
+    enum:
+        - "normal"
+        - "low-power"
+
+  clock-stretching:
+    type: boolean
+    required: false
+    description: |
+      Specifies that the driver should clock stretching i2c communication to
+      read the sensor values.
diff --git a/dts/bindings/sensor/silabs,si7006.yaml b/dts/bindings/sensor/silabs,si7006.yaml
new file mode 100644
index 0000000000..bd88337b5d
--- /dev/null
+++ b/dts/bindings/sensor/silabs,si7006.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Electronut Labs
+# SPDX-License-Identifier: Apache-2.0
+
+description: Si7006 temperature and humidity sensor
+
+compatible: "silabs,si7006"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/silabs,si7055.yaml b/dts/bindings/sensor/silabs,si7055.yaml
new file mode 100644
index 0000000000..7aac3950f1
--- /dev/null
+++ b/dts/bindings/sensor/silabs,si7055.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: Si7055 temperature sensor
+
+compatible: "silabs,si7055"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/silabs,si7060.yaml b/dts/bindings/sensor/silabs,si7060.yaml
new file mode 100644
index 0000000000..7a1f3bb4b8
--- /dev/null
+++ b/dts/bindings/sensor/silabs,si7060.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Actinius
+# SPDX-License-Identifier: Apache-2.0
+
+description: Si7060 temperature sensor
+
+compatible: "silabs,si7060"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/silabs,si7210.yaml b/dts/bindings/sensor/silabs,si7210.yaml
new file mode 100644
index 0000000000..6e64feea07
--- /dev/null
+++ b/dts/bindings/sensor/silabs,si7210.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Si7210 hall effect magnetic position and temperature sensor
+
+compatible: "silabs,si7210"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/st,hts221-common.yaml b/dts/bindings/sensor/st,hts221-common.yaml
new file mode 100644
index 0000000000..106936334c
--- /dev/null
+++ b/dts/bindings/sensor/st,hts221-common.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2017, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/st,hts221-i2c.yaml b/dts/bindings/sensor/st,hts221-i2c.yaml
new file mode 100644
index 0000000000..237aa48ae0
--- /dev/null
+++ b/dts/bindings/sensor/st,hts221-i2c.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics HTS221 humidity and temperature sensor on I2C bus
+
+compatible: "st,hts221"
+
+include: ["i2c-device.yaml", "st,hts221-common.yaml"]
diff --git a/dts/bindings/sensor/st,hts221-spi.yaml b/dts/bindings/sensor/st,hts221-spi.yaml
new file mode 100644
index 0000000000..85b30d4f49
--- /dev/null
+++ b/dts/bindings/sensor/st,hts221-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics HTS221 humidity and temperature sensor on SPI bus
+
+compatible: "st,hts221"
+
+include: ["spi-device.yaml", "st,hts221-common.yaml"]
diff --git a/dts/bindings/sensor/st,i3g4250d.yaml b/dts/bindings/sensor/st,i3g4250d.yaml
new file mode 100644
index 0000000000..a08be5c6cc
--- /dev/null
+++ b/dts/bindings/sensor/st,i3g4250d.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2021 Jonathan Hahn
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics I3G4250D 3-axis gyrometer accessed through SPI bus
+
+compatible: "st,i3g4250d"
+
+include: spi-device.yaml
diff --git a/dts/bindings/sensor/st,iis2dh-i2c.yaml b/dts/bindings/sensor/st,iis2dh-i2c.yaml
new file mode 100644
index 0000000000..646d62ff3a
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2dh-i2c.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS2DH accelerometer accessed through I2C bus
+
+compatible: "st,iis2dh"
+
+include: i2c-device.yaml
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/st,iis2dh-spi.yaml b/dts/bindings/sensor/st,iis2dh-spi.yaml
new file mode 100644
index 0000000000..867e353f9e
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2dh-spi.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS2DH accelerometer accessed through SPI bus
+
+compatible: "st,iis2dh"
+
+include: spi-device.yaml
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/st,iis2dlpc-common.yaml b/dts/bindings/sensor/st,iis2dlpc-common.yaml
new file mode 100644
index 0000000000..2efa7ac2b2
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2dlpc-common.yaml
@@ -0,0 +1,116 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    drdy-int:
+      type: int
+      required: false
+      default: 1
+      enum:
+        - 1 # drdy is generated from INT1
+        - 2 # drdy is generated from INT2
+      description: Select DRDY pin number (1 or 2).
+
+        This number represents which of the two interrupt pins
+        (INT1 or INT2) the drdy line is attached to. This property is not
+        mandatory and if not present it defaults to 1 which is the
+        configuration at power-up.
+
+    range:
+      type: int
+      required: false
+      default: 2
+      description: Range in g. Default is power-up configuration.
+      enum:
+        - 16 # 16g (1.952 mg/LSB)
+        -  8 #  8g (0.976 mg/LSB)
+        -  4 #  4g (0.488 mg/LSB)
+        -  2 #  2g (0.244 mg/LSB)
+
+    power-mode:
+      type: int
+      required: false
+      default: 0
+      description: Specify the sensor power mode. Default is power-up configuration.
+      enum:
+        - 0 # Low Power M1
+        - 1 # Low Power M2
+        - 2 # Low Power M3
+        - 3 # Low Power M4
+        - 4 # High Performance
+
+    # tap and tap-tap configuration section
+    # All default values are selected to match the power-up values.
+    # tap and tap-tap events can be generated on INT1 only.
+
+    tap-mode:
+      type: int
+      required: false
+      default: 0
+      description: Tap mode. Default is power-up configuration.
+      enum:
+        - 0 # Only Single Tap
+        - 1 # Single and Double Tap
+
+    tap-threshold:
+      type: array
+      required: false
+      default: [0, 0, 0]
+      description: |
+        Tap X/Y/Z axes threshold. Default is power-up configuration.
+        (X/Y/Z values range from 0x00 to 0x1F)
+
+        Thresholds to start the tap-event detection procedure on the X/Y/Z axes.
+        Threshold values for each axis are unsigned 5-bit corresponding
+        to a 2g acceleration full-scale range. A threshold value equal to zero
+        corresponds to disable the tap detection on that axis.
+
+        For example, if you want to set the threshold for X to 12, for Z to 14
+        and want to disable tap detection on Y, you should specify in Device Tree
+
+            tap-threshold = <12>, <0>, <14>
+
+        which is equivalent to X = 12 * 2g/32 = 750mg and Z = 14 * 2g/32 = 875mg.
+
+    tap-shock:
+      type: int
+      required: false
+      default: 0x0
+      description: |
+        Tap shock value. Default is power-up configuration.
+        (values range from 0x0 to 0x3)
+        This register represents the maximum time of an over-threshold signal
+        detection to be recognized as a tap event. Where 0 equals 4*1/ODR and
+        1LSB = 8*1/ODR.
+
+    tap-latency:
+      type: int
+      required: false
+      default: 0x0
+      description: |
+        Tap latency. Default is power-up configuration.
+        (values range from 0x0 to 0xF)
+        When double-tap recognition is enabled, this register expresses the
+        maximum time between two successive detected taps to determine a
+        double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR.
+
+    tap-quiet:
+      type: int
+      required: false
+      default: 0x0
+      description: |
+        Expected quiet time after a tap detection. Default is power-up configuration.
+        (values range from 0x0 to 0x3)
+        This register represents the time after the first detected tap in which
+        there must not be any overthreshold event. Where 0 equals 2*1/ODR
+        and 1LSB = 4*1/ODR.
diff --git a/dts/bindings/sensor/st,iis2dlpc-i2c.yaml b/dts/bindings/sensor/st,iis2dlpc-i2c.yaml
new file mode 100644
index 0000000000..d5d736585a
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2dlpc-i2c.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS2DLPC accelerometer accessed through I2C bus
+
+compatible: "st,iis2dlpc"
+
+include: ["i2c-device.yaml", "st,iis2dlpc-common.yaml"]
diff --git a/dts/bindings/sensor/st,iis2dlpc-spi.yaml b/dts/bindings/sensor/st,iis2dlpc-spi.yaml
new file mode 100644
index 0000000000..da6e37266b
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2dlpc-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS2DLPC accelerometer accessed through SPI bus
+
+compatible: "st,iis2dlpc"
+
+include: ["spi-device.yaml", "st,iis2dlpc-common.yaml"]
diff --git a/dts/bindings/sensor/st,iis2iclx-common.yaml b/dts/bindings/sensor/st,iis2iclx-common.yaml
new file mode 100644
index 0000000000..9b5d0db9a4
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2iclx-common.yaml
@@ -0,0 +1,57 @@
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    int-pin:
+      type: int
+      required: false
+      default: 1
+      enum:
+        - 1 # drdy is generated from INT1
+        - 2 # drdy is generated from INT2
+      description: Select DRDY pin number (1 or 2).
+
+        This number represents which of the two interrupt pins
+        (INT1 or INT2) the drdy line is attached to. This property is not
+        mandatory and if not present it defaults to 1 which is the
+        configuration at power-up.
+
+    range:
+      type: int
+      required: false
+      default: 3
+      description: Range in g. Default is power-up configuration.
+      enum:
+        - 0 # 500mg (0.015 mg/LSB)
+        - 1 # 3g    (0.122 mg/LSB)
+        - 2 # 1g    (0.031 mg/LSB)
+        - 3 # 2g    (0.061 mg/LSB)
+
+    odr:
+      type: int
+      required: false
+      default: 0
+      description:
+          Specify the default accelerometer output data rate expressed in samples per second (Hz).
+          Default is power-up configuration.
+      enum:
+        - 0  # Power-Down
+        - 1  # 12.5Hz
+        - 2  # 26Hz
+        - 3  # 52Hz
+        - 4  # 104Hz
+        - 5  # 208Hz
+        - 6  # 416Hz
+        - 7  # 833Hz
+        - 8  # 1660Hz
+        - 9  # 3330Hz
+        - 10 # 6660Hz
diff --git a/dts/bindings/sensor/st,iis2iclx-i2c.yaml b/dts/bindings/sensor/st,iis2iclx-i2c.yaml
new file mode 100644
index 0000000000..8bddbc9023
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2iclx-i2c.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS2ICLX 2-axis accelerometer sensor
+    accessed through I2C bus
+
+compatible: "st,iis2iclx"
+
+include: ["i2c-device.yaml", "st,iis2iclx-common.yaml"]
diff --git a/dts/bindings/sensor/st,iis2iclx-spi.yaml b/dts/bindings/sensor/st,iis2iclx-spi.yaml
new file mode 100644
index 0000000000..82f2b1a7b2
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2iclx-spi.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS2ICLX 2-axis accelerometer sensor
+    accessed through SPI bus
+
+compatible: "st,iis2iclx"
+
+include: ["spi-device.yaml", "st,iis2iclx-common.yaml"]
diff --git a/dts/bindings/sensor/st,iis2mdc-i2c.yaml b/dts/bindings/sensor/st,iis2mdc-i2c.yaml
new file mode 100644
index 0000000000..d51b481d90
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2mdc-i2c.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS2MDC magnetometer accessed through I2C bus
+
+compatible: "st,iis2mdc"
+
+include: i2c-device.yaml
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/st,iis2mdc-spi.yaml b/dts/bindings/sensor/st,iis2mdc-spi.yaml
new file mode 100644
index 0000000000..72583a61d3
--- /dev/null
+++ b/dts/bindings/sensor/st,iis2mdc-spi.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS2MDC magnetometer accessed through SPI bus
+
+compatible: "st,iis2mdc"
+
+include: spi-device.yaml
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/st,iis3dhhc-spi.yaml b/dts/bindings/sensor/st,iis3dhhc-spi.yaml
new file mode 100644
index 0000000000..ac7156a2eb
--- /dev/null
+++ b/dts/bindings/sensor/st,iis3dhhc-spi.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics IIS3DHHC 3-axis accelerometer accessed through SPI bus
+
+compatible: "st,iis3dhhc"
+
+include: spi-device.yaml
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/st,ism330dhcx-common.yaml b/dts/bindings/sensor/st,ism330dhcx-common.yaml
new file mode 100644
index 0000000000..fd390f0019
--- /dev/null
+++ b/dts/bindings/sensor/st,ism330dhcx-common.yaml
@@ -0,0 +1,136 @@
+# Copyright (c) 2021 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        DRDY gpio pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    int-pin:
+      type: int
+      required: false
+      default: 1
+      description: |
+        Select DRDY pin number (1 or 2).
+
+          Selection
+            1  drdy is generated from INT1
+            2  drdy is generated from INT2
+
+        This number represents which of the two interrupt pins
+        (INT1 or INT2) the drdy line is attached to. This property is not
+        mandatory and if not present it defaults to 1 which is the
+        configuration at power-up.
+      enum:
+        - 1
+        - 2
+
+    accel-odr:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Specify the default accelerometer output data rate expressed in samples per second (Hz).
+        Default is power-up configuration.
+
+          Selection
+            0   Power-Down
+            1   12.5Hz
+            2   26Hz
+            3   52Hz
+            4   104Hz
+            5   208Hz
+            6   416Hz
+            7   833Hz
+            8   1660Hz
+            9   3330Hz
+            10  6660Hz
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 4
+        - 5
+        - 6
+        - 7
+        - 8
+        - 9
+        - 10
+
+    accel-range:
+      type: int
+      required: false
+      default: 2
+      description: |
+        Range in g. Default is power-up configuration.
+
+          Selection
+            16  16g (0.488 mg/LSB)
+             8   8g (0.244 mg/LSB)
+             4   4g (0.122 mg/LSB)
+             2   2g (0.061 mg/LSB)
+      enum:
+        - 16
+        -  8
+        -  4
+        -  2
+
+    gyro-odr:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Specify the default gyro output data rate expressed in samples per second (Hz).
+        Default is power-up configuration.
+
+          Selection
+            0   Power-Down
+            1   12.5Hz
+            2   26Hz
+            3   52Hz
+            4   104Hz
+            5   208Hz
+            6   416Hz
+            7   833Hz
+            8   1660Hz
+            9   3330Hz
+            10  6660Hz
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 4
+        - 5
+        - 6
+        - 7
+        - 8
+        - 9
+        - 10
+
+    gyro-range:
+      type: int
+      required: false
+      default: 125
+      description: |
+        Range in dps. Default is power-up configuration.
+
+          Selection
+            125    +/- 125dps
+            250    +/- 250dps
+            500    +/- 500dps
+            1000   +/- 1000dps
+            2000   +/- 2000dps
+      enum:
+        - 125
+        - 250
+        - 500
+        - 1000
+        - 2000
diff --git a/dts/bindings/sensor/st,ism330dhcx-i2c.yaml b/dts/bindings/sensor/st,ism330dhcx-i2c.yaml
new file mode 100644
index 0000000000..8daa695e37
--- /dev/null
+++ b/dts/bindings/sensor/st,ism330dhcx-i2c.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics ISM330DHCX 6-axis IMU (Inertial Measurement Unit) sensor
+    accessed through I2C bus
+
+compatible: "st,ism330dhcx"
+
+include: ["i2c-device.yaml", "st,ism330dhcx-common.yaml"]
diff --git a/dts/bindings/sensor/st,ism330dhcx-spi.yaml b/dts/bindings/sensor/st,ism330dhcx-spi.yaml
new file mode 100644
index 0000000000..ebc33a76ff
--- /dev/null
+++ b/dts/bindings/sensor/st,ism330dhcx-spi.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics ISM330DHCX 6-axis IMU (Inertial Measurement Unit) sensor
+    accessed through SPI bus
+
+compatible: "st,ism330dhcx"
+
+include: ["spi-device.yaml", "st,ism330dhcx-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2dh-common.yaml b/dts/bindings/sensor/st,lis2dh-common.yaml
new file mode 100644
index 0000000000..aac6962eef
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2dh-common.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT1 and (optional) INT2 signal connections.  These signals
+        are active-high as produced by the sensor.
+
+    disconnect-sdo-sa0-pull-up:
+      type: boolean
+      required: false
+      description: |
+        Indicates the device driver should disconnect SDO/SA0 pull-up
+        during device initialization (e.g. to save current
+        leakage). Note that only subset of devices supported by this
+        binding have SDO/SA0 pull-up (e.g. LIS2DH12, LIS3DH).
diff --git a/dts/bindings/sensor/st,lis2dh-i2c.yaml b/dts/bindings/sensor/st,lis2dh-i2c.yaml
new file mode 100644
index 0000000000..9700f3157b
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2dh-i2c.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LIS2DH 3-axis accelerometer accessed through I2C bus
+
+compatible: "st,lis2dh"
+
+include: ["i2c-device.yaml", "st,lis2dh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2dh-spi.yaml b/dts/bindings/sensor/st,lis2dh-spi.yaml
new file mode 100644
index 0000000000..113b0d26ee
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2dh-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LIS2DH 3-axis accelerometer accessed through SPI bus
+
+compatible: "st,lis2dh"
+
+include: ["spi-device.yaml", "st,lis2dh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2dh12-i2c.yaml b/dts/bindings/sensor/st,lis2dh12-i2c.yaml
new file mode 100644
index 0000000000..8b78344b6f
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2dh12-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LIS2DH12 3-axis accelerometer
+
+compatible: "st,lis2dh12"
+
+include: ["i2c-device.yaml", "st,lis2dh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2ds12-common.yaml b/dts/bindings/sensor/st,lis2ds12-common.yaml
new file mode 100644
index 0000000000..4311c84e0f
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2ds12-common.yaml
@@ -0,0 +1,60 @@
+# Copyright (c) 2021 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    range:
+      type: int
+      required: false
+      default: 2
+      description: |
+        Range in g. Default is power-up configuration.
+
+      enum:
+        - 16 # 16g (0.488 mg/LSB)
+        -  8 #  8g (0.244 mg/LSB)
+        -  4 #  4g (0.122 mg/LSB)
+        -  2 #  2g (0.061 mg/LSB)
+
+    power-mode:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Specify the sensor power mode. Default is power-down mode
+
+      enum:
+        - 0 # Power Down (PD)
+        - 1 # Low Power (LP)
+        - 2 # High Resolution (HR)
+        - 3 # High Frequency (HF)
+
+    odr:
+      type: int
+      required: false
+      default: 0
+      description: |
+          Specify the default output data rate expressed in samples per second (Hz).
+          Default is power-down mode
+      enum:
+        - 0  # Power-Down
+        - 1  # 1Hz (available in LP mode only)
+        - 2  # 12.5Hz (available in LP and HR mode)
+        - 3  # 25Hz (available in LP and HR mode)
+        - 4  # 50Hz (available in LP and HR mode)
+        - 5  # 100Hz (available in LP and HR mode)
+        - 6  # 200Hz (available in LP and HR mode)
+        - 7  # 400Hz (available in LP and HR mode)
+        - 8  # 800Hz (available in LP and HR mode)
+        - 9  # 1600Hz (available in HF mode only)
+        - 10  # 3200Hz (available in HF mode only)
+        - 11  # 6400Hz (available in HF mode only)
diff --git a/dts/bindings/sensor/st,lis2ds12-i2c.yaml b/dts/bindings/sensor/st,lis2ds12-i2c.yaml
new file mode 100644
index 0000000000..46442ee2cc
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2ds12-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LIS2DS12 3-axis accelerometer
+
+compatible: "st,lis2ds12"
+
+include: ["i2c-device.yaml", "st,lis2ds12-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2ds12-spi.yaml b/dts/bindings/sensor/st,lis2ds12-spi.yaml
new file mode 100644
index 0000000000..d8946fa2e4
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2ds12-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LIS2DS12 3-axis accelerometer accessed through SPI bus
+
+compatible: "st,lis2ds12"
+
+include: ["spi-device.yaml", "st,lis2ds12-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2dw12-common.yaml b/dts/bindings/sensor/st,lis2dw12-common.yaml
new file mode 100644
index 0000000000..930a1a5212
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2dw12-common.yaml
@@ -0,0 +1,140 @@
+# Copyright (c) 2021 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    int-pin:
+      type: int
+      required: false
+      default: 1
+      enum:
+        - 1
+        - 2
+      description: |
+        Select DRDY pin number (1 or 2).
+
+           1 # drdy is generated from INT1
+           2 # drdy is generated from INT2
+
+        This number represents which of the two interrupt pins
+        (INT1 or INT2) the drdy line is attached to. This property is not
+        mandatory and if not present it defaults to 1 which is the
+        configuration at power-up.
+
+    range:
+      type: int
+      required: false
+      default: 2
+      description: |
+        Range in g. Default is power-up configuration.
+
+          16 # 16g (1.952 mg/LSB)
+           8 #  8g (0.976 mg/LSB)
+           4 #  4g (0.488 mg/LSB)
+           2 #  2g (0.244 mg/LSB)
+
+      enum:
+        - 16
+        -  8
+        -  4
+        -  2
+
+    power-mode:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Specify the sensor power mode. Default is power-up configuration.
+
+          0 # Low Power M1
+          1 # Low Power M2
+          2 # Low Power M3
+          3 # Low Power M4
+          4 # High Performance
+
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 4
+
+    # tap and tap-tap configuration section
+    # All default values are selected to match the power-up values.
+    # tap and tap-tap events can be generated on INT1 only.
+
+    tap-mode:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Tap mode. Default is power-up configuration.
+
+          0 # Only Single Tap
+          1 # Single and Double Tap
+
+      enum:
+        - 0
+        - 1
+
+    tap-threshold:
+      type: array
+      required: false
+      default: [0, 0, 0]
+      description: |
+        Tap X/Y/Z axes threshold. Default is power-up configuration.
+        (X/Y/Z values range from 0x00 to 0x1F)
+
+        Thresholds to start the tap-event detection procedure on the X/Y/Z axes.
+        Threshold values for each axis are unsigned 5-bit corresponding
+        to a 2g acceleration full-scale range. A threshold value equal to zero
+        corresponds to disable the tap detection on that axis.
+
+        For example, if you want to set the threshold for X to 12, for Z to 14
+        and want to disable tap detection on Y, you should specify in Device Tree
+
+            tap-threshold = <12>, <0>, <14>
+
+        which is equivalent to X = 12 * 2g/32 = 750mg and Z = 14 * 2g/32 = 875mg.
+
+    tap-shock:
+      type: int
+      required: false
+      default: 0x0
+      description: |
+        Tap shock value. Default is power-up configuration.
+        (values range from 0x0 to 0x3)
+        This register represents the maximum time of an over-threshold signal
+        detection to be recognized as a tap event. Where 0 equals 4*1/ODR and
+        1LSB = 8*1/ODR.
+
+    tap-latency:
+      type: int
+      required: false
+      default: 0x0
+      description: |
+        Tap latency. Default is power-up configuration.
+        (values range from 0x0 to 0xF)
+        When double-tap recognition is enabled, this register expresses the
+        maximum time between two successive detected taps to determine a
+        double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR.
+
+    tap-quiet:
+      type: int
+      required: false
+      default: 0x0
+      description: |
+        Expected quiet time after a tap detection. Default is power-up configuration.
+        (values range from 0x0 to 0x3)
+        This register represents the time after the first detected tap in which
+        there must not be any overthreshold event. Where 0 equals 2*1/ODR
+        and 1LSB = 4*1/ODR.
diff --git a/dts/bindings/sensor/st,lis2dw12-i2c.yaml b/dts/bindings/sensor/st,lis2dw12-i2c.yaml
new file mode 100644
index 0000000000..994648590e
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2dw12-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LIS2DW12 3-axis accelerometer
+
+compatible: "st,lis2dw12"
+
+include: ["i2c-device.yaml", "st,lis2dw12-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2dw12-spi.yaml b/dts/bindings/sensor/st,lis2dw12-spi.yaml
new file mode 100644
index 0000000000..bf16c015c0
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2dw12-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LIS2DW12 3-axis accelerometer accessed through SPI bus
+
+compatible: "st,lis2dw12"
+
+include: ["spi-device.yaml", "st,lis2dw12-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2mdl-common.yaml b/dts/bindings/sensor/st,lis2mdl-common.yaml
new file mode 100644
index 0000000000..89125cdead
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2mdl-common.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: IRQ pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    single-mode:
+      type: boolean
+      required: false
+      description: |
+        Set to config the sensor in single measurement mode. Leave
+        unset to configure the sensor in continious measurement mode.
+
+    cancel-offset:
+      type: boolean
+      required: false
+      description: |
+        Set to enable the offset cancellation. Otherwise it would be
+        disabled as default.
+
+    spi-full-duplex:
+      type: boolean
+      required: false
+      description: |
+        Enable SPI 4wires mode with separated MISO and MOSI lines
diff --git a/dts/bindings/sensor/st,lis2mdl-i2c.yaml b/dts/bindings/sensor/st,lis2mdl-i2c.yaml
new file mode 100644
index 0000000000..411976916f
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2mdl-i2c.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LIS2MDL magnetometer accessed through I2C bus
+
+compatible: "st,lis2mdl"
+
+include: ["i2c-device.yaml", "st,lis2mdl-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis2mdl-spi.yaml b/dts/bindings/sensor/st,lis2mdl-spi.yaml
new file mode 100644
index 0000000000..3a99a8b9a0
--- /dev/null
+++ b/dts/bindings/sensor/st,lis2mdl-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LIS2MDL magnetometer accessed through SPI bus
+
+compatible: "st,lis2mdl"
+
+include: ["spi-device.yaml", "st,lis2mdl-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis3dh-i2c.yaml b/dts/bindings/sensor/st,lis3dh-i2c.yaml
new file mode 100644
index 0000000000..67018c1315
--- /dev/null
+++ b/dts/bindings/sensor/st,lis3dh-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LIS3DH 3-axis accelerometer
+
+compatible: "st,lis3dh"
+
+include: ["i2c-device.yaml", "st,lis2dh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lis3mdl-magn.yaml b/dts/bindings/sensor/st,lis3mdl-magn.yaml
new file mode 100644
index 0000000000..61abc87475
--- /dev/null
+++ b/dts/bindings/sensor/st,lis3mdl-magn.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2017, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LIS3MDL magnetometer
+
+compatible: "st,lis3mdl-magn"
+
+include: i2c-device.yaml
+
+properties:
+    irq-gpios:
+      required: false
+      type: phandle-array
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/st,lps22hb-press.yaml b/dts/bindings/sensor/st,lps22hb-press.yaml
new file mode 100644
index 0000000000..4141995d9f
--- /dev/null
+++ b/dts/bindings/sensor/st,lps22hb-press.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2017, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LPS22HB pressure sensor
+
+compatible: "st,lps22hb-press"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/st,lps22hh-common.yaml b/dts/bindings/sensor/st,lps22hh-common.yaml
new file mode 100644
index 0000000000..9eee9c0f98
--- /dev/null
+++ b/dts/bindings/sensor/st,lps22hh-common.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2021 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    odr:
+      type: int
+      required: false
+      default: 0
+      description: |
+          Specify the default output data rate expressed in samples per second (Hz).
+          Default is power-down mode
+      enum:
+        - 0  # Power-Down
+        - 1  # 1Hz
+        - 2  # 10Hz
+        - 3  # 25Hz
+        - 4  # 50Hz
+        - 5  # 75Hz
+        - 6  # 100Hz
+        - 7  # 200Hz
diff --git a/dts/bindings/sensor/st,lps22hh-i2c.yaml b/dts/bindings/sensor/st,lps22hh-i2c.yaml
new file mode 100644
index 0000000000..439ac34680
--- /dev/null
+++ b/dts/bindings/sensor/st,lps22hh-i2c.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LPS22HH pressure and temperature sensor connected to I2C
+    bus
+
+compatible: "st,lps22hh"
+
+include: ["i2c-device.yaml", "st,lps22hh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lps22hh-spi.yaml b/dts/bindings/sensor/st,lps22hh-spi.yaml
new file mode 100644
index 0000000000..34dde1c071
--- /dev/null
+++ b/dts/bindings/sensor/st,lps22hh-spi.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LPS22HH pressure and temperature sensor connected to SPI
+    bus
+
+compatible: "st,lps22hh"
+
+include: ["spi-device.yaml", "st,lps22hh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lps25hb-press.yaml b/dts/bindings/sensor/st,lps25hb-press.yaml
new file mode 100644
index 0000000000..77f3f11623
--- /dev/null
+++ b/dts/bindings/sensor/st,lps25hb-press.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LPS25HB pressure sensor
+
+compatible: "st,lps25hb-press"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/st,lsm303agr-accel-i2c.yaml b/dts/bindings/sensor/st,lsm303agr-accel-i2c.yaml
new file mode 100644
index 0000000000..8ad81e61ab
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm303agr-accel-i2c.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2019 Grinn
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LSM303AGR 3-axis accelerometer accessed through I2C bus
+
+compatible: "st,lsm303agr-accel"
+
+include: ["i2c-device.yaml", "st,lis2dh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lsm303agr-accel-spi.yaml b/dts/bindings/sensor/st,lsm303agr-accel-spi.yaml
new file mode 100644
index 0000000000..44c988b23a
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm303agr-accel-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2019 Grinn
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LSM303AGR 3-axis accelerometer accessed through SPI bus
+
+compatible: "st,lsm303agr-accel"
+
+include: ["spi-device.yaml", "st,lis2dh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lsm303dlhc-accel.yaml b/dts/bindings/sensor/st,lsm303dlhc-accel.yaml
new file mode 100644
index 0000000000..6fa8fc4557
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm303dlhc-accel.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Philémon Jaermann
+# SPDX-License-Identifier: Apache-2.0
+
+description: LSM303DLHC acceleration sensor
+
+compatible: "st,lsm303dlhc-accel"
+
+include: ["i2c-device.yaml", "st,lis2dh-common.yaml"]
diff --git a/dts/bindings/sensor/st,lsm303dlhc-magn.yaml b/dts/bindings/sensor/st,lsm303dlhc-magn.yaml
new file mode 100644
index 0000000000..44ec89bb9c
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm303dlhc-magn.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018 Philémon Jaermann
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LSM303DLHC magnetometer sensor
+
+compatible: "st,lsm303dlhc-magn"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/st,lsm6ds0.yaml b/dts/bindings/sensor/st,lsm6ds0.yaml
new file mode 100644
index 0000000000..cdde4b56bf
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6ds0.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LSM6DS0 6-axis accelerometer and gyrometer
+
+compatible: "st,lsm6ds0"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/st,lsm6dsl-i2c.yaml b/dts/bindings/sensor/st,lsm6dsl-i2c.yaml
new file mode 100644
index 0000000000..61c4ecb389
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dsl-i2c.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2017, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LSM6DSL 6-axis accelerometer and gyrometer
+
+compatible: "st,lsm6dsl"
+
+include: i2c-device.yaml
+
+properties:
+    irq-gpios:
+      # This signal is active high when produced by the sensor
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/sensor/st,lsm6dsl-spi.yaml b/dts/bindings/sensor/st,lsm6dsl-spi.yaml
new file mode 100644
index 0000000000..b0f7de909c
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dsl-spi.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LSM6DSL 6-axis accelerometer and gyrometer accessed
+    through SPI bus
+
+compatible: "st,lsm6dsl"
+
+include: spi-device.yaml
+
+properties:
+    irq-gpios:
+      # This signal is active high when produced by the sensor
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/sensor/st,lsm6dso-common.yaml b/dts/bindings/sensor/st,lsm6dso-common.yaml
new file mode 100644
index 0000000000..29216e1d15
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dso-common.yaml
@@ -0,0 +1,116 @@
+# Copyright (c) 2021 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    int-pin:
+      type: int
+      required: false
+      default: 1
+      enum:
+        - 1 # drdy is generated from INT1
+        - 2 # drdy is generated from INT2
+      description: |
+        Select DRDY pin number (1 or 2).
+
+        This number represents which of the two interrupt pins
+        (INT1 or INT2) the drdy line is attached to. This property is not
+        mandatory and if not present it defaults to 1 which is the
+        configuration at power-up.
+
+    accel-pm:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Specify the accelerometer power mode.
+        Default is power-up configuration.
+      enum:
+        - 0 # High Performance mode (default)
+        - 1 # Low/Normal Power mode
+        - 2 # Ultra Low Power mode
+
+    accel-range:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Range in g. Default is power-up configuration.
+      enum:
+        - 0 # 2g  (0.061 mg/LSB)
+        - 1 # 16g (0.488 mg/LSB)
+        - 2 # 4g  (0.122 mg/LSB)
+        - 3 # 8g  (0.244 mg/LSB)
+
+    accel-odr:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Specify the default accelerometer output data rate expressed in samples per second (Hz).
+        Default is power-up configuration.
+      enum:
+        - 0  # Power-Down
+        - 1  # 12.5Hz
+        - 2  # 26Hz
+        - 3  # 52Hz
+        - 4  # 104Hz
+        - 5  # 208Hz
+        - 6  # 417Hz
+        - 7  # 833Hz
+        - 8  # 1667Hz
+        - 9  # 3333Hz
+        - 10 # 6667Hz
+
+    gyro-pm:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Specify the gyrometer power mode.
+        Default is power-up configuration.
+      enum:
+        - 0 # High Performance mode (default)
+        - 1 # Low/Normal Power mode
+
+    gyro-range:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Range in dps. Default is power-up configuration.
+      enum:
+        - 0 # 250 dps  (8.75 mdps/LSB)
+        - 1 # 125 dps  (4.375 mdps/LSB)
+        - 2 # 500 dps  (17.50 mdps/LSB)
+        - 4 # 1000 dps (35 mdps/LSB)
+        - 6 # 2000 dps (70 mdps/LSB)
+
+    gyro-odr:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Specify the default gyro output data rate expressed in samples per second (Hz).
+        Default is power-up configuration.
+      enum:
+        - 0  # Power-Down
+        - 1  # 12.5Hz
+        - 2  # 26Hz
+        - 3  # 52Hz
+        - 4  # 104Hz
+        - 5  # 208Hz
+        - 6  # 417Hz
+        - 7  # 833Hz
+        - 8  # 1667Hz
+        - 9  # 3333Hz
+        - 10 # 6667Hz
diff --git a/dts/bindings/sensor/st,lsm6dso-i2c.yaml b/dts/bindings/sensor/st,lsm6dso-i2c.yaml
new file mode 100644
index 0000000000..06277c7e8b
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dso-i2c.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LSM6DSO 6-axis IMU (Inertial Measurement Unit) sensor
+    accessed through I2C bus
+
+compatible: "st,lsm6dso"
+
+include: ["i2c-device.yaml", "st,lsm6dso-common.yaml"]
diff --git a/dts/bindings/sensor/st,lsm6dso-spi.yaml b/dts/bindings/sensor/st,lsm6dso-spi.yaml
new file mode 100644
index 0000000000..9b679b5a88
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dso-spi.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LSM6DSO 6-axis IMU (Inertial Measurement Unit) sensor
+    accessed through SPI bus
+
+compatible: "st,lsm6dso"
+
+include: ["spi-device.yaml", "st,lsm6dso-common.yaml"]
diff --git a/dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml b/dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml
new file mode 100644
index 0000000000..b1b2de9c1d
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm9ds0-gyro-i2c.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LSM9DS0-GYRO 3-axis gyro
+
+compatible: "st,lsm9ds0-gyro"
+
+include: i2c-device.yaml
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml b/dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml
new file mode 100644
index 0000000000..bfc47ecf3a
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm9ds0-mfd-i2c.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics LSM9DS0 3-axis accelerometer + magnetometer
+
+compatible: "st,lsm9ds0-mfd"
+
+include: i2c-device.yaml
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/sensor/st,stm32-temp.yaml b/dts/bindings/sensor/st,stm32-temp.yaml
new file mode 100644
index 0000000000..41007aa226
--- /dev/null
+++ b/dts/bindings/sensor/st,stm32-temp.yaml
@@ -0,0 +1,43 @@
+# Copyright (c) 2021, Eug Krashtan
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 family TEMP node
+
+compatible: "st,stm32-temp"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    io-channels:
+      required: true
+      description: ADC channel for temperature sensor
+
+    ts-voltage-mv:
+      type: int
+      default: 3300
+      description: Temperature sensor voltage in millivolts
+
+    avgslope:
+      type: int
+      default: 25
+      description: |
+        Average slope of T-V chart (in mV/C x10) according to
+        datasheet "Electrical characteristics/Operating conditions"
+        STM32F1 Table 5.3.19 (min 4 mV/C, max 4.6, default 4.3)
+        STM32F4 Table 6.3.21 default 2.5
+
+    v25:
+      type: int
+      default: 760
+      description: |
+        Voltage of temperature sensor at 25C in mV according to
+        datasheet "Electrical characteristics/Operating conditions"
+        STM32F1 Table 5.3.19 (min 1340, max 1520, default 1430)
+        STM32F4 Table 6.3.21 default 760
+
+    ntc:
+      type: boolean
+      description: Negative Temperature Coefficient. True if STM32F1
diff --git a/dts/bindings/sensor/st,stts751-i2c.yaml b/dts/bindings/sensor/st,stts751-i2c.yaml
new file mode 100644
index 0000000000..ba41e8125d
--- /dev/null
+++ b/dts/bindings/sensor/st,stts751-i2c.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2019 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics STTS751 temperature sensor connected to I2C bus
+
+compatible: "st,stts751"
+
+include: i2c-device.yaml
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY pin
+
+        This pin defaults to active high when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/st,vl53l0x.yaml b/dts/bindings/sensor/st,vl53l0x.yaml
new file mode 100644
index 0000000000..ec1c2c80e2
--- /dev/null
+++ b/dts/bindings/sensor/st,vl53l0x.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2017, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STMicroelectronics VL53L0X Time of Flight sensor
+
+compatible: "st,vl53l0x"
+
+include: i2c-device.yaml
+
+properties:
+    xshut-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/sensor/ti,bq274xx.yaml b/dts/bindings/sensor/ti,bq274xx.yaml
new file mode 100644
index 0000000000..5594f77996
--- /dev/null
+++ b/dts/bindings/sensor/ti,bq274xx.yaml
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020 Linumiz
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Texas Instruments BQ274xx Fuel Gauge
+
+compatible: "ti,bq274xx"
+
+include: i2c-device.yaml
+
+properties:
+    design-voltage:
+      type: int
+      required: true
+      description: Battery Design Voltage in mV (3300 - 4400)
+
+    design-capacity:
+      type: int
+      required: true
+      description: Battery Design Capacity in mAh
+
+    taper-current:
+      type: int
+      required: true
+      description: Battery Taper current in mAh
+
+    terminate-voltage:
+      type: int
+      required: true
+      description: Battery Terminate Voltage in mV
+
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT signal defaults to active low open drain, so requires a
+        pull-up on the board. By default it acts as an output and signals
+        specific events happening (e.g. change in State of Charge). While in
+        shutdown mode it acts as an input and toggling it will make the sensor
+        exit the mode.
diff --git a/dts/bindings/sensor/ti,fdc2x1x.yaml b/dts/bindings/sensor/ti,fdc2x1x.yaml
new file mode 100644
index 0000000000..1dded05e6c
--- /dev/null
+++ b/dts/bindings/sensor/ti,fdc2x1x.yaml
@@ -0,0 +1,259 @@
+# Copyright (c) 2020 arithmetics.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments FDC2X1X capacitive sensor
+
+compatible: "ti,fdc2x1x"
+
+include: i2c-device.yaml
+
+properties:
+    sd-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The SD pin defaults to active high when consumed by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    intb-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INTB pin defaults to active low when produced by the sensor.
+        The property value should ensure the flags properly describe
+        the signal that is presented to the driver.
+
+    fdc2x14:
+      type: boolean
+      description: |
+        Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
+
+    autoscan:
+      type: boolean
+      description: |
+        Set the Auto-Scan Mode.
+
+        false = Continuous conversion on the single channel selected by
+        "active-channel" (single channel mode).
+
+        true = Auto-Scan conversions as selected by "rr-sequence"
+        (multichannel mode).
+
+    fref:
+      type: int
+      required: true
+      description: |
+        Reference frequency of the used clock source in KHz.
+        The internal clock oscillates at around 43360 KHz (43.36 MHz)
+        at 20 degrees Celcius.
+        Recommended external clock source frequency is 40000 KHz (40 MHz).
+
+    rr-sequence:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Auto-Scan Sequence Configuration.
+        The FDC will perform a single conversion on each channel
+        in the sequence selected, and then restart the sequence continuously.
+
+        The sensor performs conversion on Channel 0 to 1 by default after
+        power-on-reset. This setting only applies if autoscan=true
+        (multichannel mode).
+
+        0 = Ch0, Ch1
+        1 = Ch0, Ch1, Ch2 (FDC2114, FDC2214 only)
+        2 = Ch0, Ch1, Ch2, Ch3 (FDC2114, FDC2214 only)
+      enum:
+        - 0
+        - 1
+        - 2
+
+    active-channel:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Selects channel for continuous conversions.
+
+        The sensor performs continuous conversion on Channel 0 by default after
+        power-on-reset. This setting only applies if autoscan=false
+        (single channel mode).
+
+        0 = Perform continuous conversions on Channel 0
+        1 = Perform continuous conversions on Channel 1
+        2 = Perform continuous conversions on Channel 2 (FDC2114, FDC2214 only)
+        3 = Perform continuous conversions on Channel 3 (FDC2114, FDC2214 only)
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+
+    deglitch:
+      type: int
+      required: true
+      description: |
+        Input deglitch filter bandwidth. Select the lowest setting that exceeds
+        the oscillation tank oscillation frequency.
+
+        1 = 1MHz
+        4 = 3.3MHz
+        5 = 10MHz
+        7 = 33MHz
+      enum:
+        - 1
+        - 4
+        - 5
+        - 7
+
+    sensor-activate-sel:
+      type: string
+      required: false
+      default: "low-power"
+      description: |
+        Sensor Activation Mode Selection.
+
+        The sensor uses low-power activation mode by default after
+        power-on-reset.
+
+        full-current = the FDC will drive maximum
+        sensor current for a shorter sensor activation time.
+
+        low-power = the FDC uses the value programmed by "idrive" during
+        sensor activation to minimize power consumption.
+      enum:
+        - "full-current"
+        - "low-power"
+
+    ref-clk-src:
+      type: string
+      required: false
+      default: "internal"
+      description: |
+        Select Reference Frequency Source.
+
+        The sensor uses the internal clock by default after power-on-reset.
+
+        internal = Use Internal oscillator as reference frequency
+        external = Reference frequency is provided from CLKIN pin.
+      enum:
+        - "internal"
+        - "external"
+
+    current-drive:
+      type: string
+      required: false
+      default: "normal"
+      description: |
+        Select Current Sensor Drive.
+
+        The sensor uses normal current drive by default after power-on-reset.
+        High current drive is not supported if autoscan=false and will default
+        to normal.
+
+        normal = The FDC will drive all channels with normal sensor current
+        (1.5mA max).
+
+        high = The FDC will drive channel 0 with current >1.5mA.
+      enum:
+        - "normal"
+        - "high"
+
+    output-gain:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Output gain control (FDC2112, FDC2114 only)
+
+        The default output gain is 0 after power-on-reset.
+
+        0 = Gain = 1   | Effective Resolution 12 bits | 100% full scale
+        1 = Gain = 4   | Effective Resolution 14 bits | 25% full scale
+        2 = Gain = 8   | Effective Resolution 15 bits | 12.5% full scale
+        3 = Gain = 16  | Effective Resolution 16 bits | 6.25% full scale
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+
+child-binding:
+  description: |
+    Settings for each channel 0-1 (FDC2112 and FDC2212) or
+    0-3 (FDC2114 and FDC2214)
+
+  properties:
+      rcount:
+        type: int
+        required: true
+        description: |
+          Channel X Reference Count Conversion Interval Time.
+          Valid range: 256 - 65535
+
+      offset:
+        type: int
+        required: false
+        default: 0
+        description: |
+          Channel X Conversion Offset (FDC2112 and FDC2212 only).
+          The default offset value after power-on-reset is 0.
+          Valid range: 0 - 65535
+
+      settlecount:
+        type: int
+        required: true
+        description: |
+          Channel X Conversion Settling.
+
+          The FDC will use this settling time to allow the LC sensor to
+          stabilize before initiation of a conversion on Channel X.
+          Valid range: 0 - 65535
+
+      fref-divider:
+        type: int
+        required: true
+        description: |
+          Channel X Reference Divider.
+
+          Sets the divider for Channel X reference.
+          Use this to scale the maximum conversion frequency.
+          Valid range: 1 - 1023
+
+      idrive:
+        type: int
+        required: true
+        description: |
+          Channel X Sensor drive current.
+
+          This field defines the Drive Current used during the settling +
+          conversion time of Channel X sensor clock.
+          Valid range: 0 - 31
+
+      fin-sel:
+        type: int
+        required: true
+        description: |
+          Channel X Sensor frequency select.
+
+          For differential sensor configuration:
+          1 = divide by 1. Choose for sensor frequencies between
+          0.01MHz and 8.75MHz
+          2 = divide by 2. Choose for sensor frequencies between 5MHz
+          and 10MHz
+
+          For single-ended sensor configuration:
+          2 = divide by 2. Choose for sensor frequencies between
+          0.01MHz and 10MHz
+        enum:
+          - 1 # Divide by 1
+          - 2 # Divide by 2
+
+      inductance:
+        type: int
+        required: true
+        description: |
+          Inductor value used on the PCB for the sensing network of the
+          specific channel, which is usually 18uH.
diff --git a/dts/bindings/sensor/ti,hdc.yaml b/dts/bindings/sensor/ti,hdc.yaml
new file mode 100644
index 0000000000..2d317ed072
--- /dev/null
+++ b/dts/bindings/sensor/ti,hdc.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments temperature and humidity sensor (e.g. HDC1008)
+
+compatible: "ti,hdc"
+
+include: i2c-device.yaml
+
+properties:
+    drdy-gpios:
+      type: phandle-array
+      required: false
+      description: Data ready pin.
+
+        The DRDYn pin of HDC sensor is open-drain, active low.
+        If connected directly the MCU pin should be configured
+        as pull-up, active low.
diff --git a/dts/bindings/sensor/ti,hdc2010.yaml b/dts/bindings/sensor/ti,hdc2010.yaml
new file mode 100644
index 0000000000..d05b24787b
--- /dev/null
+++ b/dts/bindings/sensor/ti,hdc2010.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments HDC2010 Temperature and Humidity Sensor
+
+compatible: "ti,hdc2010"
+
+include: ti,hdc20xx.yaml
diff --git a/dts/bindings/sensor/ti,hdc2021.yaml b/dts/bindings/sensor/ti,hdc2021.yaml
new file mode 100644
index 0000000000..af291ee31d
--- /dev/null
+++ b/dts/bindings/sensor/ti,hdc2021.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments HDC2021 Temperature and Humidity Sensor
+
+compatible: "ti,hdc2021"
+
+include: ti,hdc20xx.yaml
diff --git a/dts/bindings/sensor/ti,hdc2022.yaml b/dts/bindings/sensor/ti,hdc2022.yaml
new file mode 100644
index 0000000000..96f5ab7ef3
--- /dev/null
+++ b/dts/bindings/sensor/ti,hdc2022.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments HDC2022 Temperature and Humidity Sensor
+
+compatible: "ti,hdc2022"
+
+include: ti,hdc20xx.yaml
diff --git a/dts/bindings/sensor/ti,hdc2080.yaml b/dts/bindings/sensor/ti,hdc2080.yaml
new file mode 100644
index 0000000000..cdf596f152
--- /dev/null
+++ b/dts/bindings/sensor/ti,hdc2080.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments HDC2080 Temperature and Humidity Sensor
+
+compatible: "ti,hdc2080"
+
+include: ti,hdc20xx.yaml
diff --git a/dts/bindings/sensor/ti,hdc20xx.yaml b/dts/bindings/sensor/ti,hdc20xx.yaml
new file mode 100644
index 0000000000..ddd5d6c693
--- /dev/null
+++ b/dts/bindings/sensor/ti,hdc20xx.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments HDC20XX Temperature and Humidity Sensor
+
+compatible: "ti,hdc20xx"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: DRDY/INT pin.
+
+        The DRDY/INT pin of HDC20xx sensor is open-drain, active low. If
+        connected directly the MCU pin should be configured as pull-up
+        as pull-up, active low.
diff --git a/dts/bindings/sensor/ti,ina219.yaml b/dts/bindings/sensor/ti,ina219.yaml
new file mode 100644
index 0000000000..ab6d027c70
--- /dev/null
+++ b/dts/bindings/sensor/ti,ina219.yaml
@@ -0,0 +1,131 @@
+# Copyright (c) 2021 Leonard Pollak
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments Bidirectional Current/Power Sensor
+
+compatible: "ti,ina219"
+
+include: i2c-device.yaml
+
+properties:
+    lsb-microamp:
+      type: int
+      required: true
+      description: |
+        Current LSB in microAmpere
+        Current LSB = max expected current [A] / 2^15
+        example: 100 -> ~3A
+    shunt-milliohm:
+      type: int
+      required: true
+      description: |
+        Value of the shunt resistor in milliOhm
+    brng:
+      type: int
+      required: false
+      default: 1
+      description: |
+        Bus Voltage Range
+        0 = 16 V FSR
+        1 = 32 V FSR
+
+        The default of 32V is the power-on reset value of the device.
+
+        Should the expected bus voltage be below 16V set this to 0.
+      enum:
+        - 0
+        - 1
+    pg:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Programmable Gain
+        0 = 1  -> ±40 mV
+        1 = /2 -> ±80 mV
+        2 = /4 -> ±160 mV
+        3 = /8 -> ±320 mV
+
+        The default of ±320 mV is the power-on reset value of the device.
+
+        In case the expected voltage drop across the shunt resistor is lower
+        one can adjust this to get more accurate readings.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+    badc:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Bus ADC configuration
+        0  = 9 bit -> 84 µs
+        1  = 10 bit -> 148 µs
+        2  = 11 bit -> 276 µs
+        3  = 12 bit -> 532 µs
+        9  = 12 bit - 2 sample averaging -> 1.06 ms
+        10 = 12 bit - 4 sample averaging -> 2.13 ms
+        11 = 12 bit - 8 sample averaging -> 4.26 ms
+        12 = 12 bit - 16 sample averaging -> 8.51 ms
+        13 = 12 bit - 32 sample averaging -> 17.02 ms
+        14 = 12 bit - 64 sample averaging -> 34.05 ms
+        15 = 12 bit - 128 sample averaging -> 68.10 ms
+
+        The default of 12 bit is the power-on reset value of the device.
+
+        Lowering the resolution of the ADC gives less accurate readings but
+        cuts down on conversion times.
+
+        Averaging over multiple samples gives more stable readings but adds
+        to overall conversion time.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 9
+        - 10
+        - 11
+        - 12
+        - 13
+        - 14
+        - 15
+    sadc:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Shunt ADC configuration
+        0  = 9 bit -> 84 µs
+        1  = 10 bit -> 148 µs
+        2  = 11 bit -> 276 µs
+        3  = 12 bit -> 532 µs
+        9  = 12 bit - 2 sample averaging -> 1.06 ms
+        10 = 12 bit - 4 sample averaging -> 2.13 ms
+        11 = 12 bit - 8 sample averaging -> 4.26 ms
+        12 = 12 bit - 16 sample averaging -> 8.51 ms
+        13 = 12 bit - 32 sample averaging -> 17.02 ms
+        14 = 12 bit - 64 sample averaging -> 34.05 ms
+        15 = 12 bit - 128 sample averaging -> 68.10 ms
+
+        The default of 12 bit is the power-on reset value of the device.
+
+        Lowering the resolution of the ADC gives less accurate readings but
+        cuts down on conversion times.
+
+        Averaging over multiple samples gives more stable readings but adds
+        to overall conversion time.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 9
+        - 10
+        - 11
+        - 12
+        - 13
+        - 14
+        - 15
diff --git a/dts/bindings/sensor/ti,ina230.yaml b/dts/bindings/sensor/ti,ina230.yaml
new file mode 100644
index 0000000000..f74997a327
--- /dev/null
+++ b/dts/bindings/sensor/ti,ina230.yaml
@@ -0,0 +1,36 @@
+#
+# Copyright 2021 The Chromium OS Authors
+# Copyright 2021 Grinn
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: |
+    TI INA230 and INA231 Bidirectional Current and Power Monitor.
+    The <include/dt-bindings/sensor/ina230.h> file should be included
+    in the DeviceTree and it provides macro that can be used for
+    initializing the configuration register.
+
+compatible: "ti,ina230"
+
+include: ti,ina23x-common.yaml
+
+properties:
+    mask:
+      type: int
+      required: false
+      default: 0
+      # default all alert sources to disabled
+      description: Mask register, default matches the power-on reset value
+
+    alert-limit:
+      type: int
+      required: false
+      default: 0
+      # default alert limit is 0V
+      description: Alert register, default matches the power-on reset value
+
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: IRQ Alert pin
diff --git a/dts/bindings/sensor/ti,ina237.yaml b/dts/bindings/sensor/ti,ina237.yaml
new file mode 100644
index 0000000000..04477888ca
--- /dev/null
+++ b/dts/bindings/sensor/ti,ina237.yaml
@@ -0,0 +1,23 @@
+#
+# Copyright 2021 Grinn
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: |
+    TI INA237 Bidirectional Current and Power Monitor.
+    The <include/dt-bindings/sensor/ina237.h> file should be included
+    in the DeviceTree and it provides macros that can be used for
+    initializing the configuration registers.
+
+compatible: "ti,ina237"
+
+include: ti,ina23x-common.yaml
+
+properties:
+    adc-config:
+      type: int
+      required: true
+      description: |
+        Value of the ADC configuration register (ADC conversion times,
+        averaging, operating mode and etc).
diff --git a/dts/bindings/sensor/ti,ina23x-common.yaml b/dts/bindings/sensor/ti,ina23x-common.yaml
new file mode 100644
index 0000000000..9e47919f92
--- /dev/null
+++ b/dts/bindings/sensor/ti,ina23x-common.yaml
@@ -0,0 +1,33 @@
+#
+# Copyright 2021 Grinn
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+include: i2c-device.yaml
+
+properties:
+    config:
+      type: int
+      required: true
+      description: |
+        Value of the configuration register
+        e.g shunt voltage and bus voltage ADC conversion
+        times and averaging, operating mode for INA230 or
+        delay for initial ADC conversion, shunt full scale range
+        for INA237.
+
+    current-lsb:
+      type: int
+      required: true
+      description: |
+        Value of Current LSB in milliamps. When set to 1mA,
+        Current is read in A, Bus Voltage in V, Shunt
+        Voltage in V, and Power in mW. Any other value
+        results in Current, Voltage, and Power registers
+        being read in counts.
+
+    rshunt:
+      type: int
+      required: true
+      description: Shunt resistor value in milliohms
diff --git a/dts/bindings/sensor/ti,opt3001.yaml b/dts/bindings/sensor/ti,opt3001.yaml
new file mode 100644
index 0000000000..6b38f6062a
--- /dev/null
+++ b/dts/bindings/sensor/ti,opt3001.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Actinius
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments OPT3001 ambient light sensor
+
+compatible: "ti,opt3001"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/ti,tmp007.yaml b/dts/bindings/sensor/ti,tmp007.yaml
new file mode 100644
index 0000000000..5e8bc806de
--- /dev/null
+++ b/dts/bindings/sensor/ti,tmp007.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    TMP007 Digital Temperature Sensor.  See datasheet at
+    https://cdn-shop.adafruit.com/datasheets/tmp007.pdf
+
+compatible: "ti,tmp007"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Identifies the ALERT signal, which is active-low open drain when
+        produced by the sensor.
diff --git a/dts/bindings/sensor/ti,tmp108.yaml b/dts/bindings/sensor/ti,tmp108.yaml
new file mode 100644
index 0000000000..a5752078be
--- /dev/null
+++ b/dts/bindings/sensor/ti,tmp108.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Jimmy Johnson <catch22@fastmail.net>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    TMP108 Digital Temperature Sensor.  See more info at
+    https://www.ti.com/product/TMP108
+
+compatible: "ti,tmp108"
+
+include: i2c-device.yaml
+
+properties:
+    alert-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Identifies the ALERT signal, which is active-low open drain when
+        produced by the sensor.
diff --git a/dts/bindings/sensor/ti,tmp112.yaml b/dts/bindings/sensor/ti,tmp112.yaml
new file mode 100644
index 0000000000..4e303803f2
--- /dev/null
+++ b/dts/bindings/sensor/ti,tmp112.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    TMP112 Digital Temperature Sensor.  See more info at
+    https://www.ti.com/product/TMP112
+
+compatible: "ti,tmp112"
+
+include: i2c-device.yaml
+
+properties:
+  conversion-rate:
+    description: Conversion rate in mHz (milli-Hertz)
+    type: int
+    default: 4000
+    enum:
+      - 250
+      - 1000
+      - 4000
+      - 8000
+  extended-mode:
+    description: When true use 13-bit data format allowing measuring temperature up to 128°C
+    type: boolean
diff --git a/dts/bindings/sensor/ti,tmp116.yaml b/dts/bindings/sensor/ti,tmp116.yaml
new file mode 100644
index 0000000000..0753b92efa
--- /dev/null
+++ b/dts/bindings/sensor/ti,tmp116.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2019 Centaur Analytics, Inc
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments TMP116 temperature sensor
+
+compatible: "ti,tmp116"
+
+bus: tmp116
+
+include: i2c-device.yaml
diff --git a/dts/bindings/sensor/vishay,vcnl4040.yaml b/dts/bindings/sensor/vishay,vcnl4040.yaml
new file mode 100644
index 0000000000..88b2760c44
--- /dev/null
+++ b/dts/bindings/sensor/vishay,vcnl4040.yaml
@@ -0,0 +1,88 @@
+# Copyright (c) 2020 Richard Osterloh
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    VCNL4040 proximity and ambient light sensor.  See datasheet at
+    https://www.vishay.com/docs/84274/vcnl4040.pdf
+
+compatible: "vishay,vcnl4040"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The INT pin signals that a programmable interrupt function
+        for ALS and PS with upper and lower thresholds has been
+        triggered. The sensor generates an active-low level signal
+        which remains asserted until the data is read.
+
+    led-current:
+      type: int
+      required: false
+      default: 50
+      # default of 50 mA is POR (0b000) for PS_MS[LED_I] register
+      description: LED current in mA
+      enum:
+        - 50
+        - 75
+        - 100
+        - 120
+        - 140
+        - 160
+        - 180
+        - 200
+
+    led-duty-cycle:
+      type: int
+      required: false
+      default: 40
+      # default of 40 Hz is POR (0b00) for PS_CONF1[PS_Duty] register
+      description: LED duty cycle in Hz
+      enum:
+        - 40
+        - 80
+        - 160
+        - 320
+
+    proximity-it:
+      type: string
+      required: false
+      default: "1"
+      # default of 1 is POR (0b000) for PS_CONF2[PS_IT] register
+      description: Proximity integration time in T
+      enum:
+        - "1"
+        - "1.5"
+        - "2"
+        - "2.5"
+        - "3"
+        - "3.5"
+        - "4"
+        - "8"
+
+    proximity-trigger:
+      type: string
+      required: false
+      default: "disabled"
+      # default of "disabled" is POR (0b00) for PS_CONF2[PS_INT] register
+      description: Proximity trigger type
+      enum:
+        - "disabled"
+        - "close"
+        - "away"
+        - "close-away"
+
+    als-it:
+      type: int
+      required: false
+      default: 80
+      # default of 80 is POR (0b00) for ALS_CONF[ALS_IT] register
+      description: ALS integration time in ms
+      enum:
+        - 80
+        - 160
+        - 320
+        - 640
diff --git a/dts/bindings/sensor/we,wsen-itds.yaml b/dts/bindings/sensor/we,wsen-itds.yaml
new file mode 100644
index 0000000000..90a58af624
--- /dev/null
+++ b/dts/bindings/sensor/we,wsen-itds.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2020 Linumiz
+
+description: WSEN-ITDS 3-axis accel sensor
+
+compatible: "we,wsen-itds"
+
+include: i2c-device.yaml
+
+properties:
+    int-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        This property specifies the connection for INT0, the driver maps
+        all interrupts to INT0 as default. The signal to output high when
+        data produced by the sensor.
+
+    odr:
+      type: string
+      required: true
+      description: Output data rate in Hz
+      enum:
+        - "1.6"
+        - "12.5"
+        - "25"
+        - "50"
+        - "100"
+        - "200"
+        - "400"
+        - "800"
+        - "1600"
+
+    op-mode:
+      type: string
+      required: true
+      description: Operating mode of sensor
+      enum:
+        - "low-power"
+        - "normal"
+        - "high-perf"
diff --git a/dts/bindings/sensor/winsen,mhz19b.yaml b/dts/bindings/sensor/winsen,mhz19b.yaml
new file mode 100644
index 0000000000..3a503f427b
--- /dev/null
+++ b/dts/bindings/sensor/winsen,mhz19b.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2021 G-Technologies Sdn. Bhd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Winsen MHZ-19B CO2 Sensor
+
+compatible: "winsen,mhz19b"
+
+include: uart-device.yaml
+
+properties:
+  maximum-range:
+    type: int
+    required: true
+    description: CO2 detection range.
+    enum:
+      - 2000
+      - 5000
+      - 10000
+
+  abc-on:
+    type: boolean
+    required: false
+    description: |
+      Enable ABC self-calibration function
diff --git a/dts/bindings/serial/altr,jtag-uart.yaml b/dts/bindings/serial/altr,jtag-uart.yaml
new file mode 100644
index 0000000000..fd10756aa3
--- /dev/null
+++ b/dts/bindings/serial/altr,jtag-uart.yaml
@@ -0,0 +1,9 @@
+description: Altera JTAG UART
+
+compatible: "altr,jtag-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/serial/arm,cmsdk-uart.yaml b/dts/bindings/serial/arm,cmsdk-uart.yaml
new file mode 100644
index 0000000000..667670c443
--- /dev/null
+++ b/dts/bindings/serial/arm,cmsdk-uart.yaml
@@ -0,0 +1,12 @@
+description: ARM CMSDK UART
+
+compatible: "arm,cmsdk-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/arm,pl011.yaml b/dts/bindings/serial/arm,pl011.yaml
new file mode 100644
index 0000000000..5950410539
--- /dev/null
+++ b/dts/bindings/serial/arm,pl011.yaml
@@ -0,0 +1,12 @@
+description: ARM PL011 UART
+
+compatible: "arm,pl011"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/arm,sbsa-uart.yaml b/dts/bindings/serial/arm,sbsa-uart.yaml
new file mode 100644
index 0000000000..b2405b3835
--- /dev/null
+++ b/dts/bindings/serial/arm,sbsa-uart.yaml
@@ -0,0 +1,12 @@
+description: ARM SBSA UART
+
+compatible: "arm,sbsa-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
diff --git a/dts/bindings/serial/atmel,sam-uart.yaml b/dts/bindings/serial/atmel,sam-uart.yaml
new file mode 100644
index 0000000000..35f8c24783
--- /dev/null
+++ b/dts/bindings/serial/atmel,sam-uart.yaml
@@ -0,0 +1,30 @@
+description: SAM family UART
+
+compatible: "atmel,sam-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      description: |
+        PIO pin configuration for URXD & UTRD signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the UART on SAM3x would be
+           pinctrl-0 = <&pa8a_uart_urxd &pa9a_uart_utxd>;
+
+      required: true
diff --git a/dts/bindings/serial/atmel,sam-usart.yaml b/dts/bindings/serial/atmel,sam-usart.yaml
new file mode 100644
index 0000000000..74f3a41517
--- /dev/null
+++ b/dts/bindings/serial/atmel,sam-usart.yaml
@@ -0,0 +1,30 @@
+description: Atmel SAM family USART
+
+compatible: "atmel,sam-usart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      description: |
+        PIO pin configuration for RXD & TRD signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the USART0 on SAME7x would be
+           pinctrl-0 = <&pb0c_usart0_rxd0 &pb1c_usart0_txd0>;
+
+      required: true
diff --git a/dts/bindings/serial/atmel,sam0-uart.yaml b/dts/bindings/serial/atmel,sam0-uart.yaml
new file mode 100644
index 0000000000..2f016d8968
--- /dev/null
+++ b/dts/bindings/serial/atmel,sam0-uart.yaml
@@ -0,0 +1,62 @@
+description: Atmel SAM0 SERCOM UART driver
+
+compatible: "atmel,sam0-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    clock-names:
+      required: true
+
+    rxpo:
+      type: int
+      required: true
+      description: Receive Data Pinout
+
+    txpo:
+      type: int
+      required: true
+      description: Transmit Data Pinout
+
+    collision-detection:
+      type: boolean
+      description: Enable collision detection for half-duplex mode.
+
+    pinctrl-0:
+      type: phandles
+      description: |
+        PORT pin configuration for RXD & TRD signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the SERCOM0 on SAMR21 would be
+           pinctrl-0 = <&pa5d_sercom0_pad1 &pa4d_sercom0_pad0>;
+
+      required: true
+
+    dmas:
+      description: |
+        Optional TX & RX dma specifiers.  Each specifier will have a phandle
+        reference to the dmac controller, the channel number, and peripheral
+        trigger source.
+
+        For example dmas for TX, RX on SERCOM3
+           dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
+
+    dma-names:
+      description: |
+        Required if the dmas property exists.  This should be "tx" and "rx"
+        to match the dmas property.
+
+        For example
+           dma-names = "tx", "rx";
diff --git a/dts/bindings/serial/cypress,psoc6-uart.yaml b/dts/bindings/serial/cypress,psoc6-uart.yaml
new file mode 100644
index 0000000000..37fcac07a2
--- /dev/null
+++ b/dts/bindings/serial/cypress,psoc6-uart.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2018, Cypress
+# Copyright (c) 2020, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress SCB[UART]
+
+compatible: "cypress,psoc6-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      description: |
+        Port pin configuration for RX & TX signals.  We expect that the
+        phandles will reference pinctrl nodes.  These nodes will have a
+        nodelabel that matches the Cypress SoC HAL defines and be of the
+        form p<port>_<pin>_<periph><inst>_<signal>.
+
+        For example the UART on PSoC-63 Pioneer Kit would be
+           pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>;
+
+      required: true
diff --git a/dts/bindings/serial/espressif,esp32-uart.yaml b/dts/bindings/serial/espressif,esp32-uart.yaml
new file mode 100644
index 0000000000..6c056a5cd2
--- /dev/null
+++ b/dts/bindings/serial/espressif,esp32-uart.yaml
@@ -0,0 +1,32 @@
+description: ESP32 UART
+
+compatible: "espressif,esp32-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    tx-pin:
+      type: int
+      description: TX pin
+      required: true
+
+    rx-pin:
+      type: int
+      description: RX pin
+      required: true
+
+    rts-pin:
+      type: int
+      description: RTS pin
+      required: false
+
+    cts-pin:
+      type: int
+      description: CTS pin
+      required: false
diff --git a/dts/bindings/serial/gaisler,apbuart.yaml b/dts/bindings/serial/gaisler,apbuart.yaml
new file mode 100644
index 0000000000..338d737efd
--- /dev/null
+++ b/dts/bindings/serial/gaisler,apbuart.yaml
@@ -0,0 +1,9 @@
+description: GRLIB APBUART
+
+compatible: "gaisler,apbuart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/serial/gd,gd32-usart.yaml b/dts/bindings/serial/gd,gd32-usart.yaml
new file mode 100644
index 0000000000..e93455b54c
--- /dev/null
+++ b/dts/bindings/serial/gd,gd32-usart.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: GigaDevice USART
+
+compatible: "gd,gd32-usart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    rcu-periph-clock:
+      type: int
+      description: Reset Control Unit Peripheral Clock ID
+      required: true
diff --git a/dts/bindings/serial/infineon,xmc4xxx-uart.yaml b/dts/bindings/serial/infineon,xmc4xxx-uart.yaml
new file mode 100644
index 0000000000..7e689e81aa
--- /dev/null
+++ b/dts/bindings/serial/infineon,xmc4xxx-uart.yaml
@@ -0,0 +1,9 @@
+description: INFINEON XMC4XXX UART
+
+compatible: "infineon,xmc4xxx-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/serial/ite,it8xxx2-uart.yaml b/dts/bindings/serial/ite,it8xxx2-uart.yaml
new file mode 100644
index 0000000000..e3a8b8a331
--- /dev/null
+++ b/dts/bindings/serial/ite,it8xxx2-uart.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE, IT8XXX2-UART node
+
+compatible: "ite,it8xxx2-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    port-num:
+      type: int
+      required: true
+      description: Ordinal identifying the port
+
+    gpios:
+      type: phandle-array
+      required: true
+
+    uart-dev:
+      type: phandle
+      required: true
+      description: Get the handle of the UART device
diff --git a/dts/bindings/serial/litex,uart0.yaml b/dts/bindings/serial/litex,uart0.yaml
new file mode 100644
index 0000000000..c798d88080
--- /dev/null
+++ b/dts/bindings/serial/litex,uart0.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX UART
+
+compatible: "litex,uart0"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/microchip,xec-uart.yaml b/dts/bindings/serial/microchip,xec-uart.yaml
new file mode 100644
index 0000000000..fd05b7735e
--- /dev/null
+++ b/dts/bindings/serial/microchip,xec-uart.yaml
@@ -0,0 +1,43 @@
+description: Microchip XEC UART
+
+compatible: "microchip,xec-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    ldn:
+      type: int
+      required: true
+      description: logical device number
+
+    girqs:
+      type: array
+      required: true
+      description: UART GIRQ and bit position in EC interrupt aggregator
+
+    pcrs:
+      type: array
+      required: true
+      description: UART Power Clock Reset(PCR) register index and bit position
+
+    "#girq-cells":
+      type: int
+      const: 2
+
+    "#pcr-cells":
+      type: int
+      const: 2
+
+girq-cells:
+    - girq_num
+    - bitpos
+
+pcr-cells:
+    - reg_idx
+    - bitpos
diff --git a/dts/bindings/serial/microsemi,coreuart.yaml b/dts/bindings/serial/microsemi,coreuart.yaml
new file mode 100644
index 0000000000..4a56369ff3
--- /dev/null
+++ b/dts/bindings/serial/microsemi,coreuart.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive UART
+
+compatible: "microsemi,coreuart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/serial/neorv32-uart.yaml b/dts/bindings/serial/neorv32-uart.yaml
new file mode 100644
index 0000000000..c60e6066b9
--- /dev/null
+++ b/dts/bindings/serial/neorv32-uart.yaml
@@ -0,0 +1,24 @@
+description: NEORV32 UART
+
+compatible: "neorv32-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    interrupt-names:
+      required: true
+
+    current-speed:
+      required: true
+
+    syscon:
+      type: phandle
+      required: true
+      description: |
+        phandle to syscon (NEORV32 SYSINFO) node.
diff --git a/dts/bindings/serial/nordic,nrf-uart-common.yaml b/dts/bindings/serial/nordic,nrf-uart-common.yaml
new file mode 100644
index 0000000000..07bb946332
--- /dev/null
+++ b/dts/bindings/serial/nordic,nrf-uart-common.yaml
@@ -0,0 +1,99 @@
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    disable-rx:
+      type: boolean
+      description: |
+        Disable UART reception capabilities (only required to disable reception
+        if CONFIG_PINCTRL is enabled).
+
+    current-speed:
+      description: |
+        Initial baud rate setting for UART. Only a fixed set of baud
+        rates are selectable on these devices.
+      enum:
+        - 1200
+        - 2400
+        - 4800
+        - 9600
+        - 14400
+        - 19200
+        - 28800
+        - 31250
+        - 38400
+        - 56000
+        - 57600
+        - 76800
+        - 115200
+        - 230400
+        - 250000
+        - 460800
+        - 921600
+        - 1000000
+
+    tx-pin:
+      type: int
+      description: |
+        IMPORTANT: This option will only be used if the new pin control driver
+        is not enabled. It will be deprecated in the future.
+
+        The TX pin to use.
+
+        For pins P0.0 through P0.31, use the pin number. For example,
+        to use P0.16 for TX, set:
+
+          tx-pin = <16>;
+
+        For pins P1.0 through P1.31, add 32 to the pin number. For
+        example, to use P1.2 for TX, set:
+
+          tx-pin = <34>;  /* 32 + 2 */
+
+    rx-pin:
+      type: int
+      description: |
+        IMPORTANT: This option will only be used if the new pin control driver
+        is not enabled. It will be deprecated in the future.
+
+        The RX pin to use. The pin numbering scheme is the same as the
+        tx-pin property's.
+
+    rts-pin:
+      type: int
+      description: |
+        IMPORTANT: This option will only be used if the new pin control driver
+        is not enabled. It will be deprecated in the future.
+
+        The RTS pin to use. The pin numbering scheme is the same as the
+        tx-pin property's.
+
+    cts-pin:
+      type: int
+      description: |
+        IMPORTANT: This option will only be used if the new pin control driver
+        is not enabled. It will be deprecated in the future.
+
+        The CTS pin to use. The pin numbering scheme is the same as the
+        tx-pin property's.
+
+    rx-pull-up:
+      type: boolean
+      description: |
+        IMPORTANT: This option will only be used if the new pin control driver
+        is not enabled. It will be deprecated in the future.
+
+        Enable pull-up resistor on the RX pin.
+
+    cts-pull-up:
+      type: boolean
+      description: |
+        IMPORTANT: This option will only be used if the new pin control driver
+        is not enabled. It will be deprecated in the future.
+
+        Enable pull-up resistor on the CTS pin.
diff --git a/dts/bindings/serial/nordic,nrf-uart.yaml b/dts/bindings/serial/nordic,nrf-uart.yaml
new file mode 100644
index 0000000000..1a5e55a9f3
--- /dev/null
+++ b/dts/bindings/serial/nordic,nrf-uart.yaml
@@ -0,0 +1,10 @@
+description: |
+  Nordic nRF family UART.
+
+  This is the binding for the peripheral without EasyDMA support.
+  See the "nordic,nrf-uarte" binding for UARTE, i.e. UART with
+  EasyDMA.
+
+compatible: "nordic,nrf-uart"
+
+include: nordic,nrf-uart-common.yaml
diff --git a/dts/bindings/serial/nordic,nrf-uarte.yaml b/dts/bindings/serial/nordic,nrf-uarte.yaml
new file mode 100644
index 0000000000..e094ee505e
--- /dev/null
+++ b/dts/bindings/serial/nordic,nrf-uarte.yaml
@@ -0,0 +1,5 @@
+description: Nordic nRF family UARTE (UART with EasyDMA)
+
+compatible: "nordic,nrf-uarte"
+
+include: nordic,nrf-uart-common.yaml
diff --git a/dts/bindings/serial/ns16550.yaml b/dts/bindings/serial/ns16550.yaml
new file mode 100644
index 0000000000..b9f2f56ffe
--- /dev/null
+++ b/dts/bindings/serial/ns16550.yaml
@@ -0,0 +1,24 @@
+description: ns16550 UART
+
+compatible: "ns16550"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    reg-shift:
+      type: int
+      required: false
+      description: quantity to shift the register offsets by
+
+    pcp:
+      type: int
+      required: false
+      description: custom clock (PRV_CLOCK_PARAMS, if supported)
+
+    dlf:
+      type: int
+      required: false
+      description: divisor latch fraction (DLF, if supported)
diff --git a/dts/bindings/serial/nuvoton,npcx-uart.yaml b/dts/bindings/serial/nuvoton,npcx-uart.yaml
new file mode 100644
index 0000000000..d0e0e86d14
--- /dev/null
+++ b/dts/bindings/serial/nuvoton,npcx-uart.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-UART node
+
+compatible: "nuvoton,npcx-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+        required: true
+    clocks:
+        required: true
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of pinmux controllers
+    uart-rx:
+        type: phandle
+        required: true
+        description: |
+            Mapping table between Wake-Up Input (WUI) and uart rx START signal.
+
+            For example the WUI mapping on NPCX7 UART1 would be
+               uart-rx = <&wui_cr_sin1>;
diff --git a/dts/bindings/serial/nuvoton,numicro-uart.yaml b/dts/bindings/serial/nuvoton,numicro-uart.yaml
new file mode 100644
index 0000000000..7592206029
--- /dev/null
+++ b/dts/bindings/serial/nuvoton,numicro-uart.yaml
@@ -0,0 +1,9 @@
+description: NUVOTON NUMICRO FAMILY UART
+
+compatible: "nuvoton,numicro-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/serial/nxp,imx-iuart.yaml b/dts/bindings/serial/nxp,imx-iuart.yaml
new file mode 100644
index 0000000000..546f31653b
--- /dev/null
+++ b/dts/bindings/serial/nxp,imx-iuart.yaml
@@ -0,0 +1,16 @@
+description: |
+    This binding gives a base representation of the NXP iMX IUART
+
+compatible: "nxp,imx-iuart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    clocks:
+      required: true
diff --git a/dts/bindings/serial/nxp,imx-uart.yaml b/dts/bindings/serial/nxp,imx-uart.yaml
new file mode 100644
index 0000000000..ce8f1b8a09
--- /dev/null
+++ b/dts/bindings/serial/nxp,imx-uart.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: iMX UART
+
+compatible: "nxp,imx-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    modem-mode:
+     type: int
+     required: true
+     description: Set the UART Port to modem mode 0 (dce) 64 (dte)
+
+    rdc:
+     type: int
+     required: true
+     description: Set the RDC permission for this peripheral
diff --git a/dts/bindings/serial/nxp,kinetis-lpsci.yaml b/dts/bindings/serial/nxp,kinetis-lpsci.yaml
new file mode 100644
index 0000000000..d74ec03f09
--- /dev/null
+++ b/dts/bindings/serial/nxp,kinetis-lpsci.yaml
@@ -0,0 +1,16 @@
+description: Kinetis LPSCI UART
+
+compatible: "nxp,kinetis-lpsci"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
diff --git a/dts/bindings/serial/nxp,kinetis-lpuart.yaml b/dts/bindings/serial/nxp,kinetis-lpuart.yaml
new file mode 100644
index 0000000000..afcde99e06
--- /dev/null
+++ b/dts/bindings/serial/nxp,kinetis-lpuart.yaml
@@ -0,0 +1,12 @@
+description: Kinetis LPUART
+
+compatible: "nxp,kinetis-lpuart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/nxp,kinetis-uart.yaml b/dts/bindings/serial/nxp,kinetis-uart.yaml
new file mode 100644
index 0000000000..ae3ed052e8
--- /dev/null
+++ b/dts/bindings/serial/nxp,kinetis-uart.yaml
@@ -0,0 +1,19 @@
+description: Kinetis UART
+
+compatible: "nxp,kinetis-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
diff --git a/dts/bindings/serial/nxp,lpc-usart.yaml b/dts/bindings/serial/nxp,lpc-usart.yaml
new file mode 100644
index 0000000000..18fcf95795
--- /dev/null
+++ b/dts/bindings/serial/nxp,lpc-usart.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC USART
+
+compatible: "nxp,lpc-usart"
+
+include: [uart-controller.yaml, "nxp,lpc-flexcomm.yaml"]
diff --git a/dts/bindings/serial/nxp,lpc11u6x-uart.yaml b/dts/bindings/serial/nxp,lpc11u6x-uart.yaml
new file mode 100644
index 0000000000..1be3a2978d
--- /dev/null
+++ b/dts/bindings/serial/nxp,lpc11u6x-uart.yaml
@@ -0,0 +1,25 @@
+description: LPC11U6X UART
+
+compatible: "nxp,lpc11u6x-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    pinmuxs:
+      type: phandle-array
+      required: true
+      description: RX and TX pinmux
+
+    pinmux-names:
+      type: string-array
+      required: true
+      description: UART pins names
diff --git a/dts/bindings/serial/openisa,rv32m1-lpuart.yaml b/dts/bindings/serial/openisa,rv32m1-lpuart.yaml
new file mode 100644
index 0000000000..a88da82f9e
--- /dev/null
+++ b/dts/bindings/serial/openisa,rv32m1-lpuart.yaml
@@ -0,0 +1,12 @@
+description: OpenISA LPUART
+
+compatible: "openisa,rv32m1-lpuart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/renesas,rcar-scif.yaml b/dts/bindings/serial/renesas,rcar-scif.yaml
new file mode 100644
index 0000000000..bdc76844cc
--- /dev/null
+++ b/dts/bindings/serial/renesas,rcar-scif.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021, IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+#
+description: Renesas R-Car UART controller
+
+compatible: "renesas,rcar-scif"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
diff --git a/dts/bindings/serial/segger,rtt-uart.yaml b/dts/bindings/serial/segger,rtt-uart.yaml
new file mode 100644
index 0000000000..698b72b0ed
--- /dev/null
+++ b/dts/bindings/serial/segger,rtt-uart.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2020, CSIRO.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Segger RTT UART
+
+compatible: "segger,rtt-uart"
+
+include: uart-controller.yaml
+
+properties:
+    tx-buffer-size:
+      type: int
+      default: 1024
+      description: |
+        Size of the RTT up buffer for transmission
+        Not used for RTT channel 0 as channel 0 is initialized at compile time,
+        see SEGGER_RTT_BUFFER_SIZE_UP.
+      required: false
+
+    rx-buffer-size:
+      type: int
+      default: 16
+      description: |
+        Size of the RTT down buffer for reception
+        Not used for RTT channel 0 as channel 0 is initialized at compile time,
+        see SEGGER_RTT_BUFFER_SIZE_DOWN.
+      required: false
diff --git a/dts/bindings/serial/sifive,uart0.yaml b/dts/bindings/serial/sifive,uart0.yaml
new file mode 100644
index 0000000000..d438a678f4
--- /dev/null
+++ b/dts/bindings/serial/sifive,uart0.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018, SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive UART
+
+compatible: "sifive,uart0"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/silabs,gecko-leuart.yaml b/dts/bindings/serial/silabs,gecko-leuart.yaml
new file mode 100644
index 0000000000..bfdb6b9bd4
--- /dev/null
+++ b/dts/bindings/serial/silabs,gecko-leuart.yaml
@@ -0,0 +1,30 @@
+description: Gecko LEUART
+
+compatible: "silabs,gecko-leuart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: peripheral ID
+
+    # Note: Not all SoC series support setting individual pin location. If this
+    # is a case all location-* properties need to have identical value.
+
+    location-rx:
+      type: array
+      required: true
+      description: RX pin configuration defined as <location port pin>
+
+    location-tx:
+      type: array
+      required: true
+      description: TX pin configuration defined as <location port pin>
diff --git a/dts/bindings/serial/silabs,gecko-uart.yaml b/dts/bindings/serial/silabs,gecko-uart.yaml
new file mode 100644
index 0000000000..a03fd6b666
--- /dev/null
+++ b/dts/bindings/serial/silabs,gecko-uart.yaml
@@ -0,0 +1,30 @@
+description: Gecko UART
+
+compatible: "silabs,gecko-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: peripheral ID
+
+    # Note: Not all SoC series support setting individual pin location. If this
+    # is a case all location-* properties need to have identical value.
+
+    location-rx:
+      type: array
+      required: true
+      description: RX pin configuration defined as <location port pin>
+
+    location-tx:
+      type: array
+      required: true
+      description: TX pin configuration defined as <location port pin>
diff --git a/dts/bindings/serial/silabs,gecko-usart.yaml b/dts/bindings/serial/silabs,gecko-usart.yaml
new file mode 100644
index 0000000000..f9c420c04a
--- /dev/null
+++ b/dts/bindings/serial/silabs,gecko-usart.yaml
@@ -0,0 +1,40 @@
+description: Gecko USART
+
+compatible: "silabs,gecko-usart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: peripheral ID
+
+    # Note: Not all SoC series support setting individual pin location. If this
+    # is a case all location-* properties need to have identical value.
+
+    location-rx:
+      type: array
+      required: true
+      description: RX pin configuration defined as <location port pin>
+
+    location-tx:
+      type: array
+      required: true
+      description: TX pin configuration defined as <location port pin>
+
+    location-rts:
+      type: array
+      required: false
+      description: RTS pin configuration defined as <location port pin>
+
+    location-cts:
+      type: array
+      required: false
+      description: CTS pin configuration defined as <location port pin>
diff --git a/dts/bindings/serial/snps,nsim-uart.yaml b/dts/bindings/serial/snps,nsim-uart.yaml
new file mode 100644
index 0000000000..f68d27cdcb
--- /dev/null
+++ b/dts/bindings/serial/snps,nsim-uart.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys ARC nSIM UART
+
+compatible: "snps,nsim-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/serial/st,stm32-lpuart.yaml b/dts/bindings/serial/st,stm32-lpuart.yaml
new file mode 100644
index 0000000000..5046d43de7
--- /dev/null
+++ b/dts/bindings/serial/st,stm32-lpuart.yaml
@@ -0,0 +1,21 @@
+description: STM32 LPUART
+
+compatible: "st,stm32-lpuart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
diff --git a/dts/bindings/serial/st,stm32-uart.yaml b/dts/bindings/serial/st,stm32-uart.yaml
new file mode 100644
index 0000000000..6dba470442
--- /dev/null
+++ b/dts/bindings/serial/st,stm32-uart.yaml
@@ -0,0 +1,18 @@
+description: STM32 UART
+
+compatible: "st,stm32-uart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
diff --git a/dts/bindings/serial/st,stm32-usart.yaml b/dts/bindings/serial/st,stm32-usart.yaml
new file mode 100644
index 0000000000..8d82a82715
--- /dev/null
+++ b/dts/bindings/serial/st,stm32-usart.yaml
@@ -0,0 +1,18 @@
+description: STM32 USART
+
+compatible: "st,stm32-usart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
diff --git a/dts/bindings/serial/telink,b91-uart.yaml b/dts/bindings/serial/telink,b91-uart.yaml
new file mode 100644
index 0000000000..fffb4f0e76
--- /dev/null
+++ b/dts/bindings/serial/telink,b91-uart.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021, Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink B91 UART
+
+compatible: "telink,b91-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
diff --git a/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml b/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml
new file mode 100644
index 0000000000..c6f4ad5fb5
--- /dev/null
+++ b/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2019 Brett Witherspoon
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC13xx / CC26xx UART node
+
+compatible: "ti,cc13xx-cc26xx-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    tx-pin:
+      type: array
+      required: true
+      description: TX pin
+
+    rx-pin:
+      type: array
+      required: true
+      description: RX pin
diff --git a/dts/bindings/serial/ti,cc32xx-uart.yaml b/dts/bindings/serial/ti,cc32xx-uart.yaml
new file mode 100644
index 0000000000..e8b480b365
--- /dev/null
+++ b/dts/bindings/serial/ti,cc32xx-uart.yaml
@@ -0,0 +1,12 @@
+description: TI CC32XX UART
+
+compatible: "ti,cc32xx-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/ti,msp432p4xx-uart.yaml b/dts/bindings/serial/ti,msp432p4xx-uart.yaml
new file mode 100644
index 0000000000..9d6213c85d
--- /dev/null
+++ b/dts/bindings/serial/ti,msp432p4xx-uart.yaml
@@ -0,0 +1,12 @@
+description: TI MSP432P4XX UART
+
+compatible: "ti,msp432p4xx-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/ti,stellaris-uart.yaml b/dts/bindings/serial/ti,stellaris-uart.yaml
new file mode 100644
index 0000000000..c5b1276908
--- /dev/null
+++ b/dts/bindings/serial/ti,stellaris-uart.yaml
@@ -0,0 +1,12 @@
+description: TI Stellaris UART
+
+compatible: "ti,stellaris-uart"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/serial/uart-controller.yaml b/dts/bindings/serial/uart-controller.yaml
new file mode 100644
index 0000000000..d2674e14d9
--- /dev/null
+++ b/dts/bindings/serial/uart-controller.yaml
@@ -0,0 +1,31 @@
+# Common fields for UART controllers
+
+include: base.yaml
+
+bus: uart
+
+properties:
+    clock-frequency:
+      type: int
+      required: false
+      description: Clock frequency information for UART operation
+    current-speed:
+      type: int
+      required: false
+      description: Initial baud rate setting for UART
+    label:
+      required: true
+    hw-flow-control:
+      type: boolean
+      required: false
+      description: Set to enable RTS/CTS flow control at boot time
+    parity:
+      required: false
+      type: string
+      description: |
+        Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
+        and 2 for even parity. Default to none if not specified.
+      enum:
+        - "none"
+        - "odd"
+        - "even"
diff --git a/dts/bindings/serial/uart-device.yaml b/dts/bindings/serial/uart-device.yaml
new file mode 100644
index 0000000000..f87d6e94da
--- /dev/null
+++ b/dts/bindings/serial/uart-device.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for UART devices
+
+include: base.yaml
+
+on-bus: uart
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/serial/xlnx,xps-uartlite-1.00.a.yaml b/dts/bindings/serial/xlnx,xps-uartlite-1.00.a.yaml
new file mode 100644
index 0000000000..85516108fc
--- /dev/null
+++ b/dts/bindings/serial/xlnx,xps-uartlite-1.00.a.yaml
@@ -0,0 +1,9 @@
+description: Xilinx UART Lite IP
+
+compatible: "xlnx,xps-uartlite-1.00.a"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/serial/xlnx,xuartps.yaml b/dts/bindings/serial/xlnx,xuartps.yaml
new file mode 100644
index 0000000000..de5239ab6d
--- /dev/null
+++ b/dts/bindings/serial/xlnx,xuartps.yaml
@@ -0,0 +1,9 @@
+description: Xilinx PS UART
+
+compatible: "xlnx,xuartps"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/serial/zephyr,cdc-acm-uart.yaml b/dts/bindings/serial/zephyr,cdc-acm-uart.yaml
new file mode 100644
index 0000000000..7afe390cdb
--- /dev/null
+++ b/dts/bindings/serial/zephyr,cdc-acm-uart.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: USB CDC ACM UART
+
+compatible: "zephyr,cdc-acm-uart"
+
+include: uart-controller.yaml
+
+on-bus: usb
diff --git a/dts/bindings/serial/zephyr,native-posix-uart.yaml b/dts/bindings/serial/zephyr,native-posix-uart.yaml
new file mode 100644
index 0000000000..7cd8d186e8
--- /dev/null
+++ b/dts/bindings/serial/zephyr,native-posix-uart.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Jan Van Winkel (jan.van_winkel@dxplore.eu)
+# SPDX-License-Identifier: Apache-2.0
+
+description: Native POSIX UART
+
+compatible: "zephyr,native-posix-uart"
+
+include: uart-controller.yaml
diff --git a/dts/bindings/spi/atmel,sam-spi.yaml b/dts/bindings/spi/atmel,sam-spi.yaml
new file mode 100644
index 0000000000..764d85e687
--- /dev/null
+++ b/dts/bindings/spi/atmel,sam-spi.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2018, qianfan Zhao
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM SPI controller
+
+compatible: "atmel,sam-spi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
+      description: |
+        PIO pin configuration for the various SPI signals that includes
+        MISO, MOSI, SPCK, and possibly various chip selects signals.  We
+        expect that the phandles will reference pinctrl nodes.  These
+        nodes will have a nodelabel that matches the Atmel SoC HAL defines
+        and be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the SPI on SAME7x would be
+           pinctrl-0 = <&pd20b_spi0_miso &pd21b_spi0_mosi &pd22b_spi0_spck>;
diff --git a/dts/bindings/spi/atmel,sam0-spi.yaml b/dts/bindings/spi/atmel,sam0-spi.yaml
new file mode 100644
index 0000000000..9dd13c6791
--- /dev/null
+++ b/dts/bindings/spi/atmel,sam0-spi.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2018, Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 SERCOM SPI controller
+
+compatible: "atmel,sam0-spi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+    clock-names:
+      required: true
+
+    dipo:
+      type: int
+      required: true
+      description: Data In Pinout
+
+    dopo:
+      type: int
+      required: true
+      description: Data Out Pinout
+
+    dmas:
+      description: |
+        Optional TX & RX dma specifiers.  Each specifier will have a phandle
+        reference to the dmac controller, the channel number, and peripheral
+        trigger source.
+
+        For example dmas for TX, RX on SERCOM3
+           dmas = <&dmac 0 0xb>, <&dmac 1 0xa>;
+
+    dma-names:
+      description: |
+        Required if the dmas property exists.  This should be "tx" and "rx"
+        to match the dmas property.
+
+        For example
+           dma-names = "tx", "rx";
diff --git a/dts/bindings/spi/cypress,psoc6-spi.yaml b/dts/bindings/spi/cypress,psoc6-spi.yaml
new file mode 100644
index 0000000000..e496c20e2f
--- /dev/null
+++ b/dts/bindings/spi/cypress,psoc6-spi.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress SBC[SPI]
+
+compatible: "cypress,psoc6-spi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      description: |
+        Port pin configuration for the various SPI signals that includes
+        MISO, MOSI, SCK, and possibly various chip selects signals.  We
+        expect that the phandles will reference pinctrl nodes.  These
+        nodes will have a nodelabel that matches the Cypress SoC HAL defines
+        and be of the form p<port>_<pin>_<periph><inst>_<signal>.
+
+        For example the SPI on PSoC-63 Pioneer Kit would be
+           pinctrl-0 = <&p12_0_spi6_mosi &p12_1_spi6_miso &p12_2_spi6_clk &p12_3_spi6_sel0>;
+
+      required: true
diff --git a/dts/bindings/spi/espressif,esp32-spi.yaml b/dts/bindings/spi/espressif,esp32-spi.yaml
new file mode 100644
index 0000000000..a765ea4046
--- /dev/null
+++ b/dts/bindings/spi/espressif,esp32-spi.yaml
@@ -0,0 +1,79 @@
+description: ESP32 SPI
+
+compatible: "espressif,esp32-spi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    miso-pin:
+      type: int
+      description: MISO pin
+      required: true
+
+    mosi-pin:
+      type: int
+      description: MOSI pin
+      required: true
+
+    sclk-pin:
+      type: int
+      description: SPI generated clock pin
+      required: true
+
+    csel-pin:
+      type: int
+      description: chip select pin
+      required: true
+
+    use-iomux:
+      type: boolean
+      required: false
+      description: |
+        Support IO muxing for the target SPI peripheral pins
+
+        Some SPI interfaces are not allowed to mux its pins
+
+    half-duplex:
+      type: boolean
+      required: false
+      description: |
+        Enable half-duplex communication mode.
+
+        Transmit data before receiving it, instead of simultaneously
+
+    dummy-comp:
+      type: boolean
+      required: false
+      description: Enable dummy SPI compensation cycles
+
+    sio:
+      type: boolean
+      required: false
+      description: |
+        Enable 3-wire mode
+
+        Use MOSI for both sending and receiving data
+
+    dma:
+      type: boolean
+      required: false
+      description: Enable SPI DMA support
+
+    clk-as-cs:
+      type: boolean
+      required: false
+      description: |
+        Support to toggle the CS while the clock toggles
+
+        Output clock on CS line if CS is active
+
+    positive-cs:
+      type: boolean
+      required: false
+      description: Make CS positive during a transaction instead of negative
diff --git a/dts/bindings/spi/ite,it8xxx2-sspi.yaml b/dts/bindings/spi/ite,it8xxx2-sspi.yaml
new file mode 100644
index 0000000000..0653617b9f
--- /dev/null
+++ b/dts/bindings/spi/ite,it8xxx2-sspi.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: IT8XXX2 SPI
+
+compatible: "ite,it8xxx2-sspi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/spi/litex,spi.yaml b/dts/bindings/spi/litex,spi.yaml
new file mode 100644
index 0000000000..31c134b05e
--- /dev/null
+++ b/dts/bindings/spi/litex,spi.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX SPI
+
+compatible: "litex,spi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+        required: true
diff --git a/dts/bindings/spi/microchip,xec-qmspi-ldma.yaml b/dts/bindings/spi/microchip,xec-qmspi-ldma.yaml
new file mode 100644
index 0000000000..baa2b24c9a
--- /dev/null
+++ b/dts/bindings/spi/microchip,xec-qmspi-ldma.yaml
@@ -0,0 +1,106 @@
+# Copyright (c) 2018, Google LLC.
+# Copyright (c) 2021, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC QMSPI controller with local DMA
+
+compatible: "microchip,xec-qmspi-ldma"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    girqs:
+      type: array
+      required: true
+      description: |
+        An array of integers encoding each interrupt signal connection.
+        This information includes the aggregated GIRQ number, GIRQ bit
+        position, aggregated GIRQ NVIC connection, and direct NVIC
+        connection of the GIRQ bit.
+
+    pcrs:
+      type: array
+      required: true
+      description: |
+        A two entry integer array containing the QMSPI PCR sleep register
+        index and bit position.
+
+    lines:
+      type: int
+      required: false
+      description: |
+        QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
+        MOSI and MISO or half-duplex on MOSI only. Lines set to 2
+        or 4 indicate dual or quad I/O modes. Defaults to 1.
+
+    port-sel:
+      type: int
+      required: false
+      description: |
+        SPI Port 0, 1, or 2. Port 0 is the shared SPI, port 1 is
+        the private SPI, and port 2 is the internal SPI port for
+        chip configurations with an embedded SPI flash. Defaults
+        to port 0 (shared SPI port).
+
+    chip-select:
+      type: int
+      required: false
+      description: |
+        Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
+        Ports 1 and 2 implement CS0# only. Defaults to CS0#.
+
+    dcsckon:
+      type: int
+      required: false
+      description: |
+        Delay in QMSPI main clocks from CS# assertion to first clock edge.
+        If not present use hardware default value. Refer to chip documention
+        for QMSPI input clock frequency.
+
+    dckcsoff:
+      type: int
+      required: false
+      description: |
+        Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
+        If not presetn use hardware default value. Refer to chip documention
+        for QMSPI input clock frequency.
+
+    dldh:
+      type: int
+      required: false
+      description: |
+        Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
+        and WP#. If not present use hardware default value. Refer to chip
+        documention for QMSPI input clock frequency.
+
+    dcsda:
+      type: int
+      required: false
+      description: |
+        Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
+        If not present use hardware default value. Refer to chip documention
+        for QMSPI input clock frequency.
+
+    cs1-freq:
+      type: int
+      required: false
+      description: |
+        Allows different frequencies for CS#0 and CS1# devices. This applies
+        to ports implementing CS1#.
+
+    tctradj:
+      type: int
+      required: false
+      description: |
+        An optional signed 8-bit value for adjusting the QMSPI control signal
+        timing tap.
+
+    tsckadj:
+      type: int
+      required: false
+      description: |
+        An optional signed 8-bit value for adjusting the QMSPI clock signal
+        timing tap.
diff --git a/dts/bindings/spi/microchip,xec-qmspi.yaml b/dts/bindings/spi/microchip,xec-qmspi.yaml
new file mode 100644
index 0000000000..bb0cafa59f
--- /dev/null
+++ b/dts/bindings/spi/microchip,xec-qmspi.yaml
@@ -0,0 +1,57 @@
+# Copyright (c) 2018, Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC QMSPI controller
+
+compatible: "microchip,xec-qmspi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    port_sel:
+      type: int
+      required: true
+      description: SPI Port 0 or 1.
+
+    rxdma:
+      type: int
+      required: true
+      description: Receive DMA channel
+
+    txdma:
+      type: int
+      required: true
+      description: Transmit DMA channel
+
+    lines:
+      type: int
+      required: true
+      description: QMSPI lines 1, 2, or 4
+
+    chip_select:
+      type: int
+      required: true
+      description: Use QMSPI CS0# or CS1#
+
+    dcsckon:
+      type: int
+      required: true
+      description: Delay in system clocks from CS# assertion to first clock edge
+
+    dckcsoff:
+      type: int
+      required: true
+      description: Delay in system clocks from last clock edge to CS# de-assertion
+
+    dldh:
+      type: int
+      required: true
+      description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
+
+    dcsda:
+      type: int
+      required: true
+      description: Delay in system clocks from CS# de-assertion to CS# assertion
diff --git a/dts/bindings/spi/nordic,nrf-spi-common.yaml b/dts/bindings/spi/nordic,nrf-spi-common.yaml
new file mode 100644
index 0000000000..285a32390c
--- /dev/null
+++ b/dts/bindings/spi/nordic,nrf-spi-common.yaml
@@ -0,0 +1,43 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for Nordic nRF family SPI peripherals
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    sck-pin:
+      type: int
+      required: true
+      description: |
+        The SCK pin to use.
+
+        For pins P0.0 through P0.31, use the pin number. For example,
+        to use P0.16 for SCK, set:
+
+            sck-pin = <16>;
+
+        For pins P1.0 through P1.31, add 32 to the pin number. For
+        example, to use P1.2 for SCK, set:
+
+            sck-pin = <34>;  /* 32 + 2 */
+
+    mosi-pin:
+      type: int
+      required: true
+      description: |
+        The MOSI pin to use. The pin numbering scheme is the same as
+        the sck-pin property's.
+
+    miso-pin:
+      type: int
+      required: true
+      description: |
+        The MISO pin to use. The pin numbering scheme is the same as
+        the sck-pin property's.
diff --git a/dts/bindings/spi/nordic,nrf-spi.yaml b/dts/bindings/spi/nordic,nrf-spi.yaml
new file mode 100644
index 0000000000..07f51babe3
--- /dev/null
+++ b/dts/bindings/spi/nordic,nrf-spi.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF family SPI (SPI master)
+
+compatible: "nordic,nrf-spi"
+
+include: nordic,nrf-spi-common.yaml
+
+properties:
+    miso-pull-up:
+      type: boolean
+      required: false
+      description: Enable pull-up on MISO line
+
+    miso-pull-down:
+      type: boolean
+      required: false
+      description: Enable pull-down on MISO line
diff --git a/dts/bindings/spi/nordic,nrf-spim.yaml b/dts/bindings/spi/nordic,nrf-spim.yaml
new file mode 100644
index 0000000000..a22e7b66d2
--- /dev/null
+++ b/dts/bindings/spi/nordic,nrf-spim.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF family SPIM (SPI master with EasyDMA)
+
+compatible: "nordic,nrf-spim"
+
+include: nordic,nrf-spi-common.yaml
+
+properties:
+    miso-pull-up:
+      type: boolean
+      required: false
+      description: Enable pull-up on MISO line
+
+    miso-pull-down:
+      type: boolean
+      required: false
+      description: Enable pull-down on MISO line
+
+    anomaly-58-workaround:
+      type: boolean
+      required: false
+      description: |
+        Enables the workaround for the nRF52832 SoC SPIM PAN 58 anomaly.
+        Must be used in conjunction with
+        CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58=y
diff --git a/dts/bindings/spi/nordic,nrf-spis.yaml b/dts/bindings/spi/nordic,nrf-spis.yaml
new file mode 100644
index 0000000000..614c4d62b3
--- /dev/null
+++ b/dts/bindings/spi/nordic,nrf-spis.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF family SPIS (SPI slave with EasyDMA)
+
+compatible: "nordic,nrf-spis"
+
+include: nordic,nrf-spi-common.yaml
+
+properties:
+    csn-pin:
+      type: int
+      required: true
+      description:  |
+          The CSN pin to use. The pin numbering scheme is the same as
+          the sck-pin property's.
+
+    def-char:
+      type: int
+      required: true
+      description: |
+          Default character. Character clocked out when the slave was not
+          provided with buffers and is ignoring the transaction.
diff --git a/dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml b/dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml
new file mode 100644
index 0000000000..c74844e8d2
--- /dev/null
+++ b/dts/bindings/spi/nuvoton,npcx-spi-fiu.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-SPI-FIU controller node
+
+compatible: "nuvoton,npcx-spi-fiu"
+
+include: [spi-controller.yaml]
+
+properties:
+    reg:
+        required: true
+    clocks:
+        required: true
+    label:
+        required: true
diff --git a/dts/bindings/spi/nxp,imx-flexspi.yaml b/dts/bindings/spi/nxp,imx-flexspi.yaml
new file mode 100644
index 0000000000..6fc6e4238d
--- /dev/null
+++ b/dts/bindings/spi/nxp,imx-flexspi.yaml
@@ -0,0 +1,74 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI controller
+
+compatible: "nxp,imx-flexspi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    ahb-bufferable:
+      type: boolean
+      required: false
+      description: |
+        Enable AHB bufferable write access by setting register field
+        AHBCR[BUFFERABLEEN].
+
+    ahb-cacheable:
+      type: boolean
+      required: false
+      description: |
+        Enable AHB cacheable read access by setting register field
+        AHBCR[CACHEABLEEN].
+
+    ahb-prefetch:
+      type: boolean
+      required: false
+      description: |
+        Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN].
+
+    ahb-read-addr-opt:
+      type: boolean
+      required: false
+      description: |
+        Remove burst start address alignment limitation by setting register
+        field AHBCR[READADDROPT].
+
+    combination-mode:
+      type: boolean
+      required: false
+      description: |
+        Combine port A and port B data pins to support octal mode access by
+        setting register field MCR0[COMBINATIONEN].
+
+    sck-differential-clock:
+      type: boolean
+      required: false
+      description: |
+        Enable/disable SCKB pad use as SCKA differential clock output,
+        when enabled, Port B flash access is not available.
+
+    rx-clock-source:
+      type: int
+      required: false
+      default: 0
+      enum:
+        - 0 # Loopback internally
+        - 1 # Loopback from DQS pad
+        - 2 # Loopback from SCK pad
+        - 3 # External input from DQS pad
+      description: |
+        Source clock for flash read. See the RXCLKSRC field in register MCR0.
+        The default corresponds to the reset value of the register field.
+
+child-binding:
+    description: NXP FlexSPI port
+
+    include: nxp,imx-flexspi-device.yaml
diff --git a/dts/bindings/spi/nxp,imx-lpspi.yaml b/dts/bindings/spi/nxp,imx-lpspi.yaml
new file mode 100644
index 0000000000..48804a863a
--- /dev/null
+++ b/dts/bindings/spi/nxp,imx-lpspi.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP i.MX LPSPI controller
+
+compatible: "nxp,imx-lpspi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    pcs-sck-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds from the chip select assert to the first clock
+        edge. If not set, the minimum supported delay is used.
+
+    sck-pcs-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds from the last clock edge to the chip select
+        deassert. If not set, the minimum supported delay is used.
+
+    transfer-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds from the chip select deassert to the next chip
+        select assert. If not set, the minimum supported delay is used.
diff --git a/dts/bindings/spi/nxp,kinetis-dspi.yaml b/dts/bindings/spi/nxp,kinetis-dspi.yaml
new file mode 100644
index 0000000000..cf617ed03c
--- /dev/null
+++ b/dts/bindings/spi/nxp,kinetis-dspi.yaml
@@ -0,0 +1,95 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis DSPI controller
+
+compatible: "nxp,kinetis-dspi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    pcs-sck-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds from the chip select assert to the first clock
+        edge. If not set, the minimum supported delay is used.
+
+    sck-pcs-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds from the last clock edge to the chip select
+        deassert. If not set, the minimum supported delay is used.
+
+    transfer-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds from the chip select deassert to the next chip
+        select assert. If not set, the minimum supported delay is used.
+
+    pinctrl-0:
+      type: phandles
+      required: true
+
+    nxp,rx-tx-chn-share:
+      type: boolean
+      required: false
+      description: If the edma channel shared with tx and rx
+
+    ctar:
+      type: int
+      required: false
+      description: |
+        ctar register selection range form 0-1 for master mode, 0 for slave mode
+
+    sample-point:
+      type: int
+      required: false
+      description: |
+        Controls when the DSPI master samples SIN in the Modified Transfer Format.
+        This field is valid only when the CPHA bit in the CTAR register is 0.
+
+    continuous-sck:
+      type: boolean
+      required: false
+      description: |
+        continuous SCK enable. Note that the continuous SCK is only
+        supported for CPHA = 1.
+
+    rx-fifo-overwrite:
+      type: boolean
+      required: false
+      description: |
+        receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
+        data is ignored and the data from the transfer that generated the overflow
+        is also ignored. If ROOE = 1, the incoming data is shifted to the
+        shift register.
+
+    modified-timing-format:
+      type: boolean
+      required: false
+      description: |
+        Enables a modified transfer format to be used if true.
+
+    tx-fifo-size:
+      type: int
+      required: false
+      description: |
+        tx fifo size
+
+    rx-fifo-size:
+      type: int
+      required: false
+      description: |
+        rx fifo size
diff --git a/dts/bindings/spi/nxp,lpc-spi.yaml b/dts/bindings/spi/nxp,lpc-spi.yaml
new file mode 100644
index 0000000000..7676179a1d
--- /dev/null
+++ b/dts/bindings/spi/nxp,lpc-spi.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC SPI controller
+
+compatible: "nxp,lpc-spi"
+
+include: [spi-controller.yaml, "nxp,lpc-flexcomm.yaml"]
+
+properties:
+    pre-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds inserted between chip select assert to the first
+        clock edge. If not set, no additional delay is inserted.
+
+    post-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds inserted between the last clock edge to the chip
+        select deassert. If not set, no additional delay is inserted.
+
+    frame-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds inserted between data frames when chip select is
+        asserted and the EOF flag is set. If not set, no additional delay is
+        inserted.
+
+    transfer-delay:
+      type: int
+      required: false
+      description: |
+        Delay in nanoseconds inserted between transfers when chip select is
+        deasserted. If not set, no additional delay is inserted.
diff --git a/dts/bindings/spi/opencores,spi-simple.yaml b/dts/bindings/spi/opencores,spi-simple.yaml
new file mode 100644
index 0000000000..2e896b15ef
--- /dev/null
+++ b/dts/bindings/spi/opencores,spi-simple.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Western Digital Corporation or its affiliates
+# SPDX-License-Identifier: Apache-2.0
+
+description: OpenCores Simple SPI controller
+
+compatible: "opencores,spi-simple"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/spi/openisa,rv32m1-lpspi.yaml b/dts/bindings/spi/openisa,rv32m1-lpspi.yaml
new file mode 100644
index 0000000000..935c8ee2f0
--- /dev/null
+++ b/dts/bindings/spi/openisa,rv32m1-lpspi.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Karsten Koenig <karsten.koenig.030@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: OpenISA LPSPI controller
+
+compatible: "openisa,rv32m1-lpspi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/spi/sifive,spi0.yaml b/dts/bindings/spi/sifive,spi0.yaml
new file mode 100644
index 0000000000..f3dd241d3b
--- /dev/null
+++ b/dts/bindings/spi/sifive,spi0.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sifive SPI controller
+
+compatible: "sifive,spi0"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/spi/silabs,gecko-spi-usart.yaml b/dts/bindings/spi/silabs,gecko-spi-usart.yaml
new file mode 100644
index 0000000000..820ce9677d
--- /dev/null
+++ b/dts/bindings/spi/silabs,gecko-spi-usart.yaml
@@ -0,0 +1,35 @@
+description: GECKO USART SPI
+
+compatible: "silabs,gecko-spi-usart"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: peripheral ID
+
+    # Note: Not all SoC series support setting individual pin location. If this
+    # is a case all location-* properties need to have identical value.
+
+    location-rx:
+      type: array
+      required: true
+      description: RX pin configuration defined as <location port pin>
+
+    location-tx:
+      type: array
+      required: true
+      description: TX pin configuration defined as <location port pin>
+
+    location-clk:
+      type: array
+      required: true
+      description: CLK pin configuration defined as <location port pin>
diff --git a/dts/bindings/spi/snps,designware-spi.yaml b/dts/bindings/spi/snps,designware-spi.yaml
new file mode 100644
index 0000000000..1b9e640a4e
--- /dev/null
+++ b/dts/bindings/spi/snps,designware-spi.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys DesignWare SPI node
+
+compatible: "snps,designware-spi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/spi/spi-controller.yaml b/dts/bindings/spi/spi-controller.yaml
new file mode 100644
index 0000000000..5808ec7a08
--- /dev/null
+++ b/dts/bindings/spi/spi-controller.yaml
@@ -0,0 +1,63 @@
+# Copyright (c) 2018, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for SPI controllers
+
+include: base.yaml
+
+bus: spi
+
+properties:
+    clock-frequency:
+      type: int
+      required: false
+      description: |
+        Clock frequency the SPI peripheral is being driven at, in Hz.
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      required: true
+      const: 0
+    label:
+      required: true
+    cs-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        An array of chip select GPIOs to use. Each element
+        in the array specifies a GPIO. The index in the array
+        corresponds to the child node that the CS gpio controls.
+
+        Example:
+
+          spi@... {
+                  cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
+                                <&gpio1 10 GPIO_ACTIVE_LOW>,
+                                ...;
+
+                  spi-device@0 {
+                          reg = <0>;
+                          ...
+                  };
+                  spi-device@1 {
+                          reg = <1>;
+                          ...
+                  };
+                  ...
+          };
+
+        The child node "spi-device@0" specifies a SPI device with
+        chip select controller gpio0, pin 23, and devicetree
+        GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
+        controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
+        devices can be configured in the same way.
+
+        If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
+        choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
+        intervening hardware inverts the signal to the peripheral device or
+        the line itself is active high.
+
+        If this property is not defined, no chip select GPIOs are set.
+        SPI controllers with dedicated CS pins do not need to define
+        the cs-gpios property.
diff --git a/dts/bindings/spi/spi-device.yaml b/dts/bindings/spi/spi-device.yaml
new file mode 100644
index 0000000000..c556596375
--- /dev/null
+++ b/dts/bindings/spi/spi-device.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2018, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for SPI devices
+
+include: [base.yaml, power.yaml]
+
+on-bus: spi
+
+properties:
+    reg:
+      required: true
+    spi-max-frequency:
+      type: int
+      required: true
+      description: Maximum clock frequency of device's SPI interface in Hz
+    label:
+      required: true
+    duplex:
+      type: int
+      required: false
+      description: |
+        Duplex mode, full or half. By default it's always full duplex thus 0
+        as this is, by far, the most common mode.
+        Use the macros not the actual enum value, here is the concordance
+        list (see dt-bindings/spi/spi.h)
+          0    SPI_FULL_DUPLEX
+          2048 SPI_HALF_DUPLEX
+      enum:
+        - 0
+        - 2048
+    frame-format:
+      type: int
+      default: 0
+      required: false
+      description: |
+        Motorola or TI frame format. By default it's always Motorola's,
+        thus 0 as this is, by far, the most common format.
+        Use the macros not the actual enum value, here is the concordance
+        list (see dt-bindings/spi/spi.h)
+          0     SPI_FRAME_FORMAT_MOTOROLA
+          32768 SPI_FRAME_FORMAT_TI
+      enum:
+        - 0
+        - 32768
diff --git a/dts/bindings/spi/st,stm32-spi-common.yaml b/dts/bindings/spi/st,stm32-spi-common.yaml
new file mode 100644
index 0000000000..42b7462d6a
--- /dev/null
+++ b/dts/bindings/spi/st,stm32-spi-common.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2018, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for STM32 SPI peripherals.
+
+include: [spi-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
diff --git a/dts/bindings/spi/st,stm32-spi-fifo.yaml b/dts/bindings/spi/st,stm32-spi-fifo.yaml
new file mode 100644
index 0000000000..7f88b24dee
--- /dev/null
+++ b/dts/bindings/spi/st,stm32-spi-fifo.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 SPI controller with embedded Rx and Tx FIFOs
+
+compatible: "st,stm32-spi-fifo"
+
+include: st,stm32-spi-common.yaml
diff --git a/dts/bindings/spi/st,stm32-spi-subghz.yaml b/dts/bindings/spi/st,stm32-spi-subghz.yaml
new file mode 100644
index 0000000000..10eb1e3119
--- /dev/null
+++ b/dts/bindings/spi/st,stm32-spi-subghz.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2021 Fabio Baltieri
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 SUBGHZ SPI controller
+
+compatible: "st,stm32-spi-subghz"
+
+include:
+
+include:
+  - name: st,stm32-spi-common.yaml
+    property-blocklist:
+      - pinctrl-0
+      - pinctrl-names
+
+properties:
+    use-subghzspi-nss:
+      type: boolean
+      required: true
+      description: |
+        Control the SUBGHZPI NSS line using the PWR HAL functions. This is for
+        the special purpose SUBGHZSPI interface found in the STM32WL series.
diff --git a/dts/bindings/spi/st,stm32-spi.yaml b/dts/bindings/spi/st,stm32-spi.yaml
new file mode 100644
index 0000000000..baae63b3b5
--- /dev/null
+++ b/dts/bindings/spi/st,stm32-spi.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2018, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 SPI controller
+
+compatible: "st,stm32-spi"
+
+include: st,stm32-spi-common.yaml
diff --git a/dts/bindings/spi/telink,b91-spi.yaml b/dts/bindings/spi/telink,b91-spi.yaml
new file mode 100644
index 0000000000..5baa73b983
--- /dev/null
+++ b/dts/bindings/spi/telink,b91-spi.yaml
@@ -0,0 +1,56 @@
+# Copyright (c) 2021, Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink B91 SPI
+
+include: spi-controller.yaml
+
+compatible: "telink,b91-spi"
+
+properties:
+    reg:
+        required: true
+
+    peripheral-id:
+      type: string
+      required: true
+      enum:
+        - "PSPI_MODULE"
+        - "HSPI_MODULE"
+
+    pinctrl-0:
+      type: phandles
+      required: true
+
+    cs0-pin:
+      type: string
+      required: true
+      enum:
+        - "0"
+        - "PSPI_CSN_PC4"
+        - "PSPI_CSN_PC0"
+        - "PSPI_CSN_PD0"
+        - "HSPI_CSN_PA1"
+        - "HSPI_CSN_PB6"
+
+    cs1-pin:
+      type: string
+      required: false
+      enum:
+        - "0"
+        - "PSPI_CSN_PC4"
+        - "PSPI_CSN_PC0"
+        - "PSPI_CSN_PD0"
+        - "HSPI_CSN_PA1"
+        - "HSPI_CSN_PB6"
+
+    cs2-pin:
+      type: string
+      required: false
+      enum:
+        - "0"
+        - "PSPI_CSN_PC4"
+        - "PSPI_CSN_PC0"
+        - "PSPI_CSN_PD0"
+        - "HSPI_CSN_PA1"
+        - "HSPI_CSN_PB6"
diff --git a/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml b/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml
new file mode 100644
index 0000000000..ddbdf5a7a8
--- /dev/null
+++ b/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2019 Brett Witherspoon
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC13xx / CC26xx SPI node
+
+compatible: "ti,cc13xx-cc26xx-spi"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    sck-pin:
+      type: int
+      required: true
+      description: SCK pin
+
+    mosi-pin:
+      type: int
+      required: true
+      description: MOSI pin
+
+    miso-pin:
+      type: int
+      required: true
+      description: MISO pin
+
+    cs-pin:
+      type: int
+      required: false
+      description: CS pin
diff --git a/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml b/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml
new file mode 100644
index 0000000000..d1b54083bb
--- /dev/null
+++ b/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Xilinx AXI Quad SPI IP node
+
+compatible: "xlnx,xps-spi-2.00.a"
+
+include: spi-controller.yaml
+
+# Property names correspond to a subset of those generated by
+# https://github.com/Xilinx/device-tree-xlnx
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    xlnx,num-ss-bits:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 3
+        - 4
+      description: |
+        Number of slave select bits implemented
+
+    xlnx,num-transfer-bits:
+      type: int
+      required: true
+      enum:
+        - 8
+        - 16
+        - 32
+      description: |
+        Number of bits per transfer
diff --git a/dts/bindings/spi/zephyr,spi-bitbang.yaml b/dts/bindings/spi/zephyr,spi-bitbang.yaml
new file mode 100644
index 0000000000..61bf3501c5
--- /dev/null
+++ b/dts/bindings/spi/zephyr,spi-bitbang.yaml
@@ -0,0 +1,29 @@
+# Copyright 2021 Marc Reilly, Creative Product Design
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr SPI Bitbang driver
+
+compatible: "zephyr,spi-bitbang"
+
+include: spi-controller.yaml
+
+properties:
+    clk-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        Clock gpio info
+
+    mosi-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        MOSI gpio info. Output pin for Master Out Slave In.
+        If this is not provided then the driver will transmit 0s
+
+    miso-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        MISO gpio info. Input pin for Master In Slave Out.
+        If this is not provided the driver will read 0s
diff --git a/dts/bindings/spi/zephyr,spi-emul-controller.yaml b/dts/bindings/spi/zephyr,spi-emul-controller.yaml
new file mode 100644
index 0000000000..df45742450
--- /dev/null
+++ b/dts/bindings/spi/zephyr,spi-emul-controller.yaml
@@ -0,0 +1,12 @@
+# Copyright 2020 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr SPI Emulation controller
+
+compatible: "zephyr,spi-emul-controller"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/sram/mmio-sram.yaml b/dts/bindings/sram/mmio-sram.yaml
new file mode 100644
index 0000000000..98361916a2
--- /dev/null
+++ b/dts/bindings/sram/mmio-sram.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic on-chip SRAM description
+
+compatible: "mmio-sram"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: false
diff --git a/dts/bindings/sram/sifive,dtim0.yaml b/dts/bindings/sram/sifive,dtim0.yaml
new file mode 100644
index 0000000000..d67bef034a
--- /dev/null
+++ b/dts/bindings/sram/sifive,dtim0.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive Data Tightly-Integrated Memory
+
+compatible: "sifive,dtim0"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
diff --git a/dts/bindings/syscon/syscon.yaml b/dts/bindings/syscon/syscon.yaml
new file mode 100644
index 0000000000..d5e4fcd27b
--- /dev/null
+++ b/dts/bindings/syscon/syscon.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: System Controller Registers R/W
+
+compatible: "syscon"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+    reg-io-width:
+      type: int
+      required: false
+      description: The width of the registers in the syscon region in bytes. Default is 4 bytes.
diff --git a/dts/bindings/tach/ite,it8xxx2-tach.yaml b/dts/bindings/tach/ite,it8xxx2-tach.yaml
new file mode 100644
index 0000000000..02e34689d4
--- /dev/null
+++ b/dts/bindings/tach/ite,it8xxx2-tach.yaml
@@ -0,0 +1,40 @@
+# Copyright (c) 2021 ITE Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE, it8xxx2 Tachometer node
+
+compatible: "ite,it8xxx2-tach"
+
+include: tach.yaml
+
+properties:
+    reg:
+        required: true
+
+    dvs-bit:
+        type: int
+        required: true
+        description: tachometer data valid bit of tswctlr register
+
+    chsel-bit:
+        type: int
+        required: true
+        description: tachometer data valid status bit of tswctlr register
+
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configuration of tachometer pinmux controller
+
+    channel:
+        type: int
+        required: true
+        enum:
+              - 0
+              - 1
+        description: 0 = TACH_CHANNEL_A, 1 = TACH_CHANNEL_B
+
+    pulses-per-round:
+        type: int
+        required: true
+        description: number of pulses per round of tachometer's input
diff --git a/dts/bindings/tach/microchip,xec-tach.yaml b/dts/bindings/tach/microchip,xec-tach.yaml
new file mode 100644
index 0000000000..be849a0da0
--- /dev/null
+++ b/dts/bindings/tach/microchip,xec-tach.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2020, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC tachometer controller
+
+compatible: "microchip,xec-tach"
+
+include: tach.yaml
+
+properties:
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      type: int
+      const: 0
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/tach/nuvoton,npcx-tach.yaml b/dts/bindings/tach/nuvoton,npcx-tach.yaml
new file mode 100644
index 0000000000..13c4bdb5dd
--- /dev/null
+++ b/dts/bindings/tach/nuvoton,npcx-tach.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-Tachometer node
+
+compatible: "nuvoton,npcx-tach"
+
+include: tach.yaml
+
+properties:
+    reg:
+        required: true
+    clocks:
+        required: true
+    pinctrl-0:
+        type: phandles
+        required: false
+        description: configurations of pinmux controllers in tachometers
+    sample-clk:
+        type: int
+        required: false
+        description: |
+          sampling clock frequency of tachometer. Please notice that it must be
+          fixed to 32768 if bus in clocks property is NPCX_CLOCK_BUS_LFCLK.
+    port:
+        type: int
+        required: false
+        description: selected port of tachometer (port-A is 0 and port-B is 1)
+    pulses-per-round:
+        type: int
+        required: false
+        description: number of pulses (holes) per round of tachometer's input (encoder)
diff --git a/dts/bindings/tach/tach.yaml b/dts/bindings/tach/tach.yaml
new file mode 100644
index 0000000000..0091a27acb
--- /dev/null
+++ b/dts/bindings/tach/tach.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2020, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties for HW supported tachometers
+
+include: base.yaml
+
+bus: tach
+
+properties:
+    label:
+      required: true
diff --git a/dts/bindings/tcpc/st,stm32-ucpd.yaml b/dts/bindings/tcpc/st,stm32-ucpd.yaml
new file mode 100644
index 0000000000..8a6884c325
--- /dev/null
+++ b/dts/bindings/tcpc/st,stm32-ucpd.yaml
@@ -0,0 +1,71 @@
+# Copyright 2021 The Chromium OS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ST STM32 family USB Type-C / Power Delivery. The default values were
+    taken from the LL_UCPD_StructInit function defined in the HAL.
+
+compatible: "st,stm32-ucpd"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+    interrupts:
+      required: true
+
+    psc-ucpdclk:
+      required: false
+      default: 2
+      type: int
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+      description: |
+        Determines the division ratio of a kernel clock pre-scaler
+        producing UCPD peripheral clock (ucpd_clk). It is recommended
+        to use the pre-scaler so as to set the ucpd_clk frequency in
+        the range from 6 to 9 MHz.
+
+    ifrgap:
+      required: false
+      type: int
+      default: 17
+      description: |
+        Determines the division ratio of a ucpd_clk divider producing
+        inter-frame gap timer clock (tInterFrameGap).
+        The division ratio 15 is to apply for Tx clock at the USB PD 2.0
+        specification nominal value.
+        Valid range: 2 - 32
+
+    transwin:
+      required: false
+      type: int
+      default: 8
+      description: |
+        Determines the division ratio of a hbit_clk divider producing
+        tTransitionWindow interval.
+        Valid range: 2 - 32
+
+    hbitclkdiv:
+      required: false
+      type: int
+      default: 14
+      description: |
+        Determines the division ratio of a ucpd_clk divider producing
+        half-bit clock (hbit_clk)
+        Valid range: 1 - 64
diff --git a/dts/bindings/test/vnd,adc-temp-sensor.yaml b/dts/bindings/test/vnd,adc-temp-sensor.yaml
new file mode 100644
index 0000000000..32ca83b429
--- /dev/null
+++ b/dts/bindings/test/vnd,adc-temp-sensor.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test ADC-based temperature sensor
+
+compatible: "vnd,adc-temp-sensor"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    io-channels:
+      required: true
+      description: ADC conversion channels
+
+    io-channel-names:
+      required: true
+      description: conversion channel names
+
+    clocks:
+      required: true
+
+    pinctrl-0:
+      type: phandles
+
+    pinctrl-1:
+      type: phandles
+
+    pinctrl-2:
+      type: phandles
diff --git a/dts/bindings/test/vnd,adc.yaml b/dts/bindings/test/vnd,adc.yaml
new file mode 100644
index 0000000000..f7b274ea3b
--- /dev/null
+++ b/dts/bindings/test/vnd,adc.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test ADC
+
+compatible: "vnd,adc"
+
+include: adc-controller.yaml
+
+properties:
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
diff --git a/dts/bindings/test/vnd,array-holder.yaml b/dts/bindings/test/vnd,array-holder.yaml
new file mode 100644
index 0000000000..66637d3079
--- /dev/null
+++ b/dts/bindings/test/vnd,array-holder.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test array container
+
+compatible: "vnd,array-holder"
+
+include: [base.yaml]
+
+properties:
+  a: {type: "array"}
+  b: {type: "uint8-array"}
+  c: {type: "string-array"}
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/test/vnd,busy-sim.yaml b/dts/bindings/test/vnd,busy-sim.yaml
new file mode 100644
index 0000000000..543e7024a7
--- /dev/null
+++ b/dts/bindings/test/vnd,busy-sim.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    CPU load simulator
+
+compatible: "vnd,busy-sim"
+
+properties:
+    counter:
+      type: phandle
+      required: true
+      description: |
+        Counter device used for generating intervals.
+
+    active-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Debug pin is set to active state when cpu load is active.
diff --git a/dts/bindings/test/vnd,child-bindings.yaml b/dts/bindings/test/vnd,child-bindings.yaml
new file mode 100644
index 0000000000..3b5e725f1a
--- /dev/null
+++ b/dts/bindings/test/vnd,child-bindings.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test child bindings
+
+compatible: "vnd,child-bindings"
+
+include: [base.yaml]
+
+child-binding:
+  description: Test child binding
+  properties:
+    val:
+      type: int
+      required: true
diff --git a/dts/bindings/test/vnd,clock.yaml b/dts/bindings/test/vnd,clock.yaml
new file mode 100644
index 0000000000..325c0a2b08
--- /dev/null
+++ b/dts/bindings/test/vnd,clock.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test Clock Controller
+
+compatible: "vnd,clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - bus
+  - bits
diff --git a/dts/bindings/test/vnd,disabled-compat.yaml b/dts/bindings/test/vnd,disabled-compat.yaml
new file mode 100644
index 0000000000..5d074e0fa8
--- /dev/null
+++ b/dts/bindings/test/vnd,disabled-compat.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test disabled compatible
+
+compatible: "vnd,disabled-compat"
+
+include: base.yaml
diff --git a/dts/bindings/test/vnd,dma.yaml b/dts/bindings/test/vnd,dma.yaml
new file mode 100644
index 0000000000..3c1dfa4ebb
--- /dev/null
+++ b/dts/bindings/test/vnd,dma.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: VND DMA controller
+
+compatible: "vnd,dma"
+
+include: dma-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#dma-cells":
+      const: 2
+
+dma-cells:
+  - channel
+  - slot
diff --git a/dts/bindings/test/vnd,enum-holder-inst.yaml b/dts/bindings/test/vnd,enum-holder-inst.yaml
new file mode 100644
index 0000000000..0f6ac9b8d2
--- /dev/null
+++ b/dts/bindings/test/vnd,enum-holder-inst.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test enum property container (instance based)
+
+compatible: "vnd,enum-holder-inst"
+
+include: [base.yaml, "vnd,enum-holder.yaml"]
diff --git a/dts/bindings/test/vnd,enum-holder.yaml b/dts/bindings/test/vnd,enum-holder.yaml
new file mode 100644
index 0000000000..e4ff7a2cd0
--- /dev/null
+++ b/dts/bindings/test/vnd,enum-holder.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test enum property container
+
+compatible: "vnd,enum-holder"
+
+include: [base.yaml]
+
+properties:
+  val:
+    type: string
+    required: true
+    enum:
+      - "zero"
+      - "one"
+      - "two"
diff --git a/dts/bindings/test/vnd,enum-int-required-false-holder.yaml b/dts/bindings/test/vnd,enum-int-required-false-holder.yaml
new file mode 100644
index 0000000000..6983f64e6e
--- /dev/null
+++ b/dts/bindings/test/vnd,enum-int-required-false-holder.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test enum property container
+
+compatible: "vnd,enum-int-required-false-holder"
+
+include: [base.yaml]
+
+properties:
+  val:
+    type: int
+    required: false
+    enum:
+      - 5
+      - 6
+      - 7
+      - 8
diff --git a/dts/bindings/test/vnd,enum-required-false-holder-inst.yaml b/dts/bindings/test/vnd,enum-required-false-holder-inst.yaml
new file mode 100644
index 0000000000..e2a1c71df1
--- /dev/null
+++ b/dts/bindings/test/vnd,enum-required-false-holder-inst.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test enum property container (instance based)
+
+compatible: "vnd,enum-required-false-holder-inst"
+
+include: [base.yaml, "vnd,enum-required-false-holder.yaml"]
diff --git a/dts/bindings/test/vnd,enum-required-false-holder.yaml b/dts/bindings/test/vnd,enum-required-false-holder.yaml
new file mode 100644
index 0000000000..52de1d27bb
--- /dev/null
+++ b/dts/bindings/test/vnd,enum-required-false-holder.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2020 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test enum property container
+
+compatible: "vnd,enum-required-false-holder"
+
+include: [base.yaml]
+
+properties:
+  val:
+    type: string
+    required: false
+    enum:
+      - "zero"
+      - "one"
+      - "two"
diff --git a/dts/bindings/test/vnd,gpio-expander-common.yaml b/dts/bindings/test/vnd,gpio-expander-common.yaml
new file mode 100644
index 0000000000..9b3dfa0daf
--- /dev/null
+++ b/dts/bindings/test/vnd,gpio-expander-common.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test GPIO node
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/test/vnd,gpio-expander-i2c.yaml b/dts/bindings/test/vnd,gpio-expander-i2c.yaml
new file mode 100644
index 0000000000..4acd168540
--- /dev/null
+++ b/dts/bindings/test/vnd,gpio-expander-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: GPIO expander via I2C
+
+compatible: "vnd,gpio-expander"
+
+include: ["vnd,gpio-expander-common.yaml", i2c-device.yaml]
diff --git a/dts/bindings/test/vnd,gpio-expander-spi.yaml b/dts/bindings/test/vnd,gpio-expander-spi.yaml
new file mode 100644
index 0000000000..dcd3bbac4b
--- /dev/null
+++ b/dts/bindings/test/vnd,gpio-expander-spi.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: GPIO expander via SPI
+
+compatible: "vnd,gpio-expander"
+
+include: ["vnd,gpio-expander-common.yaml", spi-device.yaml]
diff --git a/dts/bindings/test/vnd,gpio-one-cell.yaml b/dts/bindings/test/vnd,gpio-one-cell.yaml
new file mode 100644
index 0000000000..e8b5fa1ff3
--- /dev/null
+++ b/dts/bindings/test/vnd,gpio-one-cell.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test GPIO node with one cell
+
+compatible: "vnd,gpio-one-cell"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 1
+
+gpio-cells:
+  - pin
diff --git a/dts/bindings/test/vnd,gpio.yaml b/dts/bindings/test/vnd,gpio.yaml
new file mode 100644
index 0000000000..ae84eb897a
--- /dev/null
+++ b/dts/bindings/test/vnd,gpio.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test GPIO node
+
+compatible: "vnd,gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
+
+foo-cells:
+  - foocell
+
+baz-cells:
+  - bazcell
diff --git a/dts/bindings/test/vnd,great-grandchild-bindings.yaml b/dts/bindings/test/vnd,great-grandchild-bindings.yaml
new file mode 100644
index 0000000000..c2a89b550c
--- /dev/null
+++ b/dts/bindings/test/vnd,great-grandchild-bindings.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Test binding for 3 levels of "child-binding".
+
+  Previous versions of Zephyr only allowed up to two levels of
+  "child-binding:" in a YAML file. This file is used to test that the
+  restriction no longer holds.
+
+compatible: "vnd,great-grandchild-bindings"
+
+include: [base.yaml]
+
+child-binding:
+  description: child node, no properties
+
+  child-binding:
+    description: grandchild node, no properties
+
+    child-binding:
+      description: great-grandchild node, ggc-prop property
+
+      properties:
+        ggc-prop:
+          type: int
+          required: true
diff --git a/dts/bindings/test/vnd,i2c-device.yaml b/dts/bindings/test/vnd,i2c-device.yaml
new file mode 100644
index 0000000000..a22ec3b178
--- /dev/null
+++ b/dts/bindings/test/vnd,i2c-device.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test I2C device
+
+compatible: "vnd,i2c-device"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/test/vnd,i2c-mux.yaml b/dts/bindings/test/vnd,i2c-mux.yaml
new file mode 100644
index 0000000000..c380274def
--- /dev/null
+++ b/dts/bindings/test/vnd,i2c-mux.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  I2C mux
+
+  This is an I2C device that is also (multiple) I2C controllers. We
+  model this as a node which is an I2C device, whose children are I2C
+  controllers, and whose grandchildren are therefore I2C devices.
+
+compatible: "vnd,i2c-mux"
+
+include: "i2c-device.yaml"
+
+child-binding:
+  description: I2C mux controller
+  compatible: "vnd,i2c-mux-controller"
+  include: "i2c-controller.yaml"
diff --git a/dts/bindings/test/vnd,i2c.yaml b/dts/bindings/test/vnd,i2c.yaml
new file mode 100644
index 0000000000..39f5b5b8fe
--- /dev/null
+++ b/dts/bindings/test/vnd,i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test I2C node
+
+compatible: "vnd,i2c"
+
+include: [i2c-controller.yaml, base.yaml]
diff --git a/dts/bindings/test/vnd,intc.yaml b/dts/bindings/test/vnd,intc.yaml
new file mode 100644
index 0000000000..ace8f796cb
--- /dev/null
+++ b/dts/bindings/test/vnd,intc.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2020 Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test Interrupt Controller
+
+compatible: "vnd,intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/test/vnd,interrupt-holder.yaml b/dts/bindings/test/vnd,interrupt-holder.yaml
new file mode 100644
index 0000000000..38d611ad4d
--- /dev/null
+++ b/dts/bindings/test/vnd,interrupt-holder.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test Interrupt Controller
+
+compatible: "vnd,interrupt-holder"
+
+include: [base.yaml]
+
+properties:
+    interrupts:
+      required: true
+
+    interrupt-names:
+      required: true
diff --git a/dts/bindings/test/vnd,mbox-zero-cell.yaml b/dts/bindings/test/vnd,mbox-zero-cell.yaml
new file mode 100644
index 0000000000..de88f53926
--- /dev/null
+++ b/dts/bindings/test/vnd,mbox-zero-cell.yaml
@@ -0,0 +1,11 @@
+# Copyright (c) 2021, Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: VND MBOX controller (0 cell)
+
+compatible: "vnd,mbox-zero-cell"
+
+properties:
+  label:
+    type: string
+    required: true
diff --git a/dts/bindings/test/vnd,mbox.yaml b/dts/bindings/test/vnd,mbox.yaml
new file mode 100644
index 0000000000..bb731f008c
--- /dev/null
+++ b/dts/bindings/test/vnd,mbox.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021, Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: VND MBOX controller
+
+compatible: "vnd,mbox"
+
+include: mailbox-controller.yaml
+
+properties:
+  label:
+    type: string
+    required: true
+
+mbox-cells:
+  - channel
diff --git a/dts/bindings/test/vnd,pcie.yaml b/dts/bindings/test/vnd,pcie.yaml
new file mode 100644
index 0000000000..fa178cd2ac
--- /dev/null
+++ b/dts/bindings/test/vnd,pcie.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test PCIe bus controller
+
+compatible: vnd,pcie
+
+include: base.yaml
+
+bus: pcie
diff --git a/dts/bindings/test/vnd,phandle-holder.yaml b/dts/bindings/test/vnd,phandle-holder.yaml
new file mode 100644
index 0000000000..daf0b0beba
--- /dev/null
+++ b/dts/bindings/test/vnd,phandle-holder.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test phandle property container
+
+compatible: "vnd,phandle-holder"
+
+include: [base.yaml]
+
+properties:
+  ph: {type: "phandle"}
+  phs: {type: "phandles"}
+  phs-or: {type: "phandles"}
+  pha-gpios: {type: "phandle-array"}
+  gpios: {type: "phandle-array"}
+  foos: {type: "phandle-array"}
+  foo-names: {type: "string-array"}
+  pwms: {type: "phandle-array"}
+  pwm-names: {type: "string-array"}
+  bar:
+    type: "phandle-array"
+    specifier-space: baz
+  baz-names: {type: "string-array"}
diff --git a/dts/bindings/test/vnd,pinctrl-device.yaml b/dts/bindings/test/vnd,pinctrl-device.yaml
new file mode 100644
index 0000000000..3f8e18c88b
--- /dev/null
+++ b/dts/bindings/test/vnd,pinctrl-device.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test device for pin controller.
+
+compatible: "vnd,pinctrl-device"
+
+include: [base.yaml, pinctrl-device.yaml]
diff --git a/dts/bindings/test/vnd,pinctrl-test.yaml b/dts/bindings/test/vnd,pinctrl-test.yaml
new file mode 100644
index 0000000000..d0c74ac236
--- /dev/null
+++ b/dts/bindings/test/vnd,pinctrl-test.yaml
@@ -0,0 +1,59 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Test pin controller.
+
+compatible: "vnd,pinctrl-test"
+
+include:
+    - name: base.yaml
+    - name: pincfg-node-group.yaml
+      child-binding:
+        child-binding:
+          property-allowlist:
+            - bias-pull-down
+            - bias-pull-up
+
+child-binding:
+  description: |
+    Test pin controller pin configuration nodes. Each node is composed by one or
+    more groups, each defining the configuration for a set of pins.
+
+  child-binding:
+    description: |
+      Test pin controller pin configuration group. Each group contains a list of
+      pins sharing the same set of properties. Example:
+
+      /* node representing default state for test_device0 */
+      test_device0_default: test_device0_default {
+        /* group 1 (name is arbitrary) */
+        pins1 {
+          /* configure pins 0 and 1 */
+          pins = <0>, <1>;
+          /* both pins 0 and 1 have pull-up enabled */
+          bias-pull-up;
+        };
+        ...
+        /* group N (name is arbitrary) */
+        pinsN {
+          /* configure pin M */
+          pins = <M>;
+          /* pin M has pull-down enabled */
+          bias-pull-down;
+        };
+      };
+
+      The list of supported standard properties:
+
+      - bias-pull-up: Enable pull-up resistor.
+      - bias-pull-down: Enable pull-down resistor.
+
+    properties:
+      pins:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. Each entry is a
+          32-bit integer that is just used to identify the entry for testing
+          purposes.
diff --git a/dts/bindings/test/vnd,pinctrl.yaml b/dts/bindings/test/vnd,pinctrl.yaml
new file mode 100644
index 0000000000..59169925a6
--- /dev/null
+++ b/dts/bindings/test/vnd,pinctrl.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test pin controller node
+
+compatible: "vnd,pinctrl"
+
+include: pincfg-node.yaml
diff --git a/dts/bindings/test/vnd,pwm.yaml b/dts/bindings/test/vnd,pwm.yaml
new file mode 100644
index 0000000000..0a6b11f572
--- /dev/null
+++ b/dts/bindings/test/vnd,pwm.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: VND PWM controller
+
+compatible: "vnd,pwm"
+
+include: [pwm-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#pwm-cells":
+      const: 3
+
+pwm-cells:
+  - channel
+  - period
+  - flags
diff --git a/dts/bindings/test/vnd,reg-holder.yaml b/dts/bindings/test/vnd,reg-holder.yaml
new file mode 100644
index 0000000000..c2685a49e3
--- /dev/null
+++ b/dts/bindings/test/vnd,reg-holder.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020 Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test register property container
+
+compatible: "vnd,reg-holder"
+
+include: [base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    reg-names:
+      required: true
+
+    misc-prop:
+      type: int
diff --git a/dts/bindings/test/vnd,serial.yaml b/dts/bindings/test/vnd,serial.yaml
new file mode 100644
index 0000000000..37cf76c316
--- /dev/null
+++ b/dts/bindings/test/vnd,serial.yaml
@@ -0,0 +1,13 @@
+description: Test serial port
+
+compatible: "vnd,serial"
+
+include: uart-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    baud-rate:
+      type: int
+      required: false
diff --git a/dts/bindings/test/vnd,spi-device-2.yaml b/dts/bindings/test/vnd,spi-device-2.yaml
new file mode 100644
index 0000000000..79983f1641
--- /dev/null
+++ b/dts/bindings/test/vnd,spi-device-2.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test SPI device 2
+
+compatible: "vnd,spi-device-2"
+
+include: spi-device.yaml
diff --git a/dts/bindings/test/vnd,spi-device.yaml b/dts/bindings/test/vnd,spi-device.yaml
new file mode 100644
index 0000000000..7bf2eeccc7
--- /dev/null
+++ b/dts/bindings/test/vnd,spi-device.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test SPI device
+
+compatible: "vnd,spi-device"
+
+include: spi-device.yaml
diff --git a/dts/bindings/test/vnd,spi.yaml b/dts/bindings/test/vnd,spi.yaml
new file mode 100644
index 0000000000..edd12ad202
--- /dev/null
+++ b/dts/bindings/test/vnd,spi.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test SPI node
+
+compatible: "vnd,spi"
+
+include: [spi-controller.yaml, base.yaml]
diff --git a/dts/bindings/timer/arm,armv8-timer.yaml b/dts/bindings/timer/arm,armv8-timer.yaml
new file mode 100644
index 0000000000..bf9736b73d
--- /dev/null
+++ b/dts/bindings/timer/arm,armv8-timer.yaml
@@ -0,0 +1,12 @@
+description: per-core ARM architected timer
+
+compatible: "arm,armv8-timer"
+
+include: base.yaml
+
+properties:
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/timer/arm,cmsdk-dtimer.yaml b/dts/bindings/timer/arm,cmsdk-dtimer.yaml
new file mode 100644
index 0000000000..4d5de327f1
--- /dev/null
+++ b/dts/bindings/timer/arm,cmsdk-dtimer.yaml
@@ -0,0 +1,15 @@
+description: ARM CMSDK dual timer
+
+compatible: "arm,cmsdk-dtimer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/timer/arm,cmsdk-timer.yaml b/dts/bindings/timer/arm,cmsdk-timer.yaml
new file mode 100644
index 0000000000..e5b9c70883
--- /dev/null
+++ b/dts/bindings/timer/arm,cmsdk-timer.yaml
@@ -0,0 +1,15 @@
+description: ARM CMSDK timer
+
+compatible: "arm,cmsdk-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/timer/atmel,sam-tc.yaml b/dts/bindings/timer/atmel,sam-tc.yaml
new file mode 100644
index 0000000000..b1eb447187
--- /dev/null
+++ b/dts/bindings/timer/atmel,sam-tc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Timer Counter (TC) node
+
+compatible: "atmel,sam-tc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    peripheral-id:
+      type: array
+      description: peripheral ID
+      required: true
+
+    channel:
+      type: int
+      required: false
+      description: |
+        Timer / Counter channel to use, channel 0 is the default.
+        Valid range: 0 - 2
+
+    clk:
+      type: int
+      required: false
+      description: |
+        Clock source selection as defined by TCCLKS bit-field of TC_CMR
+        register. Consult the datasheet for the details.
+
+    nodivclk:
+      type: boolean
+      required: false
+      description: |
+        If set to true the `clk` property is ignored. Instead the TC module is
+        driven directly via MCLK. Only supported on sam4e, same70, same70b,
+        samv71, samv71b SoC series.
+
+    reg-cmr:
+      type: int
+      required: false
+      description: |
+        Alternate value of the CMR (Channel Mode Register) register.
+        If specified this value will be written to the register during driver
+        instance initialization instead of the default. It can be used to
+        configure the timer / counter in the custom mode. Together with other
+        properties like channel-num, pinctrl-0 this allows e.g. to configure
+        the driver to count events generated on the TIOA, TIOB signal connected
+        to the external pin.
+
+    pinctrl-0:
+      type: phandles
+      required: false
+      description: |
+        PIO pin configuration for Timer Counter signals.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the TC0 on SAME7x would be
+           pinctrl-0 = <&pa0b_tc0_tioa0 &pa1b_tc0_tiob0>;
diff --git a/dts/bindings/timer/atmel,sam0-tc32.yaml b/dts/bindings/timer/atmel,sam0-tc32.yaml
new file mode 100644
index 0000000000..c8cf443050
--- /dev/null
+++ b/dts/bindings/timer/atmel,sam0-tc32.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 basic timer counter (TC) operating in 32-bit wide mode
+
+compatible: "atmel,sam0-tc32"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clocks:
+    required: true
+
+  clock-names:
+    required: true
+
+  label:
+    required: true
+
+  prescaler:
+    type: int
+    required: false
+    description: Timer prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 64
+      - 256
+      - 1024
diff --git a/dts/bindings/timer/espressif,esp32-systimer.yaml b/dts/bindings/timer/espressif,esp32-systimer.yaml
new file mode 100644
index 0000000000..40670d6d86
--- /dev/null
+++ b/dts/bindings/timer/espressif,esp32-systimer.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Espressif ESP32 Systimer peripheral
+
+compatible: "espressif,esp32-systimer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/timer/gaisler,gptimer.yaml b/dts/bindings/timer/gaisler,gptimer.yaml
new file mode 100644
index 0000000000..09a8c9deaf
--- /dev/null
+++ b/dts/bindings/timer/gaisler,gptimer.yaml
@@ -0,0 +1,12 @@
+description: GRLIB GPTIMER
+
+compatible: "gaisler,gptimer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/timer/intel,hpet.yaml b/dts/bindings/timer/intel,hpet.yaml
new file mode 100644
index 0000000000..4a9a16136d
--- /dev/null
+++ b/dts/bindings/timer/intel,hpet.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: HPET (High-Precision Event Timer)
+
+compatible: "intel,hpet"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/timer/ite,it8xxx2-timer.yaml b/dts/bindings/timer/ite,it8xxx2-timer.yaml
new file mode 100644
index 0000000000..73701ce1da
--- /dev/null
+++ b/dts/bindings/timer/ite,it8xxx2-timer.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE Ext-timer
+
+compatible: "ite,it8xxx2-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/timer/litex,timer0.yaml b/dts/bindings/timer/litex,timer0.yaml
new file mode 100644
index 0000000000..e892d69d4d
--- /dev/null
+++ b/dts/bindings/timer/litex,timer0.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX timer
+
+compatible: "litex,timer0"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/timer/microchip,xec-rtos-timer.yaml b/dts/bindings/timer/microchip,xec-rtos-timer.yaml
new file mode 100644
index 0000000000..30234e8249
--- /dev/null
+++ b/dts/bindings/timer/microchip,xec-rtos-timer.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2019 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC RTOS timer
+
+compatible: "microchip,xec-rtos-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    girqs:
+      type: array
+      required: true
+      description: Array of GIRQ numbers [8:26] and bit positions [0:31].
+
+    "#girq-cells":
+      type: int
+      const: 2
+
+girq-cells:
+    - girq_num
+    - bitpos
diff --git a/dts/bindings/timer/nordic,nrf-timer.yaml b/dts/bindings/timer/nordic,nrf-timer.yaml
new file mode 100644
index 0000000000..bca489bcf0
--- /dev/null
+++ b/dts/bindings/timer/nordic,nrf-timer.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF timer node
+
+compatible: "nordic,nrf-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    cc-num:
+      type: int
+      required: true
+      description: Number of capture/compare (CC) registers available
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    prescaler:
+      type: int
+      required: true
+      description: Prescaler value determines frequency (16MHz/2^prescaler)
diff --git a/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml b/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml
new file mode 100644
index 0000000000..47dbf94c47
--- /dev/null
+++ b/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Internal Timer (ITIM) node
+
+compatible: "nuvoton,npcx-itim-timer"
+
+include: base.yaml
+
+properties:
+    reg:
+        required: true
+
+    interrupts:
+        required: true
+
+    label:
+        required: true
diff --git a/dts/bindings/timer/nxp,imx-gpt.yaml b/dts/bindings/timer/nxp,imx-gpt.yaml
new file mode 100644
index 0000000000..59310cf769
--- /dev/null
+++ b/dts/bindings/timer/nxp,imx-gpt.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUX General-Purpose Timer (GPT)
+
+compatible: "nxp,imx-gpt"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    gptfreq:
+      type: int
+      required: true
+      description: gpt frequences
diff --git a/dts/bindings/timer/nxp,lpc-ctimer.yaml b/dts/bindings/timer/nxp,lpc-ctimer.yaml
new file mode 100644
index 0000000000..e787f5513b
--- /dev/null
+++ b/dts/bindings/timer/nxp,lpc-ctimer.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2021 Toby Firth
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUX Standard Timer/Counter
+
+compatible: "nxp,lpc-ctimer"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    clk-source:
+      type: int
+      required: true
+      description: clock to use
+
+    mode:
+      type: int
+      required: true
+      description: timer mode
+
+    input:
+      type: int
+      required: true
+      description: input channel
+
+    prescale:
+      type: int
+      required: true
+      description: prescale value
diff --git a/dts/bindings/timer/openisa,rv32m1-lptmr.yaml b/dts/bindings/timer/openisa,rv32m1-lptmr.yaml
new file mode 100644
index 0000000000..cb39f21a89
--- /dev/null
+++ b/dts/bindings/timer/openisa,rv32m1-lptmr.yaml
@@ -0,0 +1,15 @@
+description: OpenISA RV32M1 LPTMR peripheral
+
+compatible: "openisa,rv32m1-lptmr"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/timer/renesas,rcar-cmt.yaml b/dts/bindings/timer/renesas,rcar-cmt.yaml
new file mode 100644
index 0000000000..7a8078005d
--- /dev/null
+++ b/dts/bindings/timer/renesas,rcar-cmt.yaml
@@ -0,0 +1,23 @@
+description: Renesas R-Car CMT timer
+
+compatible: "renesas,rcar-cmt"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    clock-frequency:
+      type: int
+      required: true
+      description: Clock frequency information for Timer operation
+
+    clocks:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/timer/riscv,machine-timer.yaml b/dts/bindings/timer/riscv,machine-timer.yaml
new file mode 100644
index 0000000000..149914f406
--- /dev/null
+++ b/dts/bindings/timer/riscv,machine-timer.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: RISC-V Machine timer
+
+compatible: "nuclei,machine-timer"
+
+include: base.yaml
+
+properties:
+    clk-divider:
+      type: int
+      required: false
+      description: |
+        clk-divider specifies the division ratio to the CPU frequency that
+        clock used by machine timer.
+        This property supports the case that the machine timer and CPU use
+        different clock sources.
+        This configuration is used sometimes for such as low power consumption.
+
+        For example, the CPU clock frequency is 108MHz, and the machine timer
+        uses 27MHz, which is the CPU clock divided by 4.
+        In this case, the CPU clock frequency is defined in the CPU node
+        as follows
+
+           clock-frequency = <108000000>;
+
+        This property takes exponent of the power of 2.
+        The relationship with the frequency division ratio is as
+        following equation.
+
+           division_ratio = 2^n
+           n = log_2(division_ratio)
+
+        Setting clk-divider to 2 specifies the machine timer uses the clock
+        that CPU clock frequency divided by (2^2=)4, or 27MHz.
+
+        Devision ratio constants can be found in the
+        dt-bindings/timer/nuclei-machine-timer.h header file.
diff --git a/dts/bindings/timer/silabs,gecko-timer.yaml b/dts/bindings/timer/silabs,gecko-timer.yaml
new file mode 100644
index 0000000000..28eb33756c
--- /dev/null
+++ b/dts/bindings/timer/silabs,gecko-timer.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021, Sun Amar
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silabs gecko timer node
+
+compatible: "silabs,gecko-timer"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
diff --git a/dts/bindings/timer/st,stm32-lptim.yaml b/dts/bindings/timer/st,stm32-lptim.yaml
new file mode 100644
index 0000000000..1b45ad799a
--- /dev/null
+++ b/dts/bindings/timer/st,stm32-lptim.yaml
@@ -0,0 +1,11 @@
+# Copyright (c) 2020, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 lptim
+
+compatible: "st,stm32-lptim"
+
+include:
+  - name: st,stm32-timers.yaml
+    property-blocklist:
+        - st,prescaler
diff --git a/dts/bindings/timer/st,stm32-timers.yaml b/dts/bindings/timer/st,stm32-timers.yaml
new file mode 100644
index 0000000000..5e80398999
--- /dev/null
+++ b/dts/bindings/timer/st,stm32-timers.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2020, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 timers
+
+compatible: "st,stm32-timers"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+    interrupts:
+      required: false
+
+    st,prescaler:
+      type: int
+      required: true
+      description: |
+        Clock prescaler at the input of the timer
+        Could be in range [0 .. 0xFFFF] for STM32 General Purpose Timers (CLK/(prescaler+1) )
diff --git a/dts/bindings/timer/xlnx,ttcps.yaml b/dts/bindings/timer/xlnx,ttcps.yaml
new file mode 100644
index 0000000000..b1aa3d4f20
--- /dev/null
+++ b/dts/bindings/timer/xlnx,ttcps.yaml
@@ -0,0 +1,17 @@
+description: Xilinx ZynqMP PS TTC timer
+
+compatible: "xlnx,ttcps"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
+
+    clock-frequency:
+      type: int
+      required: true
+      description: Clock frequency information for Timer operation
diff --git a/dts/bindings/usb/atmel,sam-usbc.yaml b/dts/bindings/usb/atmel,sam-usbc.yaml
new file mode 100644
index 0000000000..929f1279ed
--- /dev/null
+++ b/dts/bindings/usb/atmel,sam-usbc.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2018 Aurelien Jarno
+# Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Atmel SAM Family USB (USBC) in device mode
+
+compatible: "atmel,sam-usbc"
+
+include: usb-ep.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: peripheral ID
+
+    pinctrl-0:
+      type: phandles
+      required: true
+      description: |
+        GPIO pin configuration for DM & DP signals. We expect that
+        the phandles will reference pinctrl nodes. These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the USBC on SAM4L would be
+          pinctrl-0 = <&pa25a_usbc_dm &pa26a_usbc_dp>;
diff --git a/dts/bindings/usb/atmel,sam-usbhs.yaml b/dts/bindings/usb/atmel,sam-usbhs.yaml
new file mode 100644
index 0000000000..1d6fa2df43
--- /dev/null
+++ b/dts/bindings/usb/atmel,sam-usbhs.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2018 Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Atmel SAM Family USB (USBHS) in device mode
+
+compatible: "atmel,sam-usbhs"
+
+include: usb-ep.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      required: true
+      description: peripheral ID
diff --git a/dts/bindings/usb/atmel,sam0-usb.yaml b/dts/bindings/usb/atmel,sam0-usb.yaml
new file mode 100644
index 0000000000..af4dcbae65
--- /dev/null
+++ b/dts/bindings/usb/atmel,sam0-usb.yaml
@@ -0,0 +1,13 @@
+description: |
+    Atmel SAM0 USB in device mode
+
+compatible: "atmel,sam0-usb"
+
+include: usb-ep.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/usb/nordic,nrf-usbd.yaml b/dts/bindings/usb/nordic,nrf-usbd.yaml
new file mode 100644
index 0000000000..4fd6c2acdd
--- /dev/null
+++ b/dts/bindings/usb/nordic,nrf-usbd.yaml
@@ -0,0 +1,26 @@
+# Copyright (c) 2018, Sundar Subramaniyan <sundar.subramaniyan@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Nordic nRF52 USB device controller
+
+compatible: "nordic,nrf-usbd"
+
+include: usb-ep.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    num-isoin-endpoints:
+      type: int
+      required: true
+      description: Number of ISOIN endpoints supported by hardware
+
+    num-isoout-endpoints:
+      type: int
+      required: true
+      description: Number of ISOOUT endpoints supported by hardware
diff --git a/dts/bindings/usb/nxp,kinetis-usbd.yaml b/dts/bindings/usb/nxp,kinetis-usbd.yaml
new file mode 100644
index 0000000000..e7ee211b24
--- /dev/null
+++ b/dts/bindings/usb/nxp,kinetis-usbd.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2018 PHYTEC Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    NPX Kinetis USBFSOTG Controller in device mode
+
+compatible: "nxp,kinetis-usbd"
+
+include: usb-ep.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/usb/nxp,mcux-usbd.yaml b/dts/bindings/usb/nxp,mcux-usbd.yaml
new file mode 100644
index 0000000000..7ddba4970e
--- /dev/null
+++ b/dts/bindings/usb/nxp,mcux-usbd.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    NPX MXRT and LPC USBOTG Controller in device mode
+
+compatible: "nxp,mcux-usbd"
+
+include: usb-ep.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/usb/snps,designware-usb.yaml b/dts/bindings/usb/snps,designware-usb.yaml
new file mode 100644
index 0000000000..68264c51b7
--- /dev/null
+++ b/dts/bindings/usb/snps,designware-usb.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys Designware USB Controller node
+
+compatible: "snps,designware-usb"
+
+include: usb-ep.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/usb/st,stm32-otgfs.yaml b/dts/bindings/usb/st,stm32-otgfs.yaml
new file mode 100644
index 0000000000..4f46a8d4a3
--- /dev/null
+++ b/dts/bindings/usb/st,stm32-otgfs.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2017, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 OTGFS controller
+
+compatible: "st,stm32-otgfs"
+
+include: [usb-ep.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    ram-size:
+      type: int
+      required: true
+      description: |
+        Size of USB dedicated RAM. STM32 SOC's reference
+        manual defines a shared FIFO size.
+
+    phys:
+      type: phandle
+      required: false
+      description: PHY provider specifier
+
+    clocks:
+      required: true
diff --git a/dts/bindings/usb/st,stm32-otghs.yaml b/dts/bindings/usb/st,stm32-otghs.yaml
new file mode 100644
index 0000000000..ea857222d8
--- /dev/null
+++ b/dts/bindings/usb/st,stm32-otghs.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2017, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 OTGHS controller
+
+compatible: "st,stm32-otghs"
+
+include: [usb-ep.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    ram-size:
+      type: int
+      required: true
+      description: |
+        Size of USB dedicated RAM. STM32 SOC's reference
+        manual defines a shared FIFO size.
+
+    phys:
+      type: phandle
+      required: false
+      description: PHY provider specifier
+
+    clocks:
+      required: true
diff --git a/dts/bindings/usb/st,stm32-usb.yaml b/dts/bindings/usb/st,stm32-usb.yaml
new file mode 100644
index 0000000000..5b4d9596ac
--- /dev/null
+++ b/dts/bindings/usb/st,stm32-usb.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2017, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 USB controller
+
+compatible: "st,stm32-usb"
+
+include: [usb-ep.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    ram-size:
+      type: int
+      required: true
+      description: |
+        Size of USB dedicated RAM. STM32 SOC's reference
+        manual defines USB packet SRAM size.
+
+    disconnect-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Some boards use a USB DISCONNECT pin to enable
+        the pull-up resistor on USB Data Positive signal.
+
+    phys:
+      type: phandle
+      required: false
+      description: PHY provider specifier
+
+    enable-pin-remap:
+      type: boolean
+      required: false
+      description: |
+        For STM32F0 series SoCs on QFN28 and TSSOP20 packages
+        enable PIN pair PA11/12 mapped instead of PA9/10 (e.g. stm32f070x6).
+        Deprecated in favor of 'remap-pa11-pa12' from 'st-stm32-pinctrl'
+
+    clocks:
+      required: true
diff --git a/dts/bindings/usb/usb-audio-hp.yaml b/dts/bindings/usb/usb-audio-hp.yaml
new file mode 100644
index 0000000000..788b717b01
--- /dev/null
+++ b/dts/bindings/usb/usb-audio-hp.yaml
@@ -0,0 +1,121 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Specific fields for USB audio headphones.
+
+description: USB Audio headphones specific fields.
+
+compatible: "usb-audio-hp"
+
+include: usb-audio.yaml
+
+properties:
+  resolution:
+    type: int
+    default: 16
+    required: false
+    enum:
+     - 8
+     - 16
+     - 24
+     - 32
+# channel configuration options
+  channel-l:
+    type: boolean
+    required: false
+    description: Enable (l) channel.
+  channel-r:
+    type: boolean
+    required: false
+    description: Enable (r) channel.
+  channel-c:
+    type: boolean
+    required: false
+    description: Enable (c) channel.
+  channel-lfe:
+    type: boolean
+    required: false
+    description: Enable (lfe) channel.
+  channel-ls:
+    type: boolean
+    required: false
+    description: Enable (ls) channel.
+  channel-rs:
+    type: boolean
+    required: false
+    description: Enable (rs) channel.
+  channel-lc:
+    type: boolean
+    required: false
+    description: Enable (lc) channel.
+  channel-rc:
+    type: boolean
+    required: false
+    description: Enable (rc) channel.
+  channel-s:
+    type: boolean
+    required: false
+    description: Enable (s) channel.
+  channel-sl:
+    type: boolean
+    required: false
+    description: Enable (sl) channel.
+  channel-sr:
+    type: boolean
+    required: false
+    description: Enable (sr) channel.
+  channel-t:
+    type: boolean
+    required: false
+    description: Enable (t) channel.
+  channel-cfg:
+    type: boolean
+    required: false
+    description: Enable (cfg) channel.
+# feature unit configuration options
+  feature-mute:
+    type: boolean
+    required: true
+    description: Enable Mute feature.
+  feature-volume:
+    type: boolean
+    required: false
+    description: |
+      Enable Volume feature.
+      Currently not supported.
+  feature-tone-control:
+    type: boolean
+    required: false
+    description: |
+      Enable Tone Control (Bass, Mid, Treble) feature.
+      Currently not supported.
+  feature-graphic-equalizer:
+    type: boolean
+    required: false
+    description: |
+      Enable  Graphic Equalizer feature.
+      Currently not supported.
+  feature-automatic-gain-control:
+    type: boolean
+    required: false
+    description: |
+      Enable Autoamtic Gain Control feature.
+      Currently not supported.
+  feature-delay:
+    type: boolean
+    required: false
+    description: |
+      Enable Delay feature.
+      Currently not supported.
+  feature-bass-boost:
+    type: boolean
+    required: false
+    description: |
+      Enable Bass Boost feature.
+      Currently not supported.
+  feature-loudness:
+    type: boolean
+    required: false
+    description: |
+      Enable Loudness feature.
+      Currently not supported.
diff --git a/dts/bindings/usb/usb-audio-hs.yaml b/dts/bindings/usb/usb-audio-hs.yaml
new file mode 100644
index 0000000000..61d79d20ad
--- /dev/null
+++ b/dts/bindings/usb/usb-audio-hs.yaml
@@ -0,0 +1,243 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Specific fields for USB audio headset.
+
+description: USB Audio headset specific fields.
+
+compatible: "usb-audio-hs"
+
+include: usb-audio.yaml
+
+properties:
+  mic-resolution:
+    type: int
+    default: 16
+    required: false
+    enum:
+     - 8
+     - 16
+     - 24
+     - 32
+  mic-sync-type:
+    required: false
+    default: "Synchronous"
+    type: string
+    description: |
+      Type of endpoint synchronization for IN devices.
+      Default value is Sychronous.
+      Adaptive is not supported.
+    enum:
+     - "No Synchronization"
+     - "Asynchronous"
+     - "Adaptive"
+     - "Synchronous"
+  hp-resolution:
+    type: int
+    default: 16
+    required: false
+    enum:
+     - 8
+     - 16
+     - 24
+     - 32
+# microphone channel configuration options
+  mic-channel-l:
+    type: boolean
+    required: false
+    description: Enable (l) channel.
+  mic-channel-r:
+    type: boolean
+    required: false
+    description: Enable (r) channel.
+  mic-channel-c:
+    type: boolean
+    required: false
+    description: Enable (c) channel.
+  mic-channel-lfe:
+    type: boolean
+    required: false
+    description: Enable (lfe) channel.
+  mic-channel-ls:
+    type: boolean
+    required: false
+    description: Enable (ls) channel.
+  mic-channel-rs:
+    type: boolean
+    required: false
+    description: Enable (rs) channel.
+  mic-channel-lc:
+    type: boolean
+    required: false
+    description: Enable (lc) channel.
+  mic-channel-rc:
+    type: boolean
+    required: false
+    description: Enable (rc) channel.
+  mic-channel-s:
+    type: boolean
+    required: false
+    description: Enable (s) channel.
+  mic-channel-sl:
+    type: boolean
+    required: false
+    description: Enable (sl) channel.
+  mic-channel-sr:
+    type: boolean
+    required: false
+    description: Enable (sr) channel.
+  mic-channel-t:
+    type: boolean
+    required: false
+    description: Enable (t) channel.
+  mic-channel-cfg:
+    type: boolean
+    required: false
+    description: Enable (cfg) channel.
+# microphone feature unit configuration options
+  mic-feature-mute:
+    type: boolean
+    required: true
+    description: Enable Mute feature.
+  mic-feature-volume:
+    type: boolean
+    required: false
+    description: |
+      Enable Volume feature.
+      Currently not supported.
+  mic-feature-tone-control:
+    type: boolean
+    required: false
+    description: |
+      Enable Tone Control (Bass, Mid, Treble) feature.
+      Currently not supported.
+  mic-feature-graphic-equalizer:
+    type: boolean
+    required: false
+    description: |
+      Enable  Graphic Equalizer feature.
+      Currently not supported.
+  mic-feature-automatic-gain-control:
+    type: boolean
+    required: false
+    description: |
+      Enable Autoamtic Gain Control feature.
+      Currently not supported.
+  mic-feature-delay:
+    type: boolean
+    required: false
+    description: |
+      Enable Delay feature.
+      Currently not supported.
+  mic-feature-bass-boost:
+    type: boolean
+    required: false
+    description: |
+      Enable Bass Boost feature.
+      Currently not supported.
+  mic-feature-loudness:
+    type: boolean
+    required: false
+    description: |
+      Enable Loudness feature.
+      Currently not supported.
+# headphones channel configuration options
+  hp-channel-l:
+    type: boolean
+    required: false
+    description: Enable (l) channel.
+  hp-channel-r:
+    type: boolean
+    required: false
+    description: Enable (r) channel.
+  hp-channel-c:
+    type: boolean
+    required: false
+    description: Enable (c) channel.
+  hp-channel-lfe:
+    type: boolean
+    required: false
+    description: Enable (lfe) channel.
+  hp-channel-ls:
+    type: boolean
+    required: false
+    description: Enable (ls) channel.
+  hp-channel-rs:
+    type: boolean
+    required: false
+    description: Enable (rs) channel.
+  hp-channel-lc:
+    type: boolean
+    required: false
+    description: Enable (lc) channel.
+  hp-channel-rc:
+    type: boolean
+    required: false
+    description: Enable (rc) channel.
+  hp-channel-s:
+    type: boolean
+    required: false
+    description: Enable (s) channel.
+  hp-channel-sl:
+    type: boolean
+    required: false
+    description: Enable (sl) channel.
+  hp-channel-sr:
+    type: boolean
+    required: false
+    description: Enable (sr) channel.
+  hp-channel-t:
+    type: boolean
+    required: false
+    description: Enable (t) channel.
+  hp-channel-cfg:
+    type: boolean
+    required: false
+    description: Enable (cfg) channel.
+# headphones feature unit configuration options
+  hp-feature-mute:
+    type: boolean
+    required: true
+    description: Enable Mute feature.
+  hp-feature-volume:
+    type: boolean
+    required: false
+    description: |
+      Enable Volume feature.
+      Currently not supported.
+  hp-feature-tone-control:
+    type: boolean
+    required: false
+    description: |
+      Enable Tone Control (Bass, Mid, Treble) feature.
+      Currently not supported.
+  hp-feature-graphic-equalizer:
+    type: boolean
+    required: false
+    description: |
+      Enable  Graphic Equalizer feature.
+      Currently not supported.
+  hp-feature-automatic-gain-control:
+    type: boolean
+    required: false
+    description: |
+      Enable Autoamtic Gain Control feature.
+      Currently not supported.
+  hp-feature-delay:
+    type: boolean
+    required: false
+    description: |
+      Enable Delay feature.
+      Currently not supported.
+  hp-feature-bass-boost:
+    type: boolean
+    required: false
+    description: |
+      Enable Bass Boost feature.
+      Currently not supported.
+  hp-feature-loudness:
+    type: boolean
+    required: false
+    description: |
+      Enable Loudness feature.
+      Currently not supported.
diff --git a/dts/bindings/usb/usb-audio-mic.yaml b/dts/bindings/usb/usb-audio-mic.yaml
new file mode 100644
index 0000000000..eb71b700bc
--- /dev/null
+++ b/dts/bindings/usb/usb-audio-mic.yaml
@@ -0,0 +1,134 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Specific fields for USB audio microphone.
+
+description: USB Audio microphone specific fields.
+
+compatible: "usb-audio-mic"
+
+include: usb-audio.yaml
+
+properties:
+  resolution:
+    type: int
+    default: 16
+    required: false
+    enum:
+     - 8
+     - 16
+     - 24
+     - 32
+  sync-type:
+    required: false
+    default: "Synchronous"
+    type: string
+    description: |
+      Type of endpoint synchronization for IN devices.
+      Default value is Sychronous.
+      Adaptive is not supported.
+    enum:
+     - "No Synchronization"
+     - "Asynchronous"
+     - "Adaptive"
+     - "Synchronous"
+# channel configuration options
+  channel-l:
+    type: boolean
+    required: false
+    description: Enable (l) channel.
+  channel-r:
+    type: boolean
+    required: false
+    description: Enable (r) channel.
+  channel-c:
+    type: boolean
+    required: false
+    description: Enable (c) channel.
+  channel-lfe:
+    type: boolean
+    required: false
+    description: Enable (lfe) channel.
+  channel-ls:
+    type: boolean
+    required: false
+    description: Enable (ls) channel.
+  channel-rs:
+    type: boolean
+    required: false
+    description: Enable (rs) channel.
+  channel-lc:
+    type: boolean
+    required: false
+    description: Enable (lc) channel.
+  channel-rc:
+    type: boolean
+    required: false
+    description: Enable (rc) channel.
+  channel-s:
+    type: boolean
+    required: false
+    description: Enable (s) channel.
+  channel-sl:
+    type: boolean
+    required: false
+    description: Enable (sl) channel.
+  channel-sr:
+    type: boolean
+    required: false
+    description: Enable (sr) channel.
+  channel-t:
+    type: boolean
+    required: false
+    description: Enable (t) channel.
+  channel-cfg:
+    type: boolean
+    required: false
+    description: Enable (cfg) channel.
+# feature unit configuration options
+  feature-mute:
+    type: boolean
+    required: true
+    description: Enable Mute feature.
+  feature-volume:
+    type: boolean
+    required: false
+    description: |
+      Enable Volume feature.
+      Currently not supported.
+  feature-tone-control:
+    type: boolean
+    required: false
+    description: |
+      Enable Tone Control (Bass, Mid, Treble) feature.
+      Currently not supported.
+  feature-graphic-equalizer:
+    type: boolean
+    required: false
+    description: |
+      Enable  Graphic Equalizer feature.
+      Currently not supported.
+  feature-automatic-gain-control:
+    type: boolean
+    required: false
+    description: |
+      Enable Autoamtic Gain Control feature.
+      Currently not supported.
+  feature-delay:
+    type: boolean
+    required: false
+    description: |
+      Enable Delay feature.
+      Currently not supported.
+  feature-bass-boost:
+    type: boolean
+    required: false
+    description: |
+      Enable Bass Boost feature.
+      Currently not supported.
+  feature-loudness:
+    type: boolean
+    required: false
+    description: |
+      Enable Loudness feature.
+      Currently not supported.
diff --git a/dts/bindings/usb/usb-audio.yaml b/dts/bindings/usb/usb-audio.yaml
new file mode 100644
index 0000000000..21b4ce7b8f
--- /dev/null
+++ b/dts/bindings/usb/usb-audio.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for USB audio class
+
+description: Common fields for USB audio devices
+compatible: "usb-audio"
+
+properties:
+  label:
+    required: true
+    type: string
+    description: Human readable string describing the device (used as device_get_binding() argument)
diff --git a/dts/bindings/usb/usb-controller.yaml b/dts/bindings/usb/usb-controller.yaml
new file mode 100644
index 0000000000..0521b79bb1
--- /dev/null
+++ b/dts/bindings/usb/usb-controller.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2018, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for USB controllers
+
+include: base.yaml
+
+bus: usb
+
+properties:
+    maximum-speed:
+      type: string
+      required: false
+      description: Configures USB controllers to work up to a specific
+                   speed. Valid arguments are "super-speed", "high-speed",
+                   "full-speed" and "low-speed". If this is not passed
+                   via DT, USB controllers should use their maximum
+                   hardware capability.
+      enum:
+         - "low-speed"
+         - "full-speed"
+         - "high-speed"
+         - "super-speed"
+
+    label:
+      required: true
+
+    vbus-gpios:
+      type: phandle-array
+      required: false
+      description: Control VBUS via GPIO pin.
diff --git a/dts/bindings/usb/usb-ep.yaml b/dts/bindings/usb/usb-ep.yaml
new file mode 100644
index 0000000000..66b4b5396c
--- /dev/null
+++ b/dts/bindings/usb/usb-ep.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2018, I-SENSE group of ICCS
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields that give the number of endpoints supported by the USB hardware
+
+include: usb-controller.yaml
+
+properties:
+    num-bidir-endpoints:
+      type: int
+      required: true
+      description: |
+        Number of bi-directional endpoints supported by hardware
+        (including EP0)
+
+    num-in-endpoints:
+      type: int
+      required: false
+      description: |
+        Number of IN endpoints supported by hardware
+        (including EP0 IN)
+
+    num-out-endpoints:
+      type: int
+      required: false
+      description: |
+        Number of OUT endpoints supported by hardware
+        (including EP0 OUT)
diff --git a/dts/bindings/usb/zephyr,native-posix-udc.yaml b/dts/bindings/usb/zephyr,native-posix-udc.yaml
new file mode 100644
index 0000000000..42794b3ed4
--- /dev/null
+++ b/dts/bindings/usb/zephyr,native-posix-udc.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Native POSIX USB device controller
+
+compatible: "zephyr,native-posix-udc"
+
+include: usb-controller.yaml
diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt
new file mode 100644
index 0000000000..373cbd83f9
--- /dev/null
+++ b/dts/bindings/vendor-prefixes.txt
@@ -0,0 +1,691 @@
+# Device tree binding vendor prefix registry. Keep this list in
+# alphabetical order.
+#
+# This isn't an exhaustive list, but you should add new prefixes to it
+# before using them to avoid name-space collisions.
+#
+# The contents of this file are parsed during documentation generation.
+# Anything that starts with a '#' is treated as a comment and ignored.
+# Non-empty lines should be in this format:
+#
+# <vendor-prefix><TAB><Full name of vendor>
+
+abb	ABB
+abilis	Abilis Systems
+abracon	Abracon Corporation
+abt	ShenZhen Asia Better Technology Ltd.
+acer	Acer Inc.
+acme	Acme Systems srl
+actions	Actions Semiconductor Co., Ltd.
+active-semi	Active-Semi International Inc
+ad	Avionic Design GmbH
+adafruit	Adafruit Industries, LLC
+adapteva	Adapteva, Inc.
+adaptrum	Adaptrum, Inc.
+adh	AD Holdings Plc.
+adi	Analog Devices, Inc.
+advantech	Advantech Corporation
+aeroflexgaisler	Aeroflex Gaisler AB
+aesop	AESOP Embedded Forum
+al	Annapurna Labs
+alcatel	Alcatel
+allegro	Allegro DVT
+allo	Allo.com
+allwinner	Allwinner Technology Co., Ltd.
+alphascale	AlphaScale Integrated Circuits Systems, Inc.
+alps	Alps Electric Co., Ltd.
+alt	Altus-Escon-Company BV
+altr	Altera Corp.
+amarula	Amarula Solutions
+amazon	Amazon.com, Inc.
+amcc	Applied Micro Circuits Corporation (APM, formally AMCC)
+amd	Advanced Micro Devices (AMD), Inc.
+amediatech	Shenzhen Amediatech Technology Co., Ltd
+amlogic	Amlogic, Inc.
+ampere	Ampere Computing LLC
+ampire	Ampire Co., Ltd.
+ams	AMS AG
+amstaos	AMS-Taos Inc.
+analogix	Analogix Semiconductor, Inc.
+andestech	Andes Technology Corporation
+anvo	Anvo-Systems Dresden GmbH
+aosong	Guangzhou Aosong Electronic Co., Ltd.
+apa	Apa Electronic Co., Ltd
+apm	Applied Micro Circuits Corporation (APM)
+apple	Apple Inc.
+aptina	Aptina Imaging
+arasan	Arasan Chip Systems
+archermind	ArcherMind Technology (Nanjing) Co., Ltd.
+arc	Synopsys, Inc. (formerly ARC International PLC)
+arctic	Arctic Sand
+arcx	arcx Inc. / Archronix Inc.
+arduino	Arduino
+aries	Aries Embedded GmbH
+arm	ARM Ltd.
+armadeus	ARMadeus Systems SARL
+arrow	Arrow Electronics
+artesyn	Artesyn Embedded Technologies Inc.
+asahi-kasei	Asahi Kasei Corp.
+asmedia	ASMedia Technology Inc.
+asc	All Sensors Corporation
+aspeed	ASPEED Technology Inc.
+asus	AsusTek Computer Inc.
+atlas	Atlas Scientific LLC
+atmel	Atmel Corporation
+auo	AU Optronics Corporation
+auvidea	Auvidea GmbH
+avago	Avago Technologies
+avia	avia semiconductor
+avic	Shanghai AVIC Optoelectronics Co., Ltd.
+avnet	Avnet, Inc.
+awinic	Shanghai Awinic Technology Co., Ltd.
+axentia	Axentia Technologies AB
+axis	Axis Communications AB
+azoteq	Azoteq (Pty) Ltd
+azw	Shenzhen AZW Technology Co., Ltd.
+baikal	BAIKAL ELECTRONICS, JSC
+bananapi	BIPAI KEJI LIMITED
+beacon	Compass Electronics Group, LLC
+beagle	BeagleBoard.org Foundation
+bhf	Beckhoff Automation GmbH & Co. KG
+bitmain	Bitmain Technologies
+blutek	BluTek Power
+boe	BOE Technology Group Co., Ltd.
+bosch	Bosch Sensortec GmbH
+boundary	Boundary Devices Inc.
+broadmobi	Shanghai Broadmobi Communication Technology Co.,Ltd.
+brcm	Broadcom Corporation
+buffalo	Buffalo, Inc.
+bur	B&R Industrial Automation GmbH
+bticino	Bticino International
+calaosystems	CALAO Systems SAS
+calxeda	Calxeda
+canaan	Canaan, Inc.
+caninos	Caninos Loucos Program
+capella	Capella Microsystems, Inc
+cascoda	Cascoda, Ltd.
+catalyst	Catalyst Semiconductor, Inc.
+cavium	Cavium, Inc.
+cdns	Cadence Design Systems Inc.
+cdtech	CDTech(H.K.) Electronics Limited
+cellwise	CellWise Microelectronics Co., Ltd
+ceva	Ceva, Inc.
+checkpoint	Check Point Software Technologies Ltd.
+chefree	Chefree Technology Corp.
+chipidea	Chipidea, Inc
+chipone	ChipOne
+chipspark	ChipSPARK
+chrontel	Chrontel, Inc.
+chrp	Common Hardware Reference Platform
+chunghwa	Chunghwa Picture Tubes Ltd.
+chuwi	Chuwi Innovation Ltd.
+ciaa	Computadora Industrial Abierta Argentina
+cirrus	Cirrus Logic, Inc.
+cisco	Cisco Systems, Inc.
+cloudengines	Cloud Engines, Inc.
+cnm	Chips&Media, Inc.
+cnxt	Conexant Systems, Inc.
+colorfly	Colorful GRP, Shenzhen Xueyushi Technology Ltd.
+compulab	CompuLab Ltd.
+coreriver	CORERIVER Semiconductor Co.,Ltd.
+corpro	Chengdu Corpro Technology Co., Ltd.
+cortina	Cortina Systems, Inc.
+cosmic	Cosmic Circuits
+crane	Crane Connectivity Solutions
+creative	Creative Technology Ltd
+crystalfontz	Crystalfontz America, Inc.
+csky	Hangzhou C-SKY Microsystems Co., Ltd
+csq	Shenzen Chuangsiqi Technology Co.,Ltd.
+cubietech	Cubietech, Ltd.
+cypress	Cypress Semiconductor Corporation
+cznic	CZ.NIC, z.s.p.o.
+dallas	Maxim Integrated Products (formerly Dallas Semiconductor)
+dataimage	DataImage, Inc.
+davicom	DAVICOM Semiconductor, Inc.
+decawave	Qorvo, Inc (formerly Decawave)
+dell	Dell Inc.
+delta	Delta Electronics, Inc.
+denx	Denx Software Engineering
+devantech	Devantech, Ltd.
+dfi	DFI Inc.
+dh	DH electronics GmbH
+difrnce	Shenzhen Yagu Electronic Technology Co., Ltd.
+digi	Digi International Inc.
+digilent	Diglent, Inc.
+dioo	Dioo Microcircuit Co., Ltd
+dlc	DLC Display Co., Ltd.
+dlg	Dialog Semiconductor
+dlink	D-Link Corporation
+dmo	Data Modul AG
+domintech	Domintech Co., Ltd.
+dongwoon	Dongwoon Anatech
+dptechnics	DPTechnics
+dragino	Dragino Technology Co., Limited
+dserve	dServe Technology B.V.
+dynaimage	Dyna-Image
+ea	Embedded Artists AB
+ebang	Zhejiang Ebang Communication Co., Ltd
+ebs-systart	EBS-SYSTART GmbH
+ebv	EBV Elektronik
+eckelmann	Eckelmann AG
+edt	Emerging Display Technologies
+eeti	eGalax_eMPIA Technology Inc
+einfochips	Einfochips
+elan	Elan Microelectronic Corp.
+element14	Element14 (A Premier Farnell Company)
+elgin	Elgin S/A.
+elida	Shenzhen Elida Technology Co., Ltd.
+elimo	Elimo Engineering Ltd.
+embest	Shenzhen Embest Technology Co., Ltd.
+emlid	Emlid, Ltd.
+emmicro	EM Microelectronic
+empire-electronix	Empire Electronix
+emtrion	emtrion GmbH
+endless	Endless Mobile, Inc.
+ene	ENE Technology, Inc.
+energymicro	Silicon Laboratories (formerly Energy Micro AS)
+engicam	Engicam S.r.l.
+epcos	EPCOS AG
+epfl	Ecole Polytechnique Fédérale de Lausanne
+epson	Seiko Epson Corp.
+espressif	Espressif Systems
+est	ESTeem Wireless Modems
+ettus	NI Ettus Research
+eukrea	Eukréa Electromatique
+everest	Everest Semiconductor Co. Ltd.
+everlight	Everlight Electronics Co. Ltd.
+everspin	Everspin Technologies, Inc.
+evervision	Evervision Electronics Co. Ltd.
+exar	Exar Corporation
+excito	Excito
+ezchip	EZchip Semiconductor
+facebook	Facebook
+fairphone	Fairphone B.V.
+faraday	Faraday Technology Corporation
+fastrax	Fastrax Oy
+fcs	Fairchild Semiconductor
+feixin	Shenzhen Feixin Photoelectic Co., Ltd
+feiyang	Shenzhen Fly Young Technology Co.,LTD.
+fii	Foxconn Industrial Internet
+firefly	Firefly
+focaltech	FocalTech Systems Co.,Ltd
+frida	Shenzhen Frida LCD Co., Ltd.
+friendlyarm	Guangzhou FriendlyARM Computer Tech Co., Ltd
+fsl	Freescale Semiconductor
+ftdi	Future Technology Devices International Ltd.
+fujitsu	Fujitsu Ltd.
+gaisler	Gaisler
+gardena	GARDENA GmbH
+gateworks	Gateworks Corporation
+gcw	Game Consoles Worldwide
+gd	GigaDevice Semiconductor
+ge	General Electric Company
+geekbuying	GeekBuying
+gef	GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+GEFanuc	GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+gemei	Gemei Digital Technology Co., Ltd.
+geniatech	Geniatech, Inc.
+giantec	Giantec Semiconductor, Inc.
+giantplus	Giantplus Technology Co., Ltd.
+globalscale	Globalscale Technologies, Inc.
+globaltop	GlobalTop Technology, Inc.
+gmt	Global Mixed-mode Technology, Inc.
+gooddisplay	Dalian Good Display Co., Ltd.
+goodix	Shenzhen Huiding Technology Co., Ltd.
+google	Google, Inc.
+greeled	GreeLed Electronic Ltd.
+grinn	Grinn
+grmn	Garmin Limited
+gumstix	Gumstix, Inc.
+hannstar	HannStar Display Corporation
+haoyu	Haoyu Microelectronic Co. Ltd.
+hardkernel	Hardkernel Co., Ltd
+hideep	HiDeep Inc.
+himax	Himax Technologies, Inc.
+hirschmann	Hirschmann Automation and Control GmbH
+hisilicon	Hisilicon Limited.
+hit	Hitachi Ltd.
+hitex	Hitex Development Tools
+holt	Holt Integrated Circuits, Inc.
+honestar	Honestar Technologies Co., Ltd.
+honeywell	Honeywell
+hoperf	HOPERF Microelectronics Co. Ltd
+hoperun	Jiangsu HopeRun Software Co., Ltd.
+hp	Hewlett Packard
+hsg	HannStar Display Co.
+holtek	Holtek Semiconductor, Inc.
+hugsun	Shenzhen Hugsun Technology Co. Ltd.
+hwacom	HwaCom Systems Inc.
+hycon	Hycon Technology Corp.
+hydis	Hydis Technologies
+hyundai	Hyundai Technology
+i2se	I2SE GmbH
+ibm	International Business Machines (IBM)
+icplus	IC Plus Corp.
+idt	Integrated Device Technologies, Inc.
+ifi	Ingenieurburo Fur Ic-Technologie (I/F/I)
+ilitek	ILI Technology Corporation (ILITEK)
+img	Imagination Technologies Ltd.
+imi	Integrated Micro-Electronics Inc.
+incircuit	In-Circuit GmbH
+inet-tek	Shenzhen iNet Mobile Internet Technology Co., Ltd
+infineon	Infineon Technologies
+inforce	Inforce Computing
+inventek	Inventek Systems
+ivo	InfoVision Optoelectronics Kunshan Co. Ltd.
+ingenic	Ingenic Semiconductor
+innolux	Innolux Corporation
+inside-secure	INSIDE Secure
+inspur	Inspur Corporation
+intel	Intel Corporation
+intercontrol	Inter Control Group
+invensense	InvenSense Inc.
+inversepath	Inverse Path
+iom	Iomega Corporation
+isee	ISEE 2007 S.L.
+isil	Intersil
+issi	Integrated Silicon Solutions Inc.
+ite	ITE Tech. Inc.
+itead	ITEAD Intelligent Systems Co.Ltd
+iwave	iWave Systems Technologies Pvt. Ltd.
+jdi	Japan Display Inc.
+jedec	JEDEC Solid State Technology Association
+jesurun	Shenzhen Jesurun Electronics Business Dept.
+jianda	Jiandangjing Technology Co., Ltd.
+kam	Kamstrup A/S
+karo	Ka-Ro electronics GmbH
+keithkoep	Keith & Koep GmbH
+keymile	Keymile GmbH
+khadas	Khadas
+kiebackpeter	Kieback & Peter GmbH
+kinetic	Kinetic Technologies
+kingdisplay	King & Display Technology Co., Ltd.
+kingnovel	Kingnovel Technology Co., Ltd.
+kionix	Kionix, Inc.
+kobo	Rakuten Kobo Inc.
+kobol	Kobol Innovations Pte. Ltd.
+koe	Kaohsiung Opto-Electronics Inc.
+kontron	Kontron S&T AG
+kosagi	Sutajio Ko-Usagi PTE Ltd.
+kvg	Kverneland Group
+kyo	Kyocera Corporation
+lacie	LaCie
+laird	Laird PLC
+lairdconnect	Laird Connectivity
+lamobo	Ketai Huajie Technology Co., Ltd.
+lantiq	Lantiq Semiconductor
+lattice	Lattice Semiconductor
+leadtek	Shenzhen Leadtek Technology Co., Ltd.
+leez	Leez
+lego	LEGO Systems A/S
+lemaker	Shenzhen LeMaker Technology Co., Ltd.
+lenovo	Lenovo Group Ltd.
+lg	LG Corporation
+lgphilips	LG Display
+libretech	Shenzhen Libre Technology Co., Ltd
+licheepi	Lichee Pi
+linaro	Linaro Limited
+linksprite	LinkSprite Technologies, Inc.
+linksys	Belkin International, Inc. (Linksys)
+linutronix	Linutronix GmbH
+linux	Linux-specific binding
+linx	Linx Technologies
+litex	LiteX SoC builder
+lltc	Linear Technology Corporation
+logicpd	Logic PD, Inc.
+logictechno	Logic Technologies Limited
+longcheer	Longcheer Technology (Shanghai) Co., Ltd.
+lontium	Lontium Semiconductor Corporation
+loongson	Loongson Technology Corporation Limited
+lsi	LSI Corp. (LSI Logic)
+lwn	Liebherr-Werk Nenzing GmbH
+lxa	Linux Automation GmbH
+m5stack	M5Stack
+macnica	Macnica Americas
+mantix	Mantix Display Technology Co.,Ltd.
+mapleboard	Mapleboard.org
+marvell	Marvell Technology Group Ltd.
+maxbotix	MaxBotix Inc.
+maxim	Maxim Integrated Products
+mbvl	Mobiveil Inc.
+mcube	mCube
+meas	Measurement Specialties
+mecer	Mustek Limited
+mediatek	MediaTek Inc.
+megachips	MegaChips
+mele	Shenzhen MeLE Digital Technology Ltd.
+melexis	Melexis N.V.
+melfas	MELFAS Inc.
+mellanox	Mellanox Technologies
+memsic	MEMSIC Inc.
+menlo	Menlo Systems GmbH
+mentor	Mentor Graphics
+meraki	Cisco Meraki, LLC
+merrii	Merrii Technology Co., Ltd.
+micrel	Micrel Inc.
+microbit	Micro:bit Educational Foundation
+microchip	Microchip Technology Inc.
+microcrystal	Micro Crystal AG
+micron	Micron Technology Inc.
+microsemi	Microchip Technology Inc. (formerly Microsemi Corporation)
+microsoft	Microsoft Corporation
+microsys	MicroSys Electronics GmbH
+mikroe	MikroElektronika d.o.o.
+mikrotik	MikroTik
+miniand	Miniand Tech
+minix	MINIX Technology Ltd.
+miramems	MiraMEMS Sensing Technology Co., Ltd.
+mitsubishi	Mitsubishi Electric Corporation
+modtronix	Modtronix Engineering
+mosaixtech	Mosaix Technologies, Inc.
+motorola	Motorola, Inc.
+moxa	Moxa Inc.
+mpl	MPL AG
+mps	Monolithic Power Systems Inc.
+mqmaker	mqmaker Inc.
+mrvl	Marvell Technology Group Ltd.
+mscc	Microsemi Corporation
+msi	Micro-Star International Co. Ltd.
+mstar	MStar Semiconductor, Inc. (acquired by MediaTek Inc.)
+mti	Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
+multi-inno	Multi-Inno Technology Co.,Ltd
+mundoreader	Mundo Reader S.L.
+murata	Murata Manufacturing Co., Ltd.
+mxicy	Macronix International Co., Ltd.
+myir	MYIR Tech Limited
+national	National Semiconductor
+nec	NEC LCD Technologies, Ltd.
+neonode	Neonode Inc.
+netgear	NETGEAR
+netlogic	Broadcom Corporation (formerly NetLogic Microsystems)
+netron-dy	Netron DY
+netronix	Netronix, Inc.
+netxeon	Shenzhen Netxeon Technology CO., LTD
+neweast	Guangdong Neweast Optoelectronics CO., LTD
+nexbox	Nexbox
+nextthing	Next Thing Co.
+newhaven	Newhaven Display International
+ni	National Instruments
+nintendo	Nintendo
+nlt	NLT Technologies, Ltd.
+nokia	Nokia
+nordic	Nordic Semiconductor
+novtech	NovTech, Inc.
+nutsboard	NutsBoard
+nuclei	Nuclei System Technology
+nuvoton	Nuvoton Technology Corporation
+nvd	New Vision Display
+nvidia	NVIDIA
+nxp	NXP Semiconductors
+oceanic	Oceanic Systems (UK) Ltd.
+oct	Octavo Systems LLC
+okaya	Okaya Electric America, Inc.
+oki	Oki Electric Industry Co., Ltd.
+olimex	OLIMEX Ltd.
+olpc	One Laptop Per Child
+ovti	OmniVision Technologies Co., Ltd.
+onion	Onion Corporation
+onnn	ON Semiconductor Corp.
+ontat	On Tat Industrial Company
+opalkelly	Opal Kelly Incorporated
+opencores	OpenCores.org
+openisa	open-isa.org
+openrisc	OpenRISC.io
+option	Option NV
+oranth	Shenzhen Oranth Technology Co., Ltd.
+ORCL	Oracle Corporation
+orisetech	Orise Technology
+ortustech	Ortus Technology Co., Ltd.
+osddisplays	OSD Displays
+ouya	Ouya Inc.
+overkiz	Overkiz SAS
+ovti	OmniVision Technologies
+oxsemi	Oxford Semiconductor, Ltd.
+ozzmaker	OzzMaker
+panasonic	Panasonic Corporation
+parade	Parade Technologies Inc.
+particle	Particle.io
+parallax	Parallax Inc.
+pda	Precision Design Associates, Inc.
+pericom	Pericom Technology Inc.
+pervasive	Pervasive Displays, Inc.
+phicomm	PHICOMM Co., Ltd.
+phytec	PHYTEC Messtechnik GmbH
+picochip	Picochip Ltd
+pine64	Pine64
+pineriver	Shenzhen PineRiver Designs Co., Ltd.
+pixcir	PIXCIR MICROELECTRONICS Co., Ltd
+plantower	Plantower Co., Ltd
+plathome	Plat'Home Co., Ltd.
+plda	PLDA
+plx	Broadcom Corporation (formerly PLX Technology)
+ply	Plymovent Group BV
+pni	PNI Sensor Corporation
+pocketbook	PocketBook International SA
+polaroid	Polaroid Corporation
+portwell	Portwell Inc.
+poslab	Poslab Technology Co., Ltd.
+pov	Point of View International B.V.
+powertip	Powertip Tech. Corp.
+powervr	PowerVR (deprecated, use img)
+primux	Primux Trading, S.L.
+probox2	PROBOX2 (by W2COMP Co., Ltd.)
+prt	Protonic Holland
+pulsedlight	PulsedLight, Inc
+purism	Purism, SPC
+qca	Qualcomm Atheros, Inc.
+qcom	Qualcomm Technologies, Inc
+qemu	QEMU, a generic and open source machine emulator and virtualizer
+qi	Qi Hardware
+qihua	Chengdu Kaixuan Information Technology Co., Ltd.
+qiaodian	QiaoDian XianShi Corporation
+qnap	QNAP Systems, Inc.
+quectel	Quectel Wireless Solutions Co., Ltd.
+quicklogic	QuickLogic Corp.
+radxa	Radxa
+raidsonic	RaidSonic Technology GmbH
+ralink	Mediatek/Ralink Technology Corp.
+ramtron	Ramtron International
+raspberrypi	Raspberry Pi Foundation
+raydium	Raydium Semiconductor Corp.
+rda	Unisoc Communications, Inc.
+realtek	Realtek Semiconductor Corp.
+remarkable	reMarkable AS
+renesas	Renesas Electronics Corporation
+rex	iMX6 Rex Project
+rervision	Shenzhen Rervision Technology Co., Ltd.
+revotics	Revolution Robotics, Inc. (Revotics)
+richtek	Richtek Technology Corporation
+ricoh	Ricoh Co. Ltd.
+rikomagic	Rikomagic Tech Corp. Ltd
+riscv	RISC-V Foundation
+riot	Embest RIoT
+rockchip	Fuzhou Rockchip Electronics Co., Ltd
+rocktech	ROCKTECH DISPLAYS LIMITED
+rohm	ROHM Semiconductor Co., Ltd
+ronbo	Ronbo Electronics
+roofull	Shenzhen Roofull Technology Co, Ltd
+ruuvi	Ruuvi Innovations Ltd (Oy)
+roseapplepi	RoseapplePi.org
+samsung	Samsung Semiconductor
+samtec	Samtec/Softing company
+sancloud	Sancloud Ltd
+sandisk	Sandisk Corporation
+satoz	Satoz International Co., Ltd
+sbs	Smart Battery System
+schindler	Schindler
+seagate	Seagate Technology PLC
+segger	SEGGER Microcontroller GmbH
+seeed	Seeed Technology Co., Ltd
+seirobotics	Shenzhen SEI Robotics Co., Ltd
+semtech	Semtech Corporation
+sensirion	Sensirion AG
+sensortek	Sensortek Technology Corporation
+sff	Small Form Factor Committee
+sgd	Solomon Goldentek Display Corporation
+sgmicro	SG Micro Corp
+sgx	SGX Sensortech
+sharp	Sharp Corporation
+shimafuji	Shimafuji Electric, Inc.
+shiratech	Shiratech Solutions
+si-en	Si-En Technology Ltd.
+si-linux	Silicon Linux Corporation
+sifive	SiFive, Inc.
+sigma	Sigma Designs, Inc.
+sii	Seiko Instruments, Inc.
+sil	Silicon Image
+silabs	Silicon Laboratories
+silead	Silead Inc.
+silergy	Silergy Corp.
+silex-insight	Silex Insight
+siliconfile	Siliconfile Technologies lnc.
+siliconmitus	Silicon Mitus, Inc.
+siemens	Siemens AG
+simcom	SIMCom Wireless Solutions Co., LTD
+simtek	Cypress Semiconductor Corporation (Simtek Corporation)
+sinlinx	Sinlinx Electronics Technology Co., LTD
+sinovoip	SinoVoip Co., Ltd
+sipeed	Shenzhen Sipeed Technology Co., Ltd.
+sirf	SiRF Technology, Inc.
+sis	Silicon Integrated Systems Corp.
+sitronix	Sitronix Technology Corporation
+skyworks	Skyworks Solutions, Inc.
+smartlabs	SmartLabs LLC
+smsc	Standard Microsystems Corporation
+snps	Synopsys, Inc.
+starfive	StarFive Technology Co. Ltd.
+sochip	Shenzhen SoChip Technology Co., Ltd.
+socionext	Socionext Inc.
+solidrun	SolidRun
+solomon	Solomon Systech Limited
+sony	Sony Corporation
+spansion	Spansion Inc.
+sprd	Spreadtrum Communications Inc.
+sst	Silicon Storage Technology, Inc.
+sstar	Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.)
+st	STMicroelectronics
+starry	Starry Electronic Technology (ShenZhen) Co., LTD
+startek	Startek
+ste	ST-Ericsson
+stericsson	ST-Ericsson
+st-ericsson	ST-Ericsson
+summit	Summit microelectronics
+sunchip	Shenzhen Sunchip Technology Co., Ltd
+SUNW	Sun Microsystems, Inc
+supermicro	Super Micro Computer, Inc.
+silvaco	Silvaco, Inc.
+swir	Sierra Wireless
+syna	Synaptics Inc.
+synology	Synology, Inc.
+tbs	TBS Technologies
+tbs-biometrics	Touchless Biometric Systems AG
+tcg	Trusted Computing Group
+tcl	Toby Churchill Ltd.
+tcs	Shenzhen City Tang Cheng Technology Co., Ltd.
+tdo	Shangai Top Display Optoelectronics Co., Ltd
+technexion	TechNexion
+technologic	Technologic Systems
+telink	Telink Semiconductor
+tempo	Tempo Semiconductor
+techstar	Shenzhen Techstar Electronics Co., Ltd.
+terasic	Terasic Inc.
+tfc	Three Five Corp
+thine	THine Electronics, Inc.
+thingyjp	thingy.jp
+ti	Texas Instruments
+tianma	Tianma Micro-electronics Co., Ltd.
+tlm	Trusted Logic Mobility
+tmt	Tecon Microprocessor Technologies, LLC.
+topeet	Topeet
+toppoly	TPO (deprecated, use tpo)
+topwise	Topwise Communication Co., Ltd.
+toradex	Toradex AG
+toshiba	Toshiba Corporation
+toumaz	Toumaz
+tpk	TPK U.S.A. LLC
+tplink	TP-LINK Technologies Co., Ltd.
+tpo	TPO
+tq	TQ-Systems GmbH
+tronfy	Tronfy
+tronsmart	Tronsmart
+truly	Truly Semiconductors Limited
+visionox	Visionox
+tsd	Theobroma Systems Design und Consulting GmbH
+tyan	Tyan Computer Corporation
+u-blox	u-blox
+u-boot	U-Boot bootloader
+ucrobotics	uCRobotics
+ubnt	Ubiquiti Networks
+udoo	Udoo
+ugoos	Ugoos Industrial Co., Ltd.
+uniwest	United Western Technologies Corp (UniWest)
+upisemi	uPI Semiconductor Corp.
+urt	United Radiant Technology Corporation
+usi	Universal Scientific Industrial Co., Ltd.
+utoo	Aigo Digital Technology Co., Ltd.
+v3	V3 Semiconductor
+vaisala	Vaisala
+vamrs	Vamrs Ltd.
+variscite	Variscite Ltd.
+vdl	Van der Laan b.v.
+via	VIA Technologies, Inc.
+videostrong	Videostrong Technology Co., Ltd.
+virtio	Virtual I/O Device Specification, developed by the OASIS consortium
+virtual	Used for virtual device without specific vendor.
+vishay	Vishay Intertechnology, Inc
+vitesse	Vitesse Semiconductor Corporation
+vivante	Vivante Corporation
+vnd	A stand-in for a real vendor which can be used in examples and tests
+vocore	VoCore Studio
+voipac	Voipac Technologies s.r.o.
+vot	Vision Optical Technology Co., Ltd.
+vxt	VXT Ltd
+wand	Wandbord (Technexion)
+waveshare	Waveshare Electronics
+wd	Western Digital Corp.
+we	Würth Elektronik GmbH.
+weact	WeAct Studio
+wetek	WeTek Electronics, limited.
+wexler	Wexler
+whwave	Shenzhen whwave Electronics, Inc.
+wi2wi	Wi2Wi, Inc.
+winbond	Winbond Electronics corp.
+winsen	Zhengzhou Winsen Electronics Technology Co., Ltd.
+winstar	Winstar Display Corp.
+wits	Shenzhen Merrii Technology Co., Ltd. (WITS)
+wiznet	WIZnet Co., Ltd.
+wlf	Wolfson Microelectronics
+wm	Wondermedia Technologies, Inc.
+wnc	Wistron NeWeb Corporation
+wobo	Wobo
+wolfson	Cirrus Logic, Inc. (formerly Wolfson Microelectronics plc)
+worldsemi	Worldsemi Co., Limited
+x-powers	X-Powers
+xes	Extreme Engineering Solutions (X-ES)
+xiaomi	Xiaomi Technology Co., Ltd.
+xillybus	Xillybus Ltd.
+xingbangda	Shenzhen Xingbangda Display Technology Co., Ltd
+xinpeng	Shenzhen Xinpeng Technology Co., Ltd
+xiphera	Xiphera Ltd.
+xlnx	Xilinx
+xnano	Xnano
+xunlong	Shenzhen Xunlong Software CO.,Limited
+xylon	Xylon
+yamaha	Yamaha Corporation
+yes-optoelectronics	Yes Optoelectronics Co.,Ltd.
+yic	YIC System Co., Ltd.
+ylm	Shenzhen Yangliming Electronic Technology Co., Ltd.
+yna	YSH & ATIL
+yones-toptech	Yones Toptech Co., Ltd.
+ys	Shenzhen Yashi Changhua Intelligent Technology Co., Ltd.
+ysoft	Y Soft Corporation a.s.
+zealz	Zealz
+zarlink	Zarlink Semiconductor
+zeitec	ZEITEC Semiconductor Co., LTD.
+zephyr	Zephyr-specific binding
+zidoo	Shenzhen Zidoo Technology Co., Ltd.
+zii	Zodiac Inflight Innovations
+zinitix	Zinitix Co., Ltd
+zkmagic	Shenzhen Zkmagic Technology Co., Ltd.
+zte	ZTE Corp.
+zyxel	ZyXEL Communications Corp.
diff --git a/dts/bindings/video/aptina,mt9m114.yaml b/dts/bindings/video/aptina,mt9m114.yaml
new file mode 100644
index 0000000000..21dbefb541
--- /dev/null
+++ b/dts/bindings/video/aptina,mt9m114.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: MT9M114 CMOS video sensor
+
+compatible: "aptina,mt9m114"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/video/nxp,imx-csi.yaml b/dts/bindings/video/nxp,imx-csi.yaml
new file mode 100644
index 0000000000..78e467a307
--- /dev/null
+++ b/dts/bindings/video/nxp,imx-csi.yaml
@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2019, Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: NXP MCUX CMOS sensor interface
+
+compatible: "nxp,imx-csi"
+
+include: base.yaml
+
+properties:
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    sensor-label:
+      required: true
+      type: string
+      description: label of connected sensor device
diff --git a/dts/bindings/video/ovti,ov2640.yaml b/dts/bindings/video/ovti,ov2640.yaml
new file mode 100644
index 0000000000..7cacf7c091
--- /dev/null
+++ b/dts/bindings/video/ovti,ov2640.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: OV2640 CMOS video sensor
+
+compatible: "ovti,ov2640"
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The RESETn pin is asserted to disable the sensor causing a hard
+        reset.  The sensor receives this as an active-low signal.
+
+include: i2c-device.yaml
diff --git a/dts/bindings/video/ovti,ov7725.yaml b/dts/bindings/video/ovti,ov7725.yaml
new file mode 100644
index 0000000000..491967b733
--- /dev/null
+++ b/dts/bindings/video/ovti,ov7725.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2020, FrankLi Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: OV7725 CMOS video sensor
+
+compatible: "ovti,ov7725"
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        The RESETn pin is asserted to disable the sensor causing a hard
+        reset.  The sensor receives this as an active-low signal.
+
+include: i2c-device.yaml
diff --git a/dts/bindings/virtualization/qemu,ivshmem.yaml b/dts/bindings/virtualization/qemu,ivshmem.yaml
new file mode 100644
index 0000000000..22095389a9
--- /dev/null
+++ b/dts/bindings/virtualization/qemu,ivshmem.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: ivShMem device properties
+
+compatible: "qemu,ivshmem"
+
+include: base.yaml
diff --git a/dts/bindings/watchdog/arm,cmsdk-watchdog.yaml b/dts/bindings/watchdog/arm,cmsdk-watchdog.yaml
new file mode 100644
index 0000000000..e5611fc07f
--- /dev/null
+++ b/dts/bindings/watchdog/arm,cmsdk-watchdog.yaml
@@ -0,0 +1,12 @@
+description: ARM CMSDK watchdog
+
+compatible: "arm,cmsdk-watchdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
diff --git a/dts/bindings/watchdog/atmel,sam-watchdog.yaml b/dts/bindings/watchdog/atmel,sam-watchdog.yaml
new file mode 100644
index 0000000000..0b530e9ad4
--- /dev/null
+++ b/dts/bindings/watchdog/atmel,sam-watchdog.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2018, Atmel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: ATMEL SAM0 watchdog
+
+compatible: "atmel,sam-watchdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
diff --git a/dts/bindings/watchdog/atmel,sam0-watchdog.yaml b/dts/bindings/watchdog/atmel,sam0-watchdog.yaml
new file mode 100644
index 0000000000..e5288c293c
--- /dev/null
+++ b/dts/bindings/watchdog/atmel,sam0-watchdog.yaml
@@ -0,0 +1,15 @@
+description: Atmel SAM0 watchdog
+
+compatible: "atmel,sam0-watchdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/watchdog/espressif,esp32-watchdog.yaml b/dts/bindings/watchdog/espressif,esp32-watchdog.yaml
new file mode 100644
index 0000000000..2a3c7d07cd
--- /dev/null
+++ b/dts/bindings/watchdog/espressif,esp32-watchdog.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2019, Mohamed ElShahawi
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ESP32 watchdog. ESP32 contains 3x Watchdog timers, 2x Main System Watchdog
+    Timer (MWDT), 1x RTC Watchdog Timer (RWDT). RWDT is not supported yet.
+
+compatible: "espressif,esp32-watchdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: false
diff --git a/dts/bindings/watchdog/ite,it8xxx2-watchdog.yaml b/dts/bindings/watchdog/ite,it8xxx2-watchdog.yaml
new file mode 100644
index 0000000000..0d0668ccfe
--- /dev/null
+++ b/dts/bindings/watchdog/ite,it8xxx2-watchdog.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE watchdog timer
+
+include: base.yaml
+
+compatible: "ite,it8xxx2-watchdog"
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/watchdog/microchip,xec-watchdog.yaml b/dts/bindings/watchdog/microchip,xec-watchdog.yaml
new file mode 100644
index 0000000000..c7a7c41242
--- /dev/null
+++ b/dts/bindings/watchdog/microchip,xec-watchdog.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC watchdog timer
+
+include: base.yaml
+
+compatible: "microchip,xec-watchdog"
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/watchdog/nordic,nrf-watchdog.yaml b/dts/bindings/watchdog/nordic,nrf-watchdog.yaml
new file mode 100644
index 0000000000..f4e5c0c8b9
--- /dev/null
+++ b/dts/bindings/watchdog/nordic,nrf-watchdog.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic Semiconductor nRF watchdog
+
+compatible: "nordic,nrf-watchdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml b/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml
new file mode 100644
index 0000000000..e27ec9733c
--- /dev/null
+++ b/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-TWD node
+
+compatible: "nuvoton,npcx-watchdog"
+
+include: [base.yaml]
+
+properties:
+    reg:
+        required: true
+    label:
+        required: true
+    t0-out:
+        type: phandle
+        required: true
+        description: |
+            Mapping table between Wake-Up Input (WUI) and t0-out timer expired signal.
+            For example, the WUI mapping on NPCX7 t0-out timer would be
+               t0-out = <&wui_t0out>;
diff --git a/dts/bindings/watchdog/nxp,imx-wdog.yaml b/dts/bindings/watchdog/nxp,imx-wdog.yaml
new file mode 100644
index 0000000000..c8616ab916
--- /dev/null
+++ b/dts/bindings/watchdog/nxp,imx-wdog.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: imxRT watchdog
+
+compatible: "nxp,imx-wdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/watchdog/nxp,kinetis-wdog.yaml b/dts/bindings/watchdog/nxp,kinetis-wdog.yaml
new file mode 100644
index 0000000000..eaa809ac15
--- /dev/null
+++ b/dts/bindings/watchdog/nxp,kinetis-wdog.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis watchdog
+
+compatible: "nxp,kinetis-wdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
diff --git a/dts/bindings/watchdog/nxp,kinetis-wdog32.yaml b/dts/bindings/watchdog/nxp,kinetis-wdog32.yaml
new file mode 100644
index 0000000000..cc0b1584fc
--- /dev/null
+++ b/dts/bindings/watchdog/nxp,kinetis-wdog32.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis watchdog (WDOG32)
+
+compatible: "nxp,kinetis-wdog32"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    clk-source:
+      type: int
+      required: true
+      description: Watchdog counter clock source
+
+    clk-divider:
+      type: int
+      description: Watchdog counter clock divider
+      required: true
diff --git a/dts/bindings/watchdog/nxp,lpc-wwdt.yaml b/dts/bindings/watchdog/nxp,lpc-wwdt.yaml
new file mode 100644
index 0000000000..9b4ff35349
--- /dev/null
+++ b/dts/bindings/watchdog/nxp,lpc-wwdt.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2020 Jiri Kerestes
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC Windowed Watchdog Timer
+
+compatible: "nxp,lpc-wwdt"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    clk-divider:
+      type: int
+      description: Watchdog clock divider
+      required: true
diff --git a/dts/bindings/watchdog/sifive,wdt.yaml b/dts/bindings/watchdog/sifive,wdt.yaml
new file mode 100644
index 0000000000..f5e5998159
--- /dev/null
+++ b/dts/bindings/watchdog/sifive,wdt.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 Katsuhiro Suzuki
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive FE310 Watchdog driver
+
+compatible: "sifive,wdt"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
diff --git a/dts/bindings/watchdog/silabs,gecko-wdog.yaml b/dts/bindings/watchdog/silabs,gecko-wdog.yaml
new file mode 100644
index 0000000000..5a4c9e1664
--- /dev/null
+++ b/dts/bindings/watchdog/silabs,gecko-wdog.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2019 Interay Solutions B.V.
+# Copyright (c) Oane Kingma
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silicon Labs Gecko Family Watchdog driver
+
+compatible: "silabs,gecko-wdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
diff --git a/dts/bindings/watchdog/st,stm32-watchdog.yaml b/dts/bindings/watchdog/st,stm32-watchdog.yaml
new file mode 100644
index 0000000000..9959cb42b8
--- /dev/null
+++ b/dts/bindings/watchdog/st,stm32-watchdog.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 watchdog
+
+compatible: "st,stm32-watchdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/watchdog/st,stm32-window-watchdog.yaml b/dts/bindings/watchdog/st,stm32-window-watchdog.yaml
new file mode 100644
index 0000000000..cb15520f73
--- /dev/null
+++ b/dts/bindings/watchdog/st,stm32-window-watchdog.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2019 Centaur Analytics, Inc
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 system window watchdog
+
+compatible: "st,stm32-window-watchdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    clocks:
+      required: true
diff --git a/dts/bindings/watchdog/ti,cc32xx-watchdog.yaml b/dts/bindings/watchdog/ti,cc32xx-watchdog.yaml
new file mode 100644
index 0000000000..1528a0ea1d
--- /dev/null
+++ b/dts/bindings/watchdog/ti,cc32xx-watchdog.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2021 Pavlo Hamov <pasha.gamov@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: cc32xx watchdog
+
+compatible: "ti,cc32xx-watchdog"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
diff --git a/dts/bindings/watchdog/zephyr,counter-watchdog.yaml b/dts/bindings/watchdog/zephyr,counter-watchdog.yaml
new file mode 100644
index 0000000000..1a847435b2
--- /dev/null
+++ b/dts/bindings/watchdog/zephyr,counter-watchdog.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Counter based watchdog
+
+compatible: "zephyr,counter-watchdog"
+
+include: base.yaml
+
+properties:
+    counter:
+      type: phandle
+      required: true
+      description: |
+        Counter device used for watchdog.
diff --git a/dts/bindings/wifi/atmel,winc1500.yaml b/dts/bindings/wifi/atmel,winc1500.yaml
new file mode 100644
index 0000000000..83de2fd6d4
--- /dev/null
+++ b/dts/bindings/wifi/atmel,winc1500.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel WINC1500 WiFi module
+
+compatible: "atmel,winc1500"
+
+include: spi-device.yaml
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: true
+
+    reset-gpios:
+      type: phandle-array
+      required: true
+
+    enable-gpios:
+      type: phandle-array
+      required: true
diff --git a/dts/bindings/wifi/espressif,esp-at.yaml b/dts/bindings/wifi/espressif,esp-at.yaml
new file mode 100644
index 0000000000..d43d72338b
--- /dev/null
+++ b/dts/bindings/wifi/espressif,esp-at.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2019 Tobias Svehagen
+# SPDX-License-Identifier: Apache-2.0
+
+description: Espressif ESP8266/ESP32 WiFi modem (AT Commands)
+
+compatible: "espressif,esp-at"
+
+include: uart-device.yaml
+
+properties:
+    label:
+      required: true
+
+    power-gpios:
+      type: phandle-array
+      required: false
+
+    reset-gpios:
+      type: phandle-array
+      required: false
+
+    target-speed:
+      type: int
+      required: false
+      description:
+        UART baudrate which will be requested using AT commands and to which
+        UART interface will be reconfigured during initialization phase.
diff --git a/dts/bindings/wifi/inventek,eswifi-uart.yaml b/dts/bindings/wifi/inventek,eswifi-uart.yaml
new file mode 100644
index 0000000000..6bf3308570
--- /dev/null
+++ b/dts/bindings/wifi/inventek,eswifi-uart.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Linaro Limited
+# Copyright (c) 2020, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: es-WiFi module (uart firmware interface)
+
+compatible: "inventek,eswifi-uart"
+
+include: uart-device.yaml
+
+properties:
+    resetn-gpios:
+      type: phandle-array
+      required: true
+
+    wakeup-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/bindings/wifi/inventek,eswifi.yaml b/dts/bindings/wifi/inventek,eswifi.yaml
new file mode 100644
index 0000000000..ec444c2431
--- /dev/null
+++ b/dts/bindings/wifi/inventek,eswifi.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: es-WiFi module
+
+compatible: "inventek,eswifi"
+
+include: spi-device.yaml
+
+properties:
+    resetn-gpios:
+      type: phandle-array
+      required: true
+
+    data-gpios:
+      type: phandle-array
+      required: true
+
+    wakeup-gpios:
+      type: phandle-array
+      required: false
+
+    boot0-gpios:
+      type: phandle-array
+      required: false
diff --git a/dts/common/freq.h b/dts/common/freq.h
new file mode 100644
index 0000000000..b6e83b3771
--- /dev/null
+++ b/dts/common/freq.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __DT_FREQ_H
+#define __DT_FREQ_H
+
+#define DT_FREQ_K(x) ((x) * 1000)
+#define DT_FREQ_M(x) ((x) * 1000 * 1000)
+
+#endif /* __DT_FREQ_H */
diff --git a/dts/common/mem.h b/dts/common/mem.h
new file mode 100644
index 0000000000..49c23c69f3
--- /dev/null
+++ b/dts/common/mem.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __DT_MEM_H
+#define __DT_MEM_H
+
+#define DT_SIZE_K(x) ((x) * 1024)
+#define DT_SIZE_M(x) ((x) * 1024 * 1024)
+
+/* concatenate the values of the arguments into one */
+#define _DT_DO_CONCAT(x, y) x ## y
+
+#define DT_ADDR(a) _DT_DO_CONCAT(0x, a)
+
+#endif /* __DT_MEM_H */
diff --git a/dts/common/skeleton.dtsi b/dts/common/skeleton.dtsi
new file mode 100644
index 0000000000..ef2671c9e7
--- /dev/null
+++ b/dts/common/skeleton.dtsi
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+	aliases { };
+};
diff --git a/platforms/nuttx/cmake/px4_impl_os.cmake b/platforms/nuttx/cmake/px4_impl_os.cmake
index 9627e2785e..27e55b791b 100644
--- a/platforms/nuttx/cmake/px4_impl_os.cmake
+++ b/platforms/nuttx/cmake/px4_impl_os.cmake
@@ -62,6 +62,8 @@ function(px4_os_add_flags)
 		${PX4_SOURCE_DIR}/platforms/nuttx/NuttX/nuttx/arch/${CONFIG_ARCH}/src/common
 
 		${PX4_SOURCE_DIR}/platforms/nuttx/NuttX/apps/include
+
+		${PX4_BINARY_DIR}/dts/include/generated
 	)
 
 	# prevent using the toolchain's std c++ library
diff --git a/platforms/nuttx/src/px4/stm/CMakeLists.txt b/platforms/nuttx/src/px4/stm/CMakeLists.txt
index ec489bf559..c7335420f6 100644
--- a/platforms/nuttx/src/px4/stm/CMakeLists.txt
+++ b/platforms/nuttx/src/px4/stm/CMakeLists.txt
@@ -31,6 +31,7 @@
 #
 ############################################################################
 
+px4_add_git_submodule(TARGET git_hal_stm32 PATH hal_stm32)
 
 add_subdirectory(${PX4_CHIP})
 
diff --git a/platforms/nuttx/src/px4/stm/hal_stm32 b/platforms/nuttx/src/px4/stm/hal_stm32
new file mode 160000
index 0000000000..91531028be
--- /dev/null
+++ b/platforms/nuttx/src/px4/stm/hal_stm32
@@ -0,0 +1 @@
+Subproject commit 91531028be0bfa554ae1dd9e2b5d3ed6fd7287c3
diff --git a/src/include/devicetree.h b/src/include/devicetree.h
new file mode 100644
index 0000000000..03948046a9
--- /dev/null
+++ b/src/include/devicetree.h
@@ -0,0 +1,3059 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2020 Nordic Semiconductor
+ * Copyright (c) 2020, Linaro Ltd.
+ *
+ * Not a generated file. Feel free to modify.
+ */
+
+/**
+ * @file
+ * @brief Devicetree main header
+ *
+ * API for accessing the current application's devicetree macros.
+ */
+
+#ifndef DEVICETREE_H
+#define DEVICETREE_H
+
+#include <devicetree_unfixed.h>
+//#include <devicetree_fixups.h>
+
+#include <sys/util.h>
+
+/**
+ * @brief devicetree.h API
+ * @defgroup devicetree Devicetree
+ * @{
+ * @}
+ */
+
+/*
+ * Property suffixes
+ * -----------------
+ *
+ * These are the optional parts that come after the _P_<property>
+ * part in DT_N_<path-id>_P_<property-id> macros, or the "prop-suf"
+ * nonterminal in the DT guide's macros.bnf file.
+ *
+ * Before adding new ones, check this list to avoid conflicts. If any
+ * are missing from this list, please add them. It should be complete.
+ *
+ * _ENUM_IDX: property's value as an index into bindings enum
+ * _ENUM_TOKEN: property's value as a token into bindings enum (string
+ *              enum values are identifiers) [deprecated, use _STRING_TOKEN]
+ * _ENUM_UPPER_TOKEN: like _ENUM_TOKEN, but uppercased [deprecated, use
+ *		      _STRING_UPPER_TOKEN]
+ * _EXISTS: property is defined
+ * _FOREACH_PROP_ELEM: helper for "iterating" over values in the property
+ * _FOREACH_PROP_ELEM_VARGS: foreach functions with variable number of arguments
+ * _IDX_<i>: logical index into property
+ * _IDX_<i>_EXISTS: logical index into property is defined
+ * _IDX_<i>_PH: phandle array's phandle by index (or phandle, phandles)
+ * _IDX_<i>_VAL_<val>: phandle array's specifier value by index
+ * _IDX_<i>_VAL_<val>_EXISTS: cell value exists, by index
+ * _LEN: property logical length
+ * _NAME_<name>_PH: phandle array's phandle by name
+ * _NAME_<name>_VAL_<val>: phandle array's property specifier by name
+ * _NAME_<name>_VAL_<val>_EXISTS: cell value exists, by name
+ * _STRING_TOKEN: string property's value as a token
+ * _STRING_UPPER_TOKEN: like _STRING_TOKEN, but uppercased
+ */
+
+/**
+ * @defgroup devicetree-generic-id Node identifiers and helpers
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Name for an invalid node identifier
+ *
+ * This supports cases where factored macros can be invoked from paths where
+ * devicetree data may or may not be available.  It is a preprocessor identifier
+ * that does not match any valid devicetree node identifier.
+ */
+#define DT_INVALID_NODE _
+
+/**
+ * @brief Node identifier for the root node in the devicetree
+ */
+#define DT_ROOT DT_N
+
+/**
+ * @brief Get a node identifier for a devicetree path
+ *
+ * (This macro returns a node identifier from path components. To get
+ * a path string from a node identifier, use DT_NODE_PATH() instead.)
+ *
+ * The arguments to this macro are the names of non-root nodes in the
+ * tree required to reach the desired node, starting from the root.
+ * Non-alphanumeric characters in each name must be converted to
+ * underscores to form valid C tokens, and letters must be lowercased.
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *             soc {
+ *                     serial1: serial@40001000 {
+ *                             status = "okay";
+ *                             current-speed = <115200>;
+ *                             ...
+ *                     };
+ *             };
+ *     };
+ *
+ * You can use DT_PATH(soc, serial_40001000) to get a node identifier
+ * for the serial@40001000 node. Node labels like "serial1" cannot be
+ * used as DT_PATH() arguments; use DT_NODELABEL() for those instead.
+ *
+ * Example usage with DT_PROP() to get the current-speed property:
+ *
+ *     DT_PROP(DT_PATH(soc, serial_40001000), current_speed) // 115200
+ *
+ * (The current-speed property is also in "lowercase-and-underscores"
+ * form when used with this API.)
+ *
+ * When determining arguments to DT_PATH():
+ *
+ * - the first argument corresponds to a child node of the root ("soc" above)
+ * - a second argument corresponds to a child of the first argument
+ *   ("serial_40001000" above, from the node name "serial@40001000"
+ *   after lowercasing and changing "@" to "_")
+ * - and so on for deeper nodes in the desired node's path
+ *
+ * @param ... lowercase-and-underscores node names along the node's path,
+ *            with each name given as a separate argument
+ * @return node identifier for the node with that path
+ */
+#define DT_PATH(...) DT_PATH_INTERNAL(__VA_ARGS__)
+
+/**
+ * @brief Get a node identifier for a node label
+ *
+ * Convert non-alphanumeric characters in the node label to
+ * underscores to form valid C tokens, and lowercase all letters. Note
+ * that node labels are not the same thing as label properties.
+ *
+ * Example devicetree fragment:
+ *
+ *     serial1: serial@40001000 {
+ *             label = "UART_0";
+ *             status = "okay";
+ *             current-speed = <115200>;
+ *             ...
+ *     };
+ *
+ * The only node label in this example is "serial1".
+ *
+ * The string "UART_0" is *not* a node label; it's the value of a
+ * property named label.
+ *
+ * You can use DT_NODELABEL(serial1) to get a node identifier for the
+ * serial@40001000 node. Example usage with DT_PROP() to get the
+ * current-speed property:
+ *
+ *     DT_PROP(DT_NODELABEL(serial1), current_speed) // 115200
+ *
+ * Another example devicetree fragment:
+ *
+ *     cpu@0 {
+ *            L2_0: l2-cache {
+ *                    cache-level = <2>;
+ *                    ...
+ *            };
+ *     };
+ *
+ * Example usage to get the cache-level property:
+ *
+ *     DT_PROP(DT_NODELABEL(l2_0), cache_level) // 2
+ *
+ * Notice how "L2_0" in the devicetree is lowercased to "l2_0" in the
+ * DT_NODELABEL() argument.
+ *
+ * @param label lowercase-and-underscores node label name
+ * @return node identifier for the node with that label
+ */
+#define DT_NODELABEL(label) DT_CAT(DT_N_NODELABEL_, label)
+
+/**
+ * @brief Get a node identifier from /aliases
+ *
+ * This macro's argument is a property of the /aliases node. It
+ * returns a node identifier for the node which is aliased. Convert
+ * non-alphanumeric characters in the alias property to underscores to
+ * form valid C tokens, and lowercase all letters.
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *             aliases {
+ *                     my-serial = &serial1;
+ *             };
+ *
+ *             soc {
+ *                     serial1: serial@40001000 {
+ *                             status = "okay";
+ *                             current-speed = <115200>;
+ *                             ...
+ *                     };
+ *             };
+ *     };
+ *
+ * You can use DT_ALIAS(my_serial) to get a node identifier for the
+ * serial@40001000 node. Notice how my-serial in the devicetree
+ * becomes my_serial in the DT_ALIAS() argument. Example usage with
+ * DT_PROP() to get the current-speed property:
+ *
+ *     DT_PROP(DT_ALIAS(my_serial), current_speed) // 115200
+ *
+ * @param alias lowercase-and-underscores alias name.
+ * @return node identifier for the node with that alias
+ */
+#define DT_ALIAS(alias) DT_CAT(DT_N_ALIAS_, alias)
+
+/**
+ * @brief Get a node identifier for an instance of a compatible
+ *
+ * All nodes with a particular compatible property value are assigned
+ * instance numbers, which are zero-based indexes specific to that
+ * compatible. You can get a node identifier for these nodes by
+ * passing DT_INST() an instance number, "inst", along with the
+ * lowercase-and-underscores version of the compatible, "compat".
+ *
+ * Instance numbers have the following properties:
+ *
+ * - for each compatible, instance numbers start at 0 and are contiguous
+ * - exactly one instance number is assigned for each node with a compatible,
+ *   **including disabled nodes**
+ * - enabled nodes (status property is "okay" or missing) are assigned the
+ *   instance numbers starting from 0, and disabled nodes have instance
+ *   numbers which are greater than those of any enabled node
+ *
+ * No other guarantees are made. In particular:
+ *
+ * - instance numbers **in no way reflect** any numbering scheme that
+ *   might exist in SoC documentation, node labels or unit addresses,
+ *   or properties of the /aliases node (use DT_NODELABEL() or DT_ALIAS()
+ *   for those)
+ * - there **is no general guarantee** that the same node will have
+ *   the same instance number between builds, even if you are building
+ *   the same application again in the same build directory
+ *
+ * Example devicetree fragment:
+ *
+ *     serial1: serial@40001000 {
+ *             compatible = "vnd,soc-serial";
+ *             status = "disabled";
+ *             current-speed = <9600>;
+ *             ...
+ *     };
+ *
+ *     serial2: serial@40002000 {
+ *             compatible = "vnd,soc-serial";
+ *             status = "okay";
+ *             current-speed = <57600>;
+ *             ...
+ *     };
+ *
+ *     serial3: serial@40003000 {
+ *             compatible = "vnd,soc-serial";
+ *             current-speed = <115200>;
+ *             ...
+ *     };
+ *
+ * Assuming no other nodes in the devicetree have compatible
+ * "vnd,soc-serial", that compatible has nodes with instance numbers
+ * 0, 1, and 2.
+ *
+ * The nodes serial@40002000 and serial@40003000 are both enabled, so
+ * their instance numbers are 0 and 1, but no guarantees are made
+ * regarding which node has which instance number.
+ *
+ * Since serial@40001000 is the only disabled node, it has instance
+ * number 2, since disabled nodes are assigned the largest instance
+ * numbers. Therefore:
+ *
+ *     // Could be 57600 or 115200. There is no way to be sure:
+ *     // either serial@40002000 or serial@40003000 could
+ *     // have instance number 0, so this could be the current-speed
+ *     // property of either of those nodes.
+ *     DT_PROP(DT_INST(0, vnd_soc_serial), current_speed)
+ *
+ *     // Could be 57600 or 115200, for the same reason.
+ *     // If the above expression expands to 57600, then
+ *     // this expands to 115200, and vice-versa.
+ *     DT_PROP(DT_INST(1, vnd_soc_serial), current_speed)
+ *
+ *     // 9600, because there is only one disabled node, and
+ *     // disabled nodes are "at the the end" of the instance
+ *     // number "list".
+ *     DT_PROP(DT_INST(2, vnd_soc_serial), current_speed)
+ *
+ * Notice how "vnd,soc-serial" in the devicetree becomes vnd_soc_serial
+ * (without quotes) in the DT_INST() arguments. (As usual, current-speed
+ * in the devicetree becomes current_speed as well.)
+ *
+ * Nodes whose "compatible" property has multiple values are assigned
+ * independent instance numbers for each compatible.
+ *
+ * @param inst instance number for compatible "compat"
+ * @param compat lowercase-and-underscores compatible, without quotes
+ * @return node identifier for the node with that instance number and
+ *         compatible
+ */
+#define DT_INST(inst, compat) UTIL_CAT(DT_N_INST, DT_DASH(inst, compat))
+
+/**
+ * @brief Get a node identifier for a parent node
+ *
+ * Example devicetree fragment:
+ *
+ *     parent: parent-node {
+ *             child: child-node {
+ *                     ...
+ *             };
+ *     };
+ *
+ * The following are equivalent ways to get the same node identifier:
+ *
+ *     DT_NODELABEL(parent)
+ *     DT_PARENT(DT_NODELABEL(child))
+ *
+ * @param node_id node identifier
+ * @return a node identifier for the node's parent
+ */
+#define DT_PARENT(node_id) UTIL_CAT(node_id, _PARENT)
+
+/**
+ * @brief Get a DT_DRV_COMPAT parent's node identifier
+ * @param inst instance number
+ * @return a node identifier for the instance's parent
+ */
+#define DT_INST_PARENT(inst) DT_PARENT(DT_DRV_INST(inst))
+
+/**
+ * @brief Get a node identifier for a grandparent node
+ *
+ * Example devicetree fragment:
+ *
+ *     gparent: grandparent-node {
+ *             parent: parent-node {
+ *                     child: child-node { ... }
+ *             };
+ *     };
+ *
+ * The following are equivalent ways to get the same node identifier:
+ *
+ *     DT_GPARENT(DT_NODELABEL(child))
+ *     DT_PARENT(DT_PARENT(DT_NODELABEL(child))
+ *
+ * @param node_id node identifier
+ * @return a node identifier for the node's parent's parent
+ */
+#define DT_GPARENT(node_id) DT_PARENT(DT_PARENT(node_id))
+
+/**
+ * @brief Get a node identifier for a child node
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *             soc-label: soc {
+ *                     serial1: serial@40001000 {
+ *                             status = "okay";
+ *                             current-speed = <115200>;
+ *                             ...
+ *                     };
+ *             };
+ *     };
+ *
+ * Example usage with @ref DT_PROP() to get the status of the
+ * serial@40001000 node:
+ *
+ *     #define SOC_NODE DT_NODELABEL(soc_label)
+ *     DT_PROP(DT_CHILD(SOC_NODE, serial_40001000), status) // "okay"
+ *
+ * Node labels like "serial1" cannot be used as the "child" argument
+ * to this macro. Use DT_NODELABEL() for that instead.
+ *
+ * You can also use DT_FOREACH_CHILD() to iterate over node
+ * identifiers for all of a node's children.
+ *
+ * @param node_id node identifier
+ * @param child lowercase-and-underscores child node name
+ * @return node identifier for the node with the name referred to by 'child'
+ */
+#define DT_CHILD(node_id, child) UTIL_CAT(node_id, DT_S_PREFIX(child))
+
+/**
+ * @brief Get a node identifier for a status "okay" node with a compatible
+ *
+ * Use this if you want to get an arbitrary enabled node with a given
+ * compatible, and you do not care which one you get. If any enabled
+ * nodes with the given compatible exist, a node identifier for one
+ * of them is returned. Otherwise, @p DT_INVALID_NODE is returned.
+ *
+ * Example devicetree fragment:
+ *
+ *	node-a {
+ *		compatible = "vnd,device";
+ *		status = "okay";
+ *	};
+ *
+ *	node-b {
+ *		compatible = "vnd,device";
+ *		status = "okay";
+ *	};
+ *
+ *	node-c {
+ *		compatible = "vnd,device";
+ *		status = "disabled";
+ *	};
+ *
+ * Example usage:
+ *
+ *     DT_COMPAT_GET_ANY_STATUS_OKAY(vnd_device)
+ *
+ * This expands to a node identifier for either @p node-a or @p
+ * node-b. It will not expand to a node identifier for @p node-c,
+ * because that node does not have status "okay".
+ *
+ * @param compat lowercase-and-underscores compatible, without quotes
+ * @return node identifier for a node with that compatible, or DT_INVALID_NODE
+ */
+#define DT_COMPAT_GET_ANY_STATUS_OKAY(compat)			\
+	COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(compat),	\
+		    (DT_INST(0, compat)),		\
+		    (DT_INVALID_NODE))
+
+/**
+ * @brief Get a devicetree node's full path as a string literal
+ *
+ * This returns the path to a node from a node identifier. To get a
+ * node identifier from path components instead, use DT_PATH().
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *             soc {
+ *                     node: my-node@12345678 { ... };
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *    DT_NODE_PATH(DT_NODELABEL(node)) // "/soc/my-node@12345678"
+ *    DT_NODE_PATH(DT_PATH(soc))       // "/soc"
+ *    DT_NODE_PATH(DT_ROOT)            // "/"
+ *
+ * @param node_id node identifier
+ * @return the node's full path in the devicetree
+ */
+#define DT_NODE_PATH(node_id) DT_CAT(node_id, _PATH)
+
+/**
+ * @brief Get a devicetree node's name with unit-address as a string literal
+ *
+ * This returns the node name and unit-address from a node identifier.
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *             soc {
+ *                     node: my-node@12345678 { ... };
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *    DT_NODE_FULL_NAME(DT_NODELABEL(node)) // "my-node@12345678"
+ *
+ * @param node_id node identifier
+ * @return the node's name with unit-address as a string in the devicetree
+ */
+#define DT_NODE_FULL_NAME(node_id) DT_CAT(node_id, _FULL_NAME)
+
+/**
+ * @brief Do node_id1 and node_id2 refer to the same node?
+ *
+ * Both "node_id1" and "node_id2" must be node identifiers for nodes
+ * that exist in the devicetree (if unsure, you can check with
+ * DT_NODE_EXISTS()).
+ *
+ * The expansion evaluates to 0 or 1, but may not be a literal integer
+ * 0 or 1.
+ *
+ * @param node_id1 first node identifer
+ * @param node_id2 second node identifier
+ * @return an expression that evaluates to 1 if the node identifiers
+ *         refer to the same node, and evaluates to 0 otherwise
+ */
+#define DT_SAME_NODE(node_id1, node_id2) \
+	(DT_DEP_ORD(node_id1) == (DT_DEP_ORD(node_id2)))
+
+/* Implementation note: distinct nodes have distinct node identifiers.
+ * See include/devicetree/ordinals.h. */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-generic-prop Property accessors
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get a devicetree property value
+ *
+ * For properties whose bindings have the following types, this macro
+ * expands to:
+ *
+ * - string: a string literal
+ * - boolean: 0 if the property is false, or 1 if it is true
+ * - int: the property's value as an integer literal
+ * - array, uint8-array, string-array: an initializer expression in braces,
+ *   whose elements are integer or string literals (like {0, 1, 2},
+ *   {"hello", "world"}, etc.)
+ * - phandle: a node identifier for the node with that phandle
+ *
+ * A property's type is usually defined by its binding. In some
+ * special cases, it has an assumed type defined by the devicetree
+ * specification even when no binding is available: "compatible" has
+ * type string-array, "status" and "label" have type string, and
+ * "interrupt-controller" has type boolean.
+ *
+ * For other properties or properties with unknown type due to a
+ * missing binding, behavior is undefined.
+ *
+ * For usage examples, see @ref DT_PATH(), @ref DT_ALIAS(), @ref
+ * DT_NODELABEL(), and @ref DT_INST() above.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ * @return a representation of the property's value
+ */
+#define DT_PROP(node_id, prop) DT_CAT(node_id, _P_##prop)
+
+/**
+ * @brief Get a property's logical length
+ *
+ * Here, "length" is a number of elements, which may differ from the
+ * property's size in bytes.
+ *
+ * The return value depends on the property's type:
+ *
+ * - for types array, string-array, and uint8-array, this expands
+ *   to the number of elements in the array
+ * - for type phandles, this expands to the number of phandles
+ * - for type phandle-array, this expands to the number of
+ *   phandle and specifier blocks in the property
+ *
+ * These properties are handled as special cases:
+ *
+ * - reg property: use DT_NUM_REGS(node_id) instead
+ * - interrupts property: use DT_NUM_IRQS(node_id) instead
+ *
+ * It is an error to use this macro with the ranges, dma-ranges, reg
+ * or interrupts properties.
+ *
+ * For other properties, behavior is undefined.
+ *
+ * @param node_id node identifier
+ * @param prop a lowercase-and-underscores property with a logical length
+ * @return the property's length
+ */
+#define DT_PROP_LEN(node_id, prop) DT_PROP(node_id, prop##_LEN)
+
+/**
+ * @brief Like DT_PROP_LEN(), but with a fallback to default_value
+ *
+ * If the property is defined (as determined by DT_NODE_HAS_PROP()),
+ * this expands to DT_PROP_LEN(node_id, prop). The default_value
+ * parameter is not expanded in this case.
+ *
+ * Otherwise, this expands to default_value.
+ *
+ * @param node_id node identifier
+ * @param prop a lowercase-and-underscores property with a logical length
+ * @param default_value a fallback value to expand to
+ * @return the property's length or the given default value
+ */
+#define DT_PROP_LEN_OR(node_id, prop, default_value) \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \
+		    (DT_PROP_LEN(node_id, prop)), (default_value))
+
+/**
+ * @brief Is index "idx" valid for an array type property?
+ *
+ * If this returns 1, then DT_PROP_BY_IDX(node_id, prop, idx) or
+ * DT_PHA_BY_IDX(node_id, prop, idx, ...) are valid at index "idx".
+ * If it returns 0, it is an error to use those macros with that index.
+ *
+ * These properties are handled as special cases:
+ *
+ * - reg property: use DT_REG_HAS_IDX(node_id, idx) instead
+ * - interrupts property: use DT_IRQ_HAS_IDX(node_id, idx) instead
+ *
+ * It is an error to use this macro with the reg or interrupts properties.
+ *
+ * @param node_id node identifier
+ * @param prop a lowercase-and-underscores property with a logical length
+ * @param idx index to check
+ * @return An expression which evaluates to 1 if "idx" is a valid index
+ *         into the given property, and 0 otherwise.
+ */
+#define DT_PROP_HAS_IDX(node_id, prop, idx) \
+	IS_ENABLED(DT_CAT6(node_id, _P_, prop, _IDX_, idx, _EXISTS))
+
+/**
+ * @brief Get the value at index "idx" in an array type property
+ *
+ * It might help to read the argument order as being similar to
+ * "node->property[index]".
+ *
+ * When the property's binding has type array, string-array,
+ * uint8-array, or phandles, this expands to the idx-th array element
+ * as an integer, string literal, or node identifier respectively.
+ *
+ * These properties are handled as special cases:
+ *
+ * - reg property: use DT_REG_ADDR_BY_IDX() or DT_REG_SIZE_BY_IDX() instead
+ * - interrupts property: use DT_IRQ_BY_IDX() instead
+ *
+ * For non-array properties, behavior is undefined.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ * @param idx the index to get
+ * @return a representation of the idx-th element of the property
+ */
+#define DT_PROP_BY_IDX(node_id, prop, idx) DT_PROP(node_id, prop##_IDX_##idx)
+
+/**
+ * @brief Like DT_PROP(), but with a fallback to default_value
+ *
+ * If the value exists, this expands to DT_PROP(node_id, prop).
+ * The default_value parameter is not expanded in this case.
+ *
+ * Otherwise, this expands to default_value.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ * @param default_value a fallback value to expand to
+ * @return the property's value or default_value
+ */
+#define DT_PROP_OR(node_id, prop, default_value) \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \
+		    (DT_PROP(node_id, prop)), (default_value))
+
+/**
+ * @brief Equivalent to DT_PROP(node_id, label)
+ *
+ * This is a convenience for the Zephyr device API, which uses label
+ * properties as device_get_binding() arguments.
+ * @param node_id node identifier
+ * @return node's label property value
+ */
+#define DT_LABEL(node_id) DT_PROP(node_id, label)
+
+/**
+ * @brief Get a property value's index into its enumeration values
+ *
+ * The return values start at zero.
+ *
+ * Example devicetree fragment:
+ *
+ *     usb1: usb@12340000 {
+ *             maximum-speed = "full-speed";
+ *     };
+ *     usb2: usb@12341000 {
+ *             maximum-speed = "super-speed";
+ *     };
+ *
+ * Example bindings fragment:
+ *
+ *     properties:
+ *       maximum-speed:
+ *         type: string
+ *         enum:
+ *            - "low-speed"
+ *            - "full-speed"
+ *            - "high-speed"
+ *            - "super-speed"
+ *
+ * Example usage:
+ *
+ *     DT_ENUM_IDX(DT_NODELABEL(usb1), maximum_speed) // 1
+ *     DT_ENUM_IDX(DT_NODELABEL(usb2), maximum_speed) // 3
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ * @return zero-based index of the property's value in its enum: list
+ */
+#define DT_ENUM_IDX(node_id, prop) DT_PROP(node_id, prop##_ENUM_IDX)
+
+/**
+ * @brief Like DT_ENUM_IDX(), but with a fallback to a default enum index
+ *
+ * If the value exists, this expands to its zero based index value thanks to
+ * DT_ENUM_IDX(node_id, prop).
+ *
+ * Otherwise, this expands to provided default index enum value.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ * @param default_idx_value a fallback index value to expand to
+ * @return zero-based index of the property's value in its enum if present,
+ *         default_idx_value ohterwise
+ */
+#define DT_ENUM_IDX_OR(node_id, prop, default_idx_value) \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \
+		    (DT_ENUM_IDX(node_id, prop)), (default_idx_value))
+
+/**
+ * @brief Get a string property's value as a token.
+ *
+ * This removes "the quotes" from string-valued properties, and converts
+ * non-alphanumeric characters to underscores. That can be useful, for example,
+ * when programmatically using the value to form a C variable or code.
+ *
+ * DT_STRING_TOKEN() can only be used for properties with string type.
+ *
+ * It is an error to use DT_STRING_TOKEN() in other circumstances.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             prop = "foo";
+ *     };
+ *     n2: node-2 {
+ *             prop = "FOO";
+ *     }
+ *     n3: node-3 {
+ *             prop = "123 foo";
+ *     };
+ *
+ * Example bindings fragment:
+ *
+ *     properties:
+ *       prop:
+ *         type: string
+ *
+ * Example usage:
+ *
+ *     DT_STRING_TOKEN(DT_NODELABEL(n1), prop) // foo
+ *     DT_STRING_TOKEN(DT_NODELABEL(n2), prop) // FOO
+ *     DT_STRING_TOKEN(DT_NODELABEL(n3), prop) // 123_foo
+ *
+ * Notice how:
+ *
+ * - Unlike C identifiers, the property values may begin with a
+ *   number. It's the user's responsibility not to use such values as
+ *   the name of a C identifier.
+ *
+ * - The uppercased "FOO" in the DTS remains @p FOO as a token. It is
+ *   *not* converted to @p foo.
+ *
+ * - The whitespace in the DTS "123 foo" string is converted to @p
+ *   123_foo as a token.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property string name
+ * @return the value of @p prop as a token, i.e. without any quotes
+ *         and with special characters converted to underscores
+ */
+#define DT_STRING_TOKEN(node_id, prop) \
+	DT_CAT4(node_id, _P_, prop, _STRING_TOKEN)
+
+/**
+ * @brief Like DT_STRING_TOKEN(), but uppercased.
+ *
+ * This removes "the quotes and capitalize" from string-valued properties, and
+ * converts non-alphanumeric characters to underscores. That can be useful, for
+ * example, when programmatically using the value to form a C variable or code.
+ *
+ * DT_STRING_UPPER_TOKEN() can only be used for properties with string type.
+ *
+ * It is an error to use DT_STRING_UPPER_TOKEN() in other circumstances.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             prop = "foo";
+ *     };
+ *     n2: node-2 {
+ *             prop = "123 foo";
+ *     };
+ *
+ * Example bindings fragment:
+ *
+ *     properties:
+ *       prop:
+ *         type: string
+ *
+ * Example usage:
+ *
+ *     DT_STRING_UPPER_TOKEN(DT_NODELABEL(n1), prop) // FOO
+ *     DT_STRING_UPPER_TOKEN(DT_NODELABEL(n2), prop) // 123_FOO
+ *
+ * Notice how:
+ *
+ * - Unlike C identifiers, the property values may begin with a
+ *   number. It's the user's responsibility not to use such values as
+ *   the name of a C identifier.
+ *
+ * - The lowercased "foo" in the DTS becomes @p FOO as a token, i.e.
+ *   it is uppercased.
+ *
+ * - The whitespace in the DTS "123 foo" string is converted to @p
+ *   123_FOO as a token, i.e. it is uppercased and whitespace becomes
+ *   an underscore.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property string name
+ * @return the value of @p prop as a token, i.e. without any quotes
+ *         and with special characters converted to underscores
+ */
+#define DT_STRING_UPPER_TOKEN(node_id, prop) \
+	DT_CAT4(node_id, _P_, prop, _STRING_UPPER_TOKEN)
+
+/**
+ * @brief Get an enumeration property's value as a token.
+ *
+ * This allows you to "remove the quotes" from some string-valued
+ * properties. That can be useful, for example, when pasting the
+ * values onto some other token to form an enum in C using the @p ##
+ * preprocessor operator.
+ *
+ * DT_ENUM_TOKEN() can only be used for properties with string type
+ * whose binding has an "enum:". The values in the binding's "enum:"
+ * list must be unique after converting non-alphanumeric characters to
+ * underscores.
+ *
+ * It is an error to use DT_ENUM_TOKEN() in other circumstances.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             prop = "foo";
+ *     };
+ *     n2: node-2 {
+ *             prop = "FOO";
+ *     }
+ *     n3: node-3 {
+ *             prop = "123 foo";
+ *     };
+ *
+ * Example bindings fragment:
+ *
+ *     properties:
+ *       prop:
+ *         type: string
+ *         enum:
+ *            - "foo"
+ *            - "FOO"
+ *            - "123 foo"
+ *
+ * Example usage:
+ *
+ *     DT_ENUM_TOKEN(DT_NODELABEL(n1), prop) // foo
+ *     DT_ENUM_TOKEN(DT_NODELABEL(n2), prop) // FOO
+ *     DT_ENUM_TOKEN(DT_NODELABEL(n3), prop) // 123_foo
+ *
+ * Notice how:
+ *
+ * - Unlike C identifiers, the property values may begin with a
+ *   number. It's the user's responsibility not to use such values as
+ *   the name of a C identifier.
+ *
+ * - The uppercased "FOO" in the DTS remains @p FOO as a token. It is
+     *not* converted to @p foo.
+ *
+ * - The whitespace in the DTS "123 foo" string is converted to @p
+ *   123_foo as a token.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name with suitable
+ *             enumeration of values in its binding
+ * @return the value of @p prop as a token, i.e. without any quotes
+ *         and with special characters converted to underscores
+ */
+#define DT_ENUM_TOKEN(node_id, prop) \
+	__DEPRECATED_MACRO \
+	DT_CAT4(node_id, _P_, prop, _ENUM_TOKEN)
+
+/**
+ * @brief Like DT_ENUM_TOKEN(), but uppercased
+ *
+ * This allows you to "remove the quotes and capitalize" some string-valued
+ * properties.
+ *
+ * DT_ENUM_UPPER_TOKEN() can only be used for properties with string type
+ * whose binding has an "enum:". The values in the binding's "enum:"
+ * list must be unique after converting non-alphanumeric characters to
+ * underscores and capitalizating any letters.
+ *
+ * It is an error to use DT_ENUM_UPPER_TOKEN() in other circumstances.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             prop = "foo";
+ *     };
+ *     n2: node-2 {
+ *             prop = "123 foo";
+ *     };
+ *
+ * Example bindings fragment:
+ *
+ *     properties:
+ *       prop:
+ *         type: string
+ *         enum:
+ *            - "foo"
+ *            - "123 foo"
+ *
+ * Example usage:
+ *
+ *     DT_ENUM_TOKEN((DT_NODELABEL(n1), prop) // FOO
+ *     DT_ENUM_TOKEN((DT_NODELABEL(n2), prop) // 123_FOO
+ *
+ * Notice how:
+ *
+ * - Unlike C identifiers, the property values may begin with a
+ *   number. It's the user's responsibility not to use such values as
+ *   the name of a C identifier.
+ *
+ * - The lowercased "foo" in the DTS becomes @p FOO as a token, i.e.
+ *   it is uppercased.
+ *
+ * - The whitespace in the DTS "123 foo" string is converted to @p
+ *   123_FOO as a token, i.e. it is uppercased and whitespace becomes
+ *   an underscore.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name with suitable
+ *             enumeration of values in its binding
+ * @return the value of @p prop as a capitalized token, i.e. upper case,
+ *         without any quotes, and with special characters converted to
+ *         underscores
+ */
+#define DT_ENUM_UPPER_TOKEN(node_id, prop) \
+	__DEPRECATED_MACRO \
+	DT_CAT4(node_id, _P_, prop, _ENUM_UPPER_TOKEN)
+
+/*
+ * phandle properties
+ *
+ * These are special-cased to manage the impedance mismatch between
+ * phandles, which are just uint32_t node properties that only make sense
+ * within the tree itself, and C values.
+ */
+
+/**
+ * @brief Get a property value from a phandle in a property.
+ *
+ * This is a shorthand for:
+ *
+ *     DT_PROP(DT_PHANDLE_BY_IDX(node_id, phs, idx), prop)
+ *
+ * That is, "prop" is a property of the phandle's node, not a
+ * property of "node_id".
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             foo = <&n2 &n3>;
+ *     };
+ *
+ *     n2: node-2 {
+ *             bar = <42>;
+ *     };
+ *
+ *     n3: node-3 {
+ *             baz = <43>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     #define N1 DT_NODELABEL(n1)
+ *
+ *     DT_PROP_BY_PHANDLE_IDX(N1, foo, 0, bar) // 42
+ *     DT_PROP_BY_PHANDLE_IDX(N1, foo, 1, baz) // 43
+ *
+ * @param node_id node identifier
+ * @param phs lowercase-and-underscores property with type "phandle",
+ *            "phandles", or "phandle-array"
+ * @param idx logical index into "phs", which must be zero if "phs"
+ *            has type "phandle"
+ * @param prop lowercase-and-underscores property of the phandle's node
+ * @return the property's value
+ */
+#define DT_PROP_BY_PHANDLE_IDX(node_id, phs, idx, prop) \
+	DT_PROP(DT_PHANDLE_BY_IDX(node_id, phs, idx), prop)
+
+/**
+ * @brief Like DT_PROP_BY_PHANDLE_IDX(), but with a fallback to
+ * default_value.
+ *
+ * If the value exists, this expands to DT_PROP_BY_PHANDLE_IDX(node_id, phs,
+ * idx, prop). The default_value parameter is not expanded in this
+ * case.
+ *
+ * Otherwise, this expands to default_value.
+ *
+ * @param node_id node identifier
+ * @param phs lowercase-and-underscores property with type "phandle",
+ *            "phandles", or "phandle-array"
+ * @param idx logical index into "phs", which must be zero if "phs"
+ *            has type "phandle"
+ * @param prop lowercase-and-underscores property of the phandle's node
+ * @param default_value a fallback value to expand to
+ * @return the property's value
+ */
+#define DT_PROP_BY_PHANDLE_IDX_OR(node_id, phs, idx, prop, default_value) \
+	DT_PROP_OR(DT_PHANDLE_BY_IDX(node_id, phs, idx), prop, default_value)
+
+/**
+ * @brief Get a property value from a phandle's node
+ *
+ * This is equivalent to DT_PROP_BY_PHANDLE_IDX(node_id, ph, 0, prop).
+ *
+ * @param node_id node identifier
+ * @param ph lowercase-and-underscores property of "node_id"
+ *           with type "phandle"
+ * @param prop lowercase-and-underscores property of the phandle's node
+ * @return the property's value
+ */
+#define DT_PROP_BY_PHANDLE(node_id, ph, prop) \
+	DT_PROP_BY_PHANDLE_IDX(node_id, ph, 0, prop)
+
+/**
+ * @brief Get a phandle-array specifier cell value at an index
+ *
+ * It might help to read the argument order as being similar to
+ * "node->phandle_array[index].cell". That is, the cell value is in
+ * the "pha" property of "node_id", inside the specifier at index
+ * "idx".
+ *
+ * Example devicetree fragment:
+ *
+ *     gpio0: gpio@... {
+ *             #gpio-cells = <2>;
+ *     };
+ *
+ *     gpio1: gpio@... {
+ *             #gpio-cells = <2>;
+ *     };
+ *
+ *     led: led_0 {
+ *             gpios = <&gpio0 17 0x1>, <&gpio1 5 0x3>;
+ *     };
+ *
+ * Bindings fragment for the gpio0 and gpio1 nodes:
+ *
+ *     gpio-cells:
+ *       - pin
+ *       - flags
+ *
+ * Above, "gpios" has two elements:
+ *
+ * - index 0 has specifier <17 0x1>, so its "pin" cell is 17, and its
+ *   "flags" cell is 0x1
+ * - index 1 has specifier <5 0x3>, so "pin" is 5 and "flags" is 0x3
+ *
+ * Example usage:
+ *
+ *     #define LED DT_NODELABEL(led)
+ *
+ *     DT_PHA_BY_IDX(LED, gpios, 0, pin)   // 17
+ *     DT_PHA_BY_IDX(LED, gpios, 1, flags) // 0x3
+ *
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param idx logical index into "pha"
+ * @param cell lowercase-and-underscores cell name within the specifier
+ *             at "pha" index "idx"
+ * @return the cell's value
+ */
+#define DT_PHA_BY_IDX(node_id, pha, idx, cell) \
+	DT_PROP(node_id, pha##_IDX_##idx##_VAL_##cell)
+
+/**
+ * @brief Like DT_PHA_BY_IDX(), but with a fallback to default_value.
+ *
+ * If the value exists, this expands to DT_PHA_BY_IDX(node_id, pha,
+ * idx, cell). The default_value parameter is not expanded in this
+ * case.
+ *
+ * Otherwise, this expands to default_value.
+ *
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param idx logical index into "pha"
+ * @param cell lowercase-and-underscores cell name within the specifier
+ *             at "pha" index "idx"
+ * @param default_value a fallback value to expand to
+ * @return the cell's value or "default_value"
+ */
+#define DT_PHA_BY_IDX_OR(node_id, pha, idx, cell, default_value) \
+	DT_PROP_OR(node_id, pha##_IDX_##idx##_VAL_##cell, default_value)
+/* Implementation note: the _IDX_##idx##_VAL_##cell##_EXISTS
+ * macros are defined, so it's safe to use DT_PROP_OR() here, because
+ * that uses an IS_ENABLED() on the _EXISTS macro.
+ */
+
+/**
+ * @brief Equivalent to DT_PHA_BY_IDX(node_id, pha, 0, cell)
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell's value
+ */
+#define DT_PHA(node_id, pha, cell) DT_PHA_BY_IDX(node_id, pha, 0, cell)
+
+/**
+ * @brief Like DT_PHA(), but with a fallback to default_value
+ *
+ * If the value exists, this expands to DT_PHA(node_id, pha, cell).
+ * The default_value parameter is not expanded in this case.
+ *
+ * Otherwise, this expands to default_value.
+ *
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param cell lowercase-and-underscores cell name
+ * @param default_value a fallback value to expand to
+ * @return the cell's value or default_value
+ */
+#define DT_PHA_OR(node_id, pha, cell, default_value) \
+	DT_PHA_BY_IDX_OR(node_id, pha, 0, cell, default_value)
+
+/**
+ * @brief Get a value within a phandle-array specifier by name
+ *
+ * This is like DT_PHA_BY_IDX(), except it treats "pha" as a structure
+ * where each array element has a name.
+ *
+ * It might help to read the argument order as being similar to
+ * "node->phandle_struct.name.cell". That is, the cell value is in the
+ * "pha" property of "node_id", treated as a data structure where
+ * each array element has a name.
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             io-channels = <&adc1 10>, <&adc2 20>;
+ *             io-channel-names = "SENSOR", "BANDGAP";
+ *     };
+ *
+ * Bindings fragment for the "adc1" and "adc2" nodes:
+ *
+ *     io-channel-cells:
+ *       - input
+ *
+ * Example usage:
+ *
+ *     DT_PHA_BY_NAME(DT_NODELABEL(n), io_channels, sensor, input)  // 10
+ *     DT_PHA_BY_NAME(DT_NODELABEL(n), io_channels, bandgap, input) // 20
+ *
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param name lowercase-and-underscores name of a specifier in "pha"
+ * @param cell lowercase-and-underscores cell name in the named specifier
+ * @return the cell's value
+ */
+#define DT_PHA_BY_NAME(node_id, pha, name, cell) \
+	DT_PROP(node_id, pha##_NAME_##name##_VAL_##cell)
+
+/**
+ * @brief Like DT_PHA_BY_NAME(), but with a fallback to default_value
+ *
+ * If the value exists, this expands to DT_PHA_BY_NAME(node_id, pha,
+ * name, cell). The default_value parameter is not expanded in this case.
+ *
+ * Otherwise, this expands to default_value.
+ *
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param name lowercase-and-underscores name of a specifier in "pha"
+ * @param cell lowercase-and-underscores cell name in the named specifier
+ * @param default_value a fallback value to expand to
+ * @return the cell's value or default_value
+ */
+#define DT_PHA_BY_NAME_OR(node_id, pha, name, cell, default_value) \
+	DT_PROP_OR(node_id, pha##_NAME_##name##_VAL_##cell, default_value)
+/* Implementation note: the _NAME_##name##_VAL_##cell##_EXISTS
+ * macros are defined, so it's safe to use DT_PROP_OR() here, because
+ * that uses an IS_ENABLED() on the _EXISTS macro.
+ */
+
+/**
+ * @brief Get a phandle's node identifier from a phandle array by name
+ *
+ * It might help to read the argument order as being similar to
+ * "node->phandle_struct.name.phandle". That is, the phandle array is
+ * treated as a structure with named elements. The return value is
+ * the node identifier for a phandle inside the structure.
+ *
+ * Example devicetree fragment:
+ *
+ *     adc1: adc@... {
+ *             label = "ADC_1";
+ *     };
+ *
+ *     adc2: adc@... {
+ *             label = "ADC_2";
+ *     };
+ *
+ *     n: node {
+ *             io-channels = <&adc1 10>, <&adc2 20>;
+ *             io-channel-names = "SENSOR", "BANDGAP";
+ *     };
+ *
+ * Above, "io-channels" has two elements:
+ *
+ * - the element named "SENSOR" has phandle &adc1
+ * - the element named "BANDGAP" has phandle &adc2
+ *
+ * Example usage:
+ *
+ *     #define NODE DT_NODELABEL(n)
+ *
+ *     DT_LABEL(DT_PHANDLE_BY_NAME(NODE, io_channels, sensor))  // "ADC_1"
+ *     DT_LABEL(DT_PHANDLE_BY_NAME(NODE, io_channels, bandgap)) // "ADC_2"
+ *
+ * Notice how devicetree properties and names are lowercased, and
+ * non-alphanumeric characters are converted to underscores.
+ *
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param name lowercase-and-underscores name of an element in "pha"
+ * @return a node identifier for the node with that phandle
+ */
+#define DT_PHANDLE_BY_NAME(node_id, pha, name) \
+	DT_PROP(node_id, pha##_NAME_##name##_PH)
+
+/**
+ * @brief Get a node identifier for a phandle in a property.
+ *
+ * When a node's value at a logical index contains a phandle, this
+ * macro returns a node identifier for the node with that phandle.
+ *
+ * Therefore, if "prop" has type "phandle", "idx" must be zero. (A
+ * "phandle" type is treated as a "phandles" with a fixed length of
+ * 1).
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             foo = <&n2 &n3>;
+ *     };
+ *
+ *     n2: node-2 { ... };
+ *     n3: node-3 { ... };
+ *
+ * Above, "foo" has type phandles and has two elements:
+ *
+ * - index 0 has phandle &n2, which is node-2's phandle
+ * - index 1 has phandle &n3, which is node-3's phandle
+ *
+ * Example usage:
+ *
+ *     #define N1 DT_NODELABEL(n1)
+ *
+ *     DT_PHANDLE_BY_IDX(N1, foo, 0) // node identifier for node-2
+ *     DT_PHANDLE_BY_IDX(N1, foo, 1) // node identifier for node-3
+ *
+ * Behavior is analogous for phandle-arrays.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name in "node_id"
+ *             with type "phandle", "phandles" or "phandle-array"
+ * @param idx index into "prop"
+ * @return node identifier for the node with the phandle at that index
+ */
+#define DT_PHANDLE_BY_IDX(node_id, prop, idx) \
+	DT_CAT6(node_id, _P_, prop, _IDX_, idx, _PH)
+/*
+ * Implementation note: using DT_CAT6 above defers concatenation until
+ * after expansion of each parameter. This is important when 'idx' is
+ * expandable to a number, but it isn't one "yet".
+ */
+
+/**
+ * @brief Get a node identifier for a phandle property's value
+ *
+ * This is equivalent to DT_PHANDLE_BY_IDX(node_id, prop, 0). Its primary
+ * benefit is readability when "prop" has type "phandle".
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property of "node_id"
+ *             with type "phandle"
+ * @return a node identifier for the node pointed to by "ph"
+ */
+#define DT_PHANDLE(node_id, prop) DT_PHANDLE_BY_IDX(node_id, prop, 0)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-ranges-prop ranges property
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get the number of range blocks in the ranges property
+ *
+ * Use this instead of DT_PROP_LEN(node_id, ranges).
+ *
+ * Example devicetree fragment:
+ *
+ *     pcie0: pcie@0 {
+ *             compatible = "intel,pcie";
+ *             reg = <0 1>;
+ *             #address-cells = <3>;
+ *             #size-cells = <2>;
+ *
+ *             ranges = <0x1000000 0 0 0 0x3eff0000 0 0x10000>,
+ *                      <0x2000000 0 0x10000000 0 0x10000000 0 0x2eff0000>,
+ *                      <0x3000000 0x80 0 0x80 0 0x80 0>;
+ *     };
+ *
+ *     other: other@1 {
+ *             reg = <1 1>;
+ *
+ *             ranges = <0x0 0x0 0x0 0x3eff0000 0x10000>,
+ *                      <0x0 0x10000000 0x0 0x10000000 0x2eff0000>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_NUM_RANGES(DT_NODELABEL(pcie0)) // 3
+ *     DT_NUM_RANGES(DT_NODELABEL(other)) // 2
+ *
+ * @param node_id node identifier
+ */
+#define DT_NUM_RANGES(node_id) DT_CAT(node_id, _RANGES_NUM)
+
+/**
+ * @brief Is "idx" a valid range block index?
+ *
+ * If this returns 1, then DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(node_id, idx),
+ * DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(node_id, idx) or
+ * DT_RANGES_LENGTH_BY_IDX(node_id, idx) are valid.
+ * For DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx) the return value
+ * of DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(node_id, idx) will indicate
+ * validity.
+ * If it returns 0, it is an error to use those macros with index "idx",
+ * including DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx).
+ *
+ * Example devicetree fragment:
+ *
+ *
+ *     pcie0: pcie@0 {
+ *             compatible = "intel,pcie";
+ *             reg = <0 1>;
+ *             #address-cells = <3>;
+ *             #size-cells = <2>;
+ *
+ *             ranges = <0x1000000 0 0 0 0x3eff0000 0 0x10000>,
+ *                      <0x2000000 0 0x10000000 0 0x10000000 0 0x2eff0000>,
+ *                      <0x3000000 0x80 0 0x80 0 0x80 0>;
+ *     };
+ *
+ *     other: other@1 {
+ *             reg = <1 1>;
+ *
+ *             ranges = <0x0 0x0 0x0 0x3eff0000 0x10000>,
+ *                      <0x0 0x10000000 0x0 0x10000000 0x2eff0000>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_RANGES_HAS_IDX(DT_NODELABEL(pcie0), 0) // 1
+ *     DT_RANGES_HAS_IDX(DT_NODELABEL(pcie0), 1) // 1
+ *     DT_RANGES_HAS_IDX(DT_NODELABEL(pcie0), 2) // 1
+ *     DT_RANGES_HAS_IDX(DT_NODELABEL(pcie0), 3) // 0
+ *     DT_RANGES_HAS_IDX(DT_NODELABEL(other), 0) // 1
+ *     DT_RANGES_HAS_IDX(DT_NODELABEL(other), 1) // 1
+ *     DT_RANGES_HAS_IDX(DT_NODELABEL(other), 2) // 0
+ *     DT_RANGES_HAS_IDX(DT_NODELABEL(other), 3) // 0
+ *
+ * @param node_id node identifier
+ * @param idx index to check
+ * @return 1 if "idx" is a valid register block index,
+ *         0 otherwise.
+ */
+#define DT_RANGES_HAS_IDX(node_id, idx) \
+	IS_ENABLED(DT_CAT4(node_id, _RANGES_IDX_, idx, _EXISTS))
+
+/**
+ * @brief Does a ranges property have child bus flags at index?
+ *
+ * If this returns 1, then DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx) is valid.
+ * If it returns 0, it is an error to use this macro with index "idx".
+ * This macro only returns 1 for PCIe buses (i.e. nodes whose bindings specify they
+ * are "pcie" bus nodes.)
+ *
+ * Example devicetree fragment:
+ *
+ *     parent {
+ *             #address-cells = <2>;
+ *
+ *             pcie0: pcie@0 {
+ *                     compatible = "intel,pcie";
+ *                     reg = <0 0 1>;
+ *                     #address-cells = <3>;
+ *                     #size-cells = <2>;
+ *
+ *                     ranges = <0x1000000 0 0 0 0x3eff0000 0 0x10000>,
+ *                              <0x2000000 0 0x10000000 0 0x10000000 0 0x2eff0000>,
+ *                              <0x3000000 0x80 0 0x80 0 0x80 0>;
+ *             };
+ *
+ *             other: other@1 {
+ *                     reg = <0 1 1>;
+ *
+ *                     ranges = <0x0 0x0 0x0 0x3eff0000 0x10000>,
+ *                              <0x0 0x10000000 0x0 0x10000000 0x2eff0000>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(DT_NODELABEL(pcie0), 0) // 1
+ *     DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(DT_NODELABEL(pcie0), 1) // 1
+ *     DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(DT_NODELABEL(pcie0), 2) // 1
+ *     DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(DT_NODELABEL(pcie0), 3) // 0
+ *     DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(DT_NODELABEL(other), 0) // 0
+ *     DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(DT_NODELABEL(other), 1) // 0
+ *     DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(DT_NODELABEL(other), 2) // 0
+ *     DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(DT_NODELABEL(other), 3) // 0
+ *
+ * @param node_id node identifier
+ * @param idx logical index into the ranges array
+ * @return 1 if "idx" is a valid child bus flags index,
+ *         0 otherwise.
+ */
+#define DT_RANGES_HAS_CHILD_BUS_FLAGS_AT_IDX(node_id, idx) \
+	IS_ENABLED(DT_CAT4(node_id, _RANGES_IDX_, idx, _VAL_CHILD_BUS_FLAGS_EXISTS))
+
+/**
+ * @brief Get the ranges property child bus flags at index
+ *
+ * When the node is a PCIe bus, the Child Bus Address has an extra cell used to store some
+ * flags, thus this cell is extracted from the Child Bus Address as Child Bus Flags field.
+ *
+ * Example devicetree fragments:
+ *
+ *     parent {
+ *             #address-cells = <2>;
+ *
+ *             pcie0: pcie@0 {
+ *                     compatible = "intel,pcie";
+ *                     reg = <0 0 1>;
+ *                     #address-cells = <3>;
+ *                     #size-cells = <2>;
+ *
+ *                     ranges = <0x1000000 0 0 0 0x3eff0000 0 0x10000>,
+ *                              <0x2000000 0 0x10000000 0 0x10000000 0 0x2eff0000>,
+ *                              <0x3000000 0x80 0 0x80 0 0x80 0>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(DT_NODELABEL(pcie0), 0) // 0x1000000
+ *     DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(DT_NODELABEL(pcie0), 1) // 0x2000000
+ *     DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(DT_NODELABEL(pcie0), 2) // 0x3000000
+ *
+ * @param node_id node identifier
+ * @param idx logical index into the ranges array
+ * @returns range child bus flags field at idx
+ */
+#define DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx) \
+	DT_CAT4(node_id, _RANGES_IDX_, idx, _VAL_CHILD_BUS_FLAGS)
+
+/**
+ * @brief Get the ranges property child bus address at index
+ *
+ * When the node is a PCIe bus, the Child Bus Address has an extra cell used to store some
+ * flags, thus this cell is removed from the Child Bus Address.
+ *
+ * Example devicetree fragments:
+ *
+ *     parent {
+ *             #address-cells = <2>;
+ *
+ *             pcie0: pcie@0 {
+ *                     compatible = "intel,pcie";
+ *                     reg = <0 0 1>;
+ *                     #address-cells = <3>;
+ *                     #size-cells = <2>;
+ *
+ *                     ranges = <0x1000000 0 0 0 0x3eff0000 0 0x10000>,
+ *                              <0x2000000 0 0x10000000 0 0x10000000 0 0x2eff0000>,
+ *                              <0x3000000 0x80 0 0x80 0 0x80 0>;
+ *             };
+ *
+ *             other: other@1 {
+ *                     reg = <0 1 1>;
+ *
+ *                     ranges = <0x0 0x0 0x0 0x3eff0000 0x10000>,
+ *                              <0x0 0x10000000 0x0 0x10000000 0x2eff0000>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(DT_NODELABEL(pcie0), 0) // 0
+ *     DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(DT_NODELABEL(pcie0), 1) // 0x10000000
+ *     DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(DT_NODELABEL(pcie0), 2) // 0x8000000000
+ *     DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(DT_NODELABEL(other), 0) // 0
+ *     DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(DT_NODELABEL(other), 1) // 0x10000000
+ *
+ * @param node_id node identifier
+ * @param idx logical index into the ranges array
+ * @returns range child bus address field at idx
+ */
+#define DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(node_id, idx) \
+	DT_CAT4(node_id, _RANGES_IDX_, idx, _VAL_CHILD_BUS_ADDRESS)
+
+/**
+ * @brief Get the ranges property parent bus address at index
+ *
+ * Similarly to DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(), this properly accounts
+ * for child bus flags cells when the node is a PCIe bus.
+ *
+ * Example devicetree fragment:
+ *
+ *     parent {
+ *             #address-cells = <2>;
+ *
+ *             pcie0: pcie@0 {
+ *                     compatible = "intel,pcie";
+ *                     reg = <0 0 1>;
+ *                     #address-cells = <3>;
+ *                     #size-cells = <2>;
+ *
+ *                     ranges = <0x1000000 0 0 0 0x3eff0000 0 0x10000>,
+ *                              <0x2000000 0 0x10000000 0 0x10000000 0 0x2eff0000>,
+ *                              <0x3000000 0x80 0 0x80 0 0x80 0>;
+ *             };
+ *
+ *             other: other@1 {
+ *                     reg = <0 1 1>;
+ *
+ *                     ranges = <0x0 0x0 0x0 0x3eff0000 0x10000>,
+ *                              <0x0 0x10000000 0x0 0x10000000 0x2eff0000>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(DT_NODELABEL(pcie0), 0) // 0x3eff0000
+ *     DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(DT_NODELABEL(pcie0), 1) // 0x10000000
+ *     DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(DT_NODELABEL(pcie0), 2) // 0x8000000000
+ *     DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(DT_NODELABEL(other), 0) // 0x3eff0000
+ *     DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(DT_NODELABEL(other), 1) // 0x10000000
+ *
+ * @param node_id node identifier
+ * @param idx logical index into the ranges array
+ * @returns range parent bus address field at idx
+ */
+#define DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(node_id, idx) \
+	DT_CAT4(node_id, _RANGES_IDX_, idx, _VAL_PARENT_BUS_ADDRESS)
+
+/**
+ * @brief Get the ranges property length at index
+ *
+ * Similarly to DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(), this properly accounts
+ * for child bus flags cells when the node is a PCIe bus.
+ *
+ * Example devicetree fragment:
+ *
+ *     parent {
+ *             #address-cells = <2>;
+ *
+ *             pcie0: pcie@0 {
+ *                     compatible = "intel,pcie";
+ *                     reg = <0 0 1>;
+ *                     #address-cells = <3>;
+ *                     #size-cells = <2>;
+ *
+ *                     ranges = <0x1000000 0 0 0 0x3eff0000 0 0x10000>,
+ *                              <0x2000000 0 0x10000000 0 0x10000000 0 0x2eff0000>,
+ *                              <0x3000000 0x80 0 0x80 0 0x80 0>;
+ *             };
+ *
+ *             other: other@1 {
+ *                     reg = <0 1 1>;
+ *
+ *                     ranges = <0x0 0x0 0x0 0x3eff0000 0x10000>,
+ *                              <0x0 0x10000000 0x0 0x10000000 0x2eff0000>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_RANGES_LENGTH_BY_IDX(DT_NODELABEL(pcie0), 0) // 0x10000
+ *     DT_RANGES_LENGTH_BY_IDX(DT_NODELABEL(pcie0), 1) // 0x2eff0000
+ *     DT_RANGES_LENGTH_BY_IDX(DT_NODELABEL(pcie0), 2) // 0x8000000000
+ *     DT_RANGES_LENGTH_BY_IDX(DT_NODELABEL(other), 0) // 0x10000
+ *     DT_RANGES_LENGTH_BY_IDX(DT_NODELABEL(other), 1) // 0x2eff0000
+ *
+ * @param node_id node identifier
+ * @param idx logical index into the ranges array
+ * @returns range length field at idx
+ */
+#define DT_RANGES_LENGTH_BY_IDX(node_id, idx) \
+	DT_CAT4(node_id, _RANGES_IDX_, idx, _VAL_LENGTH)
+
+/**
+ * @brief Invokes "fn" for each entry of "node_id" ranges property
+ *
+ * The macro "fn" must take two parameters, "node_id" which will be the node
+ * identifier of the node with the ranges property and "idx" the index of
+ * the ranges block.
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node@0 {
+ *             reg = <0 0 1>;
+ *
+ *             ranges = <0x0 0x0 0x0 0x3eff0000 0x10000>,
+ *                      <0x0 0x10000000 0x0 0x10000000 0x2eff0000>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     #define RANGE_LENGTH(node_id, idx) DT_RANGES_LENGTH_BY_IDX(node_id, idx),
+ *
+ *     const uint64_t *ranges_length[] = {
+ *             DT_FOREACH_RANGE(DT_NODELABEL(n), RANGE_LENGTH)
+ *     };
+ *
+ * This expands to:
+ *
+ *     const char *ranges_length[] = {
+ *         0x10000, 0x2eff0000,
+ *     };
+ *
+ * @param node_id node identifier
+ * @param fn macro to invoke
+ */
+#define DT_FOREACH_RANGE(node_id, fn) \
+	DT_CAT(node_id, _FOREACH_RANGE)(fn)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-reg-prop reg property
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get the number of register blocks in the reg property
+ *
+ * Use this instead of DT_PROP_LEN(node_id, reg).
+ * @param node_id node identifier
+ * @return Number of register blocks in the node's "reg" property.
+ */
+#define DT_NUM_REGS(node_id) DT_CAT(node_id, _REG_NUM)
+
+/**
+ * @brief Is "idx" a valid register block index?
+ *
+ * If this returns 1, then DT_REG_ADDR_BY_IDX(node_id, idx) or
+ * DT_REG_SIZE_BY_IDX(node_id, idx) are valid.
+ * If it returns 0, it is an error to use those macros with index "idx".
+ * @param node_id node identifier
+ * @param idx index to check
+ * @return 1 if "idx" is a valid register block index,
+ *         0 otherwise.
+ */
+#define DT_REG_HAS_IDX(node_id, idx) \
+	IS_ENABLED(DT_CAT(node_id, _REG_IDX_##idx##_EXISTS))
+
+/**
+ * @brief Get the base address of the register block at index "idx"
+ * @param node_id node identifier
+ * @param idx index of the register whose address to return
+ * @return address of the idx-th register block
+ */
+#define DT_REG_ADDR_BY_IDX(node_id, idx) \
+	DT_CAT(node_id, _REG_IDX_##idx##_VAL_ADDRESS)
+
+/**
+ * @brief Get the size of the register block at index "idx"
+ *
+ * This is the size of an individual register block, not the total
+ * number of register blocks in the property; use DT_NUM_REGS() for
+ * that.
+ *
+ * @param node_id node identifier
+ * @param idx index of the register whose size to return
+ * @return size of the idx-th register block
+ */
+#define DT_REG_SIZE_BY_IDX(node_id, idx) \
+	DT_CAT(node_id, _REG_IDX_##idx##_VAL_SIZE)
+
+/**
+ * @brief Get a node's (only) register block address
+ *
+ * Equivalent to DT_REG_ADDR_BY_IDX(node_id, 0).
+ * @param node_id node identifier
+ * @return node's register block address
+ */
+#define DT_REG_ADDR(node_id) DT_REG_ADDR_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get a node's (only) register block size
+ *
+ * Equivalent to DT_REG_SIZE_BY_IDX(node_id, 0).
+ * @param node_id node identifier
+ * @return node's only register block's size
+ */
+#define DT_REG_SIZE(node_id) DT_REG_SIZE_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get a register block's base address by name
+ * @param node_id node identifier
+ * @param name lowercase-and-underscores register specifier name
+ * @return address of the register block specified by name
+ */
+#define DT_REG_ADDR_BY_NAME(node_id, name) \
+	DT_CAT(node_id, _REG_NAME_##name##_VAL_ADDRESS)
+
+/**
+ * @brief Get a register block's size by name
+ * @param node_id node identifier
+ * @param name lowercase-and-underscores register specifier name
+ * @return size of the register block specified by name
+ */
+#define DT_REG_SIZE_BY_NAME(node_id, name) \
+	DT_CAT(node_id, _REG_NAME_##name##_VAL_SIZE)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-interrupts-prop interrupts property
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get the number of interrupt sources for the node
+ *
+ * Use this instead of DT_PROP_LEN(node_id, interrupts).
+ *
+ * @param node_id node identifier
+ * @return Number of interrupt specifiers in the node's "interrupts" property.
+ */
+#define DT_NUM_IRQS(node_id) DT_CAT(node_id, _IRQ_NUM)
+
+/**
+ * @brief Is "idx" a valid interrupt index?
+ *
+ * If this returns 1, then DT_IRQ_BY_IDX(node_id, idx) is valid.
+ * If it returns 0, it is an error to use that macro with this index.
+ * @param node_id node identifier
+ * @param idx index to check
+ * @return 1 if the idx is valid for the interrupt property
+ *         0 otherwise.
+ */
+#define DT_IRQ_HAS_IDX(node_id, idx) \
+	IS_ENABLED(DT_CAT(node_id, _IRQ_IDX_##idx##_EXISTS))
+
+/**
+ * @brief Does an interrupts property have a named cell specifier at an index?
+ * If this returns 1, then DT_IRQ_BY_IDX(node_id, idx, cell) is valid.
+ * If it returns 0, it is an error to use that macro.
+ * @param node_id node identifier
+ * @param idx index to check
+ * @param cell named cell value whose existence to check
+ * @return 1 if the named cell exists in the interrupt specifier at index idx
+ *         0 otherwise.
+ */
+#define DT_IRQ_HAS_CELL_AT_IDX(node_id, idx, cell) \
+	IS_ENABLED(DT_CAT(node_id, _IRQ_IDX_##idx##_VAL_##cell##_EXISTS))
+
+/**
+ * @brief Equivalent to DT_IRQ_HAS_CELL_AT_IDX(node_id, 0, cell)
+ * @param node_id node identifier
+ * @param cell named cell value whose existence to check
+ * @return 1 if the named cell exists in the interrupt specifier at index 0
+ *         0 otherwise.
+ */
+#define DT_IRQ_HAS_CELL(node_id, cell) DT_IRQ_HAS_CELL_AT_IDX(node_id, 0, cell)
+
+/**
+ * @brief Does an interrupts property have a named specifier value at an index?
+ * If this returns 1, then DT_IRQ_BY_NAME(node_id, name, cell) is valid.
+ * If it returns 0, it is an error to use that macro.
+ * @param node_id node identifier
+ * @param name lowercase-and-underscores interrupt specifier name
+ * @return 1 if "name" is a valid named specifier
+ *         0 otherwise.
+ */
+#define DT_IRQ_HAS_NAME(node_id, name) \
+	IS_ENABLED(DT_CAT(node_id, _IRQ_NAME_##name##_VAL_irq_EXISTS))
+
+/**
+ * @brief Get a value within an interrupt specifier at an index
+ *
+ * It might help to read the argument order as being similar to
+ * "node->interrupts[index].cell".
+ *
+ * This can be used to get information about an individual interrupt
+ * when a device generates more than one.
+ *
+ * Example devicetree fragment:
+ *
+ *     my-serial: serial@... {
+ *             interrupts = < 33 0 >, < 34 1 >;
+ *     };
+ *
+ * Assuming the node's interrupt domain has "#interrupt-cells = <2>;" and
+ * the individual cells in each interrupt specifier are named "irq" and
+ * "priority" by the node's binding, here are some examples:
+ *
+ *     #define SERIAL DT_NODELABEL(my_serial)
+ *
+ *     Example usage                       Value
+ *     -------------                       -----
+ *     DT_IRQ_BY_IDX(SERIAL, 0, irq)          33
+ *     DT_IRQ_BY_IDX(SERIAL, 0, priority)      0
+ *     DT_IRQ_BY_IDX(SERIAL, 1, irq,          34
+ *     DT_IRQ_BY_IDX(SERIAL, 1, priority)      1
+ *
+ * @param node_id node identifier
+ * @param idx logical index into the interrupt specifier array
+ * @param cell cell name specifier
+ * @return the named value at the specifier given by the index
+ */
+#define DT_IRQ_BY_IDX(node_id, idx, cell)   \
+	DT_CAT(node_id, _IRQ_IDX_##idx##_VAL_##cell)
+
+/**
+ * @brief Get a value within an interrupt specifier by name
+ *
+ * It might help to read the argument order as being similar to
+ * "node->interrupts.name.cell".
+ *
+ * This can be used to get information about an individual interrupt
+ * when a device generates more than one, if the bindings give each
+ * interrupt specifier a name.
+ *
+ * @param node_id node identifier
+ * @param name lowercase-and-underscores interrupt specifier name
+ * @param cell cell name specifier
+ * @return the named value at the specifier given by the index
+ */
+#define DT_IRQ_BY_NAME(node_id, name, cell) \
+	DT_CAT(node_id, _IRQ_NAME_##name##_VAL_##cell)
+
+/**
+ * @brief Get an interrupt specifier's value
+ * Equivalent to DT_IRQ_BY_IDX(node_id, 0, cell).
+ * @param node_id node identifier
+ * @param cell cell name specifier
+ * @return the named value at that index
+ */
+#define DT_IRQ(node_id, cell) DT_IRQ_BY_IDX(node_id, 0, cell)
+
+/**
+ * @brief Get a node's (only) irq number
+ *
+ * Equivalent to DT_IRQ(node_id, irq). This is provided as a convenience
+ * for the common case where a node generates exactly one interrupt,
+ * and the IRQ number is in a cell named "irq".
+ *
+ * @param node_id node identifier
+ * @return the interrupt number for the node's only interrupt
+ */
+#define DT_IRQN(node_id) DT_IRQ(node_id, irq)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-generic-chosen Chosen nodes
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get a node identifier for a /chosen node property
+ *
+ * This is only valid to call if DT_HAS_CHOSEN(prop) is 1.
+ * @param prop lowercase-and-underscores property name for
+ *             the /chosen node
+ * @return a node identifier for the chosen node property
+ */
+#define DT_CHOSEN(prop) DT_CAT(DT_CHOSEN_, prop)
+
+/**
+ * @brief Test if the devicetree has a /chosen node
+ * @param prop lowercase-and-underscores devicetree property
+ * @return 1 if the chosen property exists and refers to a node,
+ *         0 otherwise
+ */
+#define DT_HAS_CHOSEN(prop) IS_ENABLED(DT_CHOSEN_##prop##_EXISTS)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-generic-foreach "For-each" macros
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Invokes "fn" for each child of "node_id"
+ *
+ * The macro "fn" must take one parameter, which will be the node
+ * identifier of a child node of "node_id".
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             child-1 {
+ *                     label = "foo";
+ *             };
+ *             child-2 {
+ *                     label = "bar";
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     #define LABEL_AND_COMMA(node_id) DT_LABEL(node_id),
+ *
+ *     const char *child_labels[] = {
+ *         DT_FOREACH_CHILD(DT_NODELABEL(n), LABEL_AND_COMMA)
+ *     };
+ *
+ * This expands to:
+ *
+ *     const char *child_labels[] = {
+ *         "foo", "bar",
+ *     };
+ *
+ * @param node_id node identifier
+ * @param fn macro to invoke
+ */
+#define DT_FOREACH_CHILD(node_id, fn) \
+	DT_CAT(node_id, _FOREACH_CHILD)(fn)
+
+/**
+ * @brief Invokes "fn" for each child of "node_id" with multiple arguments
+ *
+ * The macro "fn" takes multiple arguments. The first should be the node
+ * identifier for the child node. The remaining are passed-in by the caller.
+ *
+ * @param node_id node identifier
+ * @param fn macro to invoke
+ * @param ... variable number of arguments to pass to fn
+ *
+ * @see DT_FOREACH_CHILD
+ */
+#define DT_FOREACH_CHILD_VARGS(node_id, fn, ...) \
+	DT_CAT(node_id, _FOREACH_CHILD_VARGS)(fn, __VA_ARGS__)
+
+/**
+ * @brief Call "fn" on the child nodes with status "okay"
+ *
+ * The macro "fn" should take one argument, which is the node
+ * identifier for the child node.
+ *
+ * As usual, both a missing status and an "ok" status are
+ * treated as "okay".
+ *
+ * @param node_id node identifier
+ * @param fn macro to invoke
+ */
+#define DT_FOREACH_CHILD_STATUS_OKAY(node_id, fn) \
+	DT_CAT(node_id, _FOREACH_CHILD_STATUS_OKAY)(fn)
+
+/**
+ * @brief Call "fn" on the child nodes with status "okay" with multiple
+ * arguments
+ *
+ * The macro "fn" takes multiple arguments. The first should be the node
+ * identifier for the child node. The remaining are passed-in by the caller.
+ *
+ * As usual, both a missing status and an "ok" status are
+ * treated as "okay".
+ *
+ * @param node_id node identifier
+ * @param fn macro to invoke
+ * @param ... variable number of arguments to pass to fn
+ *
+ * @see DT_FOREACH_CHILD_STATUS_OKAY
+ */
+#define DT_FOREACH_CHILD_STATUS_OKAY_VARGS(node_id, fn, ...) \
+	DT_CAT(node_id, _FOREACH_CHILD_STATUS_OKAY_VARGS)(fn, __VA_ARGS__)
+
+/**
+ * @brief Invokes "fn" for each element in the value of property "prop".
+ *
+ * The macro "fn" must take three parameters: fn(node_id, prop, idx).
+ * "node_id" and "prop" are the same as what is passed to
+ * DT_FOREACH_PROP_ELEM, and "idx" is the current index into the array.
+ * The "idx" values are integer literals starting from 0.
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             my-ints = <1 2 3>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     #define TIMES_TWO(node_id, prop, idx) \
+ *	       (2 * DT_PROP_BY_IDX(node_id, prop, idx)),
+ *
+ *     int array[] = {
+ *             DT_FOREACH_PROP_ELEM(DT_NODELABEL(n), my_ints, TIMES_TWO)
+ *     };
+ *
+ * This expands to:
+ *
+ *     int array[] = {
+ *             (2 * 1), (2 * 2), (2 * 3),
+ *     };
+ *
+ * In general, this macro expands to:
+ *
+ *     fn(node_id, prop, 0) fn(node_id, prop, 1) [...] fn(node_id, prop, n-1)
+ *
+ * where "n" is the number of elements in "prop", as it would be
+ * returned by <tt>DT_PROP_LEN(node_id, prop)</tt>.
+ *
+ * The "prop" argument must refer to a property with type string,
+ * array, uint8-array, string-array, phandles, or phandle-array. It is
+ * an error to use this macro with properties of other types.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ * @param fn macro to invoke
+ */
+#define DT_FOREACH_PROP_ELEM(node_id, prop, fn)		\
+	DT_CAT4(node_id, _P_, prop, _FOREACH_PROP_ELEM)(fn)
+
+/**
+ * @brief Invokes "fn" for each element in the value of property "prop" with
+ * multiple arguments.
+ *
+ * The macro "fn" must take multiple parameters: fn(node_id, prop, idx, ...).
+ * "node_id" and "prop" are the same as what is passed to
+ * DT_FOREACH_PROP_ELEM, and "idx" is the current index into the array.
+ * The "idx" values are integer literals starting from 0. The remaining
+ * arguments are passed-in by the caller.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ * @param fn macro to invoke
+ * @param ... variable number of arguments to pass to fn
+ *
+ * @see DT_FOREACH_PROP_ELEM
+ */
+#define DT_FOREACH_PROP_ELEM_VARGS(node_id, prop, fn, ...)		\
+	DT_CAT4(node_id, _P_, prop, _FOREACH_PROP_ELEM_VARGS)(fn, __VA_ARGS__)
+
+/**
+ * @brief Invokes "fn" for each status "okay" node of a compatible.
+ *
+ * This macro expands to:
+ *
+ *     fn(node_id_1) fn(node_id_2) ... fn(node_id_n)
+ *
+ * where each "node_id_<i>" is a node identifier for some node with
+ * compatible "compat" and status "okay". Whitespace is added between
+ * expansions as shown above.
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *             a {
+ *                     compatible = "foo";
+ *                     status = "okay";
+ *             };
+ *             b {
+ *                     compatible = "foo";
+ *                     status = "disabled";
+ *             };
+ *             c {
+ *                     compatible = "foo";
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_FOREACH_STATUS_OKAY(foo, DT_NODE_PATH)
+ *
+ * This expands to one of the following:
+ *
+ *     "/a" "/c"
+ *     "/c" "/a"
+ *
+ * "One of the following" is because no guarantees are made about the
+ * order that node identifiers are passed to "fn" in the expansion.
+ *
+ * (The "/c" string literal is present because a missing status
+ * property is always treated as if the status were set to "okay".)
+ *
+ * Note also that "fn" is responsible for adding commas, semicolons,
+ * or other terminators as needed.
+ *
+ * @param compat lowercase-and-underscores devicetree compatible
+ * @param fn Macro to call for each enabled node. Must accept a
+ *           node_id as its only parameter.
+ */
+#define DT_FOREACH_STATUS_OKAY(compat, fn)				\
+	COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(compat),			\
+		    (UTIL_CAT(DT_FOREACH_OKAY_, compat)(fn)),	\
+		    ())
+
+/**
+ * @brief Invokes "fn" for each status "okay" node of a compatible
+ *        with multiple arguments.
+ *
+ * This is like DT_FOREACH_STATUS_OKAY() except you can also pass
+ * additional arguments to "fn".
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *             a {
+ *                     compatible = "foo";
+ *                     val = <3>;
+ *             };
+ *             b {
+ *                     compatible = "foo";
+ *                     val = <4>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     #define MY_FN(node_id, operator) DT_PROP(node_id, val) operator
+ *     x = DT_FOREACH_STATUS_OKAY_VARGS(foo, MY_FN, +) 0;
+ *
+ * This expands to one of the following:
+ *
+ *     x = 3 + 4 + 0;
+ *     x = 4 + 3 + 0;
+ *
+ * i.e. it sets x to 7. As with DT_FOREACH_STATUS_OKAY(), there are no
+ * guarantees about the order nodes appear in the expansion.
+ *
+ * @param compat lowercase-and-underscores devicetree compatible
+ * @param fn Macro to call for each enabled node. Must accept a
+ *           node_id as its only parameter.
+ * @param ... Additional arguments to pass to "fn"
+ */
+#define DT_FOREACH_STATUS_OKAY_VARGS(compat, fn, ...)			\
+	COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(compat),			\
+		    (UTIL_CAT(DT_FOREACH_OKAY_VARGS_,			\
+			      compat)(fn, __VA_ARGS__)),		\
+		    ())
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-generic-exist Existence checks
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Does a node identifier refer to a node?
+ *
+ * Tests whether a node identifier refers to a node which exists, i.e.
+ * is defined in the devicetree.
+ *
+ * It doesn't matter whether or not the node has a matching binding,
+ * or what the node's status value is. This is purely a check of
+ * whether the node exists at all.
+ *
+ * @param node_id a node identifier
+ * @return 1 if the node identifier refers to a node,
+ *         0 otherwise.
+ */
+#define DT_NODE_EXISTS(node_id) IS_ENABLED(DT_CAT(node_id, _EXISTS))
+
+/**
+ * @brief Does a node identifier refer to a node with a status?
+ *
+ * Example uses:
+ *
+ *     DT_NODE_HAS_STATUS(DT_PATH(soc, i2c_12340000), okay)
+ *     DT_NODE_HAS_STATUS(DT_PATH(soc, i2c_12340000), disabled)
+ *
+ * Tests whether a node identifier refers to a node which:
+ *
+ * - exists in the devicetree, and
+ * - has a status property matching the second argument
+ *   (except that either a missing status or an "ok" status
+ *   in the devicetree is treated as if it were "okay" instead)
+ *
+ * @param node_id a node identifier
+ * @param status a status as one of the tokens okay or disabled, not a string
+ * @return 1 if the node has the given status, 0 otherwise.
+ */
+#define DT_NODE_HAS_STATUS(node_id, status) \
+	DT_NODE_HAS_STATUS_INTERNAL(node_id, status)
+
+/**
+ * @brief Does the devicetree have a status "okay" node with a compatible?
+ *
+ * Test for whether the devicetree has any nodes with status "okay"
+ * and the given compatible. That is, this returns 1 if and only if
+ * there is at least one "node_id" for which both of these
+ * expressions return 1:
+ *
+ *     DT_NODE_HAS_STATUS(node_id, okay)
+ *     DT_NODE_HAS_COMPAT(node_id, compat)
+ *
+ * As usual, both a missing status and an "ok" status are treated as
+ * "okay".
+ *
+ * @param compat lowercase-and-underscores compatible, without quotes
+ * @return 1 if both of the above conditions are met, 0 otherwise
+ */
+#define DT_HAS_COMPAT_STATUS_OKAY(compat) \
+	IS_ENABLED(DT_CAT(DT_COMPAT_HAS_OKAY_, compat))
+
+/**
+ * @brief Get the number of instances of a given compatible with
+ *        status "okay"
+ * @param compat lowercase-and-underscores compatible, without quotes
+ * @return Number of instances with status "okay"
+ */
+#define DT_NUM_INST_STATUS_OKAY(compat)			\
+	UTIL_AND(DT_HAS_COMPAT_STATUS_OKAY(compat),		\
+		 UTIL_CAT(DT_N_INST, DT_DASH(compat, NUM_OKAY)))
+
+/**
+ * @brief Does a devicetree node match a compatible?
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             compatible = "vnd,specific-device", "generic-device";
+ *     }
+ *
+ * Example usages which evaluate to 1:
+ *
+ *     DT_NODE_HAS_COMPAT(DT_NODELABEL(n), vnd_specific_device)
+ *     DT_NODE_HAS_COMPAT(DT_NODELABEL(n), generic_device)
+ *
+ * This macro only uses the value of the compatible property. Whether
+ * or not a particular compatible has a matching binding has no effect
+ * on its value, nor does the node's status.
+ *
+ * @param node_id node identifier
+ * @param compat lowercase-and-underscores compatible, without quotes
+ * @return 1 if the node's compatible property contains compat,
+ *         0 otherwise.
+ */
+#define DT_NODE_HAS_COMPAT(node_id, compat) \
+	IS_ENABLED(DT_CAT(node_id, _COMPAT_MATCHES_##compat))
+
+/**
+ * @brief Does a devicetree node have a compatible and status?
+ *
+ * This is equivalent to:
+ *
+ *     (DT_NODE_HAS_COMPAT(node_id, compat) &&
+ *      DT_NODE_HAS_STATUS(node_id, status))
+ *
+ * @param node_id node identifier
+ * @param compat lowercase-and-underscores compatible, without quotes
+ * @param status okay or disabled as a token, not a string
+ */
+#define DT_NODE_HAS_COMPAT_STATUS(node_id, compat, status) \
+	DT_NODE_HAS_COMPAT(node_id, compat) && DT_NODE_HAS_STATUS(node_id, status)
+
+/**
+ * @brief Does a devicetree node have a property?
+ *
+ * Tests whether a devicetree node has a property defined.
+ *
+ * This tests whether the property is defined at all, not whether a
+ * boolean property is true or false. To get a boolean property's
+ * truth value, use DT_PROP(node_id, prop) instead.
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ * @return 1 if the node has the property, 0 otherwise.
+ */
+#define DT_NODE_HAS_PROP(node_id, prop) \
+	IS_ENABLED(DT_CAT(node_id, _P_##prop##_EXISTS))
+
+
+/**
+ * @brief Does a phandle array have a named cell specifier at an index?
+ *
+ * If this returns 1, then the phandle-array property "pha" has a cell
+ * named "cell" at index "idx", and therefore DT_PHA_BY_IDX(node_id,
+ * pha, idx, cell) is valid. If it returns 0, it's an error to use
+ * DT_PHA_BY_IDX() with the same arguments.
+ *
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param idx index to check within "pha"
+ * @param cell lowercase-and-underscores cell name whose existence to check
+ *             at index "idx"
+ * @return 1 if the named cell exists in the specifier at index idx,
+ *         0 otherwise.
+ */
+#define DT_PHA_HAS_CELL_AT_IDX(node_id, pha, idx, cell)             \
+	IS_ENABLED(DT_PROP(node_id,                                 \
+			   pha##_IDX_##idx##_VAL_##cell##_EXISTS))
+
+/**
+ * @brief Equivalent to DT_PHA_HAS_CELL_AT_IDX(node_id, pha, 0, cell)
+ * @param node_id node identifier
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param cell lowercase-and-underscores cell name whose existence to check
+ *             at index "idx"
+ * @return 1 if the named cell exists in the specifier at index 0,
+ *         0 otherwise.
+ */
+#define DT_PHA_HAS_CELL(node_id, pha, cell) \
+	DT_PHA_HAS_CELL_AT_IDX(node_id, pha, 0, cell)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-generic-bus Bus helpers
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Node's bus controller
+ *
+ * Get the node identifier of the node's bus controller. This can be
+ * used with @ref DT_PROP() to get properties of the bus controller.
+ *
+ * It is an error to use this with nodes which do not have bus
+ * controllers.
+ *
+ * Example devicetree fragment:
+ *
+ *     i2c@deadbeef {
+ *             label = "I2C_CTLR";
+ *             status = "okay";
+ *             clock-frequency = < 100000 >;
+ *
+ *             i2c_device: accelerometer@12 {
+ *                     ...
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PROP(DT_BUS(DT_NODELABEL(i2c_device)), clock_frequency) // 100000
+ *
+ * @param node_id node identifier
+ * @return a node identifier for the node's bus controller
+ */
+#define DT_BUS(node_id) DT_CAT(node_id, _BUS)
+
+/**
+ * @brief Node's bus controller's label property
+ * @param node_id node identifier
+ * @return the label property of the node's bus controller DT_BUS(node)
+ */
+#define DT_BUS_LABEL(node_id) DT_PROP(DT_BUS(node_id), label)
+
+/**
+ * @brief Is a node on a bus of a given type?
+ *
+ * Example devicetree overlay:
+ *
+ *     &i2c0 {
+ *            temp: temperature-sensor@76 {
+ *                     compatible = "vnd,some-sensor";
+ *                     reg = <0x76>;
+ *            };
+ *     };
+ *
+ * Example usage, assuming "i2c0" is an I2C bus controller node, and
+ * therefore "temp" is on an I2C bus:
+ *
+ *     DT_ON_BUS(DT_NODELABEL(temp), i2c) // 1
+ *     DT_ON_BUS(DT_NODELABEL(temp), spi) // 0
+ *
+ * @param node_id node identifier
+ * @param bus lowercase-and-underscores bus type as a C token (i.e.
+ *            without quotes)
+ * @return 1 if the node is on a bus of the given type,
+ *         0 otherwise
+ */
+#define DT_ON_BUS(node_id, bus) IS_ENABLED(DT_CAT(node_id, _BUS_##bus))
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup devicetree-inst Instance-based devicetree APIs
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Node identifier for an instance of a DT_DRV_COMPAT compatible
+ * @param inst instance number
+ * @return a node identifier for the node with DT_DRV_COMPAT compatible and
+ *         instance number "inst"
+ */
+#define DT_DRV_INST(inst) DT_INST(inst, DT_DRV_COMPAT)
+
+/**
+ * @brief Call "fn" on all child nodes of DT_DRV_INST(inst).
+ *
+ * The macro "fn" should take one argument, which is the node
+ * identifier for the child node.
+ *
+ * @param inst instance number
+ * @param fn macro to invoke on each child node identifier
+ *
+ * @see DT_FOREACH_CHILD
+ */
+#define DT_INST_FOREACH_CHILD(inst, fn) \
+	DT_FOREACH_CHILD(DT_DRV_INST(inst), fn)
+
+/**
+ * @brief Call "fn" on all child nodes of DT_DRV_INST(inst).
+ *
+ * The macro "fn" takes multiple arguments. The first should be the node
+ * identifier for the child node. The remaining are passed-in by the caller.
+ *
+ * @param inst instance number
+ * @param fn macro to invoke on each child node identifier
+ * @param ... variable number of arguments to pass to fn
+ *
+ * @see DT_FOREACH_CHILD
+ */
+#define DT_INST_FOREACH_CHILD_VARGS(inst, fn, ...) \
+	DT_FOREACH_CHILD_VARGS(DT_DRV_INST(inst), fn, __VA_ARGS__)
+
+/**
+ * @brief Get a DT_DRV_COMPAT value's index into its enumeration values
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @return zero-based index of the property's value in its enum: list
+ */
+#define DT_INST_ENUM_IDX(inst, prop) \
+	DT_ENUM_IDX(DT_DRV_INST(inst), prop)
+
+/**
+ * @brief Like DT_INST_ENUM_IDX(), but with a fallback to a default enum index
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @param default_idx_value a fallback index value to expand to
+ * @return zero-based index of the property's value in its enum if present,
+ *         default_idx_value ohterwise
+ */
+#define DT_INST_ENUM_IDX_OR(inst, prop, default_idx_value) \
+	DT_ENUM_IDX_OR(DT_DRV_INST(inst), prop, default_idx_value)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance property
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @return a representation of the property's value
+ */
+#define DT_INST_PROP(inst, prop) DT_PROP(DT_DRV_INST(inst), prop)
+
+/**
+ * @brief Get a DT_DRV_COMPAT property length
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @return logical length of the property
+ */
+#define DT_INST_PROP_LEN(inst, prop) DT_PROP_LEN(DT_DRV_INST(inst), prop)
+
+/**
+ * @brief Is index "idx" valid for an array type property
+ *        on a DT_DRV_COMPAT instance?
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @param idx index to check
+ * @return 1 if "idx" is a valid index into the given property,
+ *         0 otherwise.
+ */
+#define DT_INST_PROP_HAS_IDX(inst, prop, idx) \
+	DT_PROP_HAS_IDX(DT_DRV_INST(inst), prop, idx)
+
+/**
+ * @brief Get a DT_DRV_COMPAT element value in an array property
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @param idx the index to get
+ * @return a representation of the idx-th element of the property
+ */
+#define DT_INST_PROP_BY_IDX(inst, prop, idx) \
+	DT_PROP_BY_IDX(DT_DRV_INST(inst), prop, idx)
+
+/**
+ * @brief Like DT_INST_PROP(), but with a fallback to default_value
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @param default_value a fallback value to expand to
+ * @return DT_INST_PROP(inst, prop) or default_value
+ */
+#define DT_INST_PROP_OR(inst, prop, default_value) \
+	DT_PROP_OR(DT_DRV_INST(inst), prop, default_value)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's "label" property
+ * @param inst instance number
+ * @return instance's label property value
+ */
+#define DT_INST_LABEL(inst) DT_INST_PROP(inst, label)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's property value from a phandle's node
+ * @param inst instance number
+ * @param ph lowercase-and-underscores property of "inst"
+ *           with type "phandle"
+ * @param prop lowercase-and-underscores property of the phandle's node
+ * @return the value of "prop" as described in the DT_PROP() documentation
+ */
+#define DT_INST_PROP_BY_PHANDLE(inst, ph, prop) \
+	DT_INST_PROP_BY_PHANDLE_IDX(inst, ph, 0, prop)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's property value from a phandle in a
+ * property.
+ * @param inst instance number
+ * @param phs lowercase-and-underscores property with type "phandle",
+ *            "phandles", or "phandle-array"
+ * @param idx logical index into "phs", which must be zero if "phs"
+ *            has type "phandle"
+ * @param prop lowercase-and-underscores property of the phandle's node
+ * @return the value of "prop" as described in the DT_PROP() documentation
+ */
+#define DT_INST_PROP_BY_PHANDLE_IDX(inst, phs, idx, prop) \
+	DT_PROP_BY_PHANDLE_IDX(DT_DRV_INST(inst), phs, idx, prop)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's phandle-array specifier value at an index
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param idx logical index into the property "pha"
+ * @param cell binding's cell name within the specifier at index "idx"
+ * @return the value of the cell inside the specifier at index "idx"
+ */
+#define DT_INST_PHA_BY_IDX(inst, pha, idx, cell) \
+	DT_PHA_BY_IDX(DT_DRV_INST(inst), pha, idx, cell)
+
+/**
+ * @brief Like DT_INST_PHA_BY_IDX(), but with a fallback to default_value
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param idx logical index into the property "pha"
+ * @param cell binding's cell name within the specifier at index "idx"
+ * @param default_value a fallback value to expand to
+ * @return DT_INST_PHA_BY_IDX(inst, pha, idx, cell) or default_value
+ */
+#define DT_INST_PHA_BY_IDX_OR(inst, pha, idx, cell, default_value) \
+	DT_PHA_BY_IDX_OR(DT_DRV_INST(inst), pha, idx, cell, default_value)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's phandle-array specifier value
+ * Equivalent to DT_INST_PHA_BY_IDX(inst, pha, 0, cell)
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param cell binding's cell name for the specifier at "pha" index 0
+ * @return the cell value
+ */
+#define DT_INST_PHA(inst, pha, cell) DT_INST_PHA_BY_IDX(inst, pha, 0, cell)
+
+/**
+ * @brief Like DT_INST_PHA(), but with a fallback to default_value
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param cell binding's cell name for the specifier at "pha" index 0
+ * @param default_value a fallback value to expand to
+ * @return DT_INST_PHA(inst, pha, cell) or default_value
+ */
+#define DT_INST_PHA_OR(inst, pha, cell, default_value) \
+	DT_INST_PHA_BY_IDX_OR(inst, pha, 0, cell, default_value)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's value within a phandle-array
+ * specifier by name
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param name lowercase-and-underscores name of a specifier in "pha"
+ * @param cell binding's cell name for the named specifier
+ * @return the cell value
+ */
+#define DT_INST_PHA_BY_NAME(inst, pha, name, cell) \
+	DT_PHA_BY_NAME(DT_DRV_INST(inst), pha, name, cell)
+
+/**
+ * @brief Like DT_INST_PHA_BY_NAME(), but with a fallback to default_value
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param name lowercase-and-underscores name of a specifier in "pha"
+ * @param cell binding's cell name for the named specifier
+ * @param default_value a fallback value to expand to
+ * @return DT_INST_PHA_BY_NAME(inst, pha, name, cell) or default_value
+ */
+#define DT_INST_PHA_BY_NAME_OR(inst, pha, name, cell, default_value) \
+	DT_PHA_BY_NAME_OR(DT_DRV_INST(inst), pha, name, cell, default_value)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's phandle node identifier from a
+ * phandle array by name
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param name lowercase-and-underscores name of an element in "pha"
+ * @return node identifier for the phandle at the element named "name"
+ */
+#define DT_INST_PHANDLE_BY_NAME(inst, pha, name) \
+	DT_PHANDLE_BY_NAME(DT_DRV_INST(inst), pha, name) \
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's node identifier for a phandle in
+ * a property.
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name in "inst"
+ *             with type "phandle", "phandles" or "phandle-array"
+ * @param idx index into "prop"
+ * @return a node identifier for the phandle at index "idx" in "prop"
+ */
+#define DT_INST_PHANDLE_BY_IDX(inst, prop, idx) \
+	DT_PHANDLE_BY_IDX(DT_DRV_INST(inst), prop, idx)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's node identifier for a phandle
+ * property's value
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property of "inst"
+ *             with type "phandle"
+ * @return a node identifier for the node pointed to by "ph"
+ */
+#define DT_INST_PHANDLE(inst, prop) DT_INST_PHANDLE_BY_IDX(inst, prop, 0)
+
+/**
+ * @brief is "idx" a valid register block index on a DT_DRV_COMPAT instance?
+ * @param inst instance number
+ * @param idx index to check
+ * @return 1 if "idx" is a valid register block index,
+ *         0 otherwise.
+ */
+#define DT_INST_REG_HAS_IDX(inst, idx) DT_REG_HAS_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's idx-th register block's address
+ * @param inst instance number
+ * @param idx index of the register whose address to return
+ * @return address of the instance's idx-th register block
+ */
+#define DT_INST_REG_ADDR_BY_IDX(inst, idx) DT_REG_ADDR_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's idx-th register block's size
+ * @param inst instance number
+ * @param idx index of the register whose size to return
+ * @return size of the instance's idx-th register block
+ */
+#define DT_INST_REG_SIZE_BY_IDX(inst, idx) \
+	DT_REG_SIZE_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get a DT_DRV_COMPAT's register block address by name
+ * @param inst instance number
+ * @param name lowercase-and-underscores register specifier name
+ * @return address of the register block with the given name
+ */
+#define DT_INST_REG_ADDR_BY_NAME(inst, name) \
+	DT_REG_ADDR_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Get a DT_DRV_COMPAT's register block size by name
+ * @param inst instance number
+ * @param name lowercase-and-underscores register specifier name
+ * @return size of the register block with the given name
+ */
+#define DT_INST_REG_SIZE_BY_NAME(inst, name) \
+	DT_REG_SIZE_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Get a DT_DRV_COMPAT's (only) register block address
+ * @param inst instance number
+ * @return instance's register block address
+ */
+#define DT_INST_REG_ADDR(inst) DT_INST_REG_ADDR_BY_IDX(inst, 0)
+
+/**
+ * @brief Get a DT_DRV_COMPAT's (only) register block size
+ * @param inst instance number
+ * @return instance's register block size
+ */
+#define DT_INST_REG_SIZE(inst) DT_INST_REG_SIZE_BY_IDX(inst, 0)
+
+/**
+ * @brief Get a DT_DRV_COMPAT interrupt specifier value at an index
+ * @param inst instance number
+ * @param idx logical index into the interrupt specifier array
+ * @param cell cell name specifier
+ * @return the named value at the specifier given by the index
+ */
+#define DT_INST_IRQ_BY_IDX(inst, idx, cell) \
+	DT_IRQ_BY_IDX(DT_DRV_INST(inst), idx, cell)
+
+/**
+ * @brief Get a DT_DRV_COMPAT interrupt specifier value by name
+ * @param inst instance number
+ * @param name lowercase-and-underscores interrupt specifier name
+ * @param cell cell name specifier
+ * @return the named value at the specifier given by the index
+ */
+#define DT_INST_IRQ_BY_NAME(inst, name, cell) \
+	DT_IRQ_BY_NAME(DT_DRV_INST(inst), name, cell)
+
+/**
+ * @brief Get a DT_DRV_COMPAT interrupt specifier's value
+ * @param inst instance number
+ * @param cell cell name specifier
+ * @return the named value at that index
+ */
+#define DT_INST_IRQ(inst, cell) DT_INST_IRQ_BY_IDX(inst, 0, cell)
+
+/**
+ * @brief Get a DT_DRV_COMPAT's (only) irq number
+ * @param inst instance number
+ * @return the interrupt number for the node's only interrupt
+ */
+#define DT_INST_IRQN(inst) DT_INST_IRQ(inst, irq)
+
+/**
+ * @brief Get a DT_DRV_COMPAT's bus node identifier
+ * @param inst instance number
+ * @return node identifier for the instance's bus node
+ */
+#define DT_INST_BUS(inst) DT_BUS(DT_DRV_INST(inst))
+
+/**
+ * @brief Get a DT_DRV_COMPAT's bus node's label property
+ * @param inst instance number
+ * @return the label property of the instance's bus controller
+ */
+#define DT_INST_BUS_LABEL(inst) DT_BUS_LABEL(DT_DRV_INST(inst))
+
+/**
+ * @brief Test if a DT_DRV_COMPAT's bus type is a given type
+ * @param inst instance number
+ * @param bus a binding's bus type as a C token, lowercased and without quotes
+ * @return 1 if the given instance is on a bus of the given type,
+ *         0 otherwise
+ */
+#define DT_INST_ON_BUS(inst, bus) DT_ON_BUS(DT_DRV_INST(inst), bus)
+
+/**
+ * @brief Test if any DT_DRV_COMPAT node is on a bus of a given type
+ *        and has status okay
+ *
+ * This is a special-purpose macro which can be useful when writing
+ * drivers for devices which can appear on multiple buses. One example
+ * is a sensor device which may be wired on an I2C or SPI bus.
+ *
+ * Example devicetree overlay:
+ *
+ *     &i2c0 {
+ *            temp: temperature-sensor@76 {
+ *                     compatible = "vnd,some-sensor";
+ *                     reg = <0x76>;
+ *            };
+ *     };
+ *
+ * Example usage, assuming "i2c0" is an I2C bus controller node, and
+ * therefore "temp" is on an I2C bus:
+ *
+ *     #define DT_DRV_COMPAT vnd_some_sensor
+ *
+ *     DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) // 1
+ *
+ * @param bus a binding's bus type as a C token, lowercased and without quotes
+ * @return 1 if any enabled node with that compatible is on that bus type,
+ *         0 otherwise
+ */
+#define DT_ANY_INST_ON_BUS_STATUS_OKAY(bus) \
+	DT_COMPAT_ON_BUS_INTERNAL(DT_DRV_COMPAT, bus)
+
+/**
+ * @brief Call "fn" on all nodes with compatible DT_DRV_COMPAT
+ *        and status "okay"
+ *
+ * This macro calls "fn(inst)" on each "inst" number that refers to a
+ * node with status "okay". Whitespace is added between invocations.
+ *
+ * Example devicetree fragment:
+ *
+ *     a {
+ *             compatible = "vnd,device";
+ *             status = "okay";
+ *             label = "DEV_A";
+ *     };
+ *
+ *     b {
+ *             compatible = "vnd,device";
+ *             status = "okay";
+ *             label = "DEV_B";
+ *     };
+ *
+ *     c {
+ *             compatible = "vnd,device";
+ *             status = "disabled";
+ *             label = "DEV_C";
+ *     };
+ *
+ * Example usage:
+ *
+ *     #define DT_DRV_COMPAT vnd_device
+ *     #define MY_FN(inst) DT_INST_LABEL(inst),
+ *
+ *     DT_INST_FOREACH_STATUS_OKAY(MY_FN)
+ *
+ * This expands to:
+ *
+ *     MY_FN(0) MY_FN(1)
+ *
+ * and from there, to either this:
+ *
+ *     "DEV_A", "DEV_B",
+ *
+ * or this:
+ *
+ *     "DEV_B", "DEV_A",
+ *
+ * No guarantees are made about the order that a and b appear in the
+ * expansion.
+ *
+ * Note that "fn" is responsible for adding commas, semicolons, or
+ * other separators or terminators.
+ *
+ * Device drivers should use this macro whenever possible to
+ * instantiate a struct device for each enabled node in the devicetree
+ * of the driver's compatible DT_DRV_COMPAT.
+ *
+ * @param fn Macro to call for each enabled node. Must accept an
+ *           instance number as its only parameter.
+ */
+#define DT_INST_FOREACH_STATUS_OKAY(fn) \
+	COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT),	\
+		    (UTIL_CAT(DT_FOREACH_OKAY_INST_,		\
+			      DT_DRV_COMPAT)(fn)),		\
+		    ())
+
+/**
+ * @brief Call "fn" on all nodes with compatible DT_DRV_COMPAT
+ *        and status "okay" with multiple arguments
+ *
+ *
+ * @param fn Macro to call for each enabled node. Must accept an
+ *           instance number as its only parameter.
+ * @param ... variable number of arguments to pass to fn
+ *
+ * @see DT_INST_FOREACH_STATUS_OKAY
+ */
+#define DT_INST_FOREACH_STATUS_OKAY_VARGS(fn, ...) \
+	COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT),	\
+		    (UTIL_CAT(DT_FOREACH_OKAY_INST_VARGS_,	\
+			      DT_DRV_COMPAT)(fn, __VA_ARGS__)),	\
+		    ())
+
+/**
+ * @brief Invokes "fn" for each element of property "prop" for
+ *        a DT_DRV_COMPAT instance.
+ *
+ * Equivalent to DT_FOREACH_PROP_ELEM(DT_DRV_INST(inst), prop, fn).
+ *
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @param fn macro to invoke
+ */
+#define DT_INST_FOREACH_PROP_ELEM(inst, prop, fn) \
+	DT_FOREACH_PROP_ELEM(DT_DRV_INST(inst), prop, fn)
+
+/**
+ * @brief Invokes "fn" for each element of property "prop" for
+ *        a DT_DRV_COMPAT instance with multiple arguments.
+ *
+ * Equivalent to
+ *      DT_FOREACH_PROP_ELEM_VARGS(DT_DRV_INST(inst), prop, fn, __VA_ARGS__)
+ *
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @param fn macro to invoke
+ * @param ... variable number of arguments to pass to fn
+ *
+ * @see DT_INST_FOREACH_PROP_ELEM
+ */
+#define DT_INST_FOREACH_PROP_ELEM_VARGS(inst, prop, fn, ...) \
+	DT_FOREACH_PROP_ELEM_VARGS(DT_DRV_INST(inst), prop, fn, __VA_ARGS__)
+
+/**
+ * @brief Does a DT_DRV_COMPAT instance have a property?
+ * @param inst instance number
+ * @param prop lowercase-and-underscores property name
+ * @return 1 if the instance has the property, 0 otherwise.
+ */
+#define DT_INST_NODE_HAS_PROP(inst, prop) \
+	DT_NODE_HAS_PROP(DT_DRV_INST(inst), prop)
+
+/**
+ * @brief Does a phandle array have a named cell specifier at an index
+ *        for a DT_DRV_COMPAT instance?
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param idx index to check
+ * @param cell named cell value whose existence to check
+ * @return 1 if the named cell exists in the specifier at index idx,
+ *         0 otherwise.
+ */
+#define DT_INST_PHA_HAS_CELL_AT_IDX(inst, pha, idx, cell) \
+	DT_PHA_HAS_CELL_AT_IDX(DT_DRV_INST(inst), pha, idx, cell)
+
+/**
+ * @brief Does a phandle array have a named cell specifier at index 0
+ *        for a DT_DRV_COMPAT instance?
+ * @param inst instance number
+ * @param pha lowercase-and-underscores property with type "phandle-array"
+ * @param cell named cell value whose existence to check
+ * @return 1 if the named cell exists in the specifier at index 0,
+ *         0 otherwise.
+ */
+#define DT_INST_PHA_HAS_CELL(inst, pha, cell) \
+	DT_INST_PHA_HAS_CELL_AT_IDX(inst, pha, 0, cell)
+
+/**
+ * @brief is index valid for interrupt property on a DT_DRV_COMPAT instance?
+ * @param inst instance number
+ * @param idx logical index into the interrupt specifier array
+ * @return 1 if the idx is valid for the interrupt property
+ *         0 otherwise.
+ */
+#define DT_INST_IRQ_HAS_IDX(inst, idx) DT_IRQ_HAS_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Does a DT_DRV_COMPAT instance have an interrupt named cell specifier?
+ * @param inst instance number
+ * @param idx index to check
+ * @param cell named cell value whose existence to check
+ * @return 1 if the named cell exists in the interrupt specifier at index idx
+ *         0 otherwise.
+ */
+#define DT_INST_IRQ_HAS_CELL_AT_IDX(inst, idx, cell) \
+	DT_IRQ_HAS_CELL_AT_IDX(DT_DRV_INST(inst), idx, cell)
+
+/**
+ * @brief Does a DT_DRV_COMPAT instance have an interrupt value?
+ * @param inst instance number
+ * @param cell named cell value whose existence to check
+ * @return 1 if the named cell exists in the interrupt specifier at index 0
+ *         0 otherwise.
+ */
+#define DT_INST_IRQ_HAS_CELL(inst, cell) \
+	DT_INST_IRQ_HAS_CELL_AT_IDX(inst, 0, cell)
+
+/**
+ * @brief Does a DT_DRV_COMPAT instance have an interrupt value?
+ * @param inst instance number
+ * @param name lowercase-and-underscores interrupt specifier name
+ * @return 1 if "name" is a valid named specifier
+ */
+#define DT_INST_IRQ_HAS_NAME(inst, name) \
+	DT_IRQ_HAS_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @}
+ */
+
+/** @internal pay no attention to the man behind the curtain! */
+#define DT_PATH_INTERNAL(...) \
+	UTIL_CAT(DT_ROOT, MACRO_MAP_CAT(DT_S_PREFIX, __VA_ARGS__))
+/** @internal helper for DT_PATH(): prepends _S_ to a node name */
+#define DT_S_PREFIX(name) _S_##name
+
+/**
+ * @internal concatenation helper, 2 arguments
+ *
+ * This and the following macros are used to paste things together
+ * with "##" *after* forcing expansion on each argument.
+ *
+ * We could try to use something like UTIL_CAT(), but the compiler
+ * error messages from the util macros can be extremely long when they
+ * are misused. This unfortunately happens often with devicetree.h,
+ * since its macro-based API is fiddly and can be hard to get right.
+ *
+ * Keeping things brutally simple here hopefully makes some errors
+ * easier to read.
+ */
+#define DT_CAT(a1, a2) a1 ## a2
+/** @internal concatenation helper, 3 arguments */
+#define DT_CAT3(a1, a2, a3) a1 ## a2 ## a3
+/** @internal concatenation helper, 4 arguments */
+#define DT_CAT4(a1, a2, a3, a4) a1 ## a2 ## a3 ## a4
+/** @internal concatenation helper, 5 arguments */
+#define DT_CAT5(a1, a2, a3, a4, a5) a1 ## a2 ## a3 ## a4 ## a5
+/** @internal concatenation helper, 6 arguments */
+#define DT_CAT6(a1, a2, a3, a4, a5, a6) a1 ## a2 ## a3 ## a4 ## a5 ## a6
+/*
+ * If you need to define a bigger DT_CATN(), do so here. Don't leave
+ * any "holes" of undefined macros, please.
+ */
+
+/** @internal helper for node identifier macros to expand args */
+#define DT_DASH(...) MACRO_MAP_CAT(DT_DASH_PREFIX, __VA_ARGS__)
+/** @internal helper for DT_DASH(): prepends _ to a name */
+#define DT_DASH_PREFIX(name) _##name
+/** @internal helper for DT_NODE_HAS_STATUS */
+#define DT_NODE_HAS_STATUS_INTERNAL(node_id, status) \
+	IS_ENABLED(DT_CAT(node_id, _STATUS_ ## status))
+/** @internal helper for test cases and DT_ANY_INST_ON_BUS_STATUS_OKAY() */
+#define DT_COMPAT_ON_BUS_INTERNAL(compat, bus) \
+	IS_ENABLED(UTIL_CAT(DT_CAT(DT_COMPAT_, compat), _BUS_##bus))
+
+/* have these last so they have access to all previously defined macros */
+#include <devicetree/io-channels.h>
+#include <devicetree/clocks.h>
+#include <devicetree/gpio.h>
+#include <devicetree/spi.h>
+#include <devicetree/dma.h>
+#include <devicetree/pwms.h>
+#include <devicetree/fixed-partitions.h>
+#include <devicetree/zephyr.h>
+#include <devicetree/ordinals.h>
+#include <devicetree/pinctrl.h>
+
+#endif /* DEVICETREE_H */
diff --git a/src/include/devicetree/clocks.h b/src/include/devicetree/clocks.h
new file mode 100644
index 0000000000..b5d656b4c1
--- /dev/null
+++ b/src/include/devicetree/clocks.h
@@ -0,0 +1,359 @@
+/**
+ * @file
+ * @brief Clocks Devicetree macro public API header file.
+ */
+
+/*
+ * Copyright (c) 2020, Linaro Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_CLOCKS_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_CLOCKS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup devicetree-clocks Devicetree Clocks API
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        "clocks" phandle-array property at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... { ... };
+ *
+ *     clk2: clock-controller@... { ... };
+ *
+ *     n: node {
+ *             clocks = <&clk1 10 20>, <&clk2 30 40>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(n), 0)) // DT_NODELABEL(clk1)
+ *     DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(n), 1)) // DT_NODELABEL(clk2)
+ *
+ * @param node_id node identifier
+ * @param idx logical index into "clocks"
+ * @return the node identifier for the clock controller referenced at
+ *         index "idx"
+ * @see DT_PHANDLE_BY_IDX()
+ */
+#define DT_CLOCKS_CTLR_BY_IDX(node_id, idx) \
+	DT_PHANDLE_BY_IDX(node_id, clocks, idx)
+
+/**
+ * @brief Equivalent to DT_CLOCKS_CTLR_BY_IDX(node_id, 0)
+ * @param node_id node identifier
+ * @return a node identifier for the clocks controller at index 0
+ *         in "clocks"
+ * @see DT_CLOCKS_CTLR_BY_IDX()
+ */
+#define DT_CLOCKS_CTLR(node_id) DT_CLOCKS_CTLR_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        clocks phandle-array property at an index
+ *
+
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... { ... };
+ *
+ *     clk2: clock-controller@... { ... };
+ *
+ *     n: node {
+ *             clocks = <&clk1 10 20>, <&clk2 30 40>;
+ *             clock-names = "alpha", "beta";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_CLOCKS_CTLR_BY_NAME(DT_NODELABEL(n), beta) // DT_NODELABEL(clk2)
+ *
+ * @param node_id node identifier
+ * @param name lowercase-and-underscores name of a clocks element
+ *             as defined by the node's clock-names property
+ * @return the node identifier for the clock controller referenced by name
+ * @see DT_PHANDLE_BY_NAME()
+ */
+#define DT_CLOCKS_CTLR_BY_NAME(node_id, name) \
+	DT_PHANDLE_BY_NAME(node_id, clocks, name)
+
+/**
+ * @brief Get a label property from the node referenced by a pwms
+ *        property at an index
+ *
+ * It's an error if the clock controller node referenced by the
+ * phandle in node_id's clocks property at index "idx" has no label
+ * property.
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... {
+ *             label = "CLK_1";
+ *     };
+ *
+ *     clk2: clock-controller@... {
+ *             label = "CLK_2";
+ *     };
+ *
+ *     n: node {
+ *             clocks = <&clk1 10 20>, <&clk2 30 40>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_CLOCKS_LABEL_BY_IDX(DT_NODELABEL(n), 1) // "CLK_2"
+ *
+ * @param node_id node identifier for a node with a clocks property
+ * @param idx logical index into clocks property
+ * @return the label property of the node referenced at index "idx"
+ * @see DT_PROP_BY_PHANDLE_IDX()
+ */
+#define DT_CLOCKS_LABEL_BY_IDX(node_id, idx) \
+	__DEPRECATED_MACRO \
+	DT_PROP_BY_PHANDLE_IDX(node_id, clocks, idx, label)
+
+/**
+ * @brief Get a label property from a clocks property by name
+ *
+ * It's an error if the clock controller node referenced by the
+ * phandle in node_id's clocks property at the element named "name"
+ * has no label property.
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... {
+ *             label = "CLK_1";
+ *     };
+ *
+ *     clk2: clock-controller@... {
+ *             label = "CLK_2";
+ *     };
+ *
+ *     n: node {
+ *             clocks = <&clk1 10 20>, <&clk2 30 40>;
+ *             clock-names = "alpha", "beta";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_CLOCKS_LABEL_BY_NAME(DT_NODELABEL(n), beta) // "CLK_2"
+ *
+ * @param node_id node identifier for a node with a clocks property
+ * @param name lowercase-and-underscores name of a clocks element
+ *             as defined by the node's clock-names property
+ * @return the label property of the node referenced at the named element
+ * @see DT_PHANDLE_BY_NAME()
+ */
+#define DT_CLOCKS_LABEL_BY_NAME(node_id, name) \
+	__DEPRECATED_MACRO \
+	DT_PROP(DT_PHANDLE_BY_NAME(node_id, clocks, name), label)
+
+/**
+ * @brief Equivalent to DT_CLOCKS_LABEL_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with a clocks property
+ * @return the label property of the node referenced at index 0
+ * @see DT_CLOCKS_LABEL_BY_IDX()
+ */
+#define DT_CLOCKS_LABEL(node_id) __DEPRECATED_MACRO DT_CLOCKS_LABEL_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get a clock specifier's cell value at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... {
+ *             compatible = "vnd,clock";
+ *             #clock-cells = < 2 >;
+ *     };
+ *
+ *     n: node {
+ *             clocks = < &clk1 10 20 >, < &clk1 30 40 >;
+ *     };
+ *
+ * Bindings fragment for the vnd,clock compatible:
+ *
+ *     clock-cells:
+ *       - bus
+ *       - bits
+ *
+ * Example usage:
+ *
+ *     DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(n), 0, bus) // 10
+ *     DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(n), 1, bits) // 40
+ *
+ * @param node_id node identifier for a node with a clocks property
+ * @param idx logical index into clocks property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index "idx"
+ * @see DT_PHA_BY_IDX()
+ */
+#define DT_CLOCKS_CELL_BY_IDX(node_id, idx, cell) \
+	DT_PHA_BY_IDX(node_id, clocks, idx, cell)
+
+/**
+ * @brief Get a clock specifier's cell value by name
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... {
+ *             compatible = "vnd,clock";
+ *             #clock-cells = < 2 >;
+ *     };
+ *
+ *     n: node {
+ *             clocks = < &clk1 10 20 >, < &clk1 30 40 >;
+ *             clock-names = "alpha", "beta";
+ *     };
+ *
+ * Bindings fragment for the vnd,clock compatible:
+ *
+ *     clock-cells:
+ *       - bus
+ *       - bits
+ *
+ * Example usage:
+ *
+ *     DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(n), alpha, bus) // 10
+ *     DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(n), beta, bits) // 40
+ *
+ * @param node_id node identifier for a node with a clocks property
+ * @param name lowercase-and-underscores name of a clocks element
+ *             as defined by the node's clock-names property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value in the specifier at the named element
+ * @see DT_PHA_BY_NAME()
+ */
+#define DT_CLOCKS_CELL_BY_NAME(node_id, name, cell) \
+	DT_PHA_BY_NAME(node_id, clocks, name, cell)
+
+/**
+ * @brief Equivalent to DT_CLOCKS_CELL_BY_IDX(node_id, 0, cell)
+ * @param node_id node identifier for a node with a clocks property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index 0
+ * @see DT_CLOCKS_CELL_BY_IDX()
+ */
+#define DT_CLOCKS_CELL(node_id, cell) DT_CLOCKS_CELL_BY_IDX(node_id, 0, cell)
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        "clocks" phandle-array property at an index
+ *
+ * @param inst instance number
+ * @param idx logical index into "clocks"
+ * @return the node identifier for the clock controller referenced at
+ *         index "idx"
+ * @see DT_CLOCKS_CTLR_BY_IDX()
+ */
+#define DT_INST_CLOCKS_CTLR_BY_IDX(inst, idx) \
+	DT_CLOCKS_CTLR_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Equivalent to DT_INST_CLOCKS_CTLR_BY_IDX(inst, 0)
+ * @param inst instance number
+ * @return a node identifier for the clocks controller at index 0
+ *         in "clocks"
+ * @see DT_CLOCKS_CTLR()
+ */
+#define DT_INST_CLOCKS_CTLR(inst) DT_INST_CLOCKS_CTLR_BY_IDX(inst, 0)
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        clocks phandle-array property by name
+ *
+ * @param inst instance number
+ * @param name lowercase-and-underscores name of a clocks element
+ *             as defined by the node's clock-names property
+ * @return the node identifier for the clock controller referenced by
+ *         the named element
+ * @see DT_CLOCKS_CTLR_BY_NAME()
+ */
+#define DT_INST_CLOCKS_CTLR_BY_NAME(inst, name) \
+	DT_CLOCKS_CTLR_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's clocks
+ *        property at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into clocks property
+ * @return the label property of the node referenced at index "idx"
+ * @see DT_CLOCKS_LABEL_BY_IDX()
+ */
+#define DT_INST_CLOCKS_LABEL_BY_IDX(inst, idx) \
+	__DEPRECATED_MACRO \
+	DT_CLOCKS_LABEL_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's clocks
+ *        property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a clocks element
+ *             as defined by the node's clock-names property
+ * @return the label property of the node referenced at the named element
+ * @see DT_CLOCKS_LABEL_BY_NAME()
+ */
+#define DT_INST_CLOCKS_LABEL_BY_NAME(inst, name) \
+	__DEPRECATED_MACRO \
+	DT_CLOCKS_LABEL_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Equivalent to DT_INST_CLOCKS_LABEL_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the label property of the node referenced at index 0
+ * @see DT_CLOCKS_LABEL_BY_IDX()
+ */
+#define DT_INST_CLOCKS_LABEL(inst) DT_INST_CLOCKS_LABEL_BY_IDX(inst, 0) __DEPRECATED_MACRO
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's clock specifier's cell value
+ *        at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into clocks property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index "idx"
+ * @see DT_CLOCKS_CELL_BY_IDX()
+ */
+#define DT_INST_CLOCKS_CELL_BY_IDX(inst, idx, cell) \
+	DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(inst), idx, cell)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's clock specifier's cell value by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a clocks element
+ *             as defined by the node's clock-names property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value in the specifier at the named element
+ * @see DT_CLOCKS_CELL_BY_NAME()
+ */
+#define DT_INST_CLOCKS_CELL_BY_NAME(inst, name, cell) \
+	DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(inst), name, cell)
+
+/**
+ * @brief Equivalent to DT_INST_CLOCKS_CELL_BY_IDX(inst, 0, cell)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param cell lowercase-and-underscores cell name
+ * @return the value of the cell inside the specifier at index 0
+ */
+#define DT_INST_CLOCKS_CELL(inst, cell) \
+	DT_INST_CLOCKS_CELL_BY_IDX(inst, 0, cell)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_CLOCKS_H_ */
diff --git a/src/include/devicetree/dma.h b/src/include/devicetree/dma.h
new file mode 100644
index 0000000000..31e88e909f
--- /dev/null
+++ b/src/include/devicetree/dma.h
@@ -0,0 +1,376 @@
+/**
+ * @file
+ * @brief DMA Devicetree macro public API header file.
+ */
+
+/*
+ * Copyright (c) 2020, Linaro Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_DMAS_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_DMAS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup devicetree-dmas Devicetree DMA API
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get a label property from the node referenced by a dmas
+ *        property at an index
+ *
+ * It's an error if the DMA controller node referenced by the phandle
+ * in node_id's dmas property at index "idx" has no label property.
+ *
+ * Example devicetree fragment:
+ *
+ *     dma1: dma@... {
+ *             label = "DMA_1";
+ *     };
+ *
+ *     dma2: dma@... {
+ *             label = "DMA_2";
+ *     };
+ *
+ *     n: node {
+ *		dmas = <&dma1 1 2 0x400 0x3>,
+ *			<&dma2 6 3 0x404 0x5>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_DMAS_LABEL_BY_IDX(DT_NODELABEL(n), 1) // "DMA_2"
+ *
+ * @param node_id node identifier for a node with a dmas property
+ * @param idx logical index into dmas property
+ * @return the label property of the node referenced at index "idx"
+ */
+#define DT_DMAS_LABEL_BY_IDX(node_id, idx) \
+	__DEPRECATED_MACRO \
+	DT_PROP_BY_PHANDLE_IDX(node_id, dmas, idx, label)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's dmas
+ *        property at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into dmas property
+ * @return the label property of the node referenced at index "idx"
+ * @see DT_DMAS_LABEL_BY_IDX()
+ */
+#define DT_INST_DMAS_LABEL_BY_IDX(inst, idx) \
+	__DEPRECATED_MACRO \
+	DT_DMAS_LABEL_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get a label property from a dmas property by name
+ *
+ * It's an error if the DMA controller node referenced by the phandle
+ * in node_id's dmas property at the element named "name" has no label
+ * property.
+ *
+ * Example devicetree fragment:
+ *
+ *     dma1: dma@... {
+ *             label = "DMA_1";
+ *     };
+ *
+ *     dma2: dma@... {
+ *             label = "DMA_2";
+ *     };
+ *
+ *     n: node {
+ *		dmas = <&dma1 1 2 0x400 0x3>,
+ *			<&dma2 6 3 0x404 0x5>;
+ *		dma-names = "tx", "rx";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_DMAS_LABEL_BY_NAME(DT_NODELABEL(n), rx) // "DMA_2"
+ *
+ * @param node_id node identifier for a node with a dmas property
+ * @param name lowercase-and-underscores name of a dmas element
+ *             as defined by the node's dma-names property
+ * @return the label property of the node referenced at the named element
+ */
+#define DT_DMAS_LABEL_BY_NAME(node_id, name) \
+	__DEPRECATED_MACRO \
+	DT_PROP(DT_PHANDLE_BY_NAME(node_id, dmas, name), label)
+
+/**
+ * @brief Get the node identifier for the DMA controller from a
+ *        dmas property at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     dma1: dma@... { ... };
+ *
+ *     dma2: dma@... { ... };
+ *
+ *     n: node {
+ *		dmas = <&dma1 1 2 0x400 0x3>,
+ *			<&dma2 6 3 0x404 0x5>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_DMAS_CTLR_BY_IDX(DT_NODELABEL(n), 0) // DT_NODELABEL(dma1)
+ *     DT_DMAS_CTLR_BY_IDX(DT_NODELABEL(n), 1) // DT_NODELABEL(dma2)
+ *
+ * @param node_id node identifier for a node with a dmas property
+ * @param idx logical index into dmas property
+ * @return the node identifier for the DMA controller referenced at
+ *         index "idx"
+ * @see DT_PROP_BY_PHANDLE_IDX()
+ */
+#define DT_DMAS_CTLR_BY_IDX(node_id, idx) DT_PHANDLE_BY_IDX(node_id, dmas, idx)
+
+/**
+ * @brief Get the node identifier for the DMA controller from a
+ *        dmas property by name
+ *
+ * Example devicetree fragment:
+ *
+ *     dma1: dma@... { ... };
+ *
+ *     dma2: dma@... { ... };
+ *
+ *     n: node {
+ *		dmas = <&dma1 1 2 0x400 0x3>,
+ *			<&dma2 6 3 0x404 0x5>;
+ *		dma-names = "tx", "rx";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_DMAS_CTLR_BY_NAME(DT_NODELABEL(n), tx) // DT_NODELABEL(dma1)
+ *     DT_DMAS_CTLR_BY_NAME(DT_NODELABEL(n), rx) // DT_NODELABEL(dma2)
+ *
+ * @param node_id node identifier for a node with a dmas property
+ * @param name lowercase-and-underscores name of a dmas element
+ *             as defined by the node's dma-names property
+ * @return the node identifier for the DMA controller in the named element
+ * @see DT_PHANDLE_BY_NAME()
+ */
+#define DT_DMAS_CTLR_BY_NAME(node_id, name) \
+	DT_PHANDLE_BY_NAME(node_id, dmas, name)
+
+/**
+ * @brief Equivalent to DT_DMAS_CTLR_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with a dmas property
+ * @return the node identifier for the DMA controller at index 0
+ *         in the node's "dmas" property
+ * @see DT_DMAS_CTLR_BY_IDX()
+ */
+#define DT_DMAS_CTLR(node_id) DT_DMAS_CTLR_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's dmas
+ *        property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a dmas element
+ *             as defined by the node's dma-names property
+ * @return the label property of the node referenced at the named element
+ * @see DT_DMAS_LABEL_BY_NAME()
+ */
+#define DT_INST_DMAS_LABEL_BY_NAME(inst, name) \
+	__DEPRECATED_MACRO \
+	DT_DMAS_LABEL_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Get the node identifier for the DMA controller from a
+ *        DT_DRV_COMPAT instance's dmas property at an index
+ *
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into dmas property
+ * @return the node identifier for the DMA controller referenced at
+ *         index "idx"
+ * @see DT_DMAS_CTLR_BY_IDX()
+ */
+#define DT_INST_DMAS_CTLR_BY_IDX(inst, idx) \
+	DT_DMAS_CTLR_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get the node identifier for the DMA controller from a
+ *        DT_DRV_COMPAT instance's dmas property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a dmas element
+ *             as defined by the node's dma-names property
+ * @return the node identifier for the DMA controller in the named element
+ * @see DT_DMAS_CTLR_BY_NAME()
+ */
+#define DT_INST_DMAS_CTLR_BY_NAME(inst, name) \
+	DT_DMAS_CTLR_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Equivalent to DT_INST_DMAS_CTLR_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the node identifier for the DMA controller at index 0
+ *         in the instance's "dmas" property
+ * @see DT_DMAS_CTLR_BY_IDX()
+ */
+#define DT_INST_DMAS_CTLR(inst) DT_INST_DMAS_CTLR_BY_IDX(inst, 0)
+
+/**
+ * @brief Get a DMA specifier's cell value at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     dma1: dma@... {
+ *             compatible = "vnd,dma";
+ *             #dma-cells = <2>;
+ *     };
+ *
+ *     dma2: dma@... {
+ *             compatible = "vnd,dma";
+ *             #dma-cells = <2>;
+ *     };
+ *
+ *     n: node {
+ *		dmas = <&dma1 1 0x400>,
+ *		       <&dma2 6 0x404>;
+ *     };
+ *
+ * Bindings fragment for the vnd,dma compatible:
+ *
+ *     dma-cells:
+ *       - channel
+ *       - config
+ *
+ * Example usage:
+ *
+ *     DT_DMAS_CELL_BY_IDX(DT_NODELABEL(n), 0, channel) // 1
+ *     DT_DMAS_CELL_BY_IDX(DT_NODELABEL(n), 1, channel) // 6
+ *     DT_DMAS_CELL_BY_IDX(DT_NODELABEL(n), 0, config) // 0x400
+ *     DT_DMAS_CELL_BY_IDX(DT_NODELABEL(n), 1, config) // 0x404
+ *
+ * @param node_id node identifier for a node with a dmas property
+ * @param idx logical index into dmas property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index "idx"
+ * @see DT_PHA_BY_IDX()
+ */
+#define DT_DMAS_CELL_BY_IDX(node_id, idx, cell) \
+	DT_PHA_BY_IDX(node_id, dmas, idx, cell)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's DMA specifier's cell value at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into dmas property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index "idx"
+ * @see DT_DMAS_CELL_BY_IDX()
+ */
+#define DT_INST_DMAS_CELL_BY_IDX(inst, idx, cell) \
+	DT_PHA_BY_IDX(DT_DRV_INST(inst), dmas, idx, cell)
+
+/**
+ * @brief Get a DMA specifier's cell value by name
+ *
+ * Example devicetree fragment:
+ *
+ *     dma1: dma@... {
+ *             compatible = "vnd,dma";
+ *             #dma-cells = <2>;
+ *     };
+ *
+ *     dma2: dma@... {
+ *             compatible = "vnd,dma";
+ *             #dma-cells = <2>;
+ *     };
+ *
+ *     n: node {
+ *		dmas = <&dma1 1 0x400>,
+ *		       <&dma2 6 0x404>;
+ *		dma-names = "tx", "rx";
+ *     };
+ *
+ * Bindings fragment for the vnd,dma compatible:
+ *
+ *     dma-cells:
+ *       - channel
+ *       - config
+ *
+ * Example usage:
+ *
+ *     DT_DMAS_CELL_BY_NAME(DT_NODELABEL(n), tx, channel) // 1
+ *     DT_DMAS_CELL_BY_NAME(DT_NODELABEL(n), rx, channel) // 6
+ *     DT_DMAS_CELL_BY_NAME(DT_NODELABEL(n), tx, config) // 0x400
+ *     DT_DMAS_CELL_BY_NAME(DT_NODELABEL(n), rx, config) // 0x404
+ *
+ * @param node_id node identifier for a node with a dmas property
+ * @param name lowercase-and-underscores name of a dmas element
+ *             as defined by the node's dma-names property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value in the specifier at the named element
+ * @see DT_PHA_BY_NAME()
+ */
+#define DT_DMAS_CELL_BY_NAME(node_id, name, cell) \
+	DT_PHA_BY_NAME(node_id, dmas, name, cell)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's DMA specifier's cell value by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a dmas element
+ *             as defined by the node's dma-names property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value in the specifier at the named element
+ * @see DT_DMAS_CELL_BY_NAME()
+ */
+#define DT_INST_DMAS_CELL_BY_NAME(inst, name, cell) \
+	DT_DMAS_CELL_BY_NAME(DT_DRV_INST(inst), name, cell)
+
+/**
+ * @brief Is index "idx" valid for a dmas property?
+ * @param node_id node identifier for a node with a dmas property
+ * @param idx logical index into dmas property
+ * @return 1 if the "dmas" property has index "idx", 0 otherwise
+ */
+#define DT_DMAS_HAS_IDX(node_id, idx) \
+	IS_ENABLED(DT_CAT(node_id, _P_dmas_IDX_##idx##_EXISTS))
+
+/**
+ * @brief Is index "idx" valid for a DT_DRV_COMPAT instance's dmas property?
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into dmas property
+ * @return 1 if the "dmas" property has a specifier at index "idx", 0 otherwise
+ */
+#define DT_INST_DMAS_HAS_IDX(inst, idx) \
+	DT_DMAS_HAS_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Does a dmas property have a named element?
+ * @param node_id node identifier for a node with a dmas property
+ * @param name lowercase-and-underscores name of a dmas element
+ *             as defined by the node's dma-names property
+ * @return 1 if the dmas property has the named element, 0 otherwise
+ */
+#define DT_DMAS_HAS_NAME(node_id, name) \
+	IS_ENABLED(DT_CAT(node_id, _P_dmas_NAME_##name##_EXISTS))
+
+/**
+ * @brief Does a DT_DRV_COMPAT instance's dmas property have a named element?
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a dmas element
+ *             as defined by the node's dma-names property
+ * @return 1 if the dmas property has the named element, 0 otherwise
+ */
+#define DT_INST_DMAS_HAS_NAME(inst, name) \
+	DT_DMAS_HAS_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_DMAS_H_ */
diff --git a/src/include/devicetree/fixed-partitions.h b/src/include/devicetree/fixed-partitions.h
new file mode 100644
index 0000000000..4eeb31055c
--- /dev/null
+++ b/src/include/devicetree/fixed-partitions.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ * @brief Flash Devicetree macro public API header file.
+ */
+
+/*
+ * Copyright (c) 2020, Linaro Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_FIXED_PARTITION_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_FIXED_PARTITION_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup devicetree-fixed-partition Devicetree Fixed Partition API
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get a node identifier for a fixed partition with
+ *        a given label property
+ *
+ * Example devicetree fragment:
+ *
+ *     flash@... {
+ *              partitions {
+ *                      compatible = "fixed-partitions";
+ *                      boot_partition: partition@0 {
+ *                              label = "mcuboot";
+ *                      };
+ *                      slot0_partition: partition@c000 {
+ *                              label = "image-0";
+ *                      };
+ *                      ...
+ *              };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_NODE_BY_FIXED_PARTITION_LABEL(mcuboot) // node identifier for boot_partition
+ *     DT_NODE_BY_FIXED_PARTITION_LABEL(image_0) // node identifier for slot0_partition
+ *
+ * @param label lowercase-and-underscores label property value
+ * @return a node identifier for the partition with that label property
+ */
+#define DT_NODE_BY_FIXED_PARTITION_LABEL(label) \
+	DT_CAT(DT_COMPAT_fixed_partitions_LABEL_, label)
+
+/**
+ * @brief Test if a fixed partition with a given label property exists
+ * @param label lowercase-and-underscores label property value
+ * @return 1 if any "fixed-partitions" child node has the given label,
+ *         0 otherwise.
+ */
+#define DT_HAS_FIXED_PARTITION_LABEL(label) \
+	IS_ENABLED(DT_COMPAT_fixed_partitions_LABEL_##label##_EXISTS)
+
+/**
+ * @brief Get a numeric identifier for a fixed partition
+ * @param node_id node identifier for a fixed-partitions child node
+ * @return the partition's ID, a unique zero-based index number
+ */
+#define DT_FIXED_PARTITION_ID(node_id) DT_CAT(node_id, _PARTITION_ID)
+
+/**
+ * @brief Get the node identifier of the flash device for a partition
+ * @param node_id node identifier for a fixed-partitions child node
+ * @return the node identifier of the memory technology device that
+ * contains the fixed-partitions node.
+ */
+#define DT_MTD_FROM_FIXED_PARTITION(node_id)				\
+	COND_CODE_1(DT_NODE_HAS_COMPAT(DT_GPARENT(node_id), soc_nv_flash), \
+		    (DT_PARENT(DT_GPARENT(node_id))),			\
+		    (DT_GPARENT(node_id)))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_FIXED_PARTITION_H_ */
diff --git a/src/include/devicetree/gpio.h b/src/include/devicetree/gpio.h
new file mode 100644
index 0000000000..43d3a36f6d
--- /dev/null
+++ b/src/include/devicetree/gpio.h
@@ -0,0 +1,305 @@
+/**
+ * @file
+ * @brief GPIO Devicetree macro public API header file.
+ */
+
+/*
+ * Copyright (c) 2020, Linaro Ltd.
+ * Copyright (c) 2020 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_GPIO_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_GPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup devicetree-gpio Devicetree GPIO API
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        gpio phandle-array property at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     gpio1: gpio@... { };
+ *
+ *     gpio2: gpio@... { };
+ *
+ *     n: node {
+ *             gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                     <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(n), gpios, 1) // DT_NODELABEL(gpio2)
+ *
+ * @param node_id node identifier
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @param idx logical index into "gpio_pha"
+ * @return the node identifier for the gpio controller referenced at
+ *         index "idx"
+ * @see DT_PHANDLE_BY_IDX()
+ */
+#define DT_GPIO_CTLR_BY_IDX(node_id, gpio_pha, idx) \
+	DT_PHANDLE_BY_IDX(node_id, gpio_pha, idx)
+
+/**
+ * @brief Equivalent to DT_GPIO_CTLR_BY_IDX(node_id, gpio_pha, 0)
+ * @param node_id node identifier
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @return a node identifier for the gpio controller at index 0
+ *         in "gpio_pha"
+ * @see DT_GPIO_CTLR_BY_IDX()
+ */
+#define DT_GPIO_CTLR(node_id, gpio_pha) \
+	DT_GPIO_CTLR_BY_IDX(node_id, gpio_pha, 0)
+
+/**
+ * @brief Get a label property from a gpio phandle-array property
+ *        at an index
+ *
+ * It's an error if the GPIO controller node referenced by the phandle
+ * in node_id's "gpio_pha" property at index "idx" has no label
+ * property.
+ *
+ * Example devicetree fragment:
+ *
+ *     gpio1: gpio@... {
+ *             label = "GPIO_1";
+ *     };
+ *
+ *     gpio2: gpio@... {
+ *             label = "GPIO_2";
+ *     };
+ *
+ *     n: node {
+ *             gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                     <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_GPIO_LABEL_BY_IDX(DT_NODELABEL(n), gpios, 1) // "GPIO_2"
+ *
+ * @param node_id node identifier
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @param idx logical index into "gpio_pha"
+ * @return the label property of the node referenced at index "idx"
+ * @see DT_PHANDLE_BY_IDX()
+ */
+#define DT_GPIO_LABEL_BY_IDX(node_id, gpio_pha, idx) \
+	DT_PROP(DT_GPIO_CTLR_BY_IDX(node_id, gpio_pha, idx), label)
+
+/**
+ * @brief Equivalent to DT_GPIO_LABEL_BY_IDX(node_id, gpio_pha, 0)
+ * @param node_id node identifier
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @return the label property of the node referenced at index 0
+ * @see DT_GPIO_LABEL_BY_IDX()
+ */
+#define DT_GPIO_LABEL(node_id, gpio_pha) \
+	DT_GPIO_LABEL_BY_IDX(node_id, gpio_pha, 0)
+
+/**
+ * @brief Get a GPIO specifier's pin cell at an index
+ *
+ * This macro only works for GPIO specifiers with cells named "pin".
+ * Refer to the node's binding to check if necessary.
+ *
+ * Example devicetree fragment:
+ *
+ *     gpio1: gpio@... {
+ *             compatible = "vnd,gpio";
+ *             #gpio-cells = <2>;
+ *     };
+ *
+ *     gpio2: gpio@... {
+ *             compatible = "vnd,gpio";
+ *             #gpio-cells = <2>;
+ *     };
+ *
+ *     n: node {
+ *             gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                     <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ *     };
+ *
+ * Bindings fragment for the vnd,gpio compatible:
+ *
+ *     gpio-cells:
+ *       - pin
+ *       - flags
+ *
+ * Example usage:
+ *
+ *     DT_GPIO_PIN_BY_IDX(DT_NODELABEL(n), gpios, 0) // 10
+ *     DT_GPIO_PIN_BY_IDX(DT_NODELABEL(n), gpios, 1) // 30
+ *
+ * @param node_id node identifier
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @param idx logical index into "gpio_pha"
+ * @return the pin cell value at index "idx"
+ * @see DT_PHA_BY_IDX()
+ */
+#define DT_GPIO_PIN_BY_IDX(node_id, gpio_pha, idx) \
+	DT_PHA_BY_IDX(node_id, gpio_pha, idx, pin)
+
+/**
+ * @brief Equivalent to DT_GPIO_PIN_BY_IDX(node_id, gpio_pha, 0)
+ * @param node_id node identifier
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @return the pin cell value at index 0
+ * @see DT_GPIO_PIN_BY_IDX()
+ */
+#define DT_GPIO_PIN(node_id, gpio_pha) \
+	DT_GPIO_PIN_BY_IDX(node_id, gpio_pha, 0)
+
+/**
+ * @brief Get a GPIO specifier's flags cell at an index
+ *
+ * This macro expects GPIO specifiers with cells named "flags".
+ * If there is no "flags" cell in the GPIO specifier, zero is returned.
+ * Refer to the node's binding to check specifier cell names if necessary.
+ *
+ * Example devicetree fragment:
+ *
+ *     gpio1: gpio@... {
+ *             compatible = "vnd,gpio";
+ *             #gpio-cells = <2>;
+ *     };
+ *
+ *     gpio2: gpio@... {
+ *             compatible = "vnd,gpio";
+ *             #gpio-cells = <2>;
+ *     };
+ *
+ *     n: node {
+ *             gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                     <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ *     };
+ *
+ * Bindings fragment for the vnd,gpio compatible:
+ *
+ *     gpio-cells:
+ *       - pin
+ *       - flags
+ *
+ * Example usage:
+ *
+ *     DT_GPIO_FLAGS_BY_IDX(DT_NODELABEL(n), gpios, 0) // GPIO_ACTIVE_LOW
+ *     DT_GPIO_FLAGS_BY_IDX(DT_NODELABEL(n), gpios, 1) // GPIO_ACTIVE_HIGH
+ *
+ * @param node_id node identifier
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @param idx logical index into "gpio_pha"
+ * @return the flags cell value at index "idx", or zero if there is none
+ * @see DT_PHA_BY_IDX()
+ */
+#define DT_GPIO_FLAGS_BY_IDX(node_id, gpio_pha, idx) \
+	DT_PHA_BY_IDX_OR(node_id, gpio_pha, idx, flags, 0)
+
+/**
+ * @brief Equivalent to DT_GPIO_FLAGS_BY_IDX(node_id, gpio_pha, 0)
+ * @param node_id node identifier
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @return the flags cell value at index 0, or zero if there is none
+ * @see DT_GPIO_FLAGS_BY_IDX()
+ */
+#define DT_GPIO_FLAGS(node_id, gpio_pha) \
+	DT_GPIO_FLAGS_BY_IDX(node_id, gpio_pha, 0)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's GPIO
+ *        property at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @param idx logical index into "gpio_pha"
+ * @return the label property of the node referenced at index "idx"
+ */
+#define DT_INST_GPIO_LABEL_BY_IDX(inst, gpio_pha, idx) \
+	DT_GPIO_LABEL_BY_IDX(DT_DRV_INST(inst), gpio_pha, idx)
+
+/**
+ * @brief Equivalent to DT_INST_GPIO_LABEL_BY_IDX(inst, gpio_pha, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @return the label property of the node referenced at index 0
+ */
+#define DT_INST_GPIO_LABEL(inst, gpio_pha) \
+	DT_INST_GPIO_LABEL_BY_IDX(inst, gpio_pha, 0)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's GPIO specifier's pin cell value
+ *        at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @param idx logical index into "gpio_pha"
+ * @return the pin cell value at index "idx"
+ * @see DT_GPIO_PIN_BY_IDX()
+ */
+#define DT_INST_GPIO_PIN_BY_IDX(inst, gpio_pha, idx) \
+	DT_GPIO_PIN_BY_IDX(DT_DRV_INST(inst), gpio_pha, idx)
+
+/**
+ * @brief Equivalent to DT_INST_GPIO_PIN_BY_IDX(inst, gpio_pha, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @return the pin cell value at index 0
+ * @see DT_INST_GPIO_PIN_BY_IDX()
+ */
+#define DT_INST_GPIO_PIN(inst, gpio_pha) \
+	DT_INST_GPIO_PIN_BY_IDX(inst, gpio_pha, 0)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's GPIO specifier's flags cell
+ *        at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @param idx logical index into "gpio_pha"
+ * @return the flags cell value at index "idx", or zero if there is none
+ * @see DT_GPIO_FLAGS_BY_IDX()
+ */
+#define DT_INST_GPIO_FLAGS_BY_IDX(inst, gpio_pha, idx) \
+	DT_GPIO_FLAGS_BY_IDX(DT_DRV_INST(inst), gpio_pha, idx)
+
+/**
+ * @brief Equivalent to DT_INST_GPIO_FLAGS_BY_IDX(inst, gpio_pha, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param gpio_pha lowercase-and-underscores GPIO property with
+ *        type "phandle-array"
+ * @return the flags cell value at index 0, or zero if there is none
+ * @see DT_INST_GPIO_FLAGS_BY_IDX()
+ */
+#define DT_INST_GPIO_FLAGS(inst, gpio_pha) \
+	DT_INST_GPIO_FLAGS_BY_IDX(inst, gpio_pha, 0)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_GPIO_H_ */
diff --git a/src/include/devicetree/io-channels.h b/src/include/devicetree/io-channels.h
new file mode 100644
index 0000000000..2e93745e6f
--- /dev/null
+++ b/src/include/devicetree/io-channels.h
@@ -0,0 +1,363 @@
+/**
+ * @file
+ * @brief IO channels devicetree macro public API header file.
+ */
+
+/*
+ * Copyright (c) 2020, Linaro Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_IO_CHANNELS_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_IO_CHANNELS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup devicetree-io-channels Devicetree IO Channels API
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get a label property from the node referenced by an
+ *        io-channels property at an index
+ *
+ * It's an error if the node referenced by the phandle in node_id's
+ * io-channels property at index "idx" has no label property.
+ *
+ * Example devicetree fragment:
+ *
+ *     adc1: adc@... {
+ *             label = "ADC_1";
+ *     };
+ *
+ *     adc2: adc@... {
+ *             label = "ADC_2";
+ *     };
+ *
+ *     n: node {
+ *             io-channels = <&adc1 10>, <&adc2 20>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_IO_CHANNELS_LABEL_BY_IDX(DT_NODELABEL(n), 1) // "ADC_2"
+ *
+ * @param node_id node identifier for a node with an io-channels property
+ * @param idx logical index into io-channels property
+ * @return the label property of the node referenced at index "idx"
+ * @see DT_PROP_BY_PHANDLE_IDX()
+ */
+#define DT_IO_CHANNELS_LABEL_BY_IDX(node_id, idx) \
+	__DEPRECATED_MACRO \
+	DT_PROP_BY_PHANDLE_IDX(node_id, io_channels, idx, label)
+
+/**
+ * @brief Get a label property from an io-channels property by name
+ *
+ * It's an error if the node referenced by the phandle in node_id's
+ * io-channels property at the element named "name" has no label
+ * property.
+ *
+ * Example devicetree fragment:
+ *
+ *     adc1: adc@... {
+ *             label = "ADC_1";
+ *     };
+ *
+ *     adc2: adc@... {
+ *             label = "ADC_2";
+ *     };
+ *
+ *     n: node {
+ *             io-channels = <&adc1 10>, <&adc2 20>;
+ *             io-channel-names = "SENSOR", "BANDGAP";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_IO_CHANNELS_LABEL_BY_NAME(DT_NODELABEL(n), bandgap) // "ADC_2"
+ *
+ * @param node_id node identifier for a node with an io-channels property
+ * @param name lowercase-and-underscores name of an io-channels element
+ *             as defined by the node's io-channel-names property
+ * @return the label property of the node referenced at the named element
+ * @see DT_PHANDLE_BY_NAME()
+ */
+#define DT_IO_CHANNELS_LABEL_BY_NAME(node_id, name) \
+	__DEPRECATED_MACRO \
+	DT_PROP(DT_PHANDLE_BY_NAME(node_id, io_channels, name), label)
+
+/**
+ * @brief Equivalent to DT_IO_CHANNELS_LABEL_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with an io-channels property
+ * @return the label property of the node referenced at index 0
+ * @see DT_IO_CHANNELS_LABEL_BY_IDX()
+ */
+#define DT_IO_CHANNELS_LABEL(node_id) \
+	__DEPRECATED_MACRO DT_IO_CHANNELS_LABEL_BY_IDX(node_id, 0)
+
+/**
+ *
+ * @brief Get the node identifier for the node referenced by an
+ *        io-channels property at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     adc1: adc@... { ... };
+ *
+ *     adc2: adc@... { ... };
+ *
+ *     n: node {
+ *             io-channels = <&adc1 10>, <&adc2 20>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_IO_CHANNELS_CTLR_BY_IDX(DT_NODELABEL(n), 0) // DT_NODELABEL(adc1)
+ *     DT_IO_CHANNELS_CTLR_BY_IDX(DT_NODELABEL(n), 1) // DT_NODELABEL(adc2)
+ *
+ * @param node_id node identifier for a node with an io-channels property
+ * @param idx logical index into io-channels property
+ * @return the node identifier for the node referenced at index "idx"
+ * @see DT_PROP_BY_PHANDLE_IDX()
+ */
+#define DT_IO_CHANNELS_CTLR_BY_IDX(node_id, idx) \
+	DT_PHANDLE_BY_IDX(node_id, io_channels, idx)
+
+/**
+ * @brief Get the node identifier for the node referenced by an
+ *        io-channels property by name
+ *
+ * Example devicetree fragment:
+ *
+ *     adc1: adc@... { ... };
+ *
+ *     adc2: adc@... { ... };
+ *
+ *     n: node {
+ *             io-channels = <&adc1 10>, <&adc2 20>;
+ *             io-channel-names = "SENSOR", "BANDGAP";
+ *     };
+ *
+ * Example usage:
+ *
+ *  DT_IO_CHANNELS_CTLR_BY_NAME(DT_NODELABEL(n), sensor) // DT_NODELABEL(adc1)
+ *  DT_IO_CHANNELS_CTLR_BY_NAME(DT_NODELABEL(n), bandgap) // DT_NODELABEL(adc2)
+ *
+ * @param node_id node identifier for a node with an io-channels property
+ * @param name lowercase-and-underscores name of an io-channels element
+ *             as defined by the node's io-channel-names property
+ * @return the node identifier for the node referenced at the named element
+ * @see DT_PHANDLE_BY_NAME()
+ */
+#define DT_IO_CHANNELS_CTLR_BY_NAME(node_id, name) \
+	DT_PHANDLE_BY_NAME(node_id, io_channels, name)
+
+/**
+ * @brief Equivalent to DT_IO_CHANNELS_CTLR_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with an io-channels property
+ * @return the node identifier for the node referenced at index 0
+ *         in the node's "io-channels" property
+ * @see DT_IO_CHANNELS_CTLR_BY_IDX()
+ */
+#define DT_IO_CHANNELS_CTLR(node_id) DT_IO_CHANNELS_CTLR_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's io-channels
+ *        property at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into io-channels property
+ * @return the label property of the node referenced at index "idx"
+ * @see DT_IO_CHANNELS_LABEL_BY_IDX()
+ */
+#define DT_INST_IO_CHANNELS_LABEL_BY_IDX(inst, idx) \
+	__DEPRECATED_MACRO \
+	DT_IO_CHANNELS_LABEL_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's io-channels
+ *        property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of an io-channels element
+ *             as defined by the instance's io-channel-names property
+ * @return the label property of the node referenced at the named element
+ * @see DT_IO_CHANNELS_LABEL_BY_NAME()
+ */
+#define DT_INST_IO_CHANNELS_LABEL_BY_NAME(inst, name) \
+	__DEPRECATED_MACRO \
+	DT_IO_CHANNELS_LABEL_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Equivalent to DT_INST_IO_CHANNELS_LABEL_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the label property of the node referenced at index 0
+ */
+#define DT_INST_IO_CHANNELS_LABEL(inst) \
+	__DEPRECATED_MACRO DT_INST_IO_CHANNELS_LABEL_BY_IDX(inst, 0)
+
+/**
+ * @brief Get the node identifier from a DT_DRV_COMPAT instance's io-channels
+ *        property at an index
+ *
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into io-channels property
+ * @return the node identifier for the node referenced at index "idx"
+ * @see DT_IO_CHANNELS_CTLR_BY_IDX()
+ */
+#define DT_INST_IO_CHANNELS_CTLR_BY_IDX(inst, idx) \
+	DT_IO_CHANNELS_CTLR_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get the node identifier from a DT_DRV_COMPAT instance's io-channels
+ *        property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of an io-channels element
+ *             as defined by the node's io-channel-names property
+ * @return the node identifier for the node referenced at the named element
+ * @see DT_IO_CHANNELS_CTLR_BY_NAME()
+ */
+#define DT_INST_IO_CHANNELS_CTLR_BY_NAME(inst, name) \
+	DT_IO_CHANNELS_CTLR_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Equivalent to DT_INST_IO_CHANNELS_CTLR_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the node identifier for the node referenced at index 0
+ *         in the node's "io-channels" property
+ * @see DT_IO_CHANNELS_CTLR_BY_IDX()
+ */
+#define DT_INST_IO_CHANNELS_CTLR(inst) DT_INST_IO_CHANNELS_CTLR_BY_IDX(inst, 0)
+
+/**
+ * @brief Get an io-channels specifier input cell at an index
+ *
+ * This macro only works for io-channels specifiers with cells named
+ * "input". Refer to the node's binding to check if necessary.
+ *
+ * Example devicetree fragment:
+ *
+ *     adc1: adc@... {
+ *             compatible = "vnd,adc";
+ *             #io-channel-cells = <1>;
+ *     };
+ *
+ *     adc2: adc@... {
+ *             compatible = "vnd,adc";
+ *             #io-channel-cells = <1>;
+ *     };
+ *
+ *     n: node {
+ *             io-channels = <&adc1 10>, <&adc2 20>;
+ *     };
+ *
+ * Bindings fragment for the vnd,adc compatible:
+ *
+ *    io-channel-cells:
+ *      - input
+ *
+ * Example usage:
+ *
+ *     DT_IO_CHANNELS_INPUT_BY_IDX(DT_NODELABEL(n), 0) // 10
+ *     DT_IO_CHANNELS_INPUT_BY_IDX(DT_NODELABEL(n), 1) // 20
+ *
+ * @param node_id node identifier for a node with an io-channels property
+ * @param idx logical index into io-channels property
+ * @return the input cell in the specifier at index "idx"
+ * @see DT_PHA_BY_IDX()
+ */
+#define DT_IO_CHANNELS_INPUT_BY_IDX(node_id, idx) \
+	DT_PHA_BY_IDX(node_id, io_channels, idx, input)
+
+/**
+ * @brief Get an io-channels specifier input cell by name
+ *
+ * This macro only works for io-channels specifiers with cells named
+ * "input". Refer to the node's binding to check if necessary.
+ *
+ * Example devicetree fragment:
+ *
+ *     adc1: adc@... {
+ *             compatible = "vnd,adc";
+ *             #io-channel-cells = <1>;
+ *     };
+ *
+ *     adc2: adc@... {
+ *             compatible = "vnd,adc";
+ *             #io-channel-cells = <1>;
+ *     };
+ *
+ *     n: node {
+ *             io-channels = <&adc1 10>, <&adc2 20>;
+ *             io-channel-names = "SENSOR", "BANDGAP";
+ *     };
+ *
+ * Bindings fragment for the vnd,adc compatible:
+ *
+ *    io-channel-cells:
+ *      - input
+ *
+ * Example usage:
+ *
+ *     DT_IO_CHANNELS_INPUT_BY_NAME(DT_NODELABEL(n), sensor) // 10
+ *     DT_IO_CHANNELS_INPUT_BY_NAME(DT_NODELABEL(n), bandgap) // 20
+ *
+ * @param node_id node identifier for a node with an io-channels property
+ * @param name lowercase-and-underscores name of an io-channels element
+ *             as defined by the node's io-channel-names property
+ * @return the input cell in the specifier at the named element
+ * @see DT_PHA_BY_NAME()
+ */
+#define DT_IO_CHANNELS_INPUT_BY_NAME(node_id, name) \
+	DT_PHA_BY_NAME(node_id, io_channels, name, input)
+/**
+ * @brief Equivalent to DT_IO_CHANNELS_INPUT_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with an io-channels property
+ * @return the input cell in the specifier at index 0
+ * @see DT_IO_CHANNELS_INPUT_BY_IDX()
+ */
+#define DT_IO_CHANNELS_INPUT(node_id) DT_IO_CHANNELS_INPUT_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get an input cell from the "DT_DRV_INST(inst)" io-channels
+ *        property at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into io-channels property
+ * @return the input cell in the specifier at index "idx"
+ * @see DT_IO_CHANNELS_INPUT_BY_IDX()
+ */
+#define DT_INST_IO_CHANNELS_INPUT_BY_IDX(inst, idx) \
+	DT_IO_CHANNELS_INPUT_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get an input cell from the "DT_DRV_INST(inst)" io-channels
+ *        property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of an io-channels element
+ *             as defined by the instance's io-channel-names property
+ * @return the input cell in the specifier at the named element
+ * @see DT_IO_CHANNELS_INPUT_BY_NAME()
+ */
+#define DT_INST_IO_CHANNELS_INPUT_BY_NAME(inst, name) \
+	DT_IO_CHANNELS_INPUT_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Equivalent to DT_INST_IO_CHANNELS_INPUT_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the input cell in the specifier at index 0
+ */
+#define DT_INST_IO_CHANNELS_INPUT(inst) DT_INST_IO_CHANNELS_INPUT_BY_IDX(inst, 0)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_IO_CHANNELS_H_ */
diff --git a/src/include/devicetree/ordinals.h b/src/include/devicetree/ordinals.h
new file mode 100644
index 0000000000..c8b0302d1c
--- /dev/null
+++ b/src/include/devicetree/ordinals.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2020 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_ORDINALS_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_ORDINALS_H_
+
+/**
+ * @file
+ * @brief Devicetree node dependency ordinals
+ */
+
+/**
+ * @defgroup devicetree-dep-ord Dependency tracking
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get a node's dependency ordinal
+ * @param node_id Node identifier
+ * @return the node's dependency ordinal as an integer literal
+ */
+#define DT_DEP_ORD(node_id) DT_CAT(node_id, _ORD)
+
+/**
+ * @brief Get a list of dependency ordinals of a node's direct dependencies
+ *
+ * There is a comma after each ordinal in the expansion, **including**
+ * the last one:
+ *
+ *     DT_REQUIRES_DEP_ORDS(my_node) // required_ord_1, ..., required_ord_n,
+ *
+ * The one case DT_REQUIRES_DEP_ORDS() expands to nothing is when
+ * given the root node identifier @p DT_ROOT as argument. The root has
+ * no direct dependencies; every other node at least depends on its
+ * parent.
+ *
+ * @param node_id Node identifier
+ * @return a list of dependency ordinals, with each ordinal followed
+ *         by a comma (<tt>,</tt>), or an empty expansion
+ */
+#define DT_REQUIRES_DEP_ORDS(node_id) DT_CAT(node_id, _REQUIRES_ORDS)
+
+/**
+ * @brief Get a list of dependency ordinals of what depends directly on a node
+ *
+ * There is a comma after each ordinal in the expansion, **including**
+ * the last one:
+ *
+ *     DT_SUPPORTS_DEP_ORDS(my_node) // supported_ord_1, ..., supported_ord_n,
+ *
+ * DT_SUPPORTS_DEP_ORDS() may expand to nothing. This happens when @p node_id
+ * refers to a leaf node that nothing else depends on.
+ *
+ * @param node_id Node identifier
+ * @return a list of dependency ordinals, with each ordinal followed
+ *         by a comma (<tt>,</tt>), or an empty expansion
+ */
+#define DT_SUPPORTS_DEP_ORDS(node_id) DT_CAT(node_id, _SUPPORTS_ORDS)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's dependency ordinal
+ *
+ * Equivalent to DT_DEP_ORD(DT_DRV_INST(inst)).
+ *
+ * @param inst instance number
+ * @return The instance's dependency ordinal
+ */
+#define DT_INST_DEP_ORD(inst) DT_DEP_ORD(DT_DRV_INST(inst))
+
+/**
+ * @brief Get a list of dependency ordinals of a DT_DRV_COMPAT instance's
+ *        direct dependencies
+ *
+ * Equivalent to DT_REQUIRES_DEP_ORDS(DT_DRV_INST(inst)).
+ *
+ * @param inst instance number
+ * @return a list of dependency ordinals for the nodes the instance depends
+ *         on directly
+ */
+#define DT_INST_REQUIRES_DEP_ORDS(inst) DT_REQUIRES_DEP_ORDS(DT_DRV_INST(inst))
+
+/**
+ * @brief Get a list of dependency ordinals of what depends directly on a
+ *        DT_DRV_COMPAT instance
+ *
+ * Equivalent to DT_SUPPORTS_DEP_ORDS(DT_DRV_INST(inst)).
+ *
+ * @param inst instance number
+ * @return a list of node identifiers for the nodes that depend directly
+ *         on the instance
+ */
+#define DT_INST_SUPPORTS_DEP_ORDS(inst) DT_SUPPORTS_DEP_ORDS(DT_DRV_INST(inst))
+
+/**
+ * @}
+ */
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_ORDINALS_H_ */
diff --git a/src/include/devicetree/pinctrl.h b/src/include/devicetree/pinctrl.h
new file mode 100644
index 0000000000..a5fde6a8fc
--- /dev/null
+++ b/src/include/devicetree/pinctrl.h
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2021 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_PINCTRL_H_
+
+/**
+ * @file
+ * @brief Devicetree pin control helpers
+ */
+
+/**
+ * @defgroup devicetree-pinctrl Pin control
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get a node identifier for a phandle in a pinctrl property by index
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             pinctrl-0 = <&foo &bar>;
+ *             pinctrl-1 = <&baz &blub>;
+ *     }
+ *
+ * Example usage:
+ *
+ *     DT_PINCTRL_BY_IDX(DT_NODELABEL(n), 0, 1) // DT_NODELABEL(bar)
+ *     DT_PINCTRL_BY_IDX(DT_NODELABEL(n), 1, 0) // DT_NODELABEL(baz)
+ *
+ * @param node_id node with a pinctrl-'pc_idx' property
+ * @param pc_idx index of the pinctrl property itself
+ * @param idx index into the value of the pinctrl property
+ * @return node identifier for the phandle at index 'idx' in 'pinctrl-'pc_idx''
+ */
+#define DT_PINCTRL_BY_IDX(node_id, pc_idx, idx) \
+	DT_CAT6(node_id, _P_pinctrl_, pc_idx, _IDX_, idx, _PH)
+
+/**
+ * @brief Get a node identifier from a pinctrl-0 property
+ *
+ * This is equivalent to:
+ *
+ *     DT_PINCTRL_BY_IDX(node_id, 0, idx)
+ *
+ * It is provided for convenience since pinctrl-0 is commonly used.
+ *
+ * @param node_id node with a pinctrl-0 property
+ * @param idx index into the pinctrl-0 property
+ * @return node identifier for the phandle at index idx in the pinctrl-0
+ *         property of that node
+ */
+#define DT_PINCTRL_0(node_id, idx) DT_PINCTRL_BY_IDX(node_id, 0, idx)
+
+/**
+ * @brief Get a node identifier for a phandle inside a pinctrl node by name
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             pinctrl-0 = <&foo &bar>;
+ *             pinctrl-1 = <&baz &blub>;
+ *             pinctrl-names = "default", "sleep";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PINCTRL_BY_NAME(DT_NODELABEL(n), default, 1) // DT_NODELABEL(bar)
+ *     DT_PINCTRL_BY_NAME(DT_NODELABEL(n), sleep, 0) // DT_NODELABEL(baz)
+ *
+ * @param node_id node with a named pinctrl property
+ * @param name lowercase-and-underscores pinctrl property name
+ * @param idx index into the value of the named pinctrl property
+ * @return node identifier for the phandle at that index in the pinctrl
+ *         property
+ */
+#define DT_PINCTRL_BY_NAME(node_id, name, idx) \
+	DT_CAT6(node_id, _PINCTRL_NAME_, name, _IDX_, idx, _PH)
+
+/**
+ * @brief Convert a pinctrl name to its corresponding index
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             pinctrl-0 = <&foo &bar>;
+ *             pinctrl-1 = <&baz &blub>;
+ *             pinctrl-names = "default", "sleep";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PINCTRL_NAME_TO_IDX(DT_NODELABEL(n), default) // 0
+ *     DT_PINCTRL_NAME_TO_IDX(DT_NODELABEL(n), sleep)   // 1
+ *
+ * @param node_id node identifier with a named pinctrl property
+ * @param name lowercase-and-underscores name name of the pinctrl whose index to get
+ * @return integer literal for the index of the pinctrl property with that name
+ */
+#define DT_PINCTRL_NAME_TO_IDX(node_id, name) \
+	DT_CAT4(node_id, _PINCTRL_NAME_, name, _IDX)
+
+/**
+ * @brief Convert a pinctrl property index to its name as a token
+ *
+ * This allows you to get a pinctrl property's name, and "remove the
+ * quotes" from it.
+ *
+ * DT_PINCTRL_IDX_TO_NAME_TOKEN() can only be used if the node has a
+ * pinctrl-'pc_idx' property and a pinctrl-names property element for
+ * that index. It is an error to use it in other circumstances.
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             pinctrl-0 = <...>;
+ *             pinctrl-1 = <...>;
+ *             pinctrl-names = "default", "f.o.o2";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PINCTRL_IDX_TO_NAME_TOKEN(DT_NODELABEL(n), 0) // default
+ *     DT_PINCTRL_IDX_TO_NAME_TOKEN(DT_NODELABEL(n), 1) // f_o_o2
+ *
+ * The same caveats and restrictions that apply to DT_STRING_TOKEN()'s
+ * return value also apply here.
+ *
+ * @param node_id node identifier
+ * @param pc_idx index of a pinctrl property in that node
+ * @return name of the pinctrl property, as a token, without any quotes
+ *         and with non-alphanumeric characters converted to underscores
+ */
+#define DT_PINCTRL_IDX_TO_NAME_TOKEN(node_id, pc_idx) \
+	DT_CAT4(node_id, _PINCTRL_IDX_, pc_idx, _TOKEN)
+
+/**
+ * @brief Like DT_PINCTRL_IDX_TO_NAME_TOKEN(), but with an uppercased result
+ *
+ * This does the a similar conversion as
+ * DT_PINCTRL_IDX_TO_NAME_TOKEN(node_id, pc_idx). The only difference
+ * is that alphabetical characters in the result are uppercased.
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             pinctrl-0 = <...>;
+ *             pinctrl-1 = <...>;
+ *             pinctrl-names = "default", "f.o.o2";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PINCTRL_IDX_TO_NAME_TOKEN(DT_NODELABEL(n), 0) // DEFAULT
+ *     DT_PINCTRL_IDX_TO_NAME_TOKEN(DT_NODELABEL(n), 1) // F_O_O2
+ *
+ * The same caveats and restrictions that apply to
+ * DT_STRING_UPPER_TOKEN()'s return value also apply here.
+ */
+#define DT_PINCTRL_IDX_TO_NAME_UPPER_TOKEN(node_id, pc_idx) \
+	DT_CAT4(node_id, _PINCTRL_IDX_, pc_idx, _UPPER_TOKEN)
+
+/**
+ * @brief Get the number of phandles in a pinctrl property
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             pinctrl-0 = <&foo &bar>;
+ *     };
+ *
+ *     n2: node-2 {
+ *             pinctrl-0 = <&baz>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_NUM_PINCTRLS_BY_IDX(DT_NODELABEL(n1), 0) // 2
+ *     DT_NUM_PINCTRLS_BY_IDX(DT_NODELABEL(n2), 0) // 1
+ *
+ * @param node_id node identifier with a pinctrl property
+ * @param pc_idx index of the pinctrl property itself
+ * @return number of phandles in the property with that index
+ */
+#define DT_NUM_PINCTRLS_BY_IDX(node_id, pc_idx) \
+	DT_CAT4(node_id, _P_pinctrl_, pc_idx, _LEN)
+
+/**
+ * @brief Like DT_NUM_PINCTRLS_BY_IDX(), but by name instead
+ *
+ * Example devicetree fragment:
+ *
+ *     n: node {
+ *             pinctrl-0 = <&foo &bar>;
+ *             pinctrl-1 = <&baz>
+ *             pinctrl-names = "default", "sleep";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_NUM_PINCTRLS_BY_NAME(DT_NODELABEL(n), default) // 2
+ *     DT_NUM_PINCTRLS_BY_NAME(DT_NODELABEL(n), sleep)   // 1
+ *
+ * @param node_id node identifier with a pinctrl property
+ * @param name lowercase-and-underscores name name of the pinctrl property
+ * @return number of phandles in the property with that name
+ */
+#define DT_NUM_PINCTRLS_BY_NAME(node_id, name) \
+	DT_NUM_PINCTRLS_BY_IDX(node_id, DT_PINCTRL_NAME_TO_IDX(node_id, name))
+
+/**
+ * @brief Get the number of pinctrl properties in a node
+ *
+ * This expands to 0 if there are no pinctrl-i properties.
+ * Otherwise, it expands to the number of such properties.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             pinctrl-0 = <...>;
+ *             pinctrl-1 = <...>;
+ *     };
+ *
+ *     n2: node-2 {
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_NUM_PINCTRL_STATES(DT_NODELABEL(n1)) // 2
+ *     DT_NUM_PINCTRL_STATES(DT_NODELABEL(n2)) // 0
+ *
+ * @param node_id node identifier; may or may not have any pinctrl properties
+ * @return number of pinctrl properties in the node
+ */
+#define DT_NUM_PINCTRL_STATES(node_id) DT_CAT(node_id, _PINCTRL_NUM)
+
+/**
+ * @brief Test if a node has a pinctrl property with an index
+ *
+ * This expands to 1 if the pinctrl-'idx' property exists.
+ * Otherwise, it expands to 0.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             pinctrl-0 = <...>;
+ *             pinctrl-1 = <...>;
+ *     };
+ *
+ *     n2: node-2 {
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PINCTRL_HAS_IDX(DT_NODELABEL(n1), 0) // 1
+ *     DT_PINCTRL_HAS_IDX(DT_NODELABEL(n1), 1) // 1
+ *     DT_PINCTRL_HAS_IDX(DT_NODELABEL(n1), 2) // 0
+ *     DT_PINCTRL_HAS_IDX(DT_NODELABEL(n2), 0) // 0
+ *
+ * @param node_id node identifier; may or may not have any pinctrl properties
+ * @param pc_idx index of a pinctrl property whose existence to check
+ * @return 1 if the property exists, 0 otherwise
+ */
+#define DT_PINCTRL_HAS_IDX(node_id, pc_idx) \
+	IS_ENABLED(DT_CAT4(node_id, _PINCTRL_IDX_, pc_idx, _EXISTS))
+
+/**
+ * @brief Test if a node has a pinctrl property with a name
+ *
+ * This expands to 1 if the named pinctrl property exists.
+ * Otherwise, it expands to 0.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             pinctrl-0 = <...>;
+ *             pinctrl-names = "default";
+ *     };
+ *
+ *     n2: node-2 {
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PINCTRL_HAS_NAME(DT_NODELABEL(n1), default) // 1
+ *     DT_PINCTRL_HAS_NAME(DT_NODELABEL(n1), sleep)   // 0
+ *     DT_PINCTRL_HAS_NAME(DT_NODELABEL(n2), default) // 0
+ *
+ * @param node_id node identifier; may or may not have any pinctrl properties
+ * @param name lowercase-and-underscores pinctrl property name to check
+ * @return 1 if the property exists, 0 otherwise
+ */
+#define DT_PINCTRL_HAS_NAME(node_id, name) \
+	IS_ENABLED(DT_CAT4(node_id, _PINCTRL_NAME_, name, _EXISTS))
+
+/**
+ * @brief Get a node identifier for a phandle in a pinctrl property by index
+ *        for a DT_DRV_COMPAT instance
+ *
+ * This is equivalent to DT_PINCTRL_BY_IDX(DT_DRV_INST(inst), pc_idx, idx).
+ *
+ * @param inst instance number
+ * @param pc_idx index of the pinctrl property itself
+ * @param idx index into the value of the pinctrl property
+ * @return node identifier for the phandle at index 'idx' in 'pinctrl-'pc_idx''
+ */
+#define DT_INST_PINCTRL_BY_IDX(inst, pc_idx, idx) \
+	DT_PINCTRL_BY_IDX(DT_DRV_INST(inst), pc_idx, idx)
+
+/**
+ * @brief Get a node identifier from a pinctrl-0 property for a
+ *        DT_DRV_COMPAT instance
+ *
+ * This is equivalent to:
+ *
+ *     DT_PINCTRL_BY_IDX(DT_DRV_INST(inst), 0, idx)
+ *
+ * It is provided for convenience since pinctrl-0 is commonly used.
+ *
+ * @param inst instance number
+ * @param idx index into the pinctrl-0 property
+ * @return node identifier for the phandle at index idx in the pinctrl-0
+ *         property of that instance
+ */
+#define DT_INST_PINCTRL_0(inst, idx) \
+	DT_PINCTRL_BY_IDX(DT_DRV_INST(inst), 0, idx)
+
+/**
+ * @brief Get a node identifier for a phandle inside a pinctrl node
+ *        for a DT_DRV_COMPAT instance
+ *
+ * This is equivalent to DT_PINCTRL_BY_NAME(DT_DRV_INST(inst), name, idx).
+ *
+ * @param inst instance number
+ * @param name lowercase-and-underscores pinctrl property name
+ * @param idx index into the value of the named pinctrl property
+ * @return node identifier for the phandle at that index in the pinctrl
+ *         property
+ */
+#define DT_INST_PINCTRL_BY_NAME(inst, name, idx) \
+	DT_PINCTRL_BY_NAME(DT_DRV_INST(inst), name, idx)
+
+/**
+ * @brief Convert a pinctrl name to its corresponding index
+ *        for a DT_DRV_COMPAT instance
+ *
+ * This is equivalent to DT_PINCTRL_NAME_TO_IDX(DT_DRV_INST(inst),
+ * name).
+ *
+ * @param inst instance number
+ * @param name lowercase-and-underscores name of the pinctrl whose index to get
+ * @return integer literal for the index of the pinctrl property with that name
+ */
+#define DT_INST_PINCTRL_NAME_TO_IDX(inst, name) \
+	DT_PINCTRL_NAME_TO_IDX(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Convert a pinctrl index to its name as an uppercased token
+ *
+ * This is equivalent to
+ * DT_PINCTRL_IDX_TO_NAME_TOKEN(DT_DRV_INST(inst), pc_idx).
+ *
+ * @param inst instance number
+ * @param pc_idx index of the pinctrl property itself
+ * @return name of the pin control property as a token
+ */
+#define DT_INST_PINCTRL_IDX_TO_NAME_TOKEN(inst, pc_idx) \
+	DT_PINCTRL_IDX_TO_NAME_TOKEN(DT_DRV_INST(inst), pc_idx)
+
+/**
+ * @brief Convert a pinctrl index to its name as an uppercased token
+ *
+ * This is equivalent to
+ * DT_PINCTRL_IDX_TO_NAME_UPPER_TOKEN(DT_DRV_INST(inst), idx).
+ *
+ * @param inst instance number
+ * @param pc_idx index of the pinctrl property itself
+ * @return name of the pin control property as an uppercase token
+ */
+#define DT_INST_PINCTRL_IDX_TO_NAME_UPPER_TOKEN(inst, pc_idx) \
+	DT_PINCTRL_IDX_TO_NAME_UPPER_TOKEN(DT_DRV_INST(inst), pc_idx)
+
+/**
+ * @brief Get the number of phandles in a pinctrl property
+ *        for a DT_DRV_COMPAT instance
+ *
+ * This is equivalent to DT_NUM_PINCTRLS_BY_IDX(DT_DRV_INST(inst),
+ * pc_idx).
+ *
+ * @param inst instance number
+ * @param pc_idx index of the pinctrl property itself
+ * @return number of phandles in the property with that index
+ */
+#define DT_INST_NUM_PINCTRLS_BY_IDX(inst, pc_idx) \
+	DT_NUM_PINCTRLS_BY_IDX(DT_DRV_INST(inst), pc_idx)
+
+/**
+ * @brief Like DT_INST_NUM_PINCTRLS_BY_IDX(), but by name instead
+ *
+ * This is equivalent to DT_NUM_PINCTRLS_BY_NAME(DT_DRV_INST(inst),
+ * name).
+ *
+ * @param inst instance number
+ * @param name lowercase-and-underscores name of the pinctrl property
+ * @return number of phandles in the property with that name
+ */
+#define DT_INST_NUM_PINCTRLS_BY_NAME(inst, name) \
+	DT_NUM_PINCTRLS_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Get the number of pinctrl properties in a DT_DRV_COMPAT instance
+ *
+ * This is equivalent to DT_NUM_PINCTRL_STATES(DT_DRV_INST(inst)).
+ *
+ * @param inst instance number
+ * @return number of pinctrl properties in the instance
+ */
+#define DT_INST_NUM_PINCTRL_STATES(inst) \
+	DT_NUM_PINCTRL_STATES(DT_DRV_INST(inst))
+
+/**
+ * @brief Test if a DT_DRV_COMPAT instance has a pinctrl property
+ *        with an index
+ *
+ * This is equivalent to DT_PINCTRL_HAS_IDX(DT_DRV_INST(inst), pc_idx).
+ *
+ * @param inst instance number
+ * @param pc_idx index of a pinctrl property whose existence to check
+ * @return 1 if the property exists, 0 otherwise
+ */
+#define DT_INST_PINCTRL_HAS_IDX(inst, pc_idx) \
+	DT_PINCTRL_HAS_IDX(DT_DRV_INST(inst), pc_idx)
+
+/**
+ * @brief Test if a DT_DRV_COMPAT instance has a pinctrl property with a name
+ *
+ * This is equivalent to DT_PINCTRL_HAS_NAME(DT_DRV_INST(inst), name).
+ *
+ * @param inst instance number
+ * @param name lowercase-and-underscores pinctrl property name to check
+ * @return 1 if the property exists, 0 otherwise
+ */
+#define DT_INST_PINCTRL_HAS_NAME(inst, name) \
+	DT_PINCTRL_HAS_NAME(DT_DRV_INST(inst), name)
+
+
+/**
+ * @}
+ */
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_PINCTRL_H_ */
diff --git a/src/include/devicetree/pwms.h b/src/include/devicetree/pwms.h
new file mode 100644
index 0000000000..04a9325fde
--- /dev/null
+++ b/src/include/devicetree/pwms.h
@@ -0,0 +1,601 @@
+/**
+ * @file
+ * @brief PWMs Devicetree macro public API header file.
+ */
+
+/*
+ * Copyright (c) 2020, Linaro Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_PWMS_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_PWMS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup devicetree-pwms Devicetree PWMs API
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Get a label property from a pwms property at an index
+ *
+ * It's an error if the PWM controller node referenced by the phandle
+ * in node_id's pwms property at index "idx" has no label property.
+ *
+ * Example devicetree fragment:
+ *
+ *     pwm1: pwm-controller@... {
+ *             label = "PWM_1";
+ *     };
+ *
+ *     pwm2: pwm-controller@... {
+ *             label = "PWM_2";
+ *     };
+ *
+ *     n: node {
+ *             pwms = <&pwm1 1 PWM_POLARITY_NORMAL>,
+ *                    <&pwm2 3 PWM_POLARITY_INVERTED>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PWMS_LABEL_BY_IDX(DT_NODELABEL(n), 0) // "PWM_1"
+ *     DT_PWMS_LABEL_BY_IDX(DT_NODELABEL(n), 1) // "PWM_2"
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param idx logical index into pwms property
+ * @return the label property of the node referenced at index "idx"
+ * @see DT_PROP_BY_PHANDLE_IDX()
+ */
+#define DT_PWMS_LABEL_BY_IDX(node_id, idx) \
+	__DEPRECATED_MACRO \
+	DT_PROP_BY_PHANDLE_IDX(node_id, pwms, idx, label)
+
+/**
+ * @brief Get a label property from a pwms property by name
+ *
+ * It's an error if the PWM controller node referenced by the
+ * phandle in node_id's pwms property at the element named "name"
+ * has no label property.
+ *
+ * Example devicetree fragment:
+ *
+ *     pwm1: pwm-controller@... {
+ *             label = "PWM_1";
+ *     };
+ *
+ *     pwm2: pwm-controller@... {
+ *             label = "PWM_2";
+ *     };
+ *
+ *     n: node {
+ *             pwms = <&pwm1 1 PWM_POLARITY_NORMAL>,
+ *                    <&pwm2 3 PWM_POLARITY_INVERTED>;
+ *             pwm-names = "alpha", "beta";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PWMS_LABEL_BY_NAME(DT_NODELABEL(n), alpha) // "PWM_1"
+ *     DT_PWMS_LABEL_BY_NAME(DT_NODELABEL(n), beta)  // "PWM_2"
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the label property of the node referenced at the named element
+ * @see DT_PHANDLE_BY_NAME()
+ */
+#define DT_PWMS_LABEL_BY_NAME(node_id, name) \
+	__DEPRECATED_MACRO \
+	DT_PROP(DT_PHANDLE_BY_NAME(node_id, pwms, name), label)
+
+/**
+ * @brief Equivalent to DT_PWMS_LABEL_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with a pwms property
+ * @return the label property of the node referenced at index 0
+ * @see DT_PWMS_LABEL_BY_IDX()
+ */
+#define DT_PWMS_LABEL(node_id) __DEPRECATED_MACRO DT_PWMS_LABEL_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get the node identifier for the PWM controller from a
+ *        pwms property at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     pwm1: pwm-controller@... { ... };
+ *
+ *     pwm2: pwm-controller@... { ... };
+ *
+ *     n: node {
+ *             pwms = <&pwm1 1 PWM_POLARITY_NORMAL>,
+ *                    <&pwm2 3 PWM_POLARITY_INVERTED>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PWMS_CTLR_BY_IDX(DT_NODELABEL(n), 0) // DT_NODELABEL(pwm1)
+ *     DT_PWMS_CTLR_BY_IDX(DT_NODELABEL(n), 1) // DT_NODELABEL(pwm2)
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param idx logical index into pwms property
+ * @return the node identifier for the PWM controller referenced at
+ *         index "idx"
+ * @see DT_PROP_BY_PHANDLE_IDX()
+ */
+#define DT_PWMS_CTLR_BY_IDX(node_id, idx) \
+	DT_PHANDLE_BY_IDX(node_id, pwms, idx)
+
+/**
+ * @brief Get the node identifier for the PWM controller from a
+ *        pwms property by name
+ *
+ * Example devicetree fragment:
+ *
+ *     pwm1: pwm-controller@... { ... };
+ *
+ *    pwm2: pwm-controller@... { ... };
+ *
+ *     n: node {
+ *             pwms = <&pwm1 1 PWM_POLARITY_NORMAL>,
+ *                    <&pwm2 3 PWM_POLARITY_INVERTED>;
+ *             pwm-names = "alpha", "beta";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_PWMS_CTLR_BY_NAME(DT_NODELABEL(n), alpha) // DT_NODELABEL(pwm1)
+ *     DT_PWMS_CTLR_BY_NAME(DT_NODELABEL(n), beta)  // DT_NODELABEL(pwm2)
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the node identifier for the PWM controller in the named element
+ * @see DT_PHANDLE_BY_NAME()
+ */
+#define DT_PWMS_CTLR_BY_NAME(node_id, name) \
+	DT_PHANDLE_BY_NAME(node_id, pwms, name)
+
+/**
+ * @brief Equivalent to DT_PWMS_CTLR_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with a pwms property
+ * @return the node identifier for the PWM controller at index 0
+ *         in the node's "pwms" property
+ * @see DT_PWMS_CTLR_BY_IDX()
+ */
+#define DT_PWMS_CTLR(node_id) DT_PWMS_CTLR_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get PWM specifier's cell value at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     pwm1: pwm-controller@... {
+ *             compatible = "vnd,pwm";
+ *             label = "PWM_1";
+ *             #pwm-cells = <2>;
+ *     };
+ *
+ *     pwm2: pwm-controller@... {
+ *             compatible = "vnd,pwm";
+ *             label = "PWM_2";
+ *             #pwm-cells = <2>;
+ *     };
+ *
+ *     n: node {
+ *             pwms = <&pwm1 1 200000 PWM_POLARITY_NORMAL>,
+ *                    <&pwm2 3 100000 PWM_POLARITY_INVERTED>;
+ *     };
+ *
+ * Bindings fragment for the "vnd,pwm" compatible:
+ *
+ *     pwm-cells:
+ *       - channel
+ *       - period
+ *       - flags
+ *
+ * Example usage:
+ *
+ *     DT_PWMS_CELL_BY_IDX(DT_NODELABEL(n), 0, channel) // 1
+ *     DT_PWMS_CELL_BY_IDX(DT_NODELABEL(n), 1, channel) // 3
+ *     DT_PWMS_CELL_BY_IDX(DT_NODELABEL(n), 0, period)  // 200000
+ *     DT_PWMS_CELL_BY_IDX(DT_NODELABEL(n), 1, period)  // 100000
+ *     DT_PWMS_CELL_BY_IDX(DT_NODELABEL(n), 0, flags)   // PWM_POLARITY_NORMAL
+ *     DT_PWMS_CELL_BY_IDX(DT_NODELABEL(n), 1, flags)   // PWM_POLARITY_INVERTED
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param idx logical index into pwms property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index "idx"
+ * @see DT_PHA_BY_IDX()
+ */
+#define DT_PWMS_CELL_BY_IDX(node_id, idx, cell) \
+	DT_PHA_BY_IDX(node_id, pwms, idx, cell)
+
+/**
+ * @brief Get a PWM specifier's cell value by name
+ *
+ * Example devicetree fragment:
+ *
+ *     pwm1: pwm-controller@... {
+ *             compatible = "vnd,pwm";
+ *             label = "PWM_1";
+ *             #pwm-cells = <2>;
+ *     };
+ *
+ *     pwm2: pwm-controller@... {
+ *             compatible = "vnd,pwm";
+ *             label = "PWM_2";
+ *             #pwm-cells = <2>;
+ *     };
+ *
+ *     n: node {
+ *             pwms = <&pwm1 1 200000 PWM_POLARITY_NORMAL>,
+ *                    <&pwm2 3 100000 PWM_POLARITY_INVERTED>;
+ *             pwm-names = "alpha", "beta";
+ *     };
+ *
+ * Bindings fragment for the "vnd,pwm" compatible:
+ *
+ *     pwm-cells:
+ *       - channel
+ *       - period
+ *       - flags
+ *
+ * Example usage:
+ *
+ *     DT_PWMS_CELL_BY_NAME(DT_NODELABEL(n), alpha, channel) // 1
+ *     DT_PWMS_CELL_BY_NAME(DT_NODELABEL(n), beta, channel)  // 3
+ *     DT_PWMS_CELL_BY_NAME(DT_NODELABEL(n), alpha, period)  // 200000
+ *     DT_PWMS_CELL_BY_NAME(DT_NODELABEL(n), beta, period)   // 100000
+ *     DT_PWMS_CELL_BY_NAME(DT_NODELABEL(n), alpha, flags)   // PWM_POLARITY_NORMAL
+ *     DT_PWMS_CELL_BY_NAME(DT_NODELABEL(n), beta, flags)    // PWM_POLARITY_INVERTED
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value in the specifier at the named element
+ * @see DT_PHA_BY_NAME()
+ */
+#define DT_PWMS_CELL_BY_NAME(node_id, name, cell) \
+	DT_PHA_BY_NAME(node_id, pwms, name, cell)
+
+/**
+ * @brief Equivalent to DT_PWMS_CELL_BY_IDX(node_id, 0, cell)
+ * @param node_id node identifier for a node with a pwms property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index 0
+ * @see DT_PWMS_CELL_BY_IDX()
+ */
+#define DT_PWMS_CELL(node_id, cell) DT_PWMS_CELL_BY_IDX(node_id, 0, cell)
+
+/**
+ * @brief Get a PWM specifier's channel cell value at an index
+ *
+ * This macro only works for PWM specifiers with cells named "channel".
+ * Refer to the node's binding to check if necessary.
+ *
+ * This is equivalent to DT_PWMS_CELL_BY_IDX(node_id, idx, channel).
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param idx logical index into pwms property
+ * @return the channel cell value at index "idx"
+ * @see DT_PWMS_CELL_BY_IDX()
+ */
+#define DT_PWMS_CHANNEL_BY_IDX(node_id, idx) \
+	DT_PWMS_CELL_BY_IDX(node_id, idx, channel)
+
+/**
+ * @brief Get a PWM specifier's channel cell value by name
+ *
+ * This macro only works for PWM specifiers with cells named "channel".
+ * Refer to the node's binding to check if necessary.
+ *
+ * This is equivalent to DT_PWMS_CELL_BY_NAME(node_id, name, channel).
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the channel cell value in the specifier at the named element
+ * @see DT_PWMS_CELL_BY_NAME()
+ */
+#define DT_PWMS_CHANNEL_BY_NAME(node_id, name) \
+	DT_PWMS_CELL_BY_NAME(node_id, name, channel)
+
+/**
+ * @brief Equivalent to DT_PWMS_CHANNEL_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with a pwms property
+ * @return the channel cell value at index 0
+ * @see DT_PWMS_CHANNEL_BY_IDX()
+ */
+#define DT_PWMS_CHANNEL(node_id) DT_PWMS_CHANNEL_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get PWM specifier's period cell value at an index
+ *
+ * This macro only works for PWM specifiers with cells named "period".
+ * Refer to the node's binding to check if necessary.
+ *
+ * This is equivalent to DT_PWMS_CELL_BY_IDX(node_id, idx, period).
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param idx logical index into pwms property
+ * @return the period cell value at index "idx"
+ * @see DT_PWMS_CELL_BY_IDX()
+ */
+#define DT_PWMS_PERIOD_BY_IDX(node_id, idx) \
+	DT_PWMS_CELL_BY_IDX(node_id, idx, period)
+
+/**
+ * @brief Get a PWM specifier's period cell value by name
+ *
+ * This macro only works for PWM specifiers with cells named "period".
+ * Refer to the node's binding to check if necessary.
+ *
+ * This is equivalent to DT_PWMS_CELL_BY_NAME(node_id, name, period).
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the period cell value in the specifier at the named element
+ * @see DT_PWMS_CELL_BY_NAME()
+ */
+#define DT_PWMS_PERIOD_BY_NAME(node_id, name) \
+	DT_PWMS_CELL_BY_NAME(node_id, name, period)
+
+/**
+ * @brief Equivalent to DT_PWMS_PERIOD_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with a pwms property
+ * @return the period cell value at index 0
+ * @see DT_PWMS_PERIOD_BY_IDX()
+ */
+#define DT_PWMS_PERIOD(node_id) DT_PWMS_PERIOD_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get a PWM specifier's flags cell value at an index
+ *
+ * This macro expects PWM specifiers with cells named "flags".
+ * If there is no "flags" cell in the PWM specifier, zero is returned.
+ * Refer to the node's binding to check specifier cell names if necessary.
+ *
+ * This is equivalent to DT_PWMS_CELL_BY_IDX(node_id, idx, flags).
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param idx logical index into pwms property
+ * @return the flags cell value at index "idx", or zero if there is none
+ * @see DT_PWMS_CELL_BY_IDX()
+ */
+#define DT_PWMS_FLAGS_BY_IDX(node_id, idx) \
+	DT_PHA_BY_IDX_OR(node_id, pwms, idx, flags, 0)
+
+/**
+ * @brief Get a PWM specifier's flags cell value by name
+ *
+ * This macro expects PWM specifiers with cells named "flags".
+ * If there is no "flags" cell in the PWM specifier, zero is returned.
+ * Refer to the node's binding to check specifier cell names if necessary.
+ *
+ * This is equivalent to DT_PWMS_CELL_BY_NAME(node_id, name, flags) if
+ * there is a flags cell, but expands to zero if there is none.
+ *
+ * @param node_id node identifier for a node with a pwms property
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the flags cell value in the specifier at the named element,
+ *         or zero if there is none
+ * @see DT_PWMS_CELL_BY_NAME()
+ */
+#define DT_PWMS_FLAGS_BY_NAME(node_id, name) \
+	DT_PHA_BY_NAME_OR(node_id, pwms, name, flags, 0)
+
+/**
+ * @brief Equivalent to DT_PWMS_FLAGS_BY_IDX(node_id, 0)
+ * @param node_id node identifier for a node with a pwms property
+ * @return the flags cell value at index 0, or zero if there is none
+ * @see DT_PWMS_FLAGS_BY_IDX()
+ */
+#define DT_PWMS_FLAGS(node_id) DT_PWMS_FLAGS_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's pwms
+ *        property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into pwms property
+ * @return the label property of the node referenced at index "idx"
+ * @see DT_PWMS_LABEL_BY_IDX()
+ */
+#define DT_INST_PWMS_LABEL_BY_IDX(inst, idx) \
+	__DEPRECATED_MACRO \
+	DT_PWMS_LABEL_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get a label property from a DT_DRV_COMPAT instance's pwms
+ *        property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the label property of the node referenced at the named element
+ * @see DT_PWMS_LABEL_BY_NAME()
+ */
+#define DT_INST_PWMS_LABEL_BY_NAME(inst, name) \
+	__DEPRECATED_MACRO \
+	DT_PWMS_LABEL_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_LABEL_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the label property of the node referenced at index 0
+ * @see DT_PWMS_LABEL_BY_IDX()
+ */
+#define DT_INST_PWMS_LABEL(inst) __DEPRECATED_MACRO DT_INST_PWMS_LABEL_BY_IDX(inst, 0)
+
+/**
+ * @brief Get the node identifier for the PWM controller from a
+ *        DT_DRV_COMPAT instance's pwms property at an index
+ *
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into pwms property
+ * @return the node identifier for the PWM controller referenced at
+ *         index "idx"
+ * @see DT_PWMS_CTLR_BY_IDX()
+ */
+#define DT_INST_PWMS_CTLR_BY_IDX(inst, idx) \
+	DT_PWMS_CTLR_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Get the node identifier for the PWM controller from a
+ *        DT_DRV_COMPAT instance's pwms property by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the node identifier for the PWM controller in the named element
+ * @see DT_PWMS_CTLR_BY_NAME()
+ */
+#define DT_INST_PWMS_CTLR_BY_NAME(inst, name) \
+	DT_PWMS_CTLR_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CTLR_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the node identifier for the PWM controller at index 0
+ *         in the instance's "pwms" property
+ * @see DT_PWMS_CTLR_BY_IDX()
+ */
+#define DT_INST_PWMS_CTLR(inst) DT_INST_PWMS_CTLR_BY_IDX(inst, 0)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's PWM specifier's cell value
+ *        at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into pwms property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index "idx"
+ */
+#define DT_INST_PWMS_CELL_BY_IDX(inst, idx, cell) \
+	DT_PWMS_CELL_BY_IDX(DT_DRV_INST(inst), idx, cell)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's PWM specifier's cell value by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value in the specifier at the named element
+ * @see DT_PWMS_CELL_BY_NAME()
+ */
+#define DT_INST_PWMS_CELL_BY_NAME(inst, name, cell) \
+	DT_PWMS_CELL_BY_NAME(DT_DRV_INST(inst), name, cell)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CELL_BY_IDX(inst, 0, cell)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index 0
+ */
+#define DT_INST_PWMS_CELL(inst, cell) \
+	DT_INST_PWMS_CELL_BY_IDX(inst, 0, cell)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CELL_BY_IDX(inst, idx, channel)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into pwms property
+ * @return the channel cell value at index "idx"
+ * @see DT_INST_PWMS_CELL_BY_IDX()
+ */
+#define DT_INST_PWMS_CHANNEL_BY_IDX(inst, idx) \
+	DT_INST_PWMS_CELL_BY_IDX(inst, idx, channel)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CELL_BY_NAME(inst, name, channel)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the channel cell value in the specifier at the named element
+ * @see DT_INST_PWMS_CELL_BY_NAME()
+ */
+#define DT_INST_PWMS_CHANNEL_BY_NAME(inst, name) \
+	DT_INST_PWMS_CELL_BY_NAME(inst, name, channel)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CHANNEL_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the channel cell value at index 0
+ * @see DT_INST_PWMS_CHANNEL_BY_IDX()
+ */
+#define DT_INST_PWMS_CHANNEL(inst) DT_INST_PWMS_CHANNEL_BY_IDX(inst, 0)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CELL_BY_IDX(inst, idx, period)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into pwms property
+ * @return the period cell value at index "idx"
+ * @see DT_INST_PWMS_CELL_BY_IDX()
+ */
+#define DT_INST_PWMS_PERIOD_BY_IDX(inst, idx) \
+	DT_INST_PWMS_CELL_BY_IDX(inst, idx, period)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CELL_BY_NAME(inst, name, period)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the period cell value in the specifier at the named element
+ * @see DT_INST_PWMS_CELL_BY_NAME()
+ */
+#define DT_INST_PWMS_PERIOD_BY_NAME(inst, name) \
+	DT_INST_PWMS_CELL_BY_NAME(inst, name, period)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_PERIOD_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the period cell value at index 0
+ * @see DT_INST_PWMS_PERIOD_BY_IDX()
+ */
+#define DT_INST_PWMS_PERIOD(inst) DT_INST_PWMS_PERIOD_BY_IDX(inst, 0)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CELL_BY_IDX(inst, idx, flags)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into pwms property
+ * @return the flags cell value at index "idx", or zero if there is none
+ * @see DT_INST_PWMS_CELL_BY_IDX()
+ */
+#define DT_INST_PWMS_FLAGS_BY_IDX(inst, idx) \
+	DT_INST_PWMS_CELL_BY_IDX(inst, idx, flags)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_CELL_BY_NAME(inst, name, flags)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a pwms element
+ *             as defined by the node's pwm-names property
+ * @return the flags cell value in the specifier at the named element,
+ *         or zero if there is none
+ * @see DT_INST_PWMS_CELL_BY_NAME()
+ */
+#define DT_INST_PWMS_FLAGS_BY_NAME(inst, name) \
+	DT_INST_PWMS_CELL_BY_NAME(inst, name, flags)
+
+/**
+ * @brief Equivalent to DT_INST_PWMS_FLAGS_BY_IDX(inst, 0)
+ * @param inst DT_DRV_COMPAT instance number
+ * @return the flags cell value at index 0, or zero if there is none
+ * @see DT_INST_PWMS_FLAGS_BY_IDX()
+ */
+#define DT_INST_PWMS_FLAGS(inst) DT_INST_PWMS_FLAGS_BY_IDX(inst, 0)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_PWMS_H_ */
diff --git a/src/include/devicetree/spi.h b/src/include/devicetree/spi.h
new file mode 100644
index 0000000000..33bc0f8c8e
--- /dev/null
+++ b/src/include/devicetree/spi.h
@@ -0,0 +1,349 @@
+/**
+ * @file
+ * @brief SPI Devicetree macro public API header file.
+ */
+
+/*
+ * Copyright (c) 2020 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_SPI_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_SPI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup devicetree-spi Devicetree SPI API
+ * @ingroup devicetree
+ * @{
+ */
+
+/**
+ * @brief Does a SPI controller node have chip select GPIOs configured?
+ *
+ * SPI bus controllers use the "cs-gpios" property for configuring
+ * chip select GPIOs. Its value is a phandle-array which specifies the
+ * chip select lines.
+ *
+ * Example devicetree fragment:
+ *
+ *     spi1: spi@... {
+ *             compatible = "vnd,spi";
+ *             cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                        <&gpio2 20 GPIO_ACTIVE_LOW>;
+ *     };
+ *
+ *     spi2: spi@... {
+ *             compatible = "vnd,spi";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_SPI_HAS_CS_GPIOS(DT_NODELABEL(spi1)) // 1
+ *     DT_SPI_HAS_CS_GPIOS(DT_NODELABEL(spi2)) // 0
+ *
+ * @param spi a SPI bus controller node identifier
+ * @return 1 if "spi" has a cs-gpios property, 0 otherwise
+ */
+#define DT_SPI_HAS_CS_GPIOS(spi) DT_NODE_HAS_PROP(spi, cs_gpios)
+
+/**
+ * @brief Number of chip select GPIOs in a SPI controller's cs-gpios property
+ *
+ * Example devicetree fragment:
+ *
+ *     spi1: spi@... {
+ *             compatible = "vnd,spi";
+ *             cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                        <&gpio2 20 GPIO_ACTIVE_LOW>;
+ *     };
+ *
+ *     spi2: spi@... {
+ *             compatible = "vnd,spi";
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_SPI_NUM_CS_GPIOS(DT_NODELABEL(spi1)) // 2
+ *     DT_SPI_NUM_CS_GPIOS(DT_NODELABEL(spi2)) // 0
+ *
+ * @param spi a SPI bus controller node identifier
+ * @return Logical length of spi's cs-gpios property, or 0 if "spi" doesn't
+ *         have a cs-gpios property
+ */
+#define DT_SPI_NUM_CS_GPIOS(spi) \
+	COND_CODE_1(DT_SPI_HAS_CS_GPIOS(spi), \
+		    (DT_PROP_LEN(spi, cs_gpios)), (0))
+
+/**
+ * @brief Does a SPI device have a chip select line configured?
+ * Example devicetree fragment:
+ *
+ *     spi1: spi@... {
+ *             compatible = "vnd,spi";
+ *             cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                        <&gpio2 20 GPIO_ACTIVE_LOW>;
+ *
+ *             a: spi-dev-a@0 {
+ *                     reg = <0>;
+ *             };
+ *
+ *             b: spi-dev-b@1 {
+ *                     reg = <1>;
+ *             };
+ *     };
+ *
+ *     spi2: spi@... {
+ *             compatible = "vnd,spi";
+ *             c: spi-dev-c@0 {
+ *                     reg = <0>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_SPI_DEV_HAS_CS_GPIOS(DT_NODELABEL(a)) // 1
+ *     DT_SPI_DEV_HAS_CS_GPIOS(DT_NODELABEL(b)) // 1
+ *     DT_SPI_DEV_HAS_CS_GPIOS(DT_NODELABEL(c)) // 0
+ *
+ * @param spi_dev a SPI device node identifier
+ * @return 1 if spi_dev's bus node DT_BUS(spi_dev) has a chip select
+ *         pin at index DT_REG_ADDR(spi_dev), 0 otherwise
+ */
+#define DT_SPI_DEV_HAS_CS_GPIOS(spi_dev) DT_SPI_HAS_CS_GPIOS(DT_BUS(spi_dev))
+
+/**
+ * @brief Get a SPI device's chip select devicetree specification
+ *
+ * Example devicetree fragment:
+ *
+ * @code{.devicetree}
+ *     gpio1: gpio@... { ... };
+ *
+ *     gpio2: gpio@... { ... };
+ *
+ *     spi@... {
+ *             compatible = "vnd,spi";
+ *             cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                        <&gpio2 20 GPIO_ACTIVE_LOW>;
+ *
+ *             a: spi-dev-a@0 {
+ *                     reg = <0>;
+ *             };
+ *
+ *             b: spi-dev-b@1 {
+ *                     reg = <1>;
+ *             };
+ *     };
+ * @endcode
+ *
+ * Example usage:
+ *
+ * @code{.c}
+ *     DT_SPI_DEV_CS_GPIOS_DT_SPEC_GET(DT_NODELABEL(a)) \
+ *           // { DEVICE_DT_GET(DT_NODELABEL(gpio1)), 10, GPIO_ACTIVE_LOW }
+ *     DT_SPI_DEV_CS_GPIOS_DT_SPEC_GET(DT_NODELABEL(b)) \
+ *           // { DEVICE_DT_GET(DT_NODELABEL(gpio2)), 20, GPIO_ACTIVE_LOW }
+ * @endcode
+ *
+ * @param spi_dev a SPI device node identifier
+ * @return #gpio_dt_spec struct corresponding with spi_dev's chip select
+ */
+#define DT_SPI_DEV_CS_GPIOS_DT_SPEC_GET(spi_dev) \
+	GPIO_DT_SPEC_GET_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev))
+
+/**
+ * @brief Get a SPI device's chip select GPIO controller's node identifier
+ *
+ * Example devicetree fragment:
+ *
+ *     gpio1: gpio@... { ... };
+ *
+ *     gpio2: gpio@... { ... };
+ *
+ *     spi@... {
+ *             compatible = "vnd,spi";
+ *             cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                        <&gpio2 20 GPIO_ACTIVE_LOW>;
+ *
+ *             a: spi-dev-a@0 {
+ *                     reg = <0>;
+ *             };
+ *
+ *             b: spi-dev-b@1 {
+ *                     reg = <1>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_SPI_DEV_CS_GPIOS_CTLR(DT_NODELABEL(a)) // DT_NODELABEL(gpio1)
+ *     DT_SPI_DEV_CS_GPIOS_CTLR(DT_NODELABEL(b)) // DT_NODELABEL(gpio2)
+ *
+ * @param spi_dev a SPI device node identifier
+ * @return node identifier for spi_dev's chip select GPIO controller
+ */
+#define DT_SPI_DEV_CS_GPIOS_CTLR(spi_dev) \
+	DT_GPIO_CTLR_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev))
+
+/**
+ * @brief Get a SPI device's chip select GPIO controller's label property
+ *
+ * Example devicetree fragment:
+ *
+ *     gpio1: gpio@... {
+ *             label = "GPIO_1";
+ *     };
+ *
+ *     gpio2: gpio@... {
+ *             label = "GPIO_2";
+ *     };
+ *
+ *     spi1: spi@... {
+ *             compatible = "vnd,spi";
+ *             cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                        <&gpio2 20 GPIO_ACTIVE_LOW>;
+ *
+ *             a: spi-dev-a@0 {
+ *                     reg = <0>;
+ *             };
+ *
+ *             b: spi-dev-b@1 {
+ *                     reg = <1>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_SPI_DEV_CS_GPIOS_LABEL(DT_NODELABEL(a)) // "GPIO_1"
+ *     DT_SPI_DEV_CS_GPIOS_LABEL(DT_NODELABEL(b)) // "GPIO_2"
+ *
+ * @param spi_dev a SPI device node identifier
+ * @return label property of spi_dev's chip select GPIO controller
+ */
+#define DT_SPI_DEV_CS_GPIOS_LABEL(spi_dev) \
+	DT_GPIO_LABEL_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev))
+
+/**
+ * @brief Get a SPI device's chip select GPIO pin number
+ *
+ * It's an error if the GPIO specifier for spi_dev's entry in its
+ * bus node's cs-gpios property has no pin cell.
+ *
+ * Example devicetree fragment:
+ *
+ *     spi1: spi@... {
+ *             compatible = "vnd,spi";
+ *             cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
+ *                        <&gpio2 20 GPIO_ACTIVE_LOW>;
+ *
+ *             a: spi-dev-a@0 {
+ *                     reg = <0>;
+ *             };
+ *
+ *             b: spi-dev-b@1 {
+ *                     reg = <1>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_SPI_DEV_CS_GPIOS_PIN(DT_NODELABEL(a)) // 10
+ *     DT_SPI_DEV_CS_GPIOS_PIN(DT_NODELABEL(b)) // 20
+ *
+ * @param spi_dev a SPI device node identifier
+ * @return pin number of spi_dev's chip select GPIO
+ */
+#define DT_SPI_DEV_CS_GPIOS_PIN(spi_dev) \
+	DT_GPIO_PIN_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev))
+
+/**
+ * @brief Get a SPI device's chip select GPIO flags
+ *
+ * Example devicetree fragment:
+ *
+ *     spi1: spi@... {
+ *             compatible = "vnd,spi";
+ *             cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ *
+ *             a: spi-dev-a@0 {
+ *                     reg = <0>;
+ *             };
+ *     };
+ *
+ * Example usage:
+ *
+ *     DT_SPI_DEV_CS_GPIOS_FLAGS(DT_NODELABEL(a)) // GPIO_ACTIVE_LOW
+ *
+ * If the GPIO specifier for spi_dev's entry in its bus node's
+ * cs-gpios property has no flags cell, this expands to zero.
+ *
+ * @param spi_dev a SPI device node identifier
+ * @return flags value of spi_dev's chip select GPIO specifier, or
+ *         zero if there is none
+ */
+#define DT_SPI_DEV_CS_GPIOS_FLAGS(spi_dev) \
+	DT_GPIO_FLAGS_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev))
+
+/**
+ * @brief Equivalent to DT_SPI_DEV_HAS_CS_GPIOS(DT_DRV_INST(inst)).
+ * @param inst DT_DRV_COMPAT instance number
+ * @return 1 if the instance's bus has a CS pin at index
+ *         DT_INST_REG_ADDR(inst), 0 otherwise
+ * @see DT_SPI_DEV_HAS_CS_GPIOS()
+ */
+#define DT_INST_SPI_DEV_HAS_CS_GPIOS(inst) \
+	DT_SPI_DEV_HAS_CS_GPIOS(DT_DRV_INST(inst))
+
+/**
+ * @brief Get GPIO controller node identifier for a SPI device instance
+ * This is equivalent to DT_SPI_DEV_CS_GPIOS_CTLR(DT_DRV_INST(inst)).
+ * @param inst DT_DRV_COMPAT instance number
+ * @return node identifier for instance's chip select GPIO controller
+ * @see DT_SPI_DEV_CS_GPIOS_CTLR()
+ */
+#define DT_INST_SPI_DEV_CS_GPIOS_CTLR(inst) \
+	DT_SPI_DEV_CS_GPIOS_CTLR(DT_DRV_INST(inst))
+
+/**
+ * @brief Get GPIO controller name for a SPI device instance
+ * This is equivalent to DT_SPI_DEV_CS_GPIOS_LABEL(DT_DRV_INST(inst)).
+ * @param inst DT_DRV_COMPAT instance number
+ * @return label property of the instance's chip select GPIO controller
+ * @see DT_SPI_DEV_CS_GPIOS_LABEL()
+ */
+#define DT_INST_SPI_DEV_CS_GPIOS_LABEL(inst) \
+	DT_SPI_DEV_CS_GPIOS_LABEL(DT_DRV_INST(inst))
+
+/**
+ * @brief Equivalent to DT_SPI_DEV_CS_GPIOS_PIN(DT_DRV_INST(inst)).
+ * @param inst DT_DRV_COMPAT instance number
+ * @return pin number of the instance's chip select GPIO
+ * @see DT_SPI_DEV_CS_GPIOS_PIN()
+ */
+#define DT_INST_SPI_DEV_CS_GPIOS_PIN(inst) \
+	DT_SPI_DEV_CS_GPIOS_PIN(DT_DRV_INST(inst))
+
+/**
+ * @brief DT_SPI_DEV_CS_GPIOS_FLAGS(DT_DRV_INST(inst)).
+ * @param inst DT_DRV_COMPAT instance number
+ * @return flags value of the instance's chip select GPIO specifier,
+ *         or zero if there is none
+ * @see DT_SPI_DEV_CS_GPIOS_FLAGS()
+ */
+#define DT_INST_SPI_DEV_CS_GPIOS_FLAGS(inst) \
+	DT_SPI_DEV_CS_GPIOS_FLAGS(DT_DRV_INST(inst))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ZEPHYR_INCLUDE_DEVICETREE_SPI_H_ */
diff --git a/src/include/devicetree/zephyr.h b/src/include/devicetree/zephyr.h
new file mode 100644
index 0000000000..6d02451704
--- /dev/null
+++ b/src/include/devicetree/zephyr.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2020 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Zephyr-specific devicetree /chosen properties
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEVICETREE_ZEPHYR_H_
+#define ZEPHYR_INCLUDE_DEVICETREE_ZEPHYR_H_
+
+/**
+ * @defgroup devicetree-zephyr Zephyr's /chosen nodes
+ * @ingroup devicetree
+ * @{
+ */
+
+/*
+ * This file is currently deliberately not defining macros for some
+ * existing zephyr,foo chosen nodes, such as zephyr,sram, until there
+ * are users for them. Feel free to extend it as needed.
+ *
+ * Getting doxygen to play along with all the dts-specific ifdeffery
+ * proved too complex for DT_CHOSEN_ZEPHYR_ENTROPY_LABEL, so we document
+ * everything under a DT_DOXYGEN define.
+ */
+
+#ifdef DT_DOXYGEN
+/**
+ * @def DT_CHOSEN_ZEPHYR_ENTROPY_LABEL
+ *
+ * @brief If there is a chosen node zephyr,entropy property which has
+ *        a label property, that property's value. Undefined otherwise.
+ */
+#define DT_CHOSEN_ZEPHYR_ENTROPY_LABEL ""
+
+/**
+ * @def DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL
+ *
+ * @brief If there is a chosen node zephyr,flash-controller property which has
+ *        a label property, that property's value. Undefined otherwise.
+ */
+#define DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL ""
+
+#endif /* DT_DOXYGEN */
+
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_entropy), label)
+#define DT_CHOSEN_ZEPHYR_ENTROPY_LABEL DT_LABEL(DT_CHOSEN(zephyr_entropy))
+#endif
+
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash_controller), label)
+#define DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL \
+	DT_LABEL(DT_CHOSEN(zephyr_flash_controller))
+#endif
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/src/include/dt-bindings/adc/adc.h b/src/include/dt-bindings/adc/adc.h
new file mode 100644
index 0000000000..fafadb163b
--- /dev/null
+++ b/src/include/dt-bindings/adc/adc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2021 Google LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADC_H_
+
+/*
+ * Provide the BIT_MASK() macro for when this file is included from
+ * devicetrees.
+ */
+#ifndef BIT_MASK
+#define BIT_MASK(n) ((1 << (n)) - 1)
+#endif
+
+/** Acquisition time is expressed in microseconds. */
+#define ADC_ACQ_TIME_MICROSECONDS  (1)
+/** Acquisition time is expressed in nanoseconds. */
+#define ADC_ACQ_TIME_NANOSECONDS   (2)
+/** Acquisition time is expressed in ADC ticks. */
+#define ADC_ACQ_TIME_TICKS         (3)
+/** Macro for composing the acquisition time value in given units. */
+#define ADC_ACQ_TIME(unit, value)  (((unit) << 14) | ((value) & BIT_MASK(14)))
+/** Value indicating that the default acquisition time should be used. */
+#define ADC_ACQ_TIME_DEFAULT       0
+#define ADC_ACQ_TIME_MAX           BIT_MASK(14)
+
+#define ADC_ACQ_TIME_UNIT(time)    (((time) >> 14) & BIT_MASK(2))
+#define ADC_ACQ_TIME_VALUE(time)   ((time) & BIT_MASK(14))
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADC_H_ */
diff --git a/src/include/dt-bindings/clock/imx_ccm.h b/src/include/dt-bindings/clock/imx_ccm.h
new file mode 100644
index 0000000000..64543dc4d0
--- /dev/null
+++ b/src/include/dt-bindings/clock/imx_ccm.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017-2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_
+
+#define IMX_CCM_CORESYS_CLK		0
+#define IMX_CCM_PLATFORM_CLK		1
+#define IMX_CCM_BUS_CLK			2
+#define IMX_CCM_LPUART_CLK		3
+#define IMX_CCM_LPI2C_CLK		4
+#define IMX_CCM_LPSPI_CLK		5
+#define IMX_CCM_USDHC1_CLK		6
+#define IMX_CCM_USDHC2_CLK		7
+#define IMX_CCM_EDMA_CLK		8
+#define IMX_CCM_UART_CLK		9
+#define IMX_CCM_CAN_CLK			10
+#define IMX_CCM_GPT_CLK			11
+#define IMX_CCM_SAI1_CLK		12
+#define IMX_CCM_SAI2_CLK		13
+#define IMX_CCM_SAI3_CLK		14
+#define IMX_CCM_PWM_CLK			15
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */
diff --git a/src/include/dt-bindings/clock/imx_ccm_rev2.h b/src/include/dt-bindings/clock/imx_ccm_rev2.h
new file mode 100644
index 0000000000..9864d421c1
--- /dev/null
+++ b/src/include/dt-bindings/clock/imx_ccm_rev2.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_
+
+/* Peripheral:
+ *   range: 0 - 0xFF, starting from 0
+ *
+ * Instance:
+ *   range: 0 - 0xFF, starting from 0
+ */
+#define IMX_CCM_PERIPHERAL_MASK 0xFF00UL
+#define IMX_CCM_INSTANCE_MASK   0xFFUL
+
+#define IMX_CCM_CORESYS_CLK		0
+#define IMX_CCM_PLATFORM_CLK	0x1UL
+#define IMX_CCM_BUS_CLK			0x2UL
+/* LPUART */
+#define IMX_CCM_LPUART_CLK		0x300UL
+#define IMX_CCM_LPUART1_CLK		0x300UL
+#define IMX_CCM_LPUART2_CLK		0x301UL
+#define IMX_CCM_LPUART3_CLK		0x302UL
+#define IMX_CCM_LPUART4_CLK		0x303UL
+#define IMX_CCM_LPUART5_CLK		0x304UL
+#define IMX_CCM_LPUART6_CLK		0x305UL
+#define IMX_CCM_LPUART7_CLK		0x306UL
+#define IMX_CCM_LPUART8_CLK		0x307UL
+#define IMX_CCM_LPUART9_CLK		0x308UL
+#define IMX_CCM_LPUART10_CLK	0x309UL
+#define IMX_CCM_LPUART11_CLK	0x30aUL
+#define IMX_CCM_LPUART12_CLK	0x30bUL
+
+/* LPI2C */
+#define IMX_CCM_LPI2C_CLK		0x400UL
+#define IMX_CCM_LPI2C1_CLK		0x400UL
+#define IMX_CCM_LPI2C2_CLK		0x401UL
+#define IMX_CCM_LPI2C3_CLK		0x402UL
+#define IMX_CCM_LPI2C4_CLK		0x403UL
+#define IMX_CCM_LPI2C5_CLK		0x404UL
+#define IMX_CCM_LPI2C6_CLK		0x405UL
+
+/* LPSPI */
+#define IMX_CCM_LPSPI_CLK		0x500UL
+#define IMX_CCM_LPSPI1_CLK		0x500UL
+#define IMX_CCM_LPSPI2_CLK		0x501UL
+#define IMX_CCM_LPSPI3_CLK		0x502UL
+#define IMX_CCM_LPSPI4_CLK		0x503UL
+#define IMX_CCM_LPSPI5_CLK		0x504UL
+#define IMX_CCM_LPSPI6_CLK		0x505UL
+
+/* USDHC */
+#define IMX_CCM_USDHC1_CLK		0x600UL
+#define IMX_CCM_USDHC2_CLK		0x601UL
+
+/* DMA  */
+#define IMX_CCM_EDMA_CLK        0x700UL
+#define IMX_CCM_EDMA_LPSR_CLK   0x701UL
+
+/* PWM */
+#define IMX_CCM_PWM_CLK			0x800UL
+
+/* CAN */
+#define IMX_CCM_CAN_CLK		    0x900UL
+#define IMX_CCM_CAN1_CLK		0x900UL
+#define IMX_CCM_CAN2_CLK		0x901UL
+#define IMX_CCM_CAN3_CLK		0x902UL
+
+/* GPT */
+#define IMX_CCM_GPT_CLK		    0x1000UL
+#define IMX_CCM_GPT1_CLK		0x1000UL
+#define IMX_CCM_GPT2_CLK		0x1001UL
+#define IMX_CCM_GPT3_CLK		0x1002UL
+#define IMX_CCM_GPT4_CLK		0x1003UL
+#define IMX_CCM_GPT5_CLK		0x1004UL
+#define IMX_CCM_GPT6_CLK		0x1005UL
+
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */
diff --git a/src/include/dt-bindings/clock/kinetis_mcg.h b/src/include/dt-bindings/clock/kinetis_mcg.h
new file mode 100644
index 0000000000..6e12d768fc
--- /dev/null
+++ b/src/include/dt-bindings/clock/kinetis_mcg.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_
+
+#define KINETIS_MCG_FIXED_FREQ_CLK	0
+#define KINETIS_MCG_OUT_CLK		1
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_ */
diff --git a/src/include/dt-bindings/clock/kinetis_pcc.h b/src/include/dt-bindings/clock/kinetis_pcc.h
new file mode 100644
index 0000000000..1fcb2a8613
--- /dev/null
+++ b/src/include/dt-bindings/clock/kinetis_pcc.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_
+
+/* NXP Kinetis Peripheral Clock Controller IP sources */
+#define KINETIS_PCC_SRC_NONE_OR_EXT 0 /* Clock off or external clock is used */
+#define KINETIS_PCC_SRC_SOSC_ASYNC  1 /* System Oscillator async clock */
+#define KINETIS_PCC_SRC_SIRC_ASYNC  2 /* Slow IRC async clock */
+#define KINETIS_PCC_SRC_FIRC_ASYNC  3 /* Fast IRC async clock */
+#define KINETIS_PCC_SRC_SPLL_ASYNC  6 /* System PLL async clock */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_ */
diff --git a/src/include/dt-bindings/clock/kinetis_scg.h b/src/include/dt-bindings/clock/kinetis_scg.h
new file mode 100644
index 0000000000..638cef1c95
--- /dev/null
+++ b/src/include/dt-bindings/clock/kinetis_scg.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_
+
+/* SCG system oscillator mode */
+#define KINETIS_SCG_SOSC_MODE_EXT        0U
+#define KINETIS_SCG_SOSC_MODE_LOW_POWER  4U
+#define KINETIS_SCG_SOSC_MODE_HIGH_GAIN 12U
+
+/* SCG clock controller clock names */
+#define KINETIS_SCG_CORESYS_CLK          0U
+#define KINETIS_SCG_BUS_CLK              1U
+#define KINETIS_SCG_FLEXBUS_CLK          2U
+#define KINETIS_SCG_FLASH_CLK            3U
+#define KINETIS_SCG_SOSC_CLK             4U
+#define KINETIS_SCG_SIRC_CLK             5U
+#define KINETIS_SCG_FIRC_CLK             6U
+#define KINETIS_SCG_SPLL_CLK             7U
+#define KINETIS_SCG_SOSC_ASYNC_DIV1_CLK  8U
+#define KINETIS_SCG_SOSC_ASYNC_DIV2_CLK  9U
+#define KINETIS_SCG_SIRC_ASYNC_DIV1_CLK 10U
+#define KINETIS_SCG_SIRC_ASYNC_DIV2_CLK 11U
+#define KINETIS_SCG_FIRC_ASYNC_DIV1_CLK 12U
+#define KINETIS_SCG_FIRC_ASYNC_DIV2_CLK 13U
+#define KINETIS_SCG_SPLL_ASYNC_DIV1_CLK 14U
+#define KINETIS_SCG_SPLL_ASYNC_DIV2_CLK 15U
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_ */
diff --git a/src/include/dt-bindings/clock/kinetis_sim.h b/src/include/dt-bindings/clock/kinetis_sim.h
new file mode 100644
index 0000000000..6c06928ec8
--- /dev/null
+++ b/src/include/dt-bindings/clock/kinetis_sim.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_
+
+#define KINETIS_SIM_CORESYS_CLK		0
+#define KINETIS_SIM_PLATFORM_CLK	1
+#define KINETIS_SIM_BUS_CLK		2
+#define KINETIS_SIM_FAST_PERIPHERAL_CLK	5
+#define KINETIS_SIM_LPO_CLK		19
+#define KINETIS_SIM_DMAMUX_CLK  KINETIS_SIM_BUS_CLK
+#define KINETIS_SIM_DMA_CLK     KINETIS_SIM_CORESYS_CLK
+#define KINETIS_SIM_SIM_SOPT7   7
+
+#define KINETIS_SIM_PLLFLLSEL_MCGFLLCLK	0
+#define KINETIS_SIM_PLLFLLSEL_MCGPLLCLK	1
+#define KINETIS_SIM_PLLFLLSEL_IRC48MHZ	3
+
+#define KINETIS_SIM_ER32KSEL_OSC32KCLK	0
+#define KINETIS_SIM_ER32KSEL_RTC	2
+#define KINETIS_SIM_ER32KSEL_LPO1KHZ	3
+
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_ */
diff --git a/src/include/dt-bindings/clock/stm32_clock.h b/src/include/dt-bindings/clock/stm32_clock.h
new file mode 100644
index 0000000000..a669f49b92
--- /dev/null
+++ b/src/include/dt-bindings/clock/stm32_clock.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_
+
+/* clock bus references */
+#define STM32_CLOCK_BUS_AHB1    0
+#define STM32_CLOCK_BUS_AHB2    1
+#define STM32_CLOCK_BUS_APB1    2
+#define STM32_CLOCK_BUS_APB2    3
+#define STM32_CLOCK_BUS_APB1_2  4
+#define STM32_CLOCK_BUS_IOP     5
+#define STM32_CLOCK_BUS_AHB3    6
+#define STM32_CLOCK_BUS_AHB4    7
+#define STM32_CLOCK_BUS_AHB5    8
+#define STM32_CLOCK_BUS_AHB6    9
+#define STM32_CLOCK_BUS_APB3    10
+#define STM32_CLOCK_BUS_APB4    11
+#define STM32_CLOCK_BUS_APB5    12
+#define STM32_CLOCK_BUS_AXI     13
+#define STM32_CLOCK_BUS_MLAHB   14
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_ */
diff --git a/src/include/dt-bindings/dt-util.h b/src/include/dt-bindings/dt-util.h
new file mode 100644
index 0000000000..dc5462a2d9
--- /dev/null
+++ b/src/include/dt-bindings/dt-util.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DT_UTIL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DT_UTIL_H_
+
+/*
+ * This file exists to keep in-tree DTS clean.  This means, only
+ * #include <dt-bindings/foo.h> form should be included.  The
+ * <dt-bindings/dt-util.h> wraps <sys/util_macro.h> file exposing
+ * all macro base definitions to DTS preprocessor.  It provides
+ * necessary background to elaborate complex constructions like
+ * variable length macros with zero or more elements.
+ */
+
+#include <sys/util_macro.h>
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DT_UTIL_H_ */
diff --git a/src/include/dt-bindings/gpio/gpio.h b/src/include/dt-bindings/gpio/gpio.h
new file mode 100644
index 0000000000..10cb8660d2
--- /dev/null
+++ b/src/include/dt-bindings/gpio/gpio.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2019 Piotr Mienkowski
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_GPIO_H_
+
+/**
+ * @brief GPIO Driver APIs
+ * @defgroup gpio_interface GPIO Driver APIs
+ * @ingroup io_interfaces
+ * @{
+ */
+
+/**
+ * @name GPIO pin active level flags
+ * @{
+ */
+
+/** GPIO pin is active (has logical value '1') in low state. */
+#define GPIO_ACTIVE_LOW         (1 << 0)
+/** GPIO pin is active (has logical value '1') in high state. */
+#define GPIO_ACTIVE_HIGH        (0 << 0)
+
+/** @} */
+
+/**
+ * @name GPIO pin drive flags
+ * @{
+ */
+
+/** @cond INTERNAL_HIDDEN */
+
+/* Configures GPIO output in single-ended mode (open drain or open source). */
+#define GPIO_SINGLE_ENDED       (1 << 1)
+/* Configures GPIO output in push-pull mode */
+#define GPIO_PUSH_PULL          (0 << 1)
+
+/* Indicates single ended open drain mode (wired AND). */
+#define GPIO_LINE_OPEN_DRAIN    (1 << 2)
+/* Indicates single ended open source mode (wired OR). */
+#define GPIO_LINE_OPEN_SOURCE   (0 << 2)
+
+/** @endcond */
+
+/** Configures GPIO output in open drain mode (wired AND).
+ *
+ * @note 'Open Drain' mode also known as 'Open Collector' is an output
+ * configuration which behaves like a switch that is either connected to ground
+ * or disconnected.
+ */
+#define GPIO_OPEN_DRAIN         (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
+/** Configures GPIO output in open source mode (wired OR).
+ *
+ * @note 'Open Source' is a term used by software engineers to describe output
+ * mode opposite to 'Open Drain'. It behaves like a switch that is either
+ * connected to power supply or disconnected. There exist no corresponding
+ * hardware schematic and the term is generally unknown to hardware engineers.
+ */
+#define GPIO_OPEN_SOURCE        (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+
+/** @} */
+
+/**
+ * @name GPIO pin bias flags
+ * @{
+ */
+
+/** Enables GPIO pin pull-up. */
+#define GPIO_PULL_UP            (1 << 4)
+
+/** Enable GPIO pin pull-down. */
+#define GPIO_PULL_DOWN          (1 << 5)
+
+/** @} */
+
+/**
+ * @name GPIO pin voltage flags
+ *
+ * The voltage flags are a Zephyr specific extension of the standard GPIO
+ * flags specified by the Linux GPIO binding. Only applicable if SoC allows
+ * to configure pin voltage per individual pin.
+ *
+ * @{
+ */
+
+/** @cond INTERNAL_HIDDEN */
+#define GPIO_VOLTAGE_POS	6
+#define GPIO_VOLTAGE_MASK	(3U << GPIO_VOLTAGE_POS)
+/** @endcond */
+
+/** Set pin at the default voltage level */
+#define GPIO_VOLTAGE_DEFAULT	(0U << GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 1.8 V */
+#define GPIO_VOLTAGE_1P8	(1U << GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 3.3 V */
+#define GPIO_VOLTAGE_3P3	(2U << GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 5.0 V */
+#define GPIO_VOLTAGE_5P0	(3U << GPIO_VOLTAGE_POS)
+
+/** @} */
+
+/**
+ * @}
+ */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_GPIO_H_ */
diff --git a/src/include/dt-bindings/i2c/i2c.h b/src/include/dt-bindings/i2c/i2c.h
new file mode 100644
index 0000000000..b0a2584263
--- /dev/null
+++ b/src/include/dt-bindings/i2c/i2c.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_I2C_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_I2C_H_
+
+#define I2C_BITRATE_STANDARD	100000	/* 100 Kbit/s */
+#define I2C_BITRATE_FAST	400000	/* 400 Kbit/s */
+#define I2C_BITRATE_FAST_PLUS	1000000 /* 1 Mbit/s */
+#define I2C_BITRATE_HIGH	3400000	/* 3.4 Mbit/s */
+#define I2C_BITRATE_ULTRA	5000000 /* 5 Mbit/s */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_I2C_H_ */
diff --git a/src/include/dt-bindings/led/led.h b/src/include/dt-bindings/led/led.h
new file mode 100644
index 0000000000..fa8c194068
--- /dev/null
+++ b/src/include/dt-bindings/led/led.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020 Seagate Technology LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LED_LED_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_LED_LED_H_
+
+/* Standard LED colors */
+#define LED_COLOR_ID_WHITE      0
+#define LED_COLOR_ID_RED        1
+#define LED_COLOR_ID_GREEN      2
+#define LED_COLOR_ID_BLUE       3
+#define LED_COLOR_ID_AMBER      4
+#define LED_COLOR_ID_VIOLET     5
+#define LED_COLOR_ID_YELLOW     6
+#define LED_COLOR_ID_IR         7
+#define LED_COLOR_ID_MAX        8
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LED_LED_H_ */
diff --git a/src/include/dt-bindings/memory-controller/stm32-fmc-sdram.h b/src/include/dt-bindings/memory-controller/stm32-fmc-sdram.h
new file mode 100644
index 0000000000..9bb622d12b
--- /dev/null
+++ b/src/include/dt-bindings/memory-controller/stm32-fmc-sdram.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
+
+/* Number of column address bits */
+#define STM32_FMC_SDRAM_NC_8 0x00000000UL
+#define STM32_FMC_SDRAM_NC_9 0x00000001UL
+#define STM32_FMC_SDRAM_NC_10 0x00000002UL
+#define STM32_FMC_SDRAM_NC_11 0x00000003UL
+
+/* Number of row address bits */
+#define STM32_FMC_SDRAM_NR_11 0x00000000UL
+#define STM32_FMC_SDRAM_NR_12 0x00000004UL
+#define STM32_FMC_SDRAM_NR_13 0x00000008UL
+
+/* Memory data bus width. */
+#define STM32_FMC_SDRAM_MWID_8 0x00000000UL
+#define STM32_FMC_SDRAM_MWID_16 0x00000010UL
+#define STM32_FMC_SDRAM_MWID_32 0x00000020UL
+
+/* Number of internal banks */
+#define STM32_FMC_SDRAM_NB_2 0x00000000UL
+#define STM32_FMC_SDRAM_NB_4 0x00000040UL
+
+/* CAS Latency */
+#define STM32_FMC_SDRAM_CAS_1 0x00000080UL
+#define STM32_FMC_SDRAM_CAS_2 0x00000100UL
+#define STM32_FMC_SDRAM_CAS_3 0x00000180UL
+
+/* SDRAM clock configuration */
+#define STM32_FMC_SDRAM_SDCLK_DISABLE 0x00000000UL
+#define STM32_FMC_SDRAM_SDCLK_PERIOD_2 0x00000800UL
+#define STM32_FMC_SDRAM_SDCLK_PERIOD_3 0x00000C00UL
+
+/* Burst read */
+#define STM32_FMC_SDRAM_RBURST_DISABLE 0x00000000UL
+#define STM32_FMC_SDRAM_RBURST_ENABLE 0x00001000UL
+
+/* Read pipe */
+#define STM32_FMC_SDRAM_RPIPE_0 0x00000000UL
+#define STM32_FMC_SDRAM_RPIPE_1 0x00002000UL
+#define STM32_FMC_SDRAM_RPIPE_2 0x00004000UL
+
+#endif
diff --git a/src/include/dt-bindings/pinctrl/stm32-pinctrl-common.h b/src/include/dt-bindings/pinctrl/stm32-pinctrl-common.h
new file mode 100644
index 0000000000..a1c5bf3bdb
--- /dev/null
+++ b/src/include/dt-bindings/pinctrl/stm32-pinctrl-common.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_STM32_PINCTRL_COMMON_H_
+#define ZEPHYR_STM32_PINCTRL_COMMON_H_
+
+/**
+ * @brief numerical IDs for IO ports
+ */
+
+#define	STM32_PORTA 0	/* IO port A */
+#define	STM32_PORTB 1	/* .. */
+#define	STM32_PORTC 2
+#define	STM32_PORTD 3
+#define	STM32_PORTE 4
+#define	STM32_PORTF 5
+#define	STM32_PORTG 6
+#define	STM32_PORTH 7
+#define	STM32_PORTI 8
+#define	STM32_PORTJ 9
+#define	STM32_PORTK 10	/* IO port K */
+
+#ifndef STM32_PORTS_MAX
+#define STM32_PORTS_MAX (STM32_PORTK + 1)
+#endif
+
+#define STM32_PINMUX_FUNC_GPIO 0
+#define STM32_PINMUX_FUNC_ANALOG (STM32_PINMUX_FUNC_ALT_MAX)
+
+/**
+ * @brief helper macro to encode an IO port pin in a numerical format
+ */
+#define STM32PIN(_port, _pin) \
+	(_port << 4 | _pin)
+
+#endif	/* ZEPHYR_STM32_PINCTRL_COMMON_H_ */
diff --git a/src/include/dt-bindings/pinctrl/stm32-pinctrl.h b/src/include/dt-bindings/pinctrl/stm32-pinctrl.h
new file mode 100644
index 0000000000..cd58887dde
--- /dev/null
+++ b/src/include/dt-bindings/pinctrl/stm32-pinctrl.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_
+
+#include <dt-bindings/pinctrl/stm32-pinctrl-common.h>
+
+/* Adapted from Linux: include/dt-bindings/pinctrl/stm32-pinfunc.h */
+
+/**
+ * @brief Pin modes
+ */
+
+#define STM32_AF0     0x0
+#define STM32_AF1     0x1
+#define STM32_AF2     0x2
+#define STM32_AF3     0x3
+#define STM32_AF4     0x4
+#define STM32_AF5     0x5
+#define STM32_AF6     0x6
+#define STM32_AF7     0x7
+#define STM32_AF8     0x8
+#define STM32_AF9     0x9
+#define STM32_AF10    0xa
+#define STM32_AF11    0xb
+#define STM32_AF12    0xc
+#define STM32_AF13    0xd
+#define STM32_AF14    0xe
+#define STM32_AF15    0xf
+#define STM32_ANALOG  0x10
+
+/**
+ * @brief Macro to generate pinmux int using port, pin number and mode arguments
+ * This is inspired from Linux equivalent st,stm32f429-pinctrl binding
+ */
+
+/**
+ * @brief Pin configuration configuration bit field.
+ *
+ * Fields:
+ *
+ * - mode [ 0 : 4 ]
+ * - line [ 5 : 8 ]
+ * - port [ 9 : 12 ]
+ *
+ * @param port Port ('A'..'K')
+ * @param line Pin (0..15)
+ * @param mode Mode (ANALOG, GPIO_IN, ALTERNATE).
+ */
+
+#define STM32_MODE_SHIFT 0U
+#define STM32_MODE_MASK  0x1FU
+#define STM32_LINE_SHIFT 5U
+#define STM32_LINE_MASK  0xFU
+#define STM32_PORT_SHIFT 9U
+#define STM32_PORT_MASK  0xFU
+
+#define STM32_PINMUX(port, line, mode)					       \
+	(((((port) - 'A') & STM32_PORT_MASK) << STM32_PORT_SHIFT) |    \
+	 (((line) & STM32_LINE_MASK) << STM32_LINE_SHIFT) |	       \
+	 (((STM32_ ## mode) & STM32_MODE_MASK) << STM32_MODE_SHIFT))
+
+/**
+ * @brief PIN configuration bitfield
+ *
+ * Pin configuration is coded with the following
+ * fields
+ *    Alternate Functions [ 0 : 3 ]
+ *    GPIO Mode           [ 4 : 5 ]
+ *    GPIO Output type    [ 6 ]
+ *    GPIO Speed          [ 7 : 8 ]
+ *    GPIO PUPD config    [ 9 : 10 ]
+ *
+ * Applicable to STM32F3, STM32F4, STM32L4 series
+ */
+
+/* GPIO Mode */
+#define STM32_MODER_INPUT_MODE		(0x0<<STM32_MODER_SHIFT)
+#define STM32_MODER_OUTPUT_MODE		(0x1<<STM32_MODER_SHIFT)
+#define STM32_MODER_ALT_MODE		(0x2<<STM32_MODER_SHIFT)
+#define STM32_MODER_ANALOG_MODE	 	(0x3<<STM32_MODER_SHIFT)
+#define STM32_MODER_MASK	 	0x3
+#define STM32_MODER_SHIFT		4
+
+/* GPIO Output type */
+#define STM32_OTYPER_PUSH_PULL		(0x0<<STM32_OTYPER_SHIFT)
+#define STM32_OTYPER_OPEN_DRAIN		(0x1<<STM32_OTYPER_SHIFT)
+#define STM32_OTYPER_MASK		0x1
+#define STM32_OTYPER_SHIFT		6
+
+/* GPIO speed */
+#define STM32_OSPEEDR_LOW_SPEED		(0x0<<STM32_OSPEEDR_SHIFT)
+#define STM32_OSPEEDR_MEDIUM_SPEED	(0x1<<STM32_OSPEEDR_SHIFT)
+#define STM32_OSPEEDR_HIGH_SPEED	(0x2<<STM32_OSPEEDR_SHIFT)
+#define STM32_OSPEEDR_VERY_HIGH_SPEED	(0x3<<STM32_OSPEEDR_SHIFT)
+#define STM32_OSPEEDR_MASK		0x3
+#define STM32_OSPEEDR_SHIFT		7
+
+/* GPIO High impedance/Pull-up/pull-down */
+#define STM32_PUPDR_NO_PULL		(0x0<<STM32_PUPDR_SHIFT)
+#define STM32_PUPDR_PULL_UP		(0x1<<STM32_PUPDR_SHIFT)
+#define STM32_PUPDR_PULL_DOWN		(0x2<<STM32_PUPDR_SHIFT)
+#define STM32_PUPDR_MASK		0x3
+#define STM32_PUPDR_SHIFT		9
+
+#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_ */
diff --git a/src/include/dt-bindings/pinctrl/stm32f1-afio.h b/src/include/dt-bindings/pinctrl/stm32f1-afio.h
new file mode 100644
index 0000000000..b9bc2928cf
--- /dev/null
+++ b/src/include/dt-bindings/pinctrl/stm32f1-afio.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_STM32_AFIO_H_
+#define ZEPHYR_STM32_AFIO_H_
+
+/**
+ * @brief STM32F1 Remap configuration bit field.
+ *
+ * - reg   (0/1)      [ 0 : 0 ]
+ * - shift (0..31)    [ 1 : 5 ]
+ * - mask  (0x1, 0x3) [ 6 : 7 ]
+ * - val   (0..3)     [ 8 : 9 ]
+ *
+ * @param reg AFIO_MAPRx register (MAPR, MAPR2).
+ * @param shift Position within AFIO_MAPRx.
+ * @param mask Mask for the AFIO_MAPRx field.
+ * @param val Remap value (0, 1, 2 or 3).
+ */
+
+#define STM32_REMAP_REG_MASK    0x1U
+#define STM32_REMAP_REG_SHIFT   0U
+#define STM32_REMAP_SHIFT_MASK  0x1FU
+#define STM32_REMAP_SHIFT_SHIFT 1U
+#define STM32_REMAP_MASK_MASK   0x3U
+#define STM32_REMAP_MASK_SHIFT  6U
+#define STM32_REMAP_VAL_MASK    0x3U
+#define STM32_REMAP_VAL_SHIFT   8U
+
+#define STM32_REMAP(val, mask, shift, reg)				       \
+	((((reg) & STM32_REMAP_REG_MASK) << STM32_REMAP_REG_SHIFT) |	       \
+	 (((shift) & STM32_REMAP_SHIFT_MASK) << STM32_REMAP_SHIFT_SHIFT) |     \
+	 (((mask) & STM32_REMAP_MASK_MASK) << STM32_REMAP_MASK_SHIFT) |	       \
+	 (((val) & STM32_REMAP_VAL_MASK) << STM32_REMAP_VAL_SHIFT))
+
+
+/* Accessors for remap value */
+
+/**
+ * Obtain register field from remap configuration.
+ *
+ * @param remap Remap bit field value.
+ */
+#define STM32_REMAP_REG_GET(remap) \
+	(((remap) >> STM32_REMAP_REG_SHIFT) & STM32_REMAP_REG_MASK)
+
+/**
+ * Obtain position field from remap configuration.
+ *
+ * @param remap Remap bit field value.
+ */
+#define STM32_REMAP_SHIFT_GET(remap) \
+	(((remap) >> STM32_REMAP_SHIFT_SHIFT) & STM32_REMAP_SHIFT_MASK)
+
+/**
+ * Obtain mask field from remap configuration.
+ *
+ * @param remap Remap bit field value.
+ */
+#define STM32_REMAP_MASK_GET(remap) \
+	(((remap) >> STM32_REMAP_MASK_SHIFT) & STM32_REMAP_MASK_MASK)
+
+/**
+ * Obtain value field from remap configuration.
+ *
+ * @param remap Remap bit field value.
+ */
+#define STM32_REMAP_VAL_GET(remap) \
+	(((remap) >> STM32_REMAP_VAL_SHIFT) & STM32_REMAP_VAL_MASK)
+
+
+/* Remap values definitions, according to RM0008.pdf */
+
+#define STM32_AFIO_MAPR		0U
+#define STM32_AFIO_MAPR2	1U
+
+/** Device not remappable **/
+#define NO_REMAP		0
+
+/** SPI1 (no remap) */
+#define SPI1_REMAP0		STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR)
+/** SPI1 (remap) */
+#define SPI1_REMAP1		STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR)
+
+/** I2C1 (no remap) */
+#define I2C1_REMAP0		STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR)
+/** I2C1 (remap) */
+#define I2C1_REMAP1		STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR)
+
+/** USART1 (no remap) */
+#define USART1_REMAP0		STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR)
+/** USART1 (remap) */
+#define USART1_REMAP1		STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR)
+
+/** USART2 (no remap) */
+#define USART2_REMAP0		STM32_REMAP(0U, 0x1U, 3U, STM32_AFIO_MAPR)
+/** USART2 (remap) */
+#define USART2_REMAP1		STM32_REMAP(1U, 0x1U, 3U, STM32_AFIO_MAPR)
+
+/** USART3 (no remap) */
+#define USART3_REMAP0		STM32_REMAP(0U, 0x3U, 4U, STM32_AFIO_MAPR)
+/** USART3 (partial remap) */
+#define USART3_REMAP1		STM32_REMAP(1U, 0x3U, 4U, STM32_AFIO_MAPR)
+/** USART3 (full remap) */
+#define USART3_REMAP2		STM32_REMAP(3U, 0x3U, 4U, STM32_AFIO_MAPR)
+
+/** TIM1 (no remap) */
+#define TIM1_REMAP0		STM32_REMAP(0U, 0x3U, 6U, STM32_AFIO_MAPR)
+/** TIM1 (partial remap) */
+#define TIM1_REMAP1		STM32_REMAP(1U, 0x3U, 6U, STM32_AFIO_MAPR)
+/** TIM1 (full remap) */
+#define TIM1_REMAP2		STM32_REMAP(3U, 0x3U, 6U, STM32_AFIO_MAPR)
+
+/** TIM2 (no remap) */
+#define TIM2_REMAP0		STM32_REMAP(0U, 0x3U, 8U, STM32_AFIO_MAPR)
+/** TIM2 (partial remap 1) */
+#define TIM2_REMAP1		STM32_REMAP(1U, 0x3U, 8U, STM32_AFIO_MAPR)
+/** TIM2 (partial remap 2) */
+#define TIM2_REMAP2		STM32_REMAP(2U, 0x3U, 8U, STM32_AFIO_MAPR)
+/** TIM2 (full remap) */
+#define TIM2_REMAP3		STM32_REMAP(3U, 0x3U, 8U, STM32_AFIO_MAPR)
+
+/** TIM3 (no remap) */
+#define TIM3_REMAP0		STM32_REMAP(0U, 0x3U, 10U, STM32_AFIO_MAPR)
+/** TIM3 (partial remap 1) */
+#define TIM3_REMAP1		STM32_REMAP(1U, 0x3U, 10U, STM32_AFIO_MAPR)
+/** TIM3 (partial remap 2) */
+#define TIM3_REMAP2		STM32_REMAP(2U, 0x3U, 10U, STM32_AFIO_MAPR)
+/** TIM3 (full remap) */
+#define TIM3_REMAP3		STM32_REMAP(3U, 0x3U, 10U, STM32_AFIO_MAPR)
+
+/** TIM4 (no remap) */
+#define TIM4_REMAP0		STM32_REMAP(0U, 0x1U, 12U, STM32_AFIO_MAPR)
+/** TIM4 (remap) */
+#define TIM4_REMAP1		STM32_REMAP(1U, 0x1U, 12U, STM32_AFIO_MAPR)
+
+/** CAN (no remap) */
+#define CAN_REMAP0		STM32_REMAP(0U, 0x3U, 13U, STM32_AFIO_MAPR)
+/** CAN (partial remap) */
+#define CAN_REMAP1		STM32_REMAP(2U, 0x3U, 13U, STM32_AFIO_MAPR)
+/** CAN (full remap) */
+#define CAN_REMAP2		STM32_REMAP(3U, 0x3U, 13U, STM32_AFIO_MAPR)
+
+/** CAN1 alias */
+#define CAN1_REMAP0		CAN_REMAP0
+#define CAN1_REMAP1		CAN_REMAP1
+#define CAN1_REMAP2		CAN_REMAP2
+
+/** ETH (no remap) */
+#define ETH_REMAP0		STM32_REMAP(0U, 0x1U, 20U, STM32_AFIO_MAPR)
+/** ETH (remap) */
+#define ETH_REMAP1		STM32_REMAP(1U, 0x1U, 20U, STM32_AFIO_MAPR)
+
+/** CAN2 (no remap) */
+#define CAN2_REMAP0		STM32_REMAP(0U, 0x1U, 21U, STM32_AFIO_MAPR)
+/** CAN2 (remap) */
+#define CAN2_REMAP1		STM32_REMAP(1U, 0x1U, 21U, STM32_AFIO_MAPR)
+
+/** SPI3 (no remap) */
+#define SPI3_REMAP0		STM32_REMAP(0U, 0x1U, 27U, STM32_AFIO_MAPR)
+/** SPI3 (remap) */
+#define SPI3_REMAP1		STM32_REMAP(1U, 0x1U, 27U, STM32_AFIO_MAPR)
+
+/** I2S3 (SPI3) (no remap) */
+#define I2S3_REMAP0		SPI3_REMAP0
+/** I2S3 (SPI3) (remap) */
+#define I2S3_REMAP1		SPI3_REMAP1
+
+/** TIM9 (no remap) */
+#define TIM9_REMAP0		STM32_REMAP(0U, 0x1U, 5U, STM32_AFIO_MAPR2)
+/** TIM9 (remap) */
+#define TIM9_REMAP1		STM32_REMAP(1U, 0x1U, 5U, STM32_AFIO_MAPR2)
+
+/** TIM10 (no remap) */
+#define TIM10_REMAP0		STM32_REMAP(0U, 0x1U, 6U, STM32_AFIO_MAPR2)
+/** TIM10 (remap) */
+#define TIM10_REMAP1		STM32_REMAP(1U, 0x1U, 6U, STM32_AFIO_MAPR2)
+
+/** TIM11 (no remap) */
+#define TIM11_REMAP0		STM32_REMAP(0U, 0x1U, 7U, STM32_AFIO_MAPR2)
+/** TIM11 (remap) */
+#define TIM11_REMAP1		STM32_REMAP(1U, 0x1U, 7U, STM32_AFIO_MAPR2)
+
+/** TIM13 (no remap) */
+#define TIM13_REMAP0		STM32_REMAP(0U, 0x1U, 8U, STM32_AFIO_MAPR2)
+/** TIM13 (remap) */
+#define TIM13_REMAP1		STM32_REMAP(1U, 0x1U, 8U, STM32_AFIO_MAPR2)
+
+/** TIM14 (no remap) */
+#define TIM14_REMAP0		STM32_REMAP(0U, 0x1U, 9U, STM32_AFIO_MAPR2)
+/** TIM14 (remap) */
+#define TIM14_REMAP1		STM32_REMAP(1U, 0x1U, 9U, STM32_AFIO_MAPR2)
+
+/** TIM15 (no remap) */
+#define TIM15_REMAP0		STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR2)
+/** TIM15 (remap) */
+#define TIM15_REMAP1		STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR2)
+
+/** TIM16 (no remap) */
+#define TIM16_REMAP0		STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR2)
+/** TIM16 (remap) */
+#define TIM16_REMAP1		STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR2)
+
+/** TIM17 (no remap) */
+#define TIM17_REMAP0		STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR2)
+/** TIM17 (remap) */
+#define TIM17_REMAP1		STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR2)
+
+#endif	/* ZEPHYR_STM32_AFIO_H_ */
diff --git a/src/include/dt-bindings/pinctrl/stm32f1-pinctrl.h b/src/include/dt-bindings/pinctrl/stm32f1-pinctrl.h
new file mode 100644
index 0000000000..e97c257864
--- /dev/null
+++ b/src/include/dt-bindings/pinctrl/stm32f1-pinctrl.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_STM32_PINCTRLF1_H_
+#define ZEPHYR_STM32_PINCTRLF1_H_
+
+#include <dt-bindings/pinctrl/stm32-pinctrl-common.h>
+#include <dt-bindings/pinctrl/stm32f1-afio.h>
+
+/* Adapted from Linux: include/dt-bindings/pinctrl/stm32-pinfunc.h */
+
+/**
+ * @brief Macro to generate pinmux int using port, pin number and mode arguments
+ * This is adapted from Linux equivalent st,stm32f429-pinctrl binding
+ */
+
+/**
+ * @brief Pin configuration configuration bit field.
+ *
+ * Fields:
+ *
+ * - mode  [ 0 : 1 ]
+ * - line  [ 2 : 5 ]
+ * - port  [ 6 : 9 ]
+ * - remap [ 10 : 19 ]
+ *
+ * @param port Port ('A'..'K')
+ * @param line Pin (0..15)
+ * @param mode Pin mode (ANALOG, GPIO_IN, ALTERNATE).
+ * @param remap Pin remapping configuration (NO_REMAP, REMAP_1, ...)
+ */
+
+#define STM32_MODE_SHIFT  0U
+#define STM32_MODE_MASK   0x3U
+#define STM32_LINE_SHIFT  2U
+#define STM32_LINE_MASK   0xFU
+#define STM32_PORT_SHIFT  6U
+#define STM32_PORT_MASK   0xFU
+#define STM32_REMAP_SHIFT 10U
+#define STM32_REMAP_MASK  0x3FFU
+
+#define STM32F1_PINMUX(port, line, mode, remap)				       \
+	(((((port) - 'A') & STM32_PORT_MASK) << STM32_PORT_SHIFT) |    \
+	 (((line) & STM32_LINE_MASK) << STM32_LINE_SHIFT) |	       \
+	 (((mode) & STM32_MODE_MASK) << STM32_MODE_SHIFT) |	       \
+	 (((remap) & STM32_REMAP_MASK) << STM32_REMAP_SHIFT))
+
+/**
+ * @brief Pin modes
+ */
+
+#define ALTERNATE	0x0  /* Alternate function output */
+#define GPIO_IN		0x1  /* Input */
+#define ANALOG		0x2  /* Analog */
+
+/**
+ * @brief PIN configuration bitfield
+ *
+ * Pin configuration is coded with the following
+ * fields
+ *    GPIO I/O Mode       [ 0 ]
+ *    GPIO Input config   [ 1 : 2 ]
+ *    GPIO Output speed   [ 3 : 4 ]
+ *    GPIO Output PP/OD   [ 5 ]
+ *    GPIO Output AF/GP   [ 6 ]
+ *    GPIO PUPD Config    [ 7 : 8 ]
+ *
+ * Applicable to STM32F1 series
+ */
+
+/* Port Mode */
+#define STM32_MODE_INPUT		(0x0<<STM32_MODE_INOUT_SHIFT)
+#define STM32_MODE_OUTPUT		(0x1<<STM32_MODE_INOUT_SHIFT)
+#define STM32_MODE_INOUT_MASK		0x1
+#define STM32_MODE_INOUT_SHIFT		0
+
+/* Input Port configuration */
+#define STM32_CNF_IN_ANALOG		(0x0<<STM32_CNF_IN_SHIFT)
+#define STM32_CNF_IN_FLOAT		(0x1<<STM32_CNF_IN_SHIFT)
+#define STM32_CNF_IN_PUPD		(0x2<<STM32_CNF_IN_SHIFT)
+#define STM32_CNF_IN_MASK		0x3
+#define STM32_CNF_IN_SHIFT		1
+
+/* Output Port configuration */
+#define STM32_MODE_OUTPUT_MAX_10	(0x0<<STM32_MODE_OSPEED_SHIFT)
+#define STM32_MODE_OUTPUT_MAX_2		(0x1<<STM32_MODE_OSPEED_SHIFT)
+#define STM32_MODE_OUTPUT_MAX_50	(0x2<<STM32_MODE_OSPEED_SHIFT)
+#define STM32_MODE_OSPEED_MASK		0x3
+#define STM32_MODE_OSPEED_SHIFT		3
+
+#define STM32_CNF_PUSH_PULL		(0x0<<STM32_CNF_OUT_0_SHIFT)
+#define STM32_CNF_OPEN_DRAIN		(0x1<<STM32_CNF_OUT_0_SHIFT)
+#define STM32_CNF_OUT_0_MASK		0x1
+#define STM32_CNF_OUT_0_SHIFT		5
+
+#define STM32_CNF_GP_OUTPUT		(0x0<<STM32_CNF_OUT_1_SHIFT)
+#define STM32_CNF_ALT_FUNC		(0x1<<STM32_CNF_OUT_1_SHIFT)
+#define STM32_CNF_OUT_1_MASK		0x1
+#define STM32_CNF_OUT_1_SHIFT		6
+
+/* GPIO High impedance/Pull-up/Pull-down */
+#define STM32_PUPD_NO_PULL		(0x0<<STM32_PUPD_SHIFT)
+#define STM32_PUPD_PULL_UP		(0x1<<STM32_PUPD_SHIFT)
+#define STM32_PUPD_PULL_DOWN		(0x2<<STM32_PUPD_SHIFT)
+#define STM32_PUPD_MASK			0x3
+#define STM32_PUPD_SHIFT		7
+
+#endif	/* ZEPHYR_STM32_PINCTRLF1_H_ */
diff --git a/src/include/dt-bindings/pwm/pwm.h b/src/include/dt-bindings/pwm/pwm.h
new file mode 100644
index 0000000000..92f3157a5e
--- /dev/null
+++ b/src/include/dt-bindings/pwm/pwm.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2019 Vestas Wind Systems A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_
+
+/**
+ * @name PWM polarity flags
+ * The `PWM_POLARITY_*` flags are used with pwm_pin_set_cycles(),
+ * pwm_pin_set_usec(), pwm_pin_set_nsec() or pwm_pin_configure_capture() to
+ * specify the polarity of a PWM pin.
+ * @{
+ */
+/** PWM pin normal polarity (active-high pulse). */
+#define PWM_POLARITY_NORMAL	(0 << 0)
+
+/** PWM pin inverted polarity (active-low pulse). */
+#define PWM_POLARITY_INVERTED	(1 << 0)
+
+/** @cond INTERNAL_HIDDEN */
+#define PWM_POLARITY_MASK	0x1
+/** @endcond */
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_ */
diff --git a/src/include/dt-bindings/spi/spi.h b/src/include/dt-bindings/spi/spi.h
new file mode 100644
index 0000000000..f6854fb62d
--- /dev/null
+++ b/src/include/dt-bindings/spi/spi.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_
+
+/**
+ * @brief SPI Interface
+ * @defgroup spi_interface SPI Interface
+ * @ingroup io_interfaces
+ * @{
+ */
+
+/**
+ * @name SPI duplex mode
+ * @{
+ *
+ * Some controllers support half duplex transfer, which results in 3-wire usage.
+ * By default, full duplex will prevail.
+ */
+#define SPI_FULL_DUPLEX		(0U << 11)
+#define SPI_HALF_DUPLEX		(1U << 11)
+/** @} */
+
+/**
+ * @name SPI Frame Format
+ * @{
+ *
+ * 2 frame formats are exposed: Motorola and TI.
+ * The main difference is the behavior of the CS line. In Motorala it stays
+ * active the whole transfer. In TI, it's active only one serial clock period
+ * prior to actually make the transfer, it is thus inactive during the transfer,
+ * which ends when the clocks ends as well.
+ * By default, as it is the most commonly used, the Motorola frame format
+ * will prevail.
+ */
+#define SPI_FRAME_FORMAT_MOTOROLA	(0U << 15)
+#define SPI_FRAME_FORMAT_TI		(1U << 15)
+/** @} */
+
+/**
+ * @}
+ */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_ */
diff --git a/src/include/dt-bindings/usb/usb.h b/src/include/dt-bindings/usb/usb.h
new file mode 100644
index 0000000000..e64f28f876
--- /dev/null
+++ b/src/include/dt-bindings/usb/usb.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_USB_USB_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_USB_USB_H_
+
+/* Ideally we'd generate this enum to match what's coming out of the YAML,
+ * however, we dont have a good way to know how to name such an enum from
+ * the generation point of view, so for now we just hand code the enum.  This
+ * enum is expected to match the order in the yaml (dts/bindings/usb/usb.yaml)
+ */
+
+enum dt_usb_maximum_speed {
+	DT_USB_MAXIMUM_SPEED_LOW_SPEED,
+	DT_USB_MAXIMUM_SPEED_FULL_SPEED,
+	DT_USB_MAXIMUM_SPEED_HIGH_SPEED,
+	DT_USB_MAXIMUM_SPEED_SUPER_SPEED,
+};
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_USB_USB_H_ */
diff --git a/src/include/sys/util.h b/src/include/sys/util.h
new file mode 100644
index 0000000000..3ff39328b2
--- /dev/null
+++ b/src/include/sys/util.h
@@ -0,0 +1,393 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Misc utilities
+ *
+ * Misc utilities usable by the kernel and application code.
+ */
+
+#ifndef ZEPHYR_INCLUDE_SYS_UTIL_H_
+#define ZEPHYR_INCLUDE_SYS_UTIL_H_
+
+#include <sys/util_macro.h>
+
+/* needs to be outside _ASMLANGUAGE so 'true' and 'false' can turn
+ * into '1' and '0' for asm or linker scripts
+ */
+#include <stdbool.h>
+
+#ifndef _ASMLANGUAGE
+
+#include <zephyr/types.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup sys-util Utility Functions
+ * @{
+ */
+
+/** @brief Cast @p x, a pointer, to an unsigned integer. */
+#define POINTER_TO_UINT(x) ((uintptr_t) (x))
+/** @brief Cast @p x, an unsigned integer, to a <tt>void*</tt>. */
+#define UINT_TO_POINTER(x) ((void *) (uintptr_t) (x))
+/** @brief Cast @p x, a pointer, to a signed integer. */
+#define POINTER_TO_INT(x)  ((intptr_t) (x))
+/** @brief Cast @p x, a signed integer, to a <tt>void*</tt>. */
+#define INT_TO_POINTER(x)  ((void *) (intptr_t) (x))
+
+#if !(defined(__CHAR_BIT__) && defined(__SIZEOF_LONG__))
+#	error Missing required predefined macros for BITS_PER_LONG calculation
+#endif
+
+/** Number of bits in a long int. */
+#define BITS_PER_LONG	(__CHAR_BIT__ * __SIZEOF_LONG__)
+
+/**
+ * @brief Create a contiguous bitmask starting at bit position @p l
+ *        and ending at position @p h.
+ */
+#define GENMASK(h, l) \
+	(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+
+/** @brief Extract the Least Significant Bit from @p value. */
+#define LSB_GET(value) ((value) & -(value))
+
+/**
+ * @brief Extract a bitfield element from @p value corresponding to
+ *	  the field mask @p mask.
+ */
+#define FIELD_GET(mask, value)  (((value) & (mask)) / LSB_GET(mask))
+
+/**
+ * @brief Prepare a bitfield element using @p value with @p mask representing
+ *	  its field position and width. The result should be combined
+ *	  with other fields using a logical OR.
+ */
+#define FIELD_PREP(mask, value) (((value) * LSB_GET(mask)) & (mask))
+
+/** @brief 0 if @p cond is true-ish; causes a compile error otherwise. */
+#define ZERO_OR_COMPILE_ERROR(cond) ((int) sizeof(char[1 - 2 * !(cond)]) - 1)
+
+#if defined(__cplusplus)
+
+/* The built-in function used below for type checking in C is not
+ * supported by GNU C++.
+ */
+#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
+
+#else /* __cplusplus */
+
+/**
+ * @brief Zero if @p array has an array type, a compile error otherwise
+ *
+ * This macro is available only from C, not C++.
+ */
+#define IS_ARRAY(array) \
+	ZERO_OR_COMPILE_ERROR( \
+		!__builtin_types_compatible_p(__typeof__(array), \
+					      __typeof__(&(array)[0])))
+
+/**
+ * @brief Number of elements in the given @p array
+ *
+ * In C++, due to language limitations, this will accept as @p array
+ * any type that implements <tt>operator[]</tt>. The results may not be
+ * particulary meaningful in this case.
+ *
+ * In C, passing a pointer as @p array causes a compile error.
+ */
+#define ARRAY_SIZE(array) \
+	((long) (IS_ARRAY(array) + (sizeof(array) / sizeof((array)[0]))))
+
+#endif /* __cplusplus */
+
+/**
+ * @brief Check if a pointer @p ptr lies within @p array.
+ *
+ * In C but not C++, this causes a compile error if @p array is not an array
+ * (e.g. if @p ptr and @p array are mixed up).
+ *
+ * @param ptr a pointer
+ * @param array an array
+ * @return 1 if @p ptr is part of @p array, 0 otherwise
+ */
+#define PART_OF_ARRAY(array, ptr) \
+	((ptr) && ((ptr) >= &array[0] && (ptr) < &array[ARRAY_SIZE(array)]))
+
+/**
+ * @brief Get a pointer to a structure containing the element
+ *
+ * Example:
+ *
+ *	struct foo {
+ *		int bar;
+ *	};
+ *
+ *	struct foo my_foo;
+ *	int *ptr = &my_foo.bar;
+ *
+ *	struct foo *container = CONTAINER_OF(ptr, struct foo, bar);
+ *
+ * Above, @p container points at @p my_foo.
+ *
+ * @param ptr pointer to a structure element
+ * @param type name of the type that @p ptr is an element of
+ * @param field the name of the field within the struct @p ptr points to
+ * @return a pointer to the structure that contains @p ptr
+ */
+#define CONTAINER_OF(ptr, type, field) \
+	((type *)(((char *)(ptr)) - offsetof(type, field)))
+
+/**
+ * @brief Value of @p x rounded up to the next multiple of @p align,
+ *        which must be a power of 2.
+ */
+#define ROUND_UP(x, align)                                   \
+	(((unsigned long)(x) + ((unsigned long)(align) - 1)) & \
+	 ~((unsigned long)(align) - 1))
+
+/**
+ * @brief Value of @p x rounded down to the previous multiple of @p
+ *        align, which must be a power of 2.
+ */
+#define ROUND_DOWN(x, align)                                 \
+	((unsigned long)(x) & ~((unsigned long)(align) - 1))
+
+/** @brief Value of @p x rounded up to the next word boundary. */
+#define WB_UP(x) ROUND_UP(x, sizeof(void *))
+
+/** @brief Value of @p x rounded down to the previous word boundary. */
+#define WB_DN(x) ROUND_DOWN(x, sizeof(void *))
+
+/**
+ * @brief Ceiling function applied to @p numerator / @p divider as a fraction.
+ */
+#define ceiling_fraction(numerator, divider) \
+	(((numerator) + ((divider) - 1)) / (divider))
+
+/**
+ * @def MAX
+ * @brief The larger value between @p a and @p b.
+ * @note Arguments are evaluated twice.
+ */
+#ifndef MAX
+/* Use Z_MAX for a GCC-only, single evaluation version */
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+/**
+ * @def MIN
+ * @brief The smaller value between @p a and @p b.
+ * @note Arguments are evaluated twice.
+ */
+#ifndef MIN
+/* Use Z_MIN for a GCC-only, single evaluation version */
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/**
+ * @def CLAMP
+ * @brief Clamp a value to a given range.
+ * @note Arguments are evaluated multiple times.
+ */
+#ifndef CLAMP
+/* Use Z_CLAMP for a GCC-only, single evaluation version */
+#define CLAMP(val, low, high) (((val) <= (low)) ? (low) : MIN(val, high))
+#endif
+
+/**
+ * @brief Is @p x a power of two?
+ * @param x value to check
+ * @return true if @p x is a power of two, false otherwise
+ */
+static inline bool is_power_of_two(unsigned int x)
+{
+	return (x != 0U) && ((x & (x - 1U)) == 0U);
+}
+
+/**
+ * @brief Arithmetic shift right
+ * @param value value to shift
+ * @param shift number of bits to shift
+ * @return @p value shifted right by @p shift; opened bit positions are
+ *         filled with the sign bit
+ */
+static inline int64_t arithmetic_shift_right(int64_t value, uint8_t shift)
+{
+	int64_t sign_ext;
+
+	if (shift == 0U) {
+		return value;
+	}
+
+	/* extract sign bit */
+	sign_ext = (value >> 63) & 1;
+
+	/* make all bits of sign_ext be the same as the value's sign bit */
+	sign_ext = -sign_ext;
+
+	/* shift value and fill opened bit positions with sign bit */
+	return (value >> shift) | (sign_ext << (64 - shift));
+}
+
+/**
+ * @brief byte by byte memcpy.
+ *
+ * Copy `size` bytes of `src` into `dest`. This is guaranteed to be done byte by byte.
+ *
+ * @param dst Pointer to the destination memory.
+ * @param src Pointer to the source of the data.
+ * @param size The number of bytes to copy.
+ */
+static inline void bytecpy(void *dst, const void *src, size_t size)
+{
+	size_t i;
+
+	for (i = 0; i < size; ++i) {
+		((uint8_t *)dst)[i] = ((const uint8_t *)src)[i];
+	}
+}
+
+/**
+ * @brief byte by byte swap.
+ *
+ * Swap @a size bytes between memory regions @a a and @a b. This is
+ * guaranteed to be done byte by byte.
+ *
+ * @param a Pointer to the the first memory region.
+ * @param b Pointer to the the second memory region.
+ * @param size The number of bytes to swap.
+ */
+static inline void byteswp(void *a, void *b, size_t size)
+{
+	uint8_t t;
+	uint8_t *aa = (uint8_t *)a;
+	uint8_t *bb = (uint8_t *)b;
+
+	for (; size > 0; --size) {
+		t = *aa;
+		*aa++ = *bb;
+		*bb++ = t;
+	}
+}
+
+/**
+ * @brief      Convert a single character into a hexadecimal nibble.
+ *
+ * @param c     The character to convert
+ * @param x     The address of storage for the converted number.
+ *
+ *  @return Zero on success or (negative) error code otherwise.
+ */
+int char2hex(char c, uint8_t *x);
+
+/**
+ * @brief      Convert a single hexadecimal nibble into a character.
+ *
+ * @param c     The number to convert
+ * @param x     The address of storage for the converted character.
+ *
+ *  @return Zero on success or (negative) error code otherwise.
+ */
+int hex2char(uint8_t x, char *c);
+
+/**
+ * @brief      Convert a binary array into string representation.
+ *
+ * @param buf     The binary array to convert
+ * @param buflen  The length of the binary array to convert
+ * @param hex     Address of where to store the string representation.
+ * @param hexlen  Size of the storage area for string representation.
+ *
+ * @return     The length of the converted string, or 0 if an error occurred.
+ */
+size_t bin2hex(const uint8_t *buf, size_t buflen, char *hex, size_t hexlen);
+
+/**
+ * @brief      Convert a hexadecimal string into a binary array.
+ *
+ * @param hex     The hexadecimal string to convert
+ * @param hexlen  The length of the hexadecimal string to convert.
+ * @param buf     Address of where to store the binary data
+ * @param buflen  Size of the storage area for binary data
+ *
+ * @return     The length of the binary array, or 0 if an error occurred.
+ */
+size_t hex2bin(const char *hex, size_t hexlen, uint8_t *buf, size_t buflen);
+
+/**
+ * @brief Convert a binary coded decimal (BCD 8421) value to binary.
+ *
+ * @param bcd BCD 8421 value to convert.
+ *
+ * @return Binary representation of input value.
+ */
+static inline uint8_t bcd2bin(uint8_t bcd)
+{
+	return ((10 * (bcd >> 4)) + (bcd & 0x0F));
+}
+
+/**
+ * @brief Convert a binary value to binary coded decimal (BCD 8421).
+ *
+ * @param bin Binary value to convert.
+ *
+ * @return BCD 8421 representation of input value.
+ */
+static inline uint8_t bin2bcd(uint8_t bin)
+{
+	return (((bin / 10) << 4) | (bin % 10));
+}
+
+/**
+ * @brief      Convert a uint8_t into a decimal string representation.
+ *
+ * Convert a uint8_t value into its ASCII decimal string representation.
+ * The string is terminated if there is enough space in buf.
+ *
+ * @param buf     Address of where to store the string representation.
+ * @param buflen  Size of the storage area for string representation.
+ * @param value   The value to convert to decimal string
+ *
+ * @return     The length of the converted string (excluding terminator if
+ *             any), or 0 if an error occurred.
+ */
+uint8_t u8_to_dec(char *buf, uint8_t buflen, uint8_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+/** @brief Number of bytes in @p x kibibytes */
+#ifdef _LINKER
+/* This is used in linker scripts so need to avoid type casting there */
+#define KB(x) ((x) << 10)
+#else
+#define KB(x) (((size_t)x) << 10)
+#endif
+/** @brief Number of bytes in @p x mebibytes */
+#define MB(x) (KB(x) << 10)
+/** @brief Number of bytes in @p x gibibytes */
+#define GB(x) (MB(x) << 10)
+
+/** @brief Number of Hz in @p x kHz */
+#define KHZ(x) ((x) * 1000)
+/** @brief Number of Hz in @p x MHz */
+#define MHZ(x) (KHZ(x) * 1000)
+
+/**
+ * @}
+ */
+
+#endif /* ZEPHYR_INCLUDE_SYS_UTIL_H_ */
diff --git a/src/include/sys/util_internal.h b/src/include/sys/util_internal.h
new file mode 100644
index 0000000000..45fd7af576
--- /dev/null
+++ b/src/include/sys/util_internal.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ * Copyright (c) 2020, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Misc utilities
+ *
+ * Repetitive or obscure helper macros needed by sys/util.h.
+ */
+
+#ifndef ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_H_
+#define ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_H_
+
+#include "util_loops.h"
+
+/* IS_ENABLED() helpers */
+
+/* This is called from IS_ENABLED(), and sticks on a "_XXXX" prefix,
+ * it will now be "_XXXX1" if config_macro is "1", or just "_XXXX" if it's
+ * undefined.
+ *   ENABLED:   Z_IS_ENABLED2(_XXXX1)
+ *   DISABLED   Z_IS_ENABLED2(_XXXX)
+ */
+#define Z_IS_ENABLED1(config_macro) Z_IS_ENABLED2(_XXXX##config_macro)
+
+/* Here's the core trick, we map "_XXXX1" to "_YYYY," (i.e. a string
+ * with a trailing comma), so it has the effect of making this a
+ * two-argument tuple to the preprocessor only in the case where the
+ * value is defined to "1"
+ *   ENABLED:    _YYYY,    <--- note comma!
+ *   DISABLED:   _XXXX
+ */
+#define _XXXX1 _YYYY,
+
+/* Then we append an extra argument to fool the gcc preprocessor into
+ * accepting it as a varargs macro.
+ *                         arg1   arg2  arg3
+ *   ENABLED:   Z_IS_ENABLED3(_YYYY,    1,    0)
+ *   DISABLED   Z_IS_ENABLED3(_XXXX 1,  0)
+ */
+#define Z_IS_ENABLED2(one_or_two_args) Z_IS_ENABLED3(one_or_two_args 1, 0)
+
+/* And our second argument is thus now cooked to be 1 in the case
+ * where the value is defined to 1, and 0 if not:
+ */
+#define Z_IS_ENABLED3(ignore_this, val, ...) val
+
+/* Used internally by COND_CODE_1 and COND_CODE_0. */
+#define Z_COND_CODE_1(_flag, _if_1_code, _else_code) \
+	__COND_CODE(_XXXX##_flag, _if_1_code, _else_code)
+#define Z_COND_CODE_0(_flag, _if_0_code, _else_code) \
+	__COND_CODE(_ZZZZ##_flag, _if_0_code, _else_code)
+#define _ZZZZ0 _YYYY,
+#define __COND_CODE(one_or_two_args, _if_code, _else_code) \
+	__GET_ARG2_DEBRACKET(one_or_two_args _if_code, _else_code)
+
+/* Gets second argument and removes brackets around that argument. It
+ * is expected that the parameter is provided in brackets/parentheses.
+ */
+#define __GET_ARG2_DEBRACKET(ignore_this, val, ...) __DEBRACKET val
+
+/* Used to remove brackets from around a single argument. */
+#define __DEBRACKET(...) __VA_ARGS__
+
+/* Used by IS_EMPTY() */
+/* reference: https://gustedt.wordpress.com/2010/06/08/detect-empty-macro-arguments/ */
+#define Z_HAS_COMMA(...) \
+	NUM_VA_ARGS_LESS_1_IMPL(__VA_ARGS__, 1, 1, 1, 1, 1, 1, 1, 1, \
+	 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+	 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+	 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0)
+#define Z_TRIGGER_PARENTHESIS_(...) ,
+#define Z_IS_EMPTY_(...) \
+	Z_IS_EMPTY__( \
+		Z_HAS_COMMA(__VA_ARGS__), \
+		Z_HAS_COMMA(Z_TRIGGER_PARENTHESIS_ __VA_ARGS__), \
+		Z_HAS_COMMA(__VA_ARGS__ (/*empty*/)), \
+		Z_HAS_COMMA(Z_TRIGGER_PARENTHESIS_ __VA_ARGS__ (/*empty*/)))
+#define Z_CAT5(_0, _1, _2, _3, _4) _0 ## _1 ## _2 ## _3 ## _4
+#define Z_IS_EMPTY__(_0, _1, _2, _3) \
+	Z_HAS_COMMA(Z_CAT5(Z_IS_EMPTY_CASE_, _0, _1, _2, _3))
+#define Z_IS_EMPTY_CASE_0001 ,
+
+/* Used by LIST_DROP_EMPTY() */
+/* Adding ',' after each element would add empty element at the end of
+ * list, which is hard to remove, so instead precede each element with ',',
+ * this way first element is empty, and this one is easy to drop.
+ */
+#define Z_LIST_ADD_ELEM(e) EMPTY, e
+#define Z_LIST_DROP_FIRST(...) GET_ARGS_LESS_N(1, __VA_ARGS__)
+#define Z_LIST_NO_EMPTIES(e) \
+	COND_CODE_1(IS_EMPTY(e), (), (Z_LIST_ADD_ELEM(e)))
+
+#define UTIL_CAT(a, ...) UTIL_PRIMITIVE_CAT(a, __VA_ARGS__)
+#define UTIL_PRIMITIVE_CAT(a, ...) a##__VA_ARGS__
+#define UTIL_CHECK_N(x, n, ...) n
+#define UTIL_CHECK(...) UTIL_CHECK_N(__VA_ARGS__, 0,)
+#define UTIL_NOT(x) UTIL_CHECK(UTIL_PRIMITIVE_CAT(UTIL_NOT_, x))
+#define UTIL_NOT_0 ~, 1,
+#define UTIL_COMPL(b) UTIL_PRIMITIVE_CAT(UTIL_COMPL_, b)
+#define UTIL_COMPL_0 1
+#define UTIL_COMPL_1 0
+#define UTIL_BOOL(x) UTIL_COMPL(UTIL_NOT(x))
+
+#define UTIL_EVAL(...) __VA_ARGS__
+#define UTIL_EXPAND(...) __VA_ARGS__
+#define UTIL_REPEAT(...) UTIL_LISTIFY(__VA_ARGS__)
+
+/* Implementation details for NUM_VA_ARGS_LESS_1 */
+#define NUM_VA_ARGS_LESS_1_IMPL(				\
+	_ignored,						\
+	_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10,		\
+	_11, _12, _13, _14, _15, _16, _17, _18, _19, _20,	\
+	_21, _22, _23, _24, _25, _26, _27, _28, _29, _30,	\
+	_31, _32, _33, _34, _35, _36, _37, _38, _39, _40,	\
+	_41, _42, _43, _44, _45, _46, _47, _48, _49, _50,	\
+	_51, _52, _53, _54, _55, _56, _57, _58, _59, _60,	\
+	_61, _62, N, ...) N
+
+/* Used by MACRO_MAP_CAT */
+#define MACRO_MAP_CAT_(...)						\
+	/* To make sure it works also for 2 arguments in total */	\
+	MACRO_MAP_CAT_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__)
+#define MACRO_MAP_CAT_N_(N, ...) UTIL_CAT(MACRO_MC_, N)(__VA_ARGS__,)
+#define MACRO_MC_0(...)
+#define MACRO_MC_1(m, a, ...)  m(a)
+#define MACRO_MC_2(m, a, ...)  UTIL_CAT(m(a), MACRO_MC_1(m, __VA_ARGS__,))
+#define MACRO_MC_3(m, a, ...)  UTIL_CAT(m(a), MACRO_MC_2(m, __VA_ARGS__,))
+#define MACRO_MC_4(m, a, ...)  UTIL_CAT(m(a), MACRO_MC_3(m, __VA_ARGS__,))
+#define MACRO_MC_5(m, a, ...)  UTIL_CAT(m(a), MACRO_MC_4(m, __VA_ARGS__,))
+#define MACRO_MC_6(m, a, ...)  UTIL_CAT(m(a), MACRO_MC_5(m, __VA_ARGS__,))
+#define MACRO_MC_7(m, a, ...)  UTIL_CAT(m(a), MACRO_MC_6(m, __VA_ARGS__,))
+#define MACRO_MC_8(m, a, ...)  UTIL_CAT(m(a), MACRO_MC_7(m, __VA_ARGS__,))
+#define MACRO_MC_9(m, a, ...)  UTIL_CAT(m(a), MACRO_MC_8(m, __VA_ARGS__,))
+#define MACRO_MC_10(m, a, ...) UTIL_CAT(m(a), MACRO_MC_9(m, __VA_ARGS__,))
+#define MACRO_MC_11(m, a, ...) UTIL_CAT(m(a), MACRO_MC_10(m, __VA_ARGS__,))
+#define MACRO_MC_12(m, a, ...) UTIL_CAT(m(a), MACRO_MC_11(m, __VA_ARGS__,))
+#define MACRO_MC_13(m, a, ...) UTIL_CAT(m(a), MACRO_MC_12(m, __VA_ARGS__,))
+#define MACRO_MC_14(m, a, ...) UTIL_CAT(m(a), MACRO_MC_13(m, __VA_ARGS__,))
+#define MACRO_MC_15(m, a, ...) UTIL_CAT(m(a), MACRO_MC_14(m, __VA_ARGS__,))
+
+#endif /* ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_H_ */
diff --git a/src/include/sys/util_loops.h b/src/include/sys/util_loops.h
new file mode 100644
index 0000000000..7b2e1281ec
--- /dev/null
+++ b/src/include/sys/util_loops.h
@@ -0,0 +1,2108 @@
+/*
+ * Copyright (c) 2021, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Internals for looping macros
+ *
+ * Repetitive or obscure helper macros needed by sys/util.h.
+ */
+
+#ifndef ZEPHYR_INCLUDE_SYS_UTIL_LOOPS_H_
+#define ZEPHYR_INCLUDE_SYS_UTIL_LOOPS_H_
+
+#define Z_FOR_LOOP_GET_ARG(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, \
+				_12, _13, _14, _15, _16, _17, _18, _19, _20, \
+				_21, _22, _23, _24, _25, _26, _27, _28, _29, \
+				_30, _31, _32, _33, _34, _35, _36, _37, _38, \
+				_39, _40, _41, _42, _43, _44, _45, _46, _47, \
+				_48, _49, _50, _51, _52, _53, _54, _55, _56, \
+				_57, _58, _59, _60, _61, _62, _63, _64, N, ...) N
+
+#define Z_FOR_LOOP_0(z_call, sep, fixed_arg0, fixed_arg1, ...)
+
+#define Z_FOR_LOOP_1(z_call, sep, fixed_arg0, fixed_arg1, x) \
+	z_call(0, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_2(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_1(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(1, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_3(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_2(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(2, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_4(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_3(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(3, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_5(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_4(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(4, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_6(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_5(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(5, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_7(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_6(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(6, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_8(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_7(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(7, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_9(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_8(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(8, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_10(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_9(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(9, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_11(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_10(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(10, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_12(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_11(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(11, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_13(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_12(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(12, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_14(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_13(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(13, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_15(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_14(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(14, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_16(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_15(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(15, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_17(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_16(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(16, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_18(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_17(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(17, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_19(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_18(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(18, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_20(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_19(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(19, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_21(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_20(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(20, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_22(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_21(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(21, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_23(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_22(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(22, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_24(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_23(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(23, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_25(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_24(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(24, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_26(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_25(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(25, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_27(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_26(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(26, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_28(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_27(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(27, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_29(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_28(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(28, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_30(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_29(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(29, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_31(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_30(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(30, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_32(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_31(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(31, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_33(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_32(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(32, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_34(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_33(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(33, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_35(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_34(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(34, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_36(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_35(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(35, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_37(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_36(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(36, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_38(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_37(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(37, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_39(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_38(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(38, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_40(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_39(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(39, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_41(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_40(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(40, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_42(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_41(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(41, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_43(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_42(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(42, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_44(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_43(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(43, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_45(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_44(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(44, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_46(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_45(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(45, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_47(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_46(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(46, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_48(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_47(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(47, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_49(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_48(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(48, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_50(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_49(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(49, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_51(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_50(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(50, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_52(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_51(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(51, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_53(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_52(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(52, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_54(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_53(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(53, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_55(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_54(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(54, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_56(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_55(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(55, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_57(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_56(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(56, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_58(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_57(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(57, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_59(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_58(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(58, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_60(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_59(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(59, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_61(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_60(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(60, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_62(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_61(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(61, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_63(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_62(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(62, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_LOOP_64(z_call, sep, fixed_arg0, fixed_arg1, x, ...) \
+	Z_FOR_LOOP_63(z_call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+	__DEBRACKET sep \
+	z_call(63, x, fixed_arg0, fixed_arg1)
+
+#define Z_FOR_EACH_ENGINE(x, sep, fixed_arg0, fixed_arg1, ...) \
+	Z_FOR_LOOP_GET_ARG(__VA_ARGS__, \
+		Z_FOR_LOOP_64, \
+		Z_FOR_LOOP_63, \
+		Z_FOR_LOOP_62, \
+		Z_FOR_LOOP_61, \
+		Z_FOR_LOOP_60, \
+		Z_FOR_LOOP_59, \
+		Z_FOR_LOOP_58, \
+		Z_FOR_LOOP_57, \
+		Z_FOR_LOOP_56, \
+		Z_FOR_LOOP_55, \
+		Z_FOR_LOOP_54, \
+		Z_FOR_LOOP_53, \
+		Z_FOR_LOOP_52, \
+		Z_FOR_LOOP_51, \
+		Z_FOR_LOOP_50, \
+		Z_FOR_LOOP_49, \
+		Z_FOR_LOOP_48, \
+		Z_FOR_LOOP_47, \
+		Z_FOR_LOOP_46, \
+		Z_FOR_LOOP_45, \
+		Z_FOR_LOOP_44, \
+		Z_FOR_LOOP_43, \
+		Z_FOR_LOOP_42, \
+		Z_FOR_LOOP_41, \
+		Z_FOR_LOOP_40, \
+		Z_FOR_LOOP_39, \
+		Z_FOR_LOOP_38, \
+		Z_FOR_LOOP_37, \
+		Z_FOR_LOOP_36, \
+		Z_FOR_LOOP_35, \
+		Z_FOR_LOOP_34, \
+		Z_FOR_LOOP_33, \
+		Z_FOR_LOOP_32, \
+		Z_FOR_LOOP_31, \
+		Z_FOR_LOOP_30, \
+		Z_FOR_LOOP_29, \
+		Z_FOR_LOOP_28, \
+		Z_FOR_LOOP_27, \
+		Z_FOR_LOOP_26, \
+		Z_FOR_LOOP_25, \
+		Z_FOR_LOOP_24, \
+		Z_FOR_LOOP_23, \
+		Z_FOR_LOOP_22, \
+		Z_FOR_LOOP_21, \
+		Z_FOR_LOOP_20, \
+		Z_FOR_LOOP_19, \
+		Z_FOR_LOOP_18, \
+		Z_FOR_LOOP_17, \
+		Z_FOR_LOOP_16, \
+		Z_FOR_LOOP_15, \
+		Z_FOR_LOOP_14, \
+		Z_FOR_LOOP_13, \
+		Z_FOR_LOOP_12, \
+		Z_FOR_LOOP_11, \
+		Z_FOR_LOOP_10, \
+		Z_FOR_LOOP_9, \
+		Z_FOR_LOOP_8, \
+		Z_FOR_LOOP_7, \
+		Z_FOR_LOOP_6, \
+		Z_FOR_LOOP_5, \
+		Z_FOR_LOOP_4, \
+		Z_FOR_LOOP_3, \
+		Z_FOR_LOOP_2, \
+		Z_FOR_LOOP_1, \
+		Z_FOR_LOOP_0)(x, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__)
+
+#define Z_GET_ARG_1(_0, ...) _0
+
+#define Z_GET_ARG_2(_0, _1, ...) _1
+
+#define Z_GET_ARG_3(_0, _1, _2, ...) _2
+
+#define Z_GET_ARG_4(_0, _1, _2, _3, ...) _3
+
+#define Z_GET_ARG_5(_0, _1, _2, _3, _4, ...) _4
+
+#define Z_GET_ARG_6(_0, _1, _2, _3, _4, _5, ...) _5
+
+#define Z_GET_ARG_7(_0, _1, _2, _3, _4, _5, _6, ...) _6
+
+#define Z_GET_ARG_8(_0, _1, _2, _3, _4, _5, _6, _7, ...) _7
+
+#define Z_GET_ARG_9(_0, _1, _2, _3, _4, _5, _6, _7, _8, ...) _8
+
+#define Z_GET_ARG_10(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, ...) _9
+
+#define Z_GET_ARG_11(_0, _1, _2, _3, _4, _5, \
+			  _6, _7, _8, _9, _10, ...) _10
+
+#define Z_GET_ARG_12(_0, _1, _2, _3, _4, _5, _6,\
+			  _7, _8, _9, _10, _11, ...) _11
+
+#define Z_GET_ARG_13(_0, _1, _2, _3, _4, _5, _6, \
+			  _7, _8, _9, _10, _11, _12, ...) _12
+
+#define Z_GET_ARG_14(_0, _1, _2, _3, _4, _5, _6, \
+			  _7, _8, _9, _10, _11, _12, _13, ...) _13
+
+#define Z_GET_ARG_15(_0, _1, _2, _3, _4, _5, _6, _7, \
+			  _8, _9, _10, _11, _12, _13, _14, ...) _14
+
+#define Z_GET_ARG_16(_0, _1, _2, _3, _4, _5, _6, _7, \
+			  _8, _9, _10, _11, _12, _13, _14, _15, ...) _15
+
+#define Z_GET_ARG_17(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, ...) _16
+
+#define Z_GET_ARG_18(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, ...) _17
+
+#define Z_GET_ARG_19(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, ...) _18
+
+#define Z_GET_ARG_20(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  ...) _19
+
+#define Z_GET_ARG_21(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, ...) _20
+
+#define Z_GET_ARG_22(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, ...) _21
+
+#define Z_GET_ARG_23(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, ...) _22
+
+#define Z_GET_ARG_24(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, ...) _23
+
+#define Z_GET_ARG_25(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, ...) _24
+
+#define Z_GET_ARG_26(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, ...) _25
+
+#define Z_GET_ARG_27(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, ...) _26
+
+#define Z_GET_ARG_28(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, ...) _27
+
+#define Z_GET_ARG_29(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  ...) _28
+
+#define Z_GET_ARG_30(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, ...) _29
+
+#define Z_GET_ARG_31(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, ...) _30
+
+#define Z_GET_ARG_32(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, ...) _31
+
+#define Z_GET_ARG_33(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, ...) _32
+
+#define Z_GET_ARG_34(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, ...) _33
+
+#define Z_GET_ARG_35(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, ...) _34
+
+#define Z_GET_ARG_36(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, ...) _35
+
+#define Z_GET_ARG_37(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, ...) _36
+
+#define Z_GET_ARG_38(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, ...) _37
+
+#define Z_GET_ARG_39(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, ...) _38
+
+#define Z_GET_ARG_40(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, ...) _39
+
+#define Z_GET_ARG_41(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, ...) _40
+
+#define Z_GET_ARG_42(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, ...) _41
+
+#define Z_GET_ARG_43(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, ...) _42
+
+#define Z_GET_ARG_44(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, ...) _43
+
+#define Z_GET_ARG_45(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, ...) _44
+
+#define Z_GET_ARG_46(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, ...) _45
+
+#define Z_GET_ARG_47(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, ...) _46
+
+#define Z_GET_ARG_48(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, ...) _47
+
+#define Z_GET_ARG_49(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, ...) _48
+
+#define Z_GET_ARG_50(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, ...) _49
+
+#define Z_GET_ARG_51(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, ...) _50
+
+#define Z_GET_ARG_52(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, ...) _51
+
+#define Z_GET_ARG_53(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, ...) _52
+
+#define Z_GET_ARG_54(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, ...) _53
+
+#define Z_GET_ARG_55(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, ...) _54
+
+#define Z_GET_ARG_56(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, ...) _55
+
+#define Z_GET_ARG_57(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, \
+			  _56, ...) _56
+
+#define Z_GET_ARG_58(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, \
+			  _56, _57, ...) _57
+
+#define Z_GET_ARG_59(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, \
+			  _56, _57, _58, ...) _58
+
+#define Z_GET_ARG_60(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, \
+			  _56, _57, _58, _59, ...) _59
+
+#define Z_GET_ARG_61(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, \
+			  _56, _57, _58, _59, _60, ...) _60
+
+#define Z_GET_ARG_62(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, \
+			  _56, _57, _58, _59, _60, _61, ...) _61
+
+#define Z_GET_ARG_63(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, \
+			  _56, _57, _58, _59, _60, _61, _62, ...) _62
+
+#define Z_GET_ARG_64(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+			  _11, _12, _13, _14, _15, _16, _17, _18, _19, \
+			  _20, _21, _22, _23, _24, _25, _26, _27, _28, \
+			  _29, _30, _31, _32, _33, _34, _35, _36, _37, \
+			  _38, _39, _40, _41, _42, _43, _44, _45, _46, \
+			  _47, _48, _49, _50, _51, _52, _53, _54, _55, \
+			  _56, _57, _58, _59, _60, _61, _62, _63, ...) _63
+
+#define Z_GET_ARGS_LESS_0(...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_1(_0, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_2(_0, _1, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_3(_0, _1, _2, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_4(_0, _1, _2, _3, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_5(_0, _1, _2, _3, _4, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_6(_0, _1, _2, _3, _4, _5, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_7(_0, _1, _2, _3, _4, _5, _6, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_8(_0, _1, _2, _3, _4, _5, \
+				_6, _7, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_9(_0, _1, _2, _3, _4, _5, \
+				_6, _7, _8, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_10(_0, _1, _2, _3, _4, _5, \
+				_6, _7, _8, _9, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_11(_0, _1, _2, _3, _4, _5, \
+				_6, _7, _8, _9, _10, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_12(_0, _1, _2, _3, _4, _5, _6,\
+				_7, _8, _9, _10, _11, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_13(_0, _1, _2, _3, _4, _5, _6, \
+				_7, _8, _9, _10, _11, _12, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_14(_0, _1, _2, _3, _4, _5, _6, \
+				_7, _8, _9, _10, _11, _12, _13, \
+				...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_15(_0, _1, _2, _3, _4, _5, _6, _7, \
+				_8, _9, _10, _11, _12, _13, _14, \
+				...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_16(_0, _1, _2, _3, _4, _5, _6, _7, \
+				_8, _9, _10, _11, _12, _13, _14, _15, ...) \
+				__VA_ARGS__
+
+#define Z_GET_ARGS_LESS_17(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_18(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, ...) \
+				__VA_ARGS__
+
+#define Z_GET_ARGS_LESS_19(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, ...) \
+				__VA_ARGS__
+
+#define Z_GET_ARGS_LESS_20(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_21(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_22(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_23(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_24(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_25(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_26(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_27(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, ...) \
+				__VA_ARGS__
+
+#define Z_GET_ARGS_LESS_28(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, \
+				...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_29(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_30(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_31(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_32(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_33(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_34(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_35(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_36(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_37(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_38(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_39(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_40(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_41(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_42(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_43(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_44(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_45(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_46(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_47(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_48(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_49(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_50(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_51(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_52(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_53(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_54(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_55(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_56(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_57(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				_56, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_58(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				_56, _57, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_59(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				_56, _57, _58, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_60(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				_56, _57, _58, _59, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_61(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				_56, _57, _58, _59, _60, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_62(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				_56, _57, _58, _59, _60, _61, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_63(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				_56, _57, _58, _59, _60, _61, _62, ...) __VA_ARGS__
+
+#define Z_GET_ARGS_LESS_64(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
+				_11, _12, _13, _14, _15, _16, _17, _18, _19, \
+				_20, _21, _22, _23, _24, _25, _26, _27, _28, \
+				_29, _30, _31, _32, _33, _34, _35, _36, _37, \
+				_38, _39, _40, _41, _42, _43, _44, _45, _46, \
+				_47, _48, _49, _50, _51, _52, _53, _54, _55, \
+				_56, _57, _58, _59, _60, _61, _62, _63, ...) __VA_ARGS__
+
+#define Z_FOR_EACH_IDX_FIXED_ARG_EXEC(idx, x, fixed_arg0, fixed_arg1) \
+	fixed_arg0(idx, x, fixed_arg1)
+
+#define Z_FOR_EACH_IDX_FIXED_ARG(F, sep, fixed_arg, ...) \
+	Z_FOR_EACH_ENGINE(Z_FOR_EACH_IDX_FIXED_ARG_EXEC, sep, \
+			     F, fixed_arg, __VA_ARGS__)
+
+#define Z_FOR_EACH_FIXED_ARG_EXEC(idx, x, fixed_arg0, fixed_arg1) \
+	fixed_arg0(x, fixed_arg1)
+
+#define Z_FOR_EACH_FIXED_ARG(F, sep, fixed_arg, ...) \
+	Z_FOR_EACH_ENGINE(Z_FOR_EACH_FIXED_ARG_EXEC, sep, \
+			     F, fixed_arg, __VA_ARGS__)
+
+#define Z_FOR_EACH_IDX_EXEC(idx, x, fixed_arg0, fixed_arg1) \
+	fixed_arg0(idx, x)
+
+#define Z_FOR_EACH_IDX(F, sep, ...) \
+	Z_FOR_EACH_ENGINE(Z_FOR_EACH_IDX_EXEC, sep, F, _, __VA_ARGS__)
+
+#define Z_FOR_EACH_EXEC(idx, x, fixed_arg0, fixed_arg1) \
+	fixed_arg0(x)
+
+#define Z_FOR_EACH(F, sep, ...) \
+	Z_FOR_EACH_ENGINE(Z_FOR_EACH_EXEC, sep, F, _, __VA_ARGS__)
+
+#define Z_BYPASS(x) x
+
+/* Set of UTIL_LISTIFY particles */
+#define Z_UTIL_LISTIFY_0(F, ...)
+
+#define Z_UTIL_LISTIFY_1(F, ...) \
+	F(0, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_2(F, ...) \
+	Z_UTIL_LISTIFY_1(F, __VA_ARGS__) \
+	F(1, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_3(F, ...) \
+	Z_UTIL_LISTIFY_2(F, __VA_ARGS__) \
+	F(2, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_4(F, ...) \
+	Z_UTIL_LISTIFY_3(F, __VA_ARGS__) \
+	F(3, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_5(F, ...) \
+	Z_UTIL_LISTIFY_4(F, __VA_ARGS__) \
+	F(4, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_6(F, ...) \
+	Z_UTIL_LISTIFY_5(F, __VA_ARGS__) \
+	F(5, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_7(F, ...) \
+	Z_UTIL_LISTIFY_6(F, __VA_ARGS__) \
+	F(6, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_8(F, ...) \
+	Z_UTIL_LISTIFY_7(F, __VA_ARGS__) \
+	F(7, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_9(F, ...) \
+	Z_UTIL_LISTIFY_8(F, __VA_ARGS__) \
+	F(8, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_10(F, ...) \
+	Z_UTIL_LISTIFY_9(F, __VA_ARGS__) \
+	F(9, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_11(F, ...) \
+	Z_UTIL_LISTIFY_10(F, __VA_ARGS__) \
+	F(10, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_12(F, ...) \
+	Z_UTIL_LISTIFY_11(F, __VA_ARGS__) \
+	F(11, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_13(F, ...) \
+	Z_UTIL_LISTIFY_12(F, __VA_ARGS__) \
+	F(12, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_14(F, ...) \
+	Z_UTIL_LISTIFY_13(F, __VA_ARGS__) \
+	F(13, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_15(F, ...) \
+	Z_UTIL_LISTIFY_14(F, __VA_ARGS__) \
+	F(14, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_16(F, ...) \
+	Z_UTIL_LISTIFY_15(F, __VA_ARGS__) \
+	F(15, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_17(F, ...) \
+	Z_UTIL_LISTIFY_16(F, __VA_ARGS__) \
+	F(16, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_18(F, ...) \
+	Z_UTIL_LISTIFY_17(F, __VA_ARGS__) \
+	F(17, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_19(F, ...) \
+	Z_UTIL_LISTIFY_18(F, __VA_ARGS__) \
+	F(18, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_20(F, ...) \
+	Z_UTIL_LISTIFY_19(F, __VA_ARGS__) \
+	F(19, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_21(F, ...) \
+	Z_UTIL_LISTIFY_20(F, __VA_ARGS__) \
+	F(20, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_22(F, ...) \
+	Z_UTIL_LISTIFY_21(F, __VA_ARGS__) \
+	F(21, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_23(F, ...) \
+	Z_UTIL_LISTIFY_22(F, __VA_ARGS__) \
+	F(22, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_24(F, ...) \
+	Z_UTIL_LISTIFY_23(F, __VA_ARGS__) \
+	F(23, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_25(F, ...) \
+	Z_UTIL_LISTIFY_24(F, __VA_ARGS__) \
+	F(24, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_26(F, ...) \
+	Z_UTIL_LISTIFY_25(F, __VA_ARGS__) \
+	F(25, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_27(F, ...) \
+	Z_UTIL_LISTIFY_26(F, __VA_ARGS__) \
+	F(26, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_28(F, ...) \
+	Z_UTIL_LISTIFY_27(F, __VA_ARGS__) \
+	F(27, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_29(F, ...) \
+	Z_UTIL_LISTIFY_28(F, __VA_ARGS__) \
+	F(28, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_30(F, ...) \
+	Z_UTIL_LISTIFY_29(F, __VA_ARGS__) \
+	F(29, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_31(F, ...) \
+	Z_UTIL_LISTIFY_30(F, __VA_ARGS__) \
+	F(30, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_32(F, ...) \
+	Z_UTIL_LISTIFY_31(F, __VA_ARGS__) \
+	F(31, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_33(F, ...) \
+	Z_UTIL_LISTIFY_32(F, __VA_ARGS__) \
+	F(32, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_34(F, ...) \
+	Z_UTIL_LISTIFY_33(F, __VA_ARGS__) \
+	F(33, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_35(F, ...) \
+	Z_UTIL_LISTIFY_34(F, __VA_ARGS__) \
+	F(34, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_36(F, ...) \
+	Z_UTIL_LISTIFY_35(F, __VA_ARGS__) \
+	F(35, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_37(F, ...) \
+	Z_UTIL_LISTIFY_36(F, __VA_ARGS__) \
+	F(36, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_38(F, ...) \
+	Z_UTIL_LISTIFY_37(F, __VA_ARGS__) \
+	F(37, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_39(F, ...) \
+	Z_UTIL_LISTIFY_38(F, __VA_ARGS__) \
+	F(38, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_40(F, ...) \
+	Z_UTIL_LISTIFY_39(F, __VA_ARGS__) \
+	F(39, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_41(F, ...) \
+	Z_UTIL_LISTIFY_40(F, __VA_ARGS__) \
+	F(40, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_42(F, ...) \
+	Z_UTIL_LISTIFY_41(F, __VA_ARGS__) \
+	F(41, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_43(F, ...) \
+	Z_UTIL_LISTIFY_42(F, __VA_ARGS__) \
+	F(42, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_44(F, ...) \
+	Z_UTIL_LISTIFY_43(F, __VA_ARGS__) \
+	F(43, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_45(F, ...) \
+	Z_UTIL_LISTIFY_44(F, __VA_ARGS__) \
+	F(44, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_46(F, ...) \
+	Z_UTIL_LISTIFY_45(F, __VA_ARGS__) \
+	F(45, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_47(F, ...) \
+	Z_UTIL_LISTIFY_46(F, __VA_ARGS__) \
+	F(46, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_48(F, ...) \
+	Z_UTIL_LISTIFY_47(F, __VA_ARGS__) \
+	F(47, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_49(F, ...) \
+	Z_UTIL_LISTIFY_48(F, __VA_ARGS__) \
+	F(48, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_50(F, ...) \
+	Z_UTIL_LISTIFY_49(F, __VA_ARGS__) \
+	F(49, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_51(F, ...) \
+	Z_UTIL_LISTIFY_50(F, __VA_ARGS__) \
+	F(50, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_52(F, ...) \
+	Z_UTIL_LISTIFY_51(F, __VA_ARGS__) \
+	F(51, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_53(F, ...) \
+	Z_UTIL_LISTIFY_52(F, __VA_ARGS__) \
+	F(52, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_54(F, ...) \
+	Z_UTIL_LISTIFY_53(F, __VA_ARGS__) \
+	F(53, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_55(F, ...) \
+	Z_UTIL_LISTIFY_54(F, __VA_ARGS__) \
+	F(54, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_56(F, ...) \
+	Z_UTIL_LISTIFY_55(F, __VA_ARGS__) \
+	F(55, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_57(F, ...) \
+	Z_UTIL_LISTIFY_56(F, __VA_ARGS__) \
+	F(56, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_58(F, ...) \
+	Z_UTIL_LISTIFY_57(F, __VA_ARGS__) \
+	F(57, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_59(F, ...) \
+	Z_UTIL_LISTIFY_58(F, __VA_ARGS__) \
+	F(58, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_60(F, ...) \
+	Z_UTIL_LISTIFY_59(F, __VA_ARGS__) \
+	F(59, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_61(F, ...) \
+	Z_UTIL_LISTIFY_60(F, __VA_ARGS__) \
+	F(60, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_62(F, ...) \
+	Z_UTIL_LISTIFY_61(F, __VA_ARGS__) \
+	F(61, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_63(F, ...) \
+	Z_UTIL_LISTIFY_62(F, __VA_ARGS__) \
+	F(62, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_64(F, ...) \
+	Z_UTIL_LISTIFY_63(F, __VA_ARGS__) \
+	F(63, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_65(F, ...) \
+	Z_UTIL_LISTIFY_64(F, __VA_ARGS__) \
+	F(64, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_66(F, ...) \
+	Z_UTIL_LISTIFY_65(F, __VA_ARGS__) \
+	F(65, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_67(F, ...) \
+	Z_UTIL_LISTIFY_66(F, __VA_ARGS__) \
+	F(66, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_68(F, ...) \
+	Z_UTIL_LISTIFY_67(F, __VA_ARGS__) \
+	F(67, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_69(F, ...) \
+	Z_UTIL_LISTIFY_68(F, __VA_ARGS__) \
+	F(68, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_70(F, ...) \
+	Z_UTIL_LISTIFY_69(F, __VA_ARGS__) \
+	F(69, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_71(F, ...) \
+	Z_UTIL_LISTIFY_70(F, __VA_ARGS__) \
+	F(70, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_72(F, ...) \
+	Z_UTIL_LISTIFY_71(F, __VA_ARGS__) \
+	F(71, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_73(F, ...) \
+	Z_UTIL_LISTIFY_72(F, __VA_ARGS__) \
+	F(72, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_74(F, ...) \
+	Z_UTIL_LISTIFY_73(F, __VA_ARGS__) \
+	F(73, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_75(F, ...) \
+	Z_UTIL_LISTIFY_74(F, __VA_ARGS__) \
+	F(74, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_76(F, ...) \
+	Z_UTIL_LISTIFY_75(F, __VA_ARGS__) \
+	F(75, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_77(F, ...) \
+	Z_UTIL_LISTIFY_76(F, __VA_ARGS__) \
+	F(76, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_78(F, ...) \
+	Z_UTIL_LISTIFY_77(F, __VA_ARGS__) \
+	F(77, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_79(F, ...) \
+	Z_UTIL_LISTIFY_78(F, __VA_ARGS__) \
+	F(78, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_80(F, ...) \
+	Z_UTIL_LISTIFY_79(F, __VA_ARGS__) \
+	F(79, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_81(F, ...) \
+	Z_UTIL_LISTIFY_80(F, __VA_ARGS__) \
+	F(80, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_82(F, ...) \
+	Z_UTIL_LISTIFY_81(F, __VA_ARGS__) \
+	F(81, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_83(F, ...) \
+	Z_UTIL_LISTIFY_82(F, __VA_ARGS__) \
+	F(82, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_84(F, ...) \
+	Z_UTIL_LISTIFY_83(F, __VA_ARGS__) \
+	F(83, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_85(F, ...) \
+	Z_UTIL_LISTIFY_84(F, __VA_ARGS__) \
+	F(84, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_86(F, ...) \
+	Z_UTIL_LISTIFY_85(F, __VA_ARGS__) \
+	F(85, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_87(F, ...) \
+	Z_UTIL_LISTIFY_86(F, __VA_ARGS__) \
+	F(86, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_88(F, ...) \
+	Z_UTIL_LISTIFY_87(F, __VA_ARGS__) \
+	F(87, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_89(F, ...) \
+	Z_UTIL_LISTIFY_88(F, __VA_ARGS__) \
+	F(88, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_90(F, ...) \
+	Z_UTIL_LISTIFY_89(F, __VA_ARGS__) \
+	F(89, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_91(F, ...) \
+	Z_UTIL_LISTIFY_90(F, __VA_ARGS__) \
+	F(90, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_92(F, ...) \
+	Z_UTIL_LISTIFY_91(F, __VA_ARGS__) \
+	F(91, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_93(F, ...) \
+	Z_UTIL_LISTIFY_92(F, __VA_ARGS__) \
+	F(92, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_94(F, ...) \
+	Z_UTIL_LISTIFY_93(F, __VA_ARGS__) \
+	F(93, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_95(F, ...) \
+	Z_UTIL_LISTIFY_94(F, __VA_ARGS__) \
+	F(94, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_96(F, ...) \
+	Z_UTIL_LISTIFY_95(F, __VA_ARGS__) \
+	F(95, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_97(F, ...) \
+	Z_UTIL_LISTIFY_96(F, __VA_ARGS__) \
+	F(96, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_98(F, ...) \
+	Z_UTIL_LISTIFY_97(F, __VA_ARGS__) \
+	F(97, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_99(F, ...) \
+	Z_UTIL_LISTIFY_98(F, __VA_ARGS__) \
+	F(98, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_100(F, ...) \
+	Z_UTIL_LISTIFY_99(F, __VA_ARGS__) \
+	F(99, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_101(F, ...) \
+	Z_UTIL_LISTIFY_100(F, __VA_ARGS__) \
+	F(100, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_102(F, ...) \
+	Z_UTIL_LISTIFY_101(F, __VA_ARGS__) \
+	F(101, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_103(F, ...) \
+	Z_UTIL_LISTIFY_102(F, __VA_ARGS__) \
+	F(102, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_104(F, ...) \
+	Z_UTIL_LISTIFY_103(F, __VA_ARGS__) \
+	F(103, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_105(F, ...) \
+	Z_UTIL_LISTIFY_104(F, __VA_ARGS__) \
+	F(104, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_106(F, ...) \
+	Z_UTIL_LISTIFY_105(F, __VA_ARGS__) \
+	F(105, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_107(F, ...) \
+	Z_UTIL_LISTIFY_106(F, __VA_ARGS__) \
+	F(106, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_108(F, ...) \
+	Z_UTIL_LISTIFY_107(F, __VA_ARGS__) \
+	F(107, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_109(F, ...) \
+	Z_UTIL_LISTIFY_108(F, __VA_ARGS__) \
+	F(108, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_110(F, ...) \
+	Z_UTIL_LISTIFY_109(F, __VA_ARGS__) \
+	F(109, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_111(F, ...) \
+	Z_UTIL_LISTIFY_110(F, __VA_ARGS__) \
+	F(110, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_112(F, ...) \
+	Z_UTIL_LISTIFY_111(F, __VA_ARGS__) \
+	F(111, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_113(F, ...) \
+	Z_UTIL_LISTIFY_112(F, __VA_ARGS__) \
+	F(112, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_114(F, ...) \
+	Z_UTIL_LISTIFY_113(F, __VA_ARGS__) \
+	F(113, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_115(F, ...) \
+	Z_UTIL_LISTIFY_114(F, __VA_ARGS__) \
+	F(114, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_116(F, ...) \
+	Z_UTIL_LISTIFY_115(F, __VA_ARGS__) \
+	F(115, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_117(F, ...) \
+	Z_UTIL_LISTIFY_116(F, __VA_ARGS__) \
+	F(116, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_118(F, ...) \
+	Z_UTIL_LISTIFY_117(F, __VA_ARGS__) \
+	F(117, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_119(F, ...) \
+	Z_UTIL_LISTIFY_118(F, __VA_ARGS__) \
+	F(118, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_120(F, ...) \
+	Z_UTIL_LISTIFY_119(F, __VA_ARGS__) \
+	F(119, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_121(F, ...) \
+	Z_UTIL_LISTIFY_120(F, __VA_ARGS__) \
+	F(120, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_122(F, ...) \
+	Z_UTIL_LISTIFY_121(F, __VA_ARGS__) \
+	F(121, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_123(F, ...) \
+	Z_UTIL_LISTIFY_122(F, __VA_ARGS__) \
+	F(122, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_124(F, ...) \
+	Z_UTIL_LISTIFY_123(F, __VA_ARGS__) \
+	F(123, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_125(F, ...) \
+	Z_UTIL_LISTIFY_124(F, __VA_ARGS__) \
+	F(124, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_126(F, ...) \
+	Z_UTIL_LISTIFY_125(F, __VA_ARGS__) \
+	F(125, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_127(F, ...) \
+	Z_UTIL_LISTIFY_126(F, __VA_ARGS__) \
+	F(126, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_128(F, ...) \
+	Z_UTIL_LISTIFY_127(F, __VA_ARGS__) \
+	F(127, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_129(F, ...) \
+	Z_UTIL_LISTIFY_128(F, __VA_ARGS__) \
+	F(128, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_130(F, ...) \
+	Z_UTIL_LISTIFY_129(F, __VA_ARGS__) \
+	F(129, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_131(F, ...) \
+	Z_UTIL_LISTIFY_130(F, __VA_ARGS__) \
+	F(130, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_132(F, ...) \
+	Z_UTIL_LISTIFY_131(F, __VA_ARGS__) \
+	F(131, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_133(F, ...) \
+	Z_UTIL_LISTIFY_132(F, __VA_ARGS__) \
+	F(132, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_134(F, ...) \
+	Z_UTIL_LISTIFY_133(F, __VA_ARGS__) \
+	F(133, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_135(F, ...) \
+	Z_UTIL_LISTIFY_134(F, __VA_ARGS__) \
+	F(134, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_136(F, ...) \
+	Z_UTIL_LISTIFY_135(F, __VA_ARGS__) \
+	F(135, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_137(F, ...) \
+	Z_UTIL_LISTIFY_136(F, __VA_ARGS__) \
+	F(136, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_138(F, ...) \
+	Z_UTIL_LISTIFY_137(F, __VA_ARGS__) \
+	F(137, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_139(F, ...) \
+	Z_UTIL_LISTIFY_138(F, __VA_ARGS__) \
+	F(138, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_140(F, ...) \
+	Z_UTIL_LISTIFY_139(F, __VA_ARGS__) \
+	F(139, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_141(F, ...) \
+	Z_UTIL_LISTIFY_140(F, __VA_ARGS__) \
+	F(140, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_142(F, ...) \
+	Z_UTIL_LISTIFY_141(F, __VA_ARGS__) \
+	F(141, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_143(F, ...) \
+	Z_UTIL_LISTIFY_142(F, __VA_ARGS__) \
+	F(142, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_144(F, ...) \
+	Z_UTIL_LISTIFY_143(F, __VA_ARGS__) \
+	F(143, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_145(F, ...) \
+	Z_UTIL_LISTIFY_144(F, __VA_ARGS__) \
+	F(144, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_146(F, ...) \
+	Z_UTIL_LISTIFY_145(F, __VA_ARGS__) \
+	F(145, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_147(F, ...) \
+	Z_UTIL_LISTIFY_146(F, __VA_ARGS__) \
+	F(146, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_148(F, ...) \
+	Z_UTIL_LISTIFY_147(F, __VA_ARGS__) \
+	F(147, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_149(F, ...) \
+	Z_UTIL_LISTIFY_148(F, __VA_ARGS__) \
+	F(148, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_150(F, ...) \
+	Z_UTIL_LISTIFY_149(F, __VA_ARGS__) \
+	F(149, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_151(F, ...) \
+	Z_UTIL_LISTIFY_150(F, __VA_ARGS__) \
+	F(150, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_152(F, ...) \
+	Z_UTIL_LISTIFY_151(F, __VA_ARGS__) \
+	F(151, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_153(F, ...) \
+	Z_UTIL_LISTIFY_152(F, __VA_ARGS__) \
+	F(152, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_154(F, ...) \
+	Z_UTIL_LISTIFY_153(F, __VA_ARGS__) \
+	F(153, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_155(F, ...) \
+	Z_UTIL_LISTIFY_154(F, __VA_ARGS__) \
+	F(154, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_156(F, ...) \
+	Z_UTIL_LISTIFY_155(F, __VA_ARGS__) \
+	F(155, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_157(F, ...) \
+	Z_UTIL_LISTIFY_156(F, __VA_ARGS__) \
+	F(156, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_158(F, ...) \
+	Z_UTIL_LISTIFY_157(F, __VA_ARGS__) \
+	F(157, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_159(F, ...) \
+	Z_UTIL_LISTIFY_158(F, __VA_ARGS__) \
+	F(158, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_160(F, ...) \
+	Z_UTIL_LISTIFY_159(F, __VA_ARGS__) \
+	F(159, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_161(F, ...) \
+	Z_UTIL_LISTIFY_160(F, __VA_ARGS__) \
+	F(160, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_162(F, ...) \
+	Z_UTIL_LISTIFY_161(F, __VA_ARGS__) \
+	F(161, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_163(F, ...) \
+	Z_UTIL_LISTIFY_162(F, __VA_ARGS__) \
+	F(162, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_164(F, ...) \
+	Z_UTIL_LISTIFY_163(F, __VA_ARGS__) \
+	F(163, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_165(F, ...) \
+	Z_UTIL_LISTIFY_164(F, __VA_ARGS__) \
+	F(164, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_166(F, ...) \
+	Z_UTIL_LISTIFY_165(F, __VA_ARGS__) \
+	F(165, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_167(F, ...) \
+	Z_UTIL_LISTIFY_166(F, __VA_ARGS__) \
+	F(166, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_168(F, ...) \
+	Z_UTIL_LISTIFY_167(F, __VA_ARGS__) \
+	F(167, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_169(F, ...) \
+	Z_UTIL_LISTIFY_168(F, __VA_ARGS__) \
+	F(168, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_170(F, ...) \
+	Z_UTIL_LISTIFY_169(F, __VA_ARGS__) \
+	F(169, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_171(F, ...) \
+	Z_UTIL_LISTIFY_170(F, __VA_ARGS__) \
+	F(170, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_172(F, ...) \
+	Z_UTIL_LISTIFY_171(F, __VA_ARGS__) \
+	F(171, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_173(F, ...) \
+	Z_UTIL_LISTIFY_172(F, __VA_ARGS__) \
+	F(172, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_174(F, ...) \
+	Z_UTIL_LISTIFY_173(F, __VA_ARGS__) \
+	F(173, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_175(F, ...) \
+	Z_UTIL_LISTIFY_174(F, __VA_ARGS__) \
+	F(174, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_176(F, ...) \
+	Z_UTIL_LISTIFY_175(F, __VA_ARGS__) \
+	F(175, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_177(F, ...) \
+	Z_UTIL_LISTIFY_176(F, __VA_ARGS__) \
+	F(176, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_178(F, ...) \
+	Z_UTIL_LISTIFY_177(F, __VA_ARGS__) \
+	F(177, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_179(F, ...) \
+	Z_UTIL_LISTIFY_178(F, __VA_ARGS__) \
+	F(178, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_180(F, ...) \
+	Z_UTIL_LISTIFY_179(F, __VA_ARGS__) \
+	F(179, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_181(F, ...) \
+	Z_UTIL_LISTIFY_180(F, __VA_ARGS__) \
+	F(180, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_182(F, ...) \
+	Z_UTIL_LISTIFY_181(F, __VA_ARGS__) \
+	F(181, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_183(F, ...) \
+	Z_UTIL_LISTIFY_182(F, __VA_ARGS__) \
+	F(182, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_184(F, ...) \
+	Z_UTIL_LISTIFY_183(F, __VA_ARGS__) \
+	F(183, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_185(F, ...) \
+	Z_UTIL_LISTIFY_184(F, __VA_ARGS__) \
+	F(184, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_186(F, ...) \
+	Z_UTIL_LISTIFY_185(F, __VA_ARGS__) \
+	F(185, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_187(F, ...) \
+	Z_UTIL_LISTIFY_186(F, __VA_ARGS__) \
+	F(186, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_188(F, ...) \
+	Z_UTIL_LISTIFY_187(F, __VA_ARGS__) \
+	F(187, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_189(F, ...) \
+	Z_UTIL_LISTIFY_188(F, __VA_ARGS__) \
+	F(188, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_190(F, ...) \
+	Z_UTIL_LISTIFY_189(F, __VA_ARGS__) \
+	F(189, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_191(F, ...) \
+	Z_UTIL_LISTIFY_190(F, __VA_ARGS__) \
+	F(190, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_192(F, ...) \
+	Z_UTIL_LISTIFY_191(F, __VA_ARGS__) \
+	F(191, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_193(F, ...) \
+	Z_UTIL_LISTIFY_192(F, __VA_ARGS__) \
+	F(192, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_194(F, ...) \
+	Z_UTIL_LISTIFY_193(F, __VA_ARGS__) \
+	F(193, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_195(F, ...) \
+	Z_UTIL_LISTIFY_194(F, __VA_ARGS__) \
+	F(194, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_196(F, ...) \
+	Z_UTIL_LISTIFY_195(F, __VA_ARGS__) \
+	F(195, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_197(F, ...) \
+	Z_UTIL_LISTIFY_196(F, __VA_ARGS__) \
+	F(196, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_198(F, ...) \
+	Z_UTIL_LISTIFY_197(F, __VA_ARGS__) \
+	F(197, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_199(F, ...) \
+	Z_UTIL_LISTIFY_198(F, __VA_ARGS__) \
+	F(198, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_200(F, ...) \
+	Z_UTIL_LISTIFY_199(F, __VA_ARGS__) \
+	F(199, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_201(F, ...) \
+	Z_UTIL_LISTIFY_200(F, __VA_ARGS__) \
+	F(200, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_202(F, ...) \
+	Z_UTIL_LISTIFY_201(F, __VA_ARGS__) \
+	F(201, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_203(F, ...) \
+	Z_UTIL_LISTIFY_202(F, __VA_ARGS__) \
+	F(202, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_204(F, ...) \
+	Z_UTIL_LISTIFY_203(F, __VA_ARGS__) \
+	F(203, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_205(F, ...) \
+	Z_UTIL_LISTIFY_204(F, __VA_ARGS__) \
+	F(204, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_206(F, ...) \
+	Z_UTIL_LISTIFY_205(F, __VA_ARGS__) \
+	F(205, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_207(F, ...) \
+	Z_UTIL_LISTIFY_206(F, __VA_ARGS__) \
+	F(206, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_208(F, ...) \
+	Z_UTIL_LISTIFY_207(F, __VA_ARGS__) \
+	F(207, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_209(F, ...) \
+	Z_UTIL_LISTIFY_208(F, __VA_ARGS__) \
+	F(208, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_210(F, ...) \
+	Z_UTIL_LISTIFY_209(F, __VA_ARGS__) \
+	F(209, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_211(F, ...) \
+	Z_UTIL_LISTIFY_210(F, __VA_ARGS__) \
+	F(210, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_212(F, ...) \
+	Z_UTIL_LISTIFY_211(F, __VA_ARGS__) \
+	F(211, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_213(F, ...) \
+	Z_UTIL_LISTIFY_212(F, __VA_ARGS__) \
+	F(212, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_214(F, ...) \
+	Z_UTIL_LISTIFY_213(F, __VA_ARGS__) \
+	F(213, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_215(F, ...) \
+	Z_UTIL_LISTIFY_214(F, __VA_ARGS__) \
+	F(214, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_216(F, ...) \
+	Z_UTIL_LISTIFY_215(F, __VA_ARGS__) \
+	F(215, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_217(F, ...) \
+	Z_UTIL_LISTIFY_216(F, __VA_ARGS__) \
+	F(216, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_218(F, ...) \
+	Z_UTIL_LISTIFY_217(F, __VA_ARGS__) \
+	F(217, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_219(F, ...) \
+	Z_UTIL_LISTIFY_218(F, __VA_ARGS__) \
+	F(218, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_220(F, ...) \
+	Z_UTIL_LISTIFY_219(F, __VA_ARGS__) \
+	F(219, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_221(F, ...) \
+	Z_UTIL_LISTIFY_220(F, __VA_ARGS__) \
+	F(220, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_222(F, ...) \
+	Z_UTIL_LISTIFY_221(F, __VA_ARGS__) \
+	F(221, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_223(F, ...) \
+	Z_UTIL_LISTIFY_222(F, __VA_ARGS__) \
+	F(222, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_224(F, ...) \
+	Z_UTIL_LISTIFY_223(F, __VA_ARGS__) \
+	F(223, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_225(F, ...) \
+	Z_UTIL_LISTIFY_224(F, __VA_ARGS__) \
+	F(224, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_226(F, ...) \
+	Z_UTIL_LISTIFY_225(F, __VA_ARGS__) \
+	F(225, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_227(F, ...) \
+	Z_UTIL_LISTIFY_226(F, __VA_ARGS__) \
+	F(226, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_228(F, ...) \
+	Z_UTIL_LISTIFY_227(F, __VA_ARGS__) \
+	F(227, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_229(F, ...) \
+	Z_UTIL_LISTIFY_228(F, __VA_ARGS__) \
+	F(228, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_230(F, ...) \
+	Z_UTIL_LISTIFY_229(F, __VA_ARGS__) \
+	F(229, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_231(F, ...) \
+	Z_UTIL_LISTIFY_230(F, __VA_ARGS__) \
+	F(230, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_232(F, ...) \
+	Z_UTIL_LISTIFY_231(F, __VA_ARGS__) \
+	F(231, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_233(F, ...) \
+	Z_UTIL_LISTIFY_232(F, __VA_ARGS__) \
+	F(232, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_234(F, ...) \
+	Z_UTIL_LISTIFY_233(F, __VA_ARGS__) \
+	F(233, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_235(F, ...) \
+	Z_UTIL_LISTIFY_234(F, __VA_ARGS__) \
+	F(234, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_236(F, ...) \
+	Z_UTIL_LISTIFY_235(F, __VA_ARGS__) \
+	F(235, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_237(F, ...) \
+	Z_UTIL_LISTIFY_236(F, __VA_ARGS__) \
+	F(236, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_238(F, ...) \
+	Z_UTIL_LISTIFY_237(F, __VA_ARGS__) \
+	F(237, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_239(F, ...) \
+	Z_UTIL_LISTIFY_238(F, __VA_ARGS__) \
+	F(238, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_240(F, ...) \
+	Z_UTIL_LISTIFY_239(F, __VA_ARGS__) \
+	F(239, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_241(F, ...) \
+	Z_UTIL_LISTIFY_240(F, __VA_ARGS__) \
+	F(240, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_242(F, ...) \
+	Z_UTIL_LISTIFY_241(F, __VA_ARGS__) \
+	F(241, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_243(F, ...) \
+	Z_UTIL_LISTIFY_242(F, __VA_ARGS__) \
+	F(242, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_244(F, ...) \
+	Z_UTIL_LISTIFY_243(F, __VA_ARGS__) \
+	F(243, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_245(F, ...) \
+	Z_UTIL_LISTIFY_244(F, __VA_ARGS__) \
+	F(244, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_246(F, ...) \
+	Z_UTIL_LISTIFY_245(F, __VA_ARGS__) \
+	F(245, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_247(F, ...) \
+	Z_UTIL_LISTIFY_246(F, __VA_ARGS__) \
+	F(246, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_248(F, ...) \
+	Z_UTIL_LISTIFY_247(F, __VA_ARGS__) \
+	F(247, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_249(F, ...) \
+	Z_UTIL_LISTIFY_248(F, __VA_ARGS__) \
+	F(248, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_250(F, ...) \
+	Z_UTIL_LISTIFY_249(F, __VA_ARGS__) \
+	F(249, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_251(F, ...) \
+	Z_UTIL_LISTIFY_250(F, __VA_ARGS__) \
+	F(250, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_252(F, ...) \
+	Z_UTIL_LISTIFY_251(F, __VA_ARGS__) \
+	F(251, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_253(F, ...) \
+	Z_UTIL_LISTIFY_252(F, __VA_ARGS__) \
+	F(252, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_254(F, ...) \
+	Z_UTIL_LISTIFY_253(F, __VA_ARGS__) \
+	F(253, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_255(F, ...) \
+	Z_UTIL_LISTIFY_254(F, __VA_ARGS__) \
+	F(254, __VA_ARGS__)
+
+#define Z_UTIL_LISTIFY_256(F, ...) \
+	Z_UTIL_LISTIFY_255(F, __VA_ARGS__) \
+	F(255, __VA_ARGS__)
+
+#endif /* ZEPHYR_INCLUDE_SYS_UTIL_LOOPS_H_ */
diff --git a/src/include/sys/util_macro.h b/src/include/sys/util_macro.h
new file mode 100644
index 0000000000..fb21291950
--- /dev/null
+++ b/src/include/sys/util_macro.h
@@ -0,0 +1,601 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Macro utilities
+ *
+ * Macro utilities are the public interface for C/C++ code and device tree
+ * related implementation.  In general, C/C++ will include <sys/util.h>
+ * instead this file directly.  For device tree implementation, this file
+ * should be include instead <sys/util_internal.h>
+ */
+
+#ifndef ZEPHYR_INCLUDE_SYS_UTIL_MACROS_H_
+#define ZEPHYR_INCLUDE_SYS_UTIL_MACROS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup sys-util
+ * @{
+ */
+
+/*
+ * Most of the eldritch implementation details for all the macrobatics
+ * below (APIs like IS_ENABLED(), COND_CODE_1(), etc.) are hidden away
+ * in this file.
+ */
+#include <sys/util_internal.h>
+
+#ifndef BIT
+#if defined(_ASMLANGUAGE)
+#define BIT(n)  (1 << (n))
+#else
+/**
+ * @brief Unsigned integer with bit position @p n set (signed in
+ * assembly language).
+ */
+#define BIT(n)  (1UL << (n))
+#endif
+#endif
+
+/** @brief 64-bit unsigned integer with bit position @p _n set. */
+#define BIT64(_n) (1ULL << (_n))
+
+/**
+ * @brief Set or clear a bit depending on a boolean value
+ *
+ * The argument @p var is a variable whose value is written to as a
+ * side effect.
+ *
+ * @param var Variable to be altered
+ * @param bit Bit number
+ * @param set if 0, clears @p bit in @p var; any other value sets @p bit
+ */
+#define WRITE_BIT(var, bit, set) \
+	((var) = (set) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit)))
+
+/**
+ * @brief Bit mask with bits 0 through <tt>n-1</tt> (inclusive) set,
+ * or 0 if @p n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1UL)
+
+/**
+ * @brief 64-bit bit mask with bits 0 through <tt>n-1</tt> (inclusive) set,
+ * or 0 if @p n is 0.
+ */
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+/**
+ * @brief Check for macro definition in compiler-visible expressions
+ *
+ * This trick was pioneered in Linux as the config_enabled() macro. It
+ * has the effect of taking a macro value that may be defined to "1"
+ * or may not be defined at all and turning it into a literal
+ * expression that can be handled by the C compiler instead of just
+ * the preprocessor. It is often used with a @p CONFIG_FOO macro which
+ * may be defined to 1 via Kconfig, or left undefined.
+ *
+ * That is, it works similarly to <tt>\#if defined(CONFIG_FOO)</tt>
+ * except that its expansion is a C expression. Thus, much <tt>\#ifdef</tt>
+ * usage can be replaced with equivalents like:
+ *
+ *     if (IS_ENABLED(CONFIG_FOO)) {
+ *             do_something_with_foo
+ *     }
+ *
+ * This is cleaner since the compiler can generate errors and warnings
+ * for @p do_something_with_foo even when @p CONFIG_FOO is undefined.
+ *
+ * @param config_macro Macro to check
+ * @return 1 if @p config_macro is defined to 1, 0 otherwise (including
+ *         if @p config_macro is not defined)
+ */
+#define IS_ENABLED(config_macro) Z_IS_ENABLED1(config_macro)
+/* INTERNAL: the first pass above is just to expand any existing
+ * macros, we need the macro value to be e.g. a literal "1" at
+ * expansion time in the next macro, not "(1)", etc... Standard
+ * recursive expansion does not work.
+ */
+
+/**
+ * @brief Insert code depending on whether @p _flag expands to 1 or not.
+ *
+ * This relies on similar tricks as IS_ENABLED(), but as the result of
+ * @p _flag expansion, results in either @p _if_1_code or @p
+ * _else_code is expanded.
+ *
+ * To prevent the preprocessor from treating commas as argument
+ * separators, the @p _if_1_code and @p _else_code expressions must be
+ * inside brackets/parentheses: <tt>()</tt>. These are stripped away
+ * during macro expansion.
+ *
+ * Example:
+ *
+ *     COND_CODE_1(CONFIG_FLAG, (uint32_t x;), (there_is_no_flag();))
+ *
+ * If @p CONFIG_FLAG is defined to 1, this expands to:
+ *
+ *     uint32_t x;
+ *
+ * It expands to <tt>there_is_no_flag();</tt> otherwise.
+ *
+ * This could be used as an alternative to:
+ *
+ *     #if defined(CONFIG_FLAG) && (CONFIG_FLAG == 1)
+ *     #define MAYBE_DECLARE(x) uint32_t x
+ *     #else
+ *     #define MAYBE_DECLARE(x) there_is_no_flag()
+ *     #endif
+ *
+ *     MAYBE_DECLARE(x);
+ *
+ * However, the advantage of COND_CODE_1() is that code is resolved in
+ * place where it is used, while the @p \#if method defines @p
+ * MAYBE_DECLARE on two lines and requires it to be invoked again on a
+ * separate line. This makes COND_CODE_1() more concise and also
+ * sometimes more useful when used within another macro's expansion.
+ *
+ * @note @p _flag can be the result of preprocessor expansion, e.g.
+ *	 an expression involving <tt>NUM_VA_ARGS_LESS_1(...)</tt>.
+ *	 However, @p _if_1_code is only expanded if @p _flag expands
+ *	 to the integer literal 1. Integer expressions that evaluate
+ *	 to 1, e.g. after doing some arithmetic, will not work.
+ *
+ * @param _flag evaluated flag
+ * @param _if_1_code result if @p _flag expands to 1; must be in parentheses
+ * @param _else_code result otherwise; must be in parentheses
+ */
+#define COND_CODE_1(_flag, _if_1_code, _else_code) \
+	Z_COND_CODE_1(_flag, _if_1_code, _else_code)
+
+/**
+ * @brief Like COND_CODE_1() except tests if @p _flag is 0.
+ *
+ * This is like COND_CODE_1(), except that it tests whether @p _flag
+ * expands to the integer literal 0. It expands to @p _if_0_code if
+ * so, and @p _else_code otherwise; both of these must be enclosed in
+ * parentheses.
+ *
+ * @param _flag evaluated flag
+ * @param _if_0_code result if @p _flag expands to 0; must be in parentheses
+ * @param _else_code result otherwise; must be in parentheses
+ * @see COND_CODE_1()
+ */
+#define COND_CODE_0(_flag, _if_0_code, _else_code) \
+	Z_COND_CODE_0(_flag, _if_0_code, _else_code)
+
+/**
+ * @brief Insert code if @p _flag is defined and equals 1.
+ *
+ * Like COND_CODE_1(), this expands to @p _code if @p _flag is defined to 1;
+ * it expands to nothing otherwise.
+ *
+ * Example:
+ *
+ *     IF_ENABLED(CONFIG_FLAG, (uint32_t foo;))
+ *
+ * If @p CONFIG_FLAG is defined to 1, this expands to:
+ *
+ *     uint32_t foo;
+ *
+ * and to nothing otherwise.
+ *
+ * It can be considered as a more compact alternative to:
+ *
+ *     #if defined(CONFIG_FLAG) && (CONFIG_FLAG == 1)
+ *     uint32_t foo;
+ *     #endif
+ *
+ * @param _flag evaluated flag
+ * @param _code result if @p _flag expands to 1; must be in parentheses
+ */
+#define IF_ENABLED(_flag, _code) \
+	COND_CODE_1(_flag, _code, ())
+
+/**
+ * @brief Check if a macro has a replacement expression
+ *
+ * If @p a is a macro defined to a nonempty value, this will return
+ * true, otherwise it will return false. It only works with defined
+ * macros, so an additional @p \#ifdef test may be needed in some cases.
+ *
+ * This macro may be used with COND_CODE_1() and COND_CODE_0() while
+ * processing <tt>__VA_ARGS__</tt> to avoid processing empty arguments.
+ *
+ * Example:
+ *
+ *	#define EMPTY
+ *	#define NON_EMPTY	1
+ *	#undef  UNDEFINED
+ *	IS_EMPTY(EMPTY)
+ *	IS_EMPTY(NON_EMPTY)
+ *	IS_EMPTY(UNDEFINED)
+ *	#if defined(EMPTY) && IS_EMPTY(EMPTY) == true
+ *	some_conditional_code
+ *	#endif
+ *
+ * In above examples, the invocations of IS_EMPTY(...) return @p true,
+ * @p false, and @p true; @p some_conditional_code is included.
+ *
+ * @param ... macro to check for emptiness (may be <tt>__VA_ARGS__</tt>)
+ */
+#define IS_EMPTY(...) Z_IS_EMPTY_(__VA_ARGS__)
+
+/**
+ * @brief Remove empty arguments from list.
+ *
+ * During macro expansion, <tt>__VA_ARGS__</tt> and other preprocessor
+ * generated lists may contain empty elements, e.g.:
+ *
+ *	#define LIST ,a,b,,d,
+ *
+ * Using EMPTY to show each empty element, LIST contains:
+ *
+ *      EMPTY, a, b, EMPTY, d
+ *
+ * When processing such lists, e.g. using FOR_EACH(), all empty elements
+ * will be processed, and may require filtering out.
+ * To make that process easier, it is enough to invoke LIST_DROP_EMPTY
+ * which will remove all empty elements.
+ *
+ * Example:
+ *
+ *	LIST_DROP_EMPTY(LIST)
+ *
+ * expands to:
+ *
+ *	a, b, d
+ *
+ * @param ... list to be processed
+ */
+#define LIST_DROP_EMPTY(...) \
+	Z_LIST_DROP_FIRST(FOR_EACH(Z_LIST_NO_EMPTIES, (), __VA_ARGS__))
+
+/**
+ * @brief Macro with an empty expansion
+ *
+ * This trivial definition is provided for readability when a macro
+ * should expand to an empty result, which e.g. is sometimes needed to
+ * silence checkpatch.
+ *
+ * Example:
+ *
+ *	#define LIST_ITEM(n) , item##n
+ *
+ * The above would cause checkpatch to complain, but:
+ *
+ *	#define LIST_ITEM(n) EMPTY, item##n
+ *
+ * would not.
+ */
+#define EMPTY
+
+/**
+ * @brief Macro that expands to its argument
+ *
+ * This is useful in macros like @c FOR_EACH() when there is no
+ * transformation required on the list elements.
+ *
+ * @param V any value
+ */
+#define IDENTITY(V) V
+
+/**
+ * @brief Get nth argument from argument list.
+ *
+ * @param N Argument index to fetch. Counter from 1.
+ * @param ... Variable list of argments from which one argument is returned.
+ *
+ * @return Nth argument.
+ */
+#define GET_ARG_N(N, ...) Z_GET_ARG_##N(__VA_ARGS__)
+
+/**
+ * @brief Strips n first arguments from the argument list.
+ *
+ * @param N Number of arguments to discard.
+ * @param ... Variable list of argments.
+ *
+ * @return argument list without N first arguments.
+ */
+#define GET_ARGS_LESS_N(N, ...) Z_GET_ARGS_LESS_##N(__VA_ARGS__)
+
+/**
+ * @brief Like <tt>a || b</tt>, but does evaluation and
+ * short-circuiting at C preprocessor time.
+ *
+ * This is not the same as the binary @p || operator; in particular,
+ * @p a should expand to an integer literal 0 or 1. However, @p b
+ * can be any value.
+ *
+ * This can be useful when @p b is an expression that would cause a
+ * build error when @p a is 1.
+ */
+#define UTIL_OR(a, b) COND_CODE_1(UTIL_BOOL(a), (a), (b))
+
+/**
+ * @brief Like <tt>a && b</tt>, but does evaluation and
+ * short-circuiting at C preprocessor time.
+ *
+ * This is not the same as the binary @p &&, however; in particular,
+ * @p a should expand to an integer literal 0 or 1. However, @p b
+ * can be any value.
+ *
+ * This can be useful when @p b is an expression that would cause a
+ * build error when @p a is 0.
+ */
+#define UTIL_AND(a, b) COND_CODE_1(UTIL_BOOL(a), (b), (0))
+
+/**
+ * @brief Generates a sequence of code.
+ *
+ * Example:
+ *
+ *     #define FOO(i, _) MY_PWM ## i ,
+ *     { UTIL_LISTIFY(PWM_COUNT, FOO) }
+ *
+ * The above two lines expand to:
+ *
+ *    { MY_PWM0 , MY_PWM1 , }
+ *
+ * @param LEN The length of the sequence. Must be an integer literal less
+ *            than 255.
+ * @param F A macro function that accepts at least two arguments:
+ *          <tt>F(i, ...)</tt>. @p F is called repeatedly in the expansion.
+ *          Its first argument @p i is the index in the sequence, and
+ *          the variable list of arguments passed to UTIL_LISTIFY are passed
+ *          through to @p F.
+ *
+ * @note Calling UTIL_LISTIFY with undefined arguments has undefined
+ * behavior.
+ */
+#define UTIL_LISTIFY(LEN, F, ...) UTIL_CAT(Z_UTIL_LISTIFY_, LEN)(F, __VA_ARGS__)
+
+/**
+ * @brief Call a macro @p F on each provided argument with a given
+ *        separator between each call.
+ *
+ * Example:
+ *
+ *     #define F(x) int a##x
+ *     FOR_EACH(F, (;), 4, 5, 6);
+ *
+ * This expands to:
+ *
+ *     int a4;
+ *     int a5;
+ *     int a6;
+ *
+ * @param F Macro to invoke
+ * @param sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ *            this is required to enable providing a comma as separator.
+ * @param ... Variable argument list. The macro @p F is invoked as
+ *            <tt>F(element)</tt> for each element in the list.
+ */
+#define FOR_EACH(F, sep, ...) \
+	Z_FOR_EACH(F, sep, REVERSE_ARGS(__VA_ARGS__))
+
+/**
+ * @brief Like FOR_EACH(), but with a terminator instead of a separator,
+ *        and drops empty elements from the argument list
+ *
+ * The @p sep argument to <tt>FOR_EACH(F, (sep), a, b)</tt> is a
+ * separator which is placed between calls to @p F, like this:
+ *
+ *     FOR_EACH(F, (sep), a, b) // F(a) sep F(b)
+ *                              //               ^^^ no sep here!
+ *
+ * By contrast, the @p term argument to <tt>FOR_EACH_NONEMPTY_TERM(F, (term),
+ * a, b)</tt> is added after each time @p F appears in the expansion:
+ *
+ *     FOR_EACH_NONEMPTY_TERM(F, (term), a, b) // F(a) term F(b) term
+ *                                             //                ^^^^
+ *
+ * Further, any empty elements are dropped:
+ *
+ *     FOR_EACH_NONEMPTY_TERM(F, (term), a, EMPTY, b) // F(a) term F(b) term
+ *
+ * This is more convenient in some cases, because FOR_EACH_NONEMPTY_TERM()
+ * expands to nothing when given an empty argument list, and it's
+ * often cumbersome to write a macro @p F that does the right thing
+ * even when given an empty argument.
+ *
+ * One example is when <tt>__VA_ARGS__</tt> may or may not be empty,
+ * and the results are embedded in a larger initializer:
+ *
+ *     #define SQUARE(x) ((x)*(x))
+ *
+ *     int my_array[] = {
+ *             FOR_EACH_NONEMPTY_TERM(SQUARE, (,), FOO(...))
+ *             FOR_EACH_NONEMPTY_TERM(SQUARE, (,), BAR(...))
+ *             FOR_EACH_NONEMPTY_TERM(SQUARE, (,), BAZ(...))
+ *     };
+ *
+ * This is more convenient than:
+ *
+ * 1. figuring out whether the @p FOO, @p BAR, and @p BAZ expansions
+ *    are empty and adding a comma manually (or not) between FOR_EACH()
+ *    calls
+ * 2. rewriting SQUARE so it reacts appropriately when "x" is empty
+ *    (which would be necessary if e.g. @p FOO expands to nothing)
+ *
+ * @param F Macro to invoke on each nonempty element of the variable
+ *          arguments
+ * @param term Terminator (e.g. comma or semicolon) placed after each
+ *             invocation of F. Must be in parentheses; this is required
+ *             to enable providing a comma as separator.
+ * @param ... Variable argument list. The macro @p F is invoked as
+ *            <tt>F(element)</tt> for each nonempty element in the list.
+ */
+#define FOR_EACH_NONEMPTY_TERM(F, term, ...)				\
+	COND_CODE_0(							\
+		/* are there zero non-empty arguments ? */		\
+		NUM_VA_ARGS_LESS_1(LIST_DROP_EMPTY(__VA_ARGS__, _)),	\
+		/* if so, expand to nothing */				\
+		(),							\
+		/* otherwise, expand to: */				\
+		(/* FOR_EACH() on nonempty elements, */		\
+			FOR_EACH(F, term, LIST_DROP_EMPTY(__VA_ARGS__))	\
+			/* plus a final terminator */			\
+			__DEBRACKET term				\
+		))
+
+/**
+ * @brief Call macro @p F on each provided argument, with the argument's index
+ *        as an additional parameter.
+ *
+ * This is like FOR_EACH(), except @p F should be a macro which takes two
+ * arguments: <tt>F(index, variable_arg)</tt>.
+ *
+ * Example:
+ *
+ *     #define F(idx, x) int a##idx = x
+ *     FOR_EACH_IDX(F, (;), 4, 5, 6);
+ *
+ * This expands to:
+ *
+ *     int a0 = 4;
+ *     int a1 = 5;
+ *     int a2 = 6;
+ *
+ * @param F Macro to invoke
+ * @param sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ *            this is required to enable providing a comma as separator.
+ * @param ... Variable argument list. The macro @p F is invoked as
+ *            <tt>F(index, element)</tt> for each element in the list.
+ */
+#define FOR_EACH_IDX(F, sep, ...) \
+	Z_FOR_EACH_IDX(F, sep, REVERSE_ARGS(__VA_ARGS__))
+
+/**
+ * @brief Call macro @p F on each provided argument, with an additional fixed
+ *	  argument as a parameter.
+ *
+ * This is like FOR_EACH(), except @p F should be a macro which takes two
+ * arguments: <tt>F(variable_arg, fixed_arg)</tt>.
+ *
+ * Example:
+ *
+ *     static void func(int val, void *dev);
+ *     FOR_EACH_FIXED_ARG(func, (;), dev, 4, 5, 6);
+ *
+ * This expands to:
+ *
+ *     func(4, dev);
+ *     func(5, dev);
+ *     func(6, dev);
+ *
+ * @param F Macro to invoke
+ * @param sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ *            this is required to enable providing a comma as separator.
+ * @param fixed_arg Fixed argument passed to @p F as the second macro parameter.
+ * @param ... Variable argument list. The macro @p F is invoked as
+ *            <tt>F(element, fixed_arg)</tt> for each element in the list.
+ */
+#define FOR_EACH_FIXED_ARG(F, sep, fixed_arg, ...) \
+	Z_FOR_EACH_FIXED_ARG(F, sep, fixed_arg, REVERSE_ARGS(__VA_ARGS__))
+
+/**
+ * @brief Calls macro @p F for each variable argument with an index and fixed
+ *        argument
+ *
+ * This is like the combination of FOR_EACH_IDX() with FOR_EACH_FIXED_ARG().
+ *
+ * Example:
+ *
+ *     #define F(idx, x, fixed_arg) int fixed_arg##idx = x
+ *     FOR_EACH_IDX_FIXED_ARG(F, (;), a, 4, 5, 6);
+ *
+ * This expands to:
+ *
+ *     int a0 = 4;
+ *     int a1 = 5;
+ *     int a2 = 6;
+ *
+ * @param F Macro to invoke
+ * @param sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ *            This is required to enable providing a comma as separator.
+ * @param fixed_arg Fixed argument passed to @p F as the third macro parameter.
+ * @param ... Variable list of arguments. The macro @p F is invoked as
+ *            <tt>F(index, element, fixed_arg)</tt> for each element in
+ *            the list.
+ */
+#define FOR_EACH_IDX_FIXED_ARG(F, sep, fixed_arg, ...) \
+	Z_FOR_EACH_IDX_FIXED_ARG(F, sep, fixed_arg, REVERSE_ARGS(__VA_ARGS__))
+
+/** @brief Reverse arguments order.
+ *
+ * @param ... Variable argument list.
+ */
+#define REVERSE_ARGS(...) \
+	Z_FOR_EACH_ENGINE(Z_FOR_EACH_EXEC, (,), Z_BYPASS, _, __VA_ARGS__)
+
+/**
+ * @brief Number of arguments in the variable arguments list minus one.
+ *
+ * @param ... List of arguments
+ * @return  Number of variadic arguments in the argument list, minus one
+ */
+#define NUM_VA_ARGS_LESS_1(...) \
+	NUM_VA_ARGS_LESS_1_IMPL(__VA_ARGS__, 63, 62, 61, \
+	60, 59, 58, 57, 56, 55, 54, 53, 52, 51,		 \
+	50, 49, 48, 47, 46, 45, 44, 43, 42, 41,		 \
+	40, 39, 38, 37, 36, 35, 34, 33, 32, 31,		 \
+	30, 29, 28, 27, 26, 25, 24, 23, 22, 21,		 \
+	20, 19, 18, 17, 16, 15, 14, 13, 12, 11,		 \
+	10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, ~)
+
+/**
+ * @brief Mapping macro that pastes results together
+ *
+ * This is similar to FOR_EACH() in that it invokes a macro repeatedly
+ * on each element of <tt>__VA_ARGS__</tt>. However, unlike FOR_EACH(),
+ * MACRO_MAP_CAT() pastes the results together into a single token.
+ *
+ * For example, with this macro FOO:
+ *
+ *     #define FOO(x) item_##x##_
+ *
+ * <tt>MACRO_MAP_CAT(FOO, a, b, c),</tt> expands to the token:
+ *
+ *     item_a_item_b_item_c_
+ *
+ * @param ... Macro to expand on each argument, followed by its
+ *            arguments. (The macro should take exactly one argument.)
+ * @return The results of expanding the macro on each argument, all pasted
+ *         together
+ */
+#define MACRO_MAP_CAT(...) MACRO_MAP_CAT_(__VA_ARGS__)
+
+/**
+ * @brief Mapping macro that pastes a fixed number of results together
+ *
+ * Similar to @ref MACRO_MAP_CAT(), but expects a fixed number of
+ * arguments. If more arguments are given than are expected, the rest
+ * are ignored.
+ *
+ * @param N   Number of arguments to map
+ * @param ... Macro to expand on each argument, followed by its
+ *            arguments. (The macro should take exactly one argument.)
+ * @return The results of expanding the macro on each argument, all pasted
+ *         together
+ */
+#define MACRO_MAP_CAT_N(N, ...) MACRO_MAP_CAT_N_(N, __VA_ARGS__)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_SYS_UTIL_MACROS_H_ */
diff --git a/src/include/zephyr/types.h b/src/include/zephyr/types.h
new file mode 100644
index 0000000000..c90eedd813
--- /dev/null
+++ b/src/include/zephyr/types.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_ZEPHYR_TYPES_H_
+#define ZEPHYR_INCLUDE_ZEPHYR_TYPES_H_
+
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* 32 bits on ILP32 builds, 64 bits on LP64 builts */
+typedef unsigned long       ulong_t;
+
+/*
+ * A type with strong alignment requiremnts, similar to C11 max_align_t. It can
+ * be used to force alignment of data structures allocated on the stack or as
+ * return * type for heap allocators.
+ */
+typedef union {
+	long long       thelonglong;
+	long double     thelongdouble;
+	uintmax_t       theuintmax_t;
+	size_t          thesize_t;
+	uintptr_t       theuintptr_t;
+	void            *thepvoid;
+	void            (*thepfunc)(void);
+} z_max_align_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_ZEPHYR_TYPES_H_ */