mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-11-13 01:31:36 +08:00
WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,9 @@
|
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description: Altera JTAG UART
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compatible: "altr,jtag-uart"
|
||||
|
||||
include: uart-controller.yaml
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||||
|
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properties:
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||||
reg:
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||||
required: true
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||||
@@ -0,0 +1,12 @@
|
||||
description: ARM CMSDK UART
|
||||
|
||||
compatible: "arm,cmsdk-uart"
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||||
|
||||
include: uart-controller.yaml
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properties:
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reg:
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required: true
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||||
|
||||
interrupts:
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||||
required: true
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||||
@@ -0,0 +1,12 @@
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description: ARM PL011 UART
|
||||
|
||||
compatible: "arm,pl011"
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||||
|
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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||||
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interrupts:
|
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required: true
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@@ -0,0 +1,12 @@
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description: ARM SBSA UART
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|
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compatible: "arm,sbsa-uart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: false
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@@ -0,0 +1,30 @@
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description: SAM family UART
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compatible: "atmel,sam-uart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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||||
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peripheral-id:
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type: int
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description: peripheral ID
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required: true
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pinctrl-0:
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type: phandles
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description: |
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PIO pin configuration for URXD & UTRD signals. We expect that
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the phandles will reference pinctrl nodes. These nodes will
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have a nodelabel that matches the Atmel SoC HAL defines and
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be of the form p<port><pin><periph>_<inst>_<signal>.
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For example the UART on SAM3x would be
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pinctrl-0 = <&pa8a_uart_urxd &pa9a_uart_utxd>;
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required: true
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@@ -0,0 +1,30 @@
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description: Atmel SAM family USART
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compatible: "atmel,sam-usart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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|
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peripheral-id:
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type: int
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description: peripheral ID
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required: true
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pinctrl-0:
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type: phandles
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description: |
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PIO pin configuration for RXD & TRD signals. We expect that
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the phandles will reference pinctrl nodes. These nodes will
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have a nodelabel that matches the Atmel SoC HAL defines and
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be of the form p<port><pin><periph>_<inst>_<signal>.
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For example the USART0 on SAME7x would be
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pinctrl-0 = <&pb0c_usart0_rxd0 &pb1c_usart0_txd0>;
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required: true
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@@ -0,0 +1,62 @@
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description: Atmel SAM0 SERCOM UART driver
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compatible: "atmel,sam0-uart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clocks:
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required: true
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clock-names:
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required: true
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rxpo:
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type: int
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required: true
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description: Receive Data Pinout
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txpo:
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type: int
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required: true
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description: Transmit Data Pinout
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collision-detection:
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type: boolean
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description: Enable collision detection for half-duplex mode.
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pinctrl-0:
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type: phandles
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description: |
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PORT pin configuration for RXD & TRD signals. We expect that
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the phandles will reference pinctrl nodes. These nodes will
|
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have a nodelabel that matches the Atmel SoC HAL defines and
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be of the form p<port><pin><periph>_<inst>_<signal>.
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For example the SERCOM0 on SAMR21 would be
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pinctrl-0 = <&pa5d_sercom0_pad1 &pa4d_sercom0_pad0>;
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required: true
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dmas:
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description: |
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Optional TX & RX dma specifiers. Each specifier will have a phandle
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reference to the dmac controller, the channel number, and peripheral
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trigger source.
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For example dmas for TX, RX on SERCOM3
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dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
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dma-names:
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description: |
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Required if the dmas property exists. This should be "tx" and "rx"
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to match the dmas property.
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For example
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dma-names = "tx", "rx";
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@@ -0,0 +1,34 @@
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# Copyright (c) 2018, Cypress
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# Copyright (c) 2020, ATL Electronics
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# SPDX-License-Identifier: Apache-2.0
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description: Cypress SCB[UART]
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compatible: "cypress,psoc6-uart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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peripheral-id:
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type: int
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description: peripheral ID
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required: true
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pinctrl-0:
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type: phandles
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description: |
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Port pin configuration for RX & TX signals. We expect that the
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phandles will reference pinctrl nodes. These nodes will have a
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nodelabel that matches the Cypress SoC HAL defines and be of the
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form p<port>_<pin>_<periph><inst>_<signal>.
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For example the UART on PSoC-63 Pioneer Kit would be
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pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>;
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required: true
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@@ -0,0 +1,32 @@
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description: ESP32 UART
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compatible: "espressif,esp32-uart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: false
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tx-pin:
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type: int
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description: TX pin
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required: true
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rx-pin:
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type: int
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description: RX pin
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required: true
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rts-pin:
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type: int
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description: RTS pin
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required: false
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cts-pin:
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type: int
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description: CTS pin
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required: false
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@@ -0,0 +1,9 @@
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description: GRLIB APBUART
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compatible: "gaisler,apbuart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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@@ -0,0 +1,20 @@
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# Copyright (c) 2021, ATL Electronics
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# SPDX-License-Identifier: Apache-2.0
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description: GigaDevice USART
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compatible: "gd,gd32-usart"
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include: [uart-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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rcu-periph-clock:
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type: int
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description: Reset Control Unit Peripheral Clock ID
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required: true
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@@ -0,0 +1,9 @@
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description: INFINEON XMC4XXX UART
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compatible: "infineon,xmc4xxx-uart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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@@ -0,0 +1,26 @@
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# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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description: ITE, IT8XXX2-UART node
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compatible: "ite,it8xxx2-uart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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port-num:
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type: int
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required: true
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description: Ordinal identifying the port
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gpios:
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type: phandle-array
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required: true
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uart-dev:
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type: phandle
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required: true
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description: Get the handle of the UART device
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@@ -0,0 +1,15 @@
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# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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description: LiteX UART
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compatible: "litex,uart0"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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@@ -0,0 +1,43 @@
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description: Microchip XEC UART
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compatible: "microchip,xec-uart"
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|
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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ldn:
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type: int
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required: true
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description: logical device number
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girqs:
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type: array
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required: true
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description: UART GIRQ and bit position in EC interrupt aggregator
|
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pcrs:
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type: array
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required: true
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description: UART Power Clock Reset(PCR) register index and bit position
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"#girq-cells":
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type: int
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const: 2
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"#pcr-cells":
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type: int
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const: 2
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girq-cells:
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- girq_num
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- bitpos
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pcr-cells:
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- reg_idx
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- bitpos
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@@ -0,0 +1,12 @@
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# Copyright (c) 2018 Linaro Limited
|
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# SPDX-License-Identifier: Apache-2.0
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description: SiFive UART
|
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|
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compatible: "microsemi,coreuart"
|
||||
|
||||
include: uart-controller.yaml
|
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|
||||
properties:
|
||||
reg:
|
||||
required: true
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@@ -0,0 +1,24 @@
|
||||
description: NEORV32 UART
|
||||
|
||||
compatible: "neorv32-uart"
|
||||
|
||||
include: uart-controller.yaml
|
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|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
interrupt-names:
|
||||
required: true
|
||||
|
||||
current-speed:
|
||||
required: true
|
||||
|
||||
syscon:
|
||||
type: phandle
|
||||
required: true
|
||||
description: |
|
||||
phandle to syscon (NEORV32 SYSINFO) node.
|
||||
@@ -0,0 +1,99 @@
|
||||
include: [uart-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
disable-rx:
|
||||
type: boolean
|
||||
description: |
|
||||
Disable UART reception capabilities (only required to disable reception
|
||||
if CONFIG_PINCTRL is enabled).
|
||||
|
||||
current-speed:
|
||||
description: |
|
||||
Initial baud rate setting for UART. Only a fixed set of baud
|
||||
rates are selectable on these devices.
|
||||
enum:
|
||||
- 1200
|
||||
- 2400
|
||||
- 4800
|
||||
- 9600
|
||||
- 14400
|
||||
- 19200
|
||||
- 28800
|
||||
- 31250
|
||||
- 38400
|
||||
- 56000
|
||||
- 57600
|
||||
- 76800
|
||||
- 115200
|
||||
- 230400
|
||||
- 250000
|
||||
- 460800
|
||||
- 921600
|
||||
- 1000000
|
||||
|
||||
tx-pin:
|
||||
type: int
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
The TX pin to use.
|
||||
|
||||
For pins P0.0 through P0.31, use the pin number. For example,
|
||||
to use P0.16 for TX, set:
|
||||
|
||||
tx-pin = <16>;
|
||||
|
||||
For pins P1.0 through P1.31, add 32 to the pin number. For
|
||||
example, to use P1.2 for TX, set:
|
||||
|
||||
tx-pin = <34>; /* 32 + 2 */
|
||||
|
||||
rx-pin:
|
||||
type: int
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
The RX pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
|
||||
rts-pin:
|
||||
type: int
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
The RTS pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
|
||||
cts-pin:
|
||||
type: int
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
The CTS pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
|
||||
rx-pull-up:
|
||||
type: boolean
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
Enable pull-up resistor on the RX pin.
|
||||
|
||||
cts-pull-up:
|
||||
type: boolean
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
Enable pull-up resistor on the CTS pin.
|
||||
@@ -0,0 +1,10 @@
|
||||
description: |
|
||||
Nordic nRF family UART.
|
||||
|
||||
This is the binding for the peripheral without EasyDMA support.
|
||||
See the "nordic,nrf-uarte" binding for UARTE, i.e. UART with
|
||||
EasyDMA.
|
||||
|
||||
compatible: "nordic,nrf-uart"
|
||||
|
||||
include: nordic,nrf-uart-common.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Nordic nRF family UARTE (UART with EasyDMA)
|
||||
|
||||
compatible: "nordic,nrf-uarte"
|
||||
|
||||
include: nordic,nrf-uart-common.yaml
|
||||
@@ -0,0 +1,24 @@
|
||||
description: ns16550 UART
|
||||
|
||||
compatible: "ns16550"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
reg-shift:
|
||||
type: int
|
||||
required: false
|
||||
description: quantity to shift the register offsets by
|
||||
|
||||
pcp:
|
||||
type: int
|
||||
required: false
|
||||
description: custom clock (PRV_CLOCK_PARAMS, if supported)
|
||||
|
||||
dlf:
|
||||
type: int
|
||||
required: false
|
||||
description: divisor latch fraction (DLF, if supported)
|
||||
@@ -0,0 +1,26 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX-UART node
|
||||
|
||||
compatible: "nuvoton,npcx-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
clocks:
|
||||
required: true
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
description: configurations of pinmux controllers
|
||||
uart-rx:
|
||||
type: phandle
|
||||
required: true
|
||||
description: |
|
||||
Mapping table between Wake-Up Input (WUI) and uart rx START signal.
|
||||
|
||||
For example the WUI mapping on NPCX7 UART1 would be
|
||||
uart-rx = <&wui_cr_sin1>;
|
||||
@@ -0,0 +1,9 @@
|
||||
description: NUVOTON NUMICRO FAMILY UART
|
||||
|
||||
compatible: "nuvoton,numicro-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,16 @@
|
||||
description: |
|
||||
This binding gives a base representation of the NXP iMX IUART
|
||||
|
||||
compatible: "nxp,imx-iuart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: false
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2017, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: iMX UART
|
||||
|
||||
compatible: "nxp,imx-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
modem-mode:
|
||||
type: int
|
||||
required: true
|
||||
description: Set the UART Port to modem mode 0 (dce) 64 (dte)
|
||||
|
||||
rdc:
|
||||
type: int
|
||||
required: true
|
||||
description: Set the RDC permission for this peripheral
|
||||
@@ -0,0 +1,16 @@
|
||||
description: Kinetis LPSCI UART
|
||||
|
||||
compatible: "nxp,kinetis-lpsci"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
description: Kinetis LPUART
|
||||
|
||||
compatible: "nxp,kinetis-lpuart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,19 @@
|
||||
description: Kinetis UART
|
||||
|
||||
compatible: "nxp,kinetis-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
@@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2017, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC USART
|
||||
|
||||
compatible: "nxp,lpc-usart"
|
||||
|
||||
include: [uart-controller.yaml, "nxp,lpc-flexcomm.yaml"]
|
||||
@@ -0,0 +1,25 @@
|
||||
description: LPC11U6X UART
|
||||
|
||||
compatible: "nxp,lpc11u6x-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
pinmuxs:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: RX and TX pinmux
|
||||
|
||||
pinmux-names:
|
||||
type: string-array
|
||||
required: true
|
||||
description: UART pins names
|
||||
@@ -0,0 +1,12 @@
|
||||
description: OpenISA LPUART
|
||||
|
||||
compatible: "openisa,rv32m1-lpuart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2021, IoT.bzh
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
description: Renesas R-Car UART controller
|
||||
|
||||
compatible: "renesas,rcar-scif"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
@@ -0,0 +1,27 @@
|
||||
# Copyright (c) 2020, CSIRO.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Segger RTT UART
|
||||
|
||||
compatible: "segger,rtt-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
tx-buffer-size:
|
||||
type: int
|
||||
default: 1024
|
||||
description: |
|
||||
Size of the RTT up buffer for transmission
|
||||
Not used for RTT channel 0 as channel 0 is initialized at compile time,
|
||||
see SEGGER_RTT_BUFFER_SIZE_UP.
|
||||
required: false
|
||||
|
||||
rx-buffer-size:
|
||||
type: int
|
||||
default: 16
|
||||
description: |
|
||||
Size of the RTT down buffer for reception
|
||||
Not used for RTT channel 0 as channel 0 is initialized at compile time,
|
||||
see SEGGER_RTT_BUFFER_SIZE_DOWN.
|
||||
required: false
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2018, SiFive Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: SiFive UART
|
||||
|
||||
compatible: "sifive,uart0"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,30 @@
|
||||
description: Gecko LEUART
|
||||
|
||||
compatible: "silabs,gecko-leuart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
peripheral-id:
|
||||
type: int
|
||||
required: true
|
||||
description: peripheral ID
|
||||
|
||||
# Note: Not all SoC series support setting individual pin location. If this
|
||||
# is a case all location-* properties need to have identical value.
|
||||
|
||||
location-rx:
|
||||
type: array
|
||||
required: true
|
||||
description: RX pin configuration defined as <location port pin>
|
||||
|
||||
location-tx:
|
||||
type: array
|
||||
required: true
|
||||
description: TX pin configuration defined as <location port pin>
|
||||
@@ -0,0 +1,30 @@
|
||||
description: Gecko UART
|
||||
|
||||
compatible: "silabs,gecko-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
peripheral-id:
|
||||
type: int
|
||||
required: true
|
||||
description: peripheral ID
|
||||
|
||||
# Note: Not all SoC series support setting individual pin location. If this
|
||||
# is a case all location-* properties need to have identical value.
|
||||
|
||||
location-rx:
|
||||
type: array
|
||||
required: true
|
||||
description: RX pin configuration defined as <location port pin>
|
||||
|
||||
location-tx:
|
||||
type: array
|
||||
required: true
|
||||
description: TX pin configuration defined as <location port pin>
|
||||
@@ -0,0 +1,40 @@
|
||||
description: Gecko USART
|
||||
|
||||
compatible: "silabs,gecko-usart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
peripheral-id:
|
||||
type: int
|
||||
required: true
|
||||
description: peripheral ID
|
||||
|
||||
# Note: Not all SoC series support setting individual pin location. If this
|
||||
# is a case all location-* properties need to have identical value.
|
||||
|
||||
location-rx:
|
||||
type: array
|
||||
required: true
|
||||
description: RX pin configuration defined as <location port pin>
|
||||
|
||||
location-tx:
|
||||
type: array
|
||||
required: true
|
||||
description: TX pin configuration defined as <location port pin>
|
||||
|
||||
location-rts:
|
||||
type: array
|
||||
required: false
|
||||
description: RTS pin configuration defined as <location port pin>
|
||||
|
||||
location-cts:
|
||||
type: array
|
||||
required: false
|
||||
description: CTS pin configuration defined as <location port pin>
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2019, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Synopsys ARC nSIM UART
|
||||
|
||||
compatible: "snps,nsim-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,21 @@
|
||||
description: STM32 LPUART
|
||||
|
||||
compatible: "st,stm32-lpuart"
|
||||
|
||||
include: [uart-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
@@ -0,0 +1,18 @@
|
||||
description: STM32 UART
|
||||
|
||||
compatible: "st,stm32-uart"
|
||||
|
||||
include: [uart-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
@@ -0,0 +1,18 @@
|
||||
description: STM32 USART
|
||||
|
||||
compatible: "st,stm32-usart"
|
||||
|
||||
include: [uart-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2021, Telink Semiconductor
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Telink B91 UART
|
||||
|
||||
compatible: "telink,b91-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2019 Brett Witherspoon
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: TI SimpleLink CC13xx / CC26xx UART node
|
||||
|
||||
compatible: "ti,cc13xx-cc26xx-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
tx-pin:
|
||||
type: array
|
||||
required: true
|
||||
description: TX pin
|
||||
|
||||
rx-pin:
|
||||
type: array
|
||||
required: true
|
||||
description: RX pin
|
||||
@@ -0,0 +1,12 @@
|
||||
description: TI CC32XX UART
|
||||
|
||||
compatible: "ti,cc32xx-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
description: TI MSP432P4XX UART
|
||||
|
||||
compatible: "ti,msp432p4xx-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
description: TI Stellaris UART
|
||||
|
||||
compatible: "ti,stellaris-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,31 @@
|
||||
# Common fields for UART controllers
|
||||
|
||||
include: base.yaml
|
||||
|
||||
bus: uart
|
||||
|
||||
properties:
|
||||
clock-frequency:
|
||||
type: int
|
||||
required: false
|
||||
description: Clock frequency information for UART operation
|
||||
current-speed:
|
||||
type: int
|
||||
required: false
|
||||
description: Initial baud rate setting for UART
|
||||
label:
|
||||
required: true
|
||||
hw-flow-control:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Set to enable RTS/CTS flow control at boot time
|
||||
parity:
|
||||
required: false
|
||||
type: string
|
||||
description: |
|
||||
Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
|
||||
and 2 for even parity. Default to none if not specified.
|
||||
enum:
|
||||
- "none"
|
||||
- "odd"
|
||||
- "even"
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2018, Foundries.io
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for UART devices
|
||||
|
||||
include: base.yaml
|
||||
|
||||
on-bus: uart
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,9 @@
|
||||
description: Xilinx UART Lite IP
|
||||
|
||||
compatible: "xlnx,xps-uartlite-1.00.a"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,9 @@
|
||||
description: Xilinx PS UART
|
||||
|
||||
compatible: "xlnx,xuartps"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,10 @@
|
||||
# Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: USB CDC ACM UART
|
||||
|
||||
compatible: "zephyr,cdc-acm-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
|
||||
on-bus: usb
|
||||
@@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2019, Jan Van Winkel (jan.van_winkel@dxplore.eu)
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Native POSIX UART
|
||||
|
||||
compatible: "zephyr,native-posix-uart"
|
||||
|
||||
include: uart-controller.yaml
|
||||
Reference in New Issue
Block a user