mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-11-15 01:41:35 +08:00
WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,17 @@
|
||||
# Copyright (c) 2018 omSquare s.r.o.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Atmel SAM0 RTC
|
||||
|
||||
compatible: "atmel,sam0-rtc"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clock-generator:
|
||||
type: int
|
||||
description: clock generator index
|
||||
required: true
|
||||
@@ -0,0 +1,39 @@
|
||||
#
|
||||
# Copyright (c) 2019 Peter Bigot Consulting, LLC
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: Maxim DS3231 I2C RTC/TCXO
|
||||
|
||||
compatible: "maxim,ds3231"
|
||||
|
||||
include: i2c-device.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
32k-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
|
||||
32 KiHz open drain output
|
||||
|
||||
The DS3231 defaults to providing a 32 KiHz square wave on this
|
||||
signal. The driver does not make use of this, but applications
|
||||
may want access.
|
||||
|
||||
isw-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
|
||||
interrupt/square wave open drain output
|
||||
|
||||
The DS3231 uses this signal to notify when an alarm has triggered,
|
||||
and also to produce a square wave aligned to the countdown chain.
|
||||
Both capabilities are used within the driver. This signal must be
|
||||
present to support time set and read operations that preserve
|
||||
sub-second accuracy.
|
||||
@@ -0,0 +1,24 @@
|
||||
#
|
||||
# Copyright (c) 2021 Laird Connectivity
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: Microchip MCP7940N I2C RTC
|
||||
|
||||
compatible: "microchip,mcp7940n"
|
||||
|
||||
include: i2c-device.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
int-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
|
||||
Host input connected to the MCP7940N MFP open drain output pin
|
||||
|
||||
Notifies when an alarm has triggered by asserting this line.
|
||||
@@ -0,0 +1,54 @@
|
||||
# Copyright (c) 2019, Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip XEC basic timer
|
||||
|
||||
compatible: "microchip,xec-timer"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clock-frequency:
|
||||
required: true
|
||||
|
||||
prescaler:
|
||||
type: int
|
||||
required: true
|
||||
description: Timer frequency equals clock-frequency divided by the prescaler value
|
||||
|
||||
max-value:
|
||||
type: int
|
||||
required: true
|
||||
description: Maximum counter value the instance can handle
|
||||
|
||||
girqs:
|
||||
type: array
|
||||
required: true
|
||||
description: Array of GIRQ numbers [8:26] and bit positions [0:31].
|
||||
|
||||
pcrs:
|
||||
type: array
|
||||
required: true
|
||||
description: PCR sleep enable register index and bit position.
|
||||
|
||||
"#girq-cells":
|
||||
type: int
|
||||
const: 2
|
||||
|
||||
"#pcr-cells":
|
||||
type: int
|
||||
const: 2
|
||||
|
||||
girq-cells:
|
||||
- girq_num
|
||||
- bitpos
|
||||
|
||||
pcr-cells:
|
||||
- reg_index
|
||||
- bitpos
|
||||
@@ -0,0 +1,37 @@
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nordic nRF RTC (Real-Time Counter)
|
||||
|
||||
compatible: "nordic,nrf-rtc"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
cc-num:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Number of compare (CC) registers available.
|
||||
|
||||
On nRF53 these registers can also be used for capture.
|
||||
|
||||
# If enabled, overflow different than full range (24 bits) is handled
|
||||
# through PPI channel which ensures precise timing. If disabled then
|
||||
# counter is cleared in the interrupt which results in accumulative error
|
||||
# of counter period if top value is different than maximal.
|
||||
ppi-wrap:
|
||||
type: boolean
|
||||
description: Enable wrapping with PPI
|
||||
required: false
|
||||
|
||||
# If enabled then counter based on nRF RTC peripheral supports only maximal
|
||||
# top value. That results in code optimizations and availability of one more
|
||||
# channel
|
||||
fixed-top:
|
||||
type: boolean
|
||||
description: Enable fixed top value
|
||||
required: false
|
||||
@@ -0,0 +1,11 @@
|
||||
#
|
||||
# Copyright (c) 2021 Basalte bv
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: NXP SNVS LP/HP RTC
|
||||
|
||||
compatible: "nxp,imx-snvs-rtc"
|
||||
|
||||
include: rtc.yaml
|
||||
@@ -0,0 +1,33 @@
|
||||
# Copyright (c) 2020 Vestas Wind Systems A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Kinetis LPTMR
|
||||
|
||||
compatible: "nxp,kinetis-lptmr"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clock-frequency:
|
||||
required: true
|
||||
|
||||
prescaler:
|
||||
required: true
|
||||
|
||||
clk-source:
|
||||
type: int
|
||||
required: true
|
||||
description: Prescaler clock source (0 to 3)
|
||||
|
||||
input-pin:
|
||||
type: int
|
||||
required: false
|
||||
description: Pulse counter input pin (0 to 3).
|
||||
|
||||
active-low:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Pulse counter input pin is active-low
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright 2020 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP MCUX Periodic Interrupt Timer (PIT)
|
||||
|
||||
compatible: "nxp,kinetis-pit"
|
||||
|
||||
include: [rtc.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
pit-channel:
|
||||
type: int
|
||||
required: true
|
||||
description: pit channel to active
|
||||
|
||||
pit-period:
|
||||
type: int
|
||||
required: true
|
||||
description: pit default period in us
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2018, blik GmbH
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Kinetis RTC
|
||||
|
||||
compatible: "nxp,kinetis-rtc"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2018, blik GmbH
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for RTC devices
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
clock-frequency:
|
||||
type: int
|
||||
required: false
|
||||
description: Clock frequency information for RTC operation
|
||||
label:
|
||||
required: true
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
prescaler:
|
||||
type: int
|
||||
required: false
|
||||
description: RTC frequency equals clock-frequency divided by the prescaler value
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2019, Piotr Mienkowski
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Silabs Gecko RTCC (Real-Time Counter)
|
||||
|
||||
compatible: "silabs,gecko-rtcc"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2018, Workaround GmbH
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STM32 RTC
|
||||
|
||||
compatible: "st,stm32-rtc"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,15 @@
|
||||
#
|
||||
# Copyright (c) 2019, Texas Instruments Incorporated
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: TI SimpleLink CC13xx/CC26xx RTC
|
||||
|
||||
compatible: "ti,cc13xx-cc26xx-rtc"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,71 @@
|
||||
description: Xilinx AXI Timer IP node
|
||||
|
||||
compatible: "xlnx,xps-timer-1.00.a"
|
||||
|
||||
include: rtc.yaml
|
||||
|
||||
# Property names correspond to those used by Xilinx PetaLinux:
|
||||
# https://github.com/Xilinx/meta-xilinx
|
||||
|
||||
properties:
|
||||
clock-frequency:
|
||||
required: true
|
||||
|
||||
xlnx,count-width:
|
||||
type: int
|
||||
required: true
|
||||
enum:
|
||||
- 8
|
||||
- 16
|
||||
- 32
|
||||
description: |
|
||||
Individual timer/counter width in bits.
|
||||
|
||||
xlnx,gen0-assert:
|
||||
type: int
|
||||
required: false
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
description: |
|
||||
Active state of the generateout0 signal (0 for active-low, 1 for
|
||||
active-high).
|
||||
|
||||
xlnx,gen1-assert:
|
||||
type: int
|
||||
required: false
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
description: |
|
||||
Active state of the generateout1 signal (0 for active-low, 1 for
|
||||
active-high).
|
||||
|
||||
xlnx,one-timer-only:
|
||||
type: int
|
||||
required: true
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
description: |
|
||||
0 if both Timer 1 and Timer 2 are enabled, 1 if only Timer 1 is enabled.
|
||||
|
||||
xlnx,trig0-assert:
|
||||
type: int
|
||||
required: false
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
description: |
|
||||
Active state of the capturetrig0 signal (0 for active-low, 1 for
|
||||
active-high).
|
||||
|
||||
xlnx,trig1-assert:
|
||||
type: int
|
||||
required: false
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
description: |
|
||||
Active state of the capturetrig1 signal (0 for active-low, 1 for
|
||||
active-high).
|
||||
Reference in New Issue
Block a user