WIP: device tree MVP

dts/bindings/riscv/openisa,rv32m1-pcc.yaml

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+# Copyright (c) 2018 Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 PCC (Peripheral Clock Control) IP node
+
+compatible: "openisa,rv32m1-pcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - name

dts/bindings/riscv/riscv,cpus.yaml

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+# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+include: cpu.yaml
+
+properties:
+  mmu-type:
+    description: Memory Management Unit (MMU)
+    required: false
+    type: string
+    enum:
+      - riscv,sv32
+      - riscv,sv39
+      - riscv,sv48
+      - riscv,none
+
+  riscv,isa:
+    description: RISC-V instruction set architecture
+    required: true
+    type: string
+    enum:
+      - rv32imac
+      - rv32imafc
+      - rv32imafcb
+      - rv64imac
+      - rv64imafdc
+
+  riscv,pmpregions:
+    description: Physical Memory Protection (PMP)
+    required: true
+    type: int

dts/bindings/riscv/riscv,sifive-e24.yaml

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+# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive E24 Standard Core CPU
+
+compatible: "riscv,sifive-e24"
+
+include: riscv,sifive.yaml

dts/bindings/riscv/riscv,sifive.yaml

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+# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for SiFive RISC-V CPUs
+
+include: riscv,cpus.yaml
+
+properties:
+    hardware-exec-breakpoint-count:
+      type: int
+      required: false
+      description: Number of hardware break points