mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,33 @@
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# Copyright (c) 2020, Linaro Limited
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# Copyright (c) 2021, Gerson Fernando Budke
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Atmel SAM Pinctrl container node
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The Atmel SAM pins implements following pin configuration option:
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||||
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||||
* bias-pull-up
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* bias-pull-down
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* drive-open-drain
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||||
These options define devicetree flags that are converted to SoC flags at
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ATMEL_SAM_PIN_FLAGS().
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compatible: "atmel,sam-pinctrl"
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include: [base.yaml, pincfg-node.yaml]
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properties:
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"#address-cells":
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required: true
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||||
const: 1
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||||
"#size-cells":
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||||
required: true
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||||
const: 1
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||||
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||||
child-binding:
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||||
description: Atmel pins
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properties:
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"atmel,pins":
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type: phandle-array
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@@ -0,0 +1,55 @@
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# Copyright (c) 2020, Linaro Limited
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# Copyright (c) 2021, Gerson Fernando Budke
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||||
# SPDX-License-Identifier: Apache-2.0
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description: |
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Atmel SAM0 Pinctrl container node
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The Atmel SAM0 pins implements following pin configuration option:
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* bias-pull-up
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* bias-pull-down
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* drive-strength
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* input-enable
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* output-enable
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* pinmux-enable
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These options define devicetree flags that are converted to SoC flags at
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ATMEL_SAM0_PIN_FLAGS().
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compatible: "atmel,sam0-pinctrl"
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include:
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- name: base.yaml
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- name: pincfg-node.yaml
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child-binding:
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property-allowlist:
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- bias-pull-up
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- bias-pull-down
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- drive-strength
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- input-enable
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- output-enable
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properties:
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reg:
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required: true
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properties:
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"#address-cells":
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required: true
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const: 1
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"#size-cells":
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required: true
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const: 1
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child-binding:
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description: Atmel pins
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properties:
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"atmel,pins":
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type: phandle-array
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pinmux-enable:
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required: false
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type: boolean
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description: |
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Assign pin to an embedded device peripheral
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@@ -0,0 +1,13 @@
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description: Atmel SAM0 PINMUX
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compatible: "atmel,sam0-pinmux"
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include: base.yaml
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properties:
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reg:
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required: true
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pinmux-cells:
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- pin
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- function
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@@ -0,0 +1,36 @@
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# Copyright (c) 2020, Linaro Limited
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# Copyright (c) 2021, ATL Electronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Cypress PSoC-6 Pinctrl container node
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The Cypress PSoC-6 pins implements following pin configuration option:
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* bias-pull-up
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* bias-pull-down
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* drive-open-drain
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* drive-open-source
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* drive-push-pull (strong)
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* input-enable (input-buffer)
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These options define devicetree flags that are converted to SoC flags at
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CY_PSOC6_PIN_FLAGS().
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compatible: "cypress,psoc6-pinctrl"
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include: [base.yaml, pincfg-node.yaml]
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properties:
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"#address-cells":
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required: true
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const: 1
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"#size-cells":
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required: true
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const: 1
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child-binding:
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description: cypress pins
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properties:
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"cypress,pins":
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type: phandle-array
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@@ -0,0 +1,12 @@
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# Copyright (c) 2019 Mohamed ElShahawi
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# SPDX-License-Identifier: Apache-2.0
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description: ESP32 PINMUX
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compatible: "espressif,esp32-pinmux"
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include: base.yaml
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properties:
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reg:
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required: true
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@@ -0,0 +1,30 @@
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# Copyright (c) 2021 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The AFIO peripheral is used to configure pin remapping, EXTI sources and,
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when available, enable the I/O compensation cell.
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compatible: "gd,gd32-afio"
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include: base.yaml
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properties:
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reg:
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required: true
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label:
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required: true
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rcu-periph-clock:
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type: int
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description: Reset Control Unit Peripheral Clock ID
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required: true
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enable-cps:
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required: false
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type: boolean
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description: |
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Enable the I/O compensation cell. This option should be enabled when the
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output speed is greater than 50MHz to reduce the I/O noise effects on
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the power supply. This option is only available on certain GD32 series.
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@@ -0,0 +1,111 @@
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# Copyright (c) 2021 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The GD32 pin controller (AF model) is a singleton node responsible for
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controlling pin function selection and pin properties. For example, you can
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use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
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on the pin.
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
|
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'pinctrl' node, as shown in this example:
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/* You can put this in places like a board-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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||||
*/
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/* include pre-defined combinations for the SoC variant used by the board */
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#include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
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&pinctrl {
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/* configuration for the usart0 "default" state */
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usart0_default: usart0_default {
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/* group 1 */
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group1 {
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/* configure PA9 as USART0 TX and PA11 as USART0 CTS */
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pinmux = <USART0_TX_PA9>, <USART0_CTS_PA11>;
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};
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/* group 2 */
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group2 {
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/* configure PA10 as USART0 RX and PA12 as USART0 RTS */
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pinmux = <USART0_RX_PA10>, <USART0_RTS_PA12>;
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/* both PA10 and PA12 have pull-up enabled */
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bias-pull-up;
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};
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/* configuration for the usart0 "sleep" state */
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usart0_sleep: usart0_sleep {
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/* group 1 */
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group1 {
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/* configure PA9, PA10, PA11 and PA12 in analog mode */
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pinmux = <ANALOG_PA9>, <ANALOG_PA10>, <ANALOG_PA12>, <ANALOG_PA11>;
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};
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};
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The 'usart0_default' child node encodes the pin configurations for a
|
||||
particular state of a device; in this case, the default (that is, active)
|
||||
state. Similarly, 'usart0_sleep' child node encodes the pin configurations
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||||
for the sleep state (used in device low power mode). Note that analog mode
|
||||
is used for low power states because it disconnects the pin pull-up/down
|
||||
resistor, schmitt trigger, and output buffer.
|
||||
|
||||
As shown, pin configurations are organized in groups within each child node.
|
||||
Each group can specify a list of pin function selections in the 'pinmux'
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||||
property.
|
||||
|
||||
A group can also specify shared pin properties common to all the specified
|
||||
pins, such as the 'bias-pull-up' property in group 2. Here is a list of
|
||||
supported standard pin properties:
|
||||
|
||||
- drive-push-pull: Push-pull drive mode (default, not required).
|
||||
- drive-open-drain: Open-drain drive mode.
|
||||
- bias-disable: Disable pull-up/down (default, not required).
|
||||
- bias-pull-up: Enable pull-up resistor.
|
||||
- bias-pull-down: Enable pull-down resistor.
|
||||
- slew-rate: Set the maximum speed (and so the slew-rate) of the output
|
||||
signal (default: 2MHz).
|
||||
|
||||
Note that drive and bias options are mutually exclusive.
|
||||
|
||||
To link pin configurations with a device, use a pinctrl-N property for some
|
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number N, like this example you could place in your board's DTS file:
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||||
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#include "board-pinctrl.dtsi"
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&usart0 {
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pinctrl-0 = <&usart0_default>;
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pinctrl-1 = <&usart0_sleep>;
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||||
pinctrl-names = "default", "sleep";
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||||
};
|
||||
|
||||
compatible: "gd,gd32-pinctrl-af"
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||||
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||||
include: gd,gd32-pinctrl-common.yaml
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||||
|
||||
child-binding:
|
||||
description: |
|
||||
Each child node defines the configuration for a particular state.
|
||||
child-binding:
|
||||
description: |
|
||||
The grandchild nodes group pins that share the same pin configuration.
|
||||
properties:
|
||||
slew-rate:
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||||
required: false
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||||
type: string
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||||
default: "max-speed-2mhz"
|
||||
enum:
|
||||
- "max-speed-2mhz"
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||||
- "max-speed-25mhz"
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||||
- "max-speed-50mhz"
|
||||
- "max-speed-200mhz"
|
||||
description: |
|
||||
Set the maximum speed of a pin. This setting effectively limits the
|
||||
slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC
|
||||
default.
|
||||
@@ -0,0 +1,137 @@
|
||||
# Copyright (c) 2021 Teslabs Engineering S.L.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
The GD32 pin controller (AFIO model) is a singleton node responsible for
|
||||
controlling pin function selection and pin properties. For example, you can
|
||||
use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
|
||||
on the pin. Remapping is also supported.
|
||||
|
||||
The node has the 'pinctrl' node label set in your SoC's devicetree,
|
||||
so you can modify it like this:
|
||||
|
||||
&pinctrl {
|
||||
/* your modifications go here */
|
||||
};
|
||||
|
||||
All device pin configurations should be placed in child nodes of the
|
||||
'pinctrl' node, as shown in this example:
|
||||
|
||||
/* You can put this in places like a board-pinctrl.dtsi file in
|
||||
* your board directory, or a devicetree overlay in your application.
|
||||
*/
|
||||
|
||||
/* include pre-defined combinations for the SoC variant used by the board */
|
||||
#include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
|
||||
|
||||
&pinctrl {
|
||||
/* configuration for the usart0 "default" state */
|
||||
usart0_default: usart0_default {
|
||||
/* group 1 */
|
||||
group1 {
|
||||
/* configure PA9 as USART0 TX and PA11 as USART0 CTS (no remap) */
|
||||
pinmux = <USART0_TX_PA9_NORMP>, <USART0_CTS_PA11_NORMP>;
|
||||
};
|
||||
/* group 2 */
|
||||
group2 {
|
||||
/* configure PA10 as USART0 RX and PA12 as USART0 RTS (no remap) */
|
||||
pinmux = <USART0_RX_PA10_NORMP>, <USART0_RTS_PA12_NORMP>;
|
||||
/* both PA10 and PA12 have pull-up enabled */
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
/* configuration for the usart0 "sleep" state */
|
||||
usart0_sleep: usart0_sleep {
|
||||
/* group 1 */
|
||||
group1 {
|
||||
/* configure PA9, PA10, PA11 and PA12 in analog mode */
|
||||
pinmux = <ANALOG_PA9>, <ANALOG_PA10>, <ANALOG_PA12>, <ANALOG_PA11>;
|
||||
};
|
||||
};
|
||||
|
||||
The 'usart0_default' child node encodes the pin configurations for a
|
||||
particular state of a device; in this case, the default (that is, active)
|
||||
state. Similarly, 'usart0_sleep' child node encodes the pin configurations
|
||||
for the sleep state (used in device low power mode). Note that analog mode
|
||||
is used for low power states because it disconnects the pin pull-up/down
|
||||
resistor, schmitt trigger, and output buffer.
|
||||
|
||||
As shown, pin configurations are organized in groups within each child node.
|
||||
Each group can specify a list of pin function selections in the 'pinmux'
|
||||
property.
|
||||
|
||||
A group can also specify shared pin properties common to all the specified
|
||||
pins, such as the 'bias-pull-up' property in group 2. Here is a list of
|
||||
supported standard pin properties:
|
||||
|
||||
- drive-push-pull: Push-pull drive mode (default, not required). Only
|
||||
applies for GPIO_IN mode.
|
||||
- drive-open-drain: Open-drain drive mode. Only applies for GPIO_IN mode.
|
||||
- bias-disable: Disable pull-up/down (default, not required). Only applies
|
||||
for GPIO_IN mode.
|
||||
- bias-pull-up: Enable pull-up resistor. Only applies for GPIO_IN mode.
|
||||
- bias-pull-down: Enable pull-down resistor. Only applies for GPIO_IN mode.
|
||||
- slew-rate: Set the maximum speed (and so the slew-rate) of the output
|
||||
signal (default: 2MHz). Only applies for ALTERNATE mode.
|
||||
|
||||
Note that drive and bias options are mutually exclusive.
|
||||
|
||||
Peripherals that are remappable will have their pre-defined macros suffixed
|
||||
with the remap option being selected, for example:
|
||||
|
||||
- CAN0_RX_PA11_NORMP: No remap
|
||||
- CAN0_RX_PB8_PRMP: Partial remap
|
||||
- CAN0_RX_PD0_FRMP: Full remap
|
||||
|
||||
It is important that **ALL** pinmux entries share the same remap. For
|
||||
example:
|
||||
|
||||
&pinctrl {
|
||||
can0_default: can0_default {
|
||||
group1 {
|
||||
pinmux = <CAN0_RX_PD0_FRMP>, <CAN0_TX_PD1_FRMP>;
|
||||
/* ^^^^ ^^^^ */
|
||||
/* CAN0 pins are remapped choosing the full remap option */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
To link pin configurations with a device, use a pinctrl-N property for some
|
||||
number N, like this example you could place in your board's DTS file:
|
||||
|
||||
#include "board-pinctrl.dtsi"
|
||||
|
||||
&usart0 {
|
||||
pinctrl-0 = <&usart0_default>;
|
||||
pinctrl-1 = <&usart0_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
};
|
||||
|
||||
compatible: "gd,gd32-pinctrl-afio"
|
||||
|
||||
include: gd,gd32-pinctrl-common.yaml
|
||||
|
||||
child-binding:
|
||||
description: |
|
||||
Each child node defines the configuration for a particular state.
|
||||
child-binding:
|
||||
description: |
|
||||
The grandchild nodes group pins that share the same pin configuration.
|
||||
properties:
|
||||
slew-rate:
|
||||
required: false
|
||||
type: string
|
||||
default: "max-speed-2mhz"
|
||||
enum:
|
||||
- "max-speed-10mhz"
|
||||
- "max-speed-2mhz"
|
||||
- "max-speed-50mhz"
|
||||
- "max-speed-highest"
|
||||
description: |
|
||||
Set the maximum speed of a pin. This setting effectively limits the
|
||||
slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC
|
||||
default. The max-speed-highest option may not be available on all SoC
|
||||
variants. If selected and not available the 50 MHz maximum speed will
|
||||
be used instead. Note that usage of max-speed-highest may require
|
||||
enabling the I/O compensation cell (refer to the gd,gd32-afio binding
|
||||
for more details).
|
||||
@@ -0,0 +1,26 @@
|
||||
# Copyright (c) 2021 Teslabs Engineering S.L.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
include:
|
||||
- name: base.yaml
|
||||
- name: pincfg-node-group.yaml
|
||||
child-binding:
|
||||
child-binding:
|
||||
property-allowlist:
|
||||
- drive-push-pull
|
||||
- drive-open-drain
|
||||
- bias-disable
|
||||
- bias-pull-down
|
||||
- bias-pull-up
|
||||
|
||||
child-binding:
|
||||
child-binding:
|
||||
properties:
|
||||
pinmux:
|
||||
required: true
|
||||
type: array
|
||||
description: |
|
||||
An array of pins sharing the same group properties. The pins should
|
||||
be defined using pre-defined macros or, alternatively, using the
|
||||
GD32_PINMUX_AF or GD32_PINMUX_AFIO utility macros depending on the
|
||||
pinmux model used by the SoC series.
|
||||
@@ -0,0 +1,14 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
description: Intel S1000 pinmux
|
||||
|
||||
compatible: "intel,s1000-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
pinmux-cells:
|
||||
- pin
|
||||
- function
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ITE IT8XXX2 Pin-Mux Configuration
|
||||
|
||||
compatible: "ite,it8xxx2-pinctrl-conf"
|
||||
child-binding:
|
||||
description: ITE Pinmux configuration child node
|
||||
properties:
|
||||
pinctrls:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: Pin alternate function selection
|
||||
@@ -0,0 +1,32 @@
|
||||
# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ITE IT8XXX2 pinmux node
|
||||
|
||||
compatible: "ite,it8xxx2-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
func3_gcr:
|
||||
type: array
|
||||
required: true
|
||||
|
||||
func3_en_mask:
|
||||
type: array
|
||||
required: true
|
||||
|
||||
func4_gcr:
|
||||
type: array
|
||||
required: true
|
||||
|
||||
func4_en_mask:
|
||||
type: array
|
||||
required: true
|
||||
|
||||
pinctrl-cells:
|
||||
- pin
|
||||
- alt_func
|
||||
@@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip XEC Pinmux node
|
||||
|
||||
compatible: "microchip,xec-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
child-binding:
|
||||
description: pinmux child node
|
||||
properties:
|
||||
ph-reg:
|
||||
type: phandle
|
||||
required: true
|
||||
|
||||
port-num:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Zero based GPIO port number. Pin group 000 - 036 is port 0,
|
||||
040 - 076 is port 1, etc.
|
||||
@@ -0,0 +1,110 @@
|
||||
# Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
The nRF pin controller is a singleton node responsible for controlling
|
||||
pin function selection and pin properties. For example, you can use this
|
||||
node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
|
||||
pin.
|
||||
|
||||
The node has the 'pinctrl' node label set in your SoC's devicetree,
|
||||
so you can modify it like this:
|
||||
|
||||
&pinctrl {
|
||||
/* your modifications go here */
|
||||
};
|
||||
|
||||
All device pin configurations should be placed in child nodes of the
|
||||
'pinctrl' node, as shown in this example:
|
||||
|
||||
/* You can put this in places like a board-pinctrl.dtsi file in
|
||||
* your board directory, or a devicetree overlay in your application.
|
||||
*/
|
||||
&pinctrl {
|
||||
/* configuration for uart0 device, default state */
|
||||
uart0_default: uart0_default {
|
||||
/* group 1 ('group1' name is arbitrary) */
|
||||
group1 {
|
||||
/* configure P0.1 as UART_TX and P0.2 as UART_RTS */
|
||||
psels = <NRF_PSEL(UART_TX, 0, 1)>, <NRF_PSEL(UART_RTS, 0, 2)>;
|
||||
};
|
||||
/* group 2 */
|
||||
group2 {
|
||||
/* configure P0.3 as UART_RX and P0.4 as UART_CTS */
|
||||
psels = <NRF_PSEL(UART_RX, 0, 3)>, <NRF_PSEL(UART_CTS, 0, 4)>;
|
||||
/* both P0.3 and P0.4 are configured with pull-up */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
The 'uart0_default' child node encodes the pin configurations for a
|
||||
particular state of a device; in this case, the default (that is, active)
|
||||
state. You would specify the low-power configuration for the same device
|
||||
in a separate child node.
|
||||
|
||||
As shown, pin configurations are organized in groups within each child node.
|
||||
Each group can specify a list of pin function selections in the 'psels'
|
||||
property. The NRF_PSEL macro is used to specify a pin function selection.
|
||||
Available pin functions can be found in the
|
||||
include/dt-bindings/pinctrl/nrf-pinctrl.h header file.
|
||||
|
||||
A group can also specify shared pin properties common to all the specified
|
||||
pins, such as the 'bias-pull-up' property in group 2. Here is a list of
|
||||
supported standard pin properties:
|
||||
|
||||
- bias-disable: Disable pull-up/down (default behavior, not required).
|
||||
- bias-pull-up: Enable pull-up resistor.
|
||||
- bias-pull-down: Enable pull-down resistor.
|
||||
- low-power-enable: Configure pin as an input with input buffer
|
||||
disconnected.
|
||||
|
||||
Note that bias options are mutually exclusive.
|
||||
|
||||
To link this pin configuration with a device, use a pinctrl-N property
|
||||
for some number N, like this example you could place in your board's DTS
|
||||
file:
|
||||
|
||||
#include "board-pinctrl.dtsi"
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
compatible: "nordic,nrf-pinctrl"
|
||||
|
||||
include:
|
||||
- name: base.yaml
|
||||
- name: pincfg-node-group.yaml
|
||||
child-binding:
|
||||
child-binding:
|
||||
property-allowlist:
|
||||
- bias-disable
|
||||
- bias-pull-down
|
||||
- bias-pull-up
|
||||
- low-power-enable
|
||||
|
||||
child-binding:
|
||||
description: |
|
||||
nRF pin controller pin configuration state nodes.
|
||||
child-binding:
|
||||
description: |
|
||||
nRF pin controller pin configuration group.
|
||||
properties:
|
||||
psels:
|
||||
required: true
|
||||
type: array
|
||||
description: |
|
||||
An array of pins sharing the same group properties. The pins should
|
||||
be defined using the NRF_PSEL utility macro that encodes the port,
|
||||
pin and function.
|
||||
|
||||
drive-mode:
|
||||
type: int
|
||||
default: 0
|
||||
description: |
|
||||
Pin output drive mode. Available drive modes are pre-defined in
|
||||
nrf-pinctrl.h. Note that extra modes may not be available on certain
|
||||
devices. Defaults to standard mode for 0 and 1 (NRF_DRIVE_S0S1), the
|
||||
SoC default.
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nuvoton NPCX7 Low-Voltage level detection configuration map
|
||||
between Nuvoton NPCX GPIO and low-voltage controller (LV_GPIO_CTL)
|
||||
driver instances.
|
||||
|
||||
compatible: "nuvoton,npcx-lvolctrl-conf"
|
||||
|
||||
child-binding:
|
||||
description: Child node to present the mapping between GPIO pad and its low-voltage support
|
||||
properties:
|
||||
lvols:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: list of configurations map between io and low-voltage controllers
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX Default Low-Voltage Configurations
|
||||
|
||||
compatible: "nuvoton,npcx-lvolctrl-def"
|
||||
|
||||
include: [base.yaml]
|
||||
|
||||
properties:
|
||||
lvol-io-pads:
|
||||
type: phandles
|
||||
required: false
|
||||
description: list of low-voltage configurations that need to set by default
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nuvoton NPCX7 Pin-Mux Configuration
|
||||
Configuration map from Nuvoton NPCX GPIO to pinmux controller
|
||||
(SCFG) driver instances.
|
||||
|
||||
compatible: "nuvoton,npcx-pinctrl-conf"
|
||||
child-binding:
|
||||
description: NPCX Pinmux configuration child node
|
||||
properties:
|
||||
alts:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: A SCFG ALT (Alternative controllers) specifier for pinmuxing of npcx ec
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX Default Pins Configurations
|
||||
|
||||
compatible: "nuvoton,npcx-pinctrl-def"
|
||||
|
||||
include: [base.yaml]
|
||||
|
||||
properties:
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
description: list of configurations of pinmux controllers need to set
|
||||
@@ -0,0 +1,44 @@
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nuvoton NPCX pads configuration map between Pin Mux controller and
|
||||
Power Switch Logic (PSL) controller driver instances.
|
||||
|
||||
compatible: "nuvoton,npcx-pslctrl-conf"
|
||||
|
||||
child-binding:
|
||||
description: |
|
||||
Child node to present the mapping between pin-mux controller
|
||||
and its power switch logic (PSL) support
|
||||
|
||||
properties:
|
||||
offset:
|
||||
type: int
|
||||
required: true
|
||||
description: Offset in PSL_CTS for status and detection mode.
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
description: Pinmux controller configuration for PSL io pads.
|
||||
|
||||
polarity-0:
|
||||
type: phandles
|
||||
required: true
|
||||
description: Active polarity configuration for PSL io pads.
|
||||
|
||||
flag:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
Detection mode and type for wake-up event detection.
|
||||
5 = Configures PSL input in detecting rising edge.
|
||||
6 = Configures PSL input in in detecting level high state.
|
||||
9 = Configures PSL input in detecting falling edge.
|
||||
10 = Configures PSL input in detecting level low state.
|
||||
enum:
|
||||
- 5
|
||||
- 6
|
||||
- 9
|
||||
- 10
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX Default Power Switch Logic (PSL) input pads configurations
|
||||
|
||||
compatible: "nuvoton,npcx-pslctrl-def"
|
||||
|
||||
include: [base.yaml]
|
||||
|
||||
properties:
|
||||
psl-in-pads:
|
||||
type: phandles
|
||||
required: true
|
||||
description: |
|
||||
list of PSL input pads that are in charge of detecting the wake-up
|
||||
signals and the related circuit will turn on core power supply
|
||||
(VCC1) from standby power state (ultra-low-power mode) later.
|
||||
@@ -0,0 +1,33 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX System Configuration (Pinmux, 1.8V support and so on) node
|
||||
|
||||
compatible: "nuvoton,npcx-scfg"
|
||||
|
||||
include: [base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#alt-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a SCFG ALT (Alternative controllers) specifier
|
||||
|
||||
"#lvol-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a SCFG LV_GPIO_CTL (Low level IO controllers) specifier
|
||||
|
||||
alt-cells:
|
||||
- group
|
||||
- bit
|
||||
- inv
|
||||
|
||||
lvol-cells:
|
||||
- io_port
|
||||
- io_bit
|
||||
- ctrl
|
||||
- bit
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2021, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX IOMUXC node
|
||||
|
||||
compatible: "nxp,imx-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
pinmux-cells:
|
||||
- pin
|
||||
- function
|
||||
@@ -0,0 +1,39 @@
|
||||
description: Kinetis pinmux node
|
||||
|
||||
compatible: "nxp,kinetis-pinmux"
|
||||
|
||||
include:
|
||||
- name: base.yaml
|
||||
- name: pincfg-node.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
child-binding:
|
||||
description: |
|
||||
NXP Kinetis Pin data. A series of child nodes that describe each pin
|
||||
configuration supported by the SoC. Each node is expected to named as
|
||||
follows - <periph>_<signal>_pt<port><pin>
|
||||
|
||||
The node will have a matching node label that board dtsi files can
|
||||
utilized to reference in pinctrl-<N> properties.
|
||||
|
||||
The following is an example for UART0 CTS signal on pin 0, with mux
|
||||
value of 2.
|
||||
|
||||
uart0_cts_pta0: uart0_cts_pta0 {
|
||||
nxp,kinetis-port-pins = < 0 2 >;
|
||||
};
|
||||
|
||||
properties:
|
||||
"nxp,kinetis-port-pins":
|
||||
description: |
|
||||
The array is expected to have two elements. The first element is the
|
||||
pin number and the second element is the mux value (i.e. PCR[MUX]).
|
||||
|
||||
type: array
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2021, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC I/O Pin Configuration (IOCON) Port I/O (PIO)
|
||||
|
||||
compatible: "nxp,lpc-iocon-pio"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2021, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC I/O Pin Configuration (IOCON)
|
||||
|
||||
compatible: "nxp,lpc-iocon"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright (c) 2020 Seagate Technology LLC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP LPC11U6X pinmux (aka IOCON) node
|
||||
|
||||
compatible: "nxp,lpc11u6x-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#pinmux-cells":
|
||||
type: int
|
||||
required: true
|
||||
const: 2
|
||||
description: number of items in a pinmux specifier
|
||||
|
||||
pinmux-cells:
|
||||
- pin
|
||||
- function
|
||||
@@ -0,0 +1,16 @@
|
||||
description: RV32M1 pinmux node
|
||||
|
||||
compatible: "openisa,rv32m1-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
pinmux-cells:
|
||||
- pin
|
||||
- function
|
||||
@@ -0,0 +1,165 @@
|
||||
# Copyright (c) 2020, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Generic pin configuration schema.
|
||||
|
||||
This file is equivalent to pincfg-node.yaml but inserts properties at a
|
||||
grandchildren level, useful for group based representation.
|
||||
|
||||
child-binding:
|
||||
child-binding:
|
||||
description: |
|
||||
Many data items that are represented in a pin configuration node are
|
||||
common and generic. Pin control bindings should use the properties
|
||||
defined below where they are applicable; not all of these properties are
|
||||
relevant or useful for all hardware or binding structures. Each
|
||||
individual binding document should state which of these generic
|
||||
properties, if any, are used, and the structure of the DT nodes that
|
||||
contain these properties.
|
||||
|
||||
This is based on Linux, documentation:
|
||||
https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
|
||||
|
||||
properties:
|
||||
bias-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: disable any pin bias
|
||||
|
||||
bias-high-impedance:
|
||||
required: false
|
||||
type: boolean
|
||||
description: high impedance mode ("third-state", "floating")
|
||||
|
||||
bias-bus-hold:
|
||||
required: false
|
||||
type: boolean
|
||||
description: latch weakly
|
||||
|
||||
bias-pull-up:
|
||||
required: false
|
||||
type: boolean
|
||||
description: enable pull-up resistor
|
||||
|
||||
bias-pull-down:
|
||||
required: false
|
||||
type: boolean
|
||||
description: enable pull-down resistor
|
||||
|
||||
bias-pull-pin-default:
|
||||
required: false
|
||||
type: boolean
|
||||
description: use pin's default pull state
|
||||
|
||||
drive-push-pull:
|
||||
required: false
|
||||
type: boolean
|
||||
description: drive actively high and low
|
||||
|
||||
drive-open-drain:
|
||||
required: false
|
||||
type: boolean
|
||||
description: drive with open drain (hardware AND)
|
||||
|
||||
drive-open-source:
|
||||
required: false
|
||||
type: boolean
|
||||
description: drive with open source (hardware OR)
|
||||
|
||||
drive-strength:
|
||||
required: false
|
||||
type: int
|
||||
description: maximum sink or source current in mA
|
||||
|
||||
drive-strength-microamp:
|
||||
required: false
|
||||
type: int
|
||||
description: maximum sink or source current in μA
|
||||
|
||||
input-enable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
enable input on pin (no effect on output, such as enabling an input
|
||||
buffer)
|
||||
|
||||
input-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
disable input on pin (no effect on output, such as disabling an input
|
||||
buffer)
|
||||
|
||||
input-schmitt-enable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: enable schmitt-trigger mode
|
||||
|
||||
input-schmitt-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: disable schmitt-trigger mode
|
||||
|
||||
input-debounce:
|
||||
required: false
|
||||
type: int
|
||||
description: |
|
||||
Takes the debounce time in μsec, as argument or 0 to disable debouncing
|
||||
|
||||
power-source:
|
||||
required: false
|
||||
type: int
|
||||
description: select between different power supplies
|
||||
|
||||
low-power-enable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: enable low power mode
|
||||
|
||||
low-power-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: disable low power mode
|
||||
|
||||
output-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: disable output on a pin (such as disable an output buffer)
|
||||
|
||||
output-enable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
enable output on a pin without actively driving it (such as enabling
|
||||
an output buffer)
|
||||
|
||||
output-low:
|
||||
required: false
|
||||
type: boolean
|
||||
description: set the pin to output mode with low level
|
||||
|
||||
output-high:
|
||||
required: false
|
||||
type: boolean
|
||||
description: set the pin to output mode with high level
|
||||
|
||||
sleep-hardware-state:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
indicate this is sleep related state which will be programmed into
|
||||
the registers for the sleep state
|
||||
|
||||
slew-rate:
|
||||
required: false
|
||||
type: int
|
||||
description: set the slew rate
|
||||
|
||||
skew-delay:
|
||||
required: false
|
||||
type: int
|
||||
description: |
|
||||
This affects the expected clock skew on input pins and the delay
|
||||
before latching a value to an output pin. Typically indicates how
|
||||
many double-inverters are used to delay the signal.
|
||||
@@ -0,0 +1,160 @@
|
||||
# Copyright (c) 2020, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Generic pin configuration schema
|
||||
|
||||
child-binding:
|
||||
description: |
|
||||
Many data items that are represented in a pin configuration node are
|
||||
common and generic. Pin control bindings should use the properties
|
||||
defined below where they are applicable; not all of these properties are
|
||||
relevant or useful for all hardware or binding structures. Each
|
||||
individual binding document should state which of these generic
|
||||
properties, if any, are used, and the structure of the DT nodes that
|
||||
contain these properties.
|
||||
|
||||
This is based on Linux, documentation:
|
||||
https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
|
||||
|
||||
properties:
|
||||
bias-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: disable any pin bias
|
||||
|
||||
bias-high-impedance:
|
||||
required: false
|
||||
type: boolean
|
||||
description: high impedance mode ("third-state", "floating")
|
||||
|
||||
bias-bus-hold:
|
||||
required: false
|
||||
type: boolean
|
||||
description: latch weakly
|
||||
|
||||
bias-pull-up:
|
||||
required: false
|
||||
type: boolean
|
||||
description: enable pull-up resistor
|
||||
|
||||
bias-pull-down:
|
||||
required: false
|
||||
type: boolean
|
||||
description: enable pull-down resistor
|
||||
|
||||
bias-pull-pin-default:
|
||||
required: false
|
||||
type: boolean
|
||||
description: use pin's default pull state
|
||||
|
||||
drive-push-pull:
|
||||
required: false
|
||||
type: boolean
|
||||
description: drive actively high and low
|
||||
|
||||
drive-open-drain:
|
||||
required: false
|
||||
type: boolean
|
||||
description: drive with open drain (hardware AND)
|
||||
|
||||
drive-open-source:
|
||||
required: false
|
||||
type: boolean
|
||||
description: drive with open source (hardware OR)
|
||||
|
||||
drive-strength:
|
||||
required: false
|
||||
type: int
|
||||
description: maximum sink or source current in mA
|
||||
|
||||
drive-strength-microamp:
|
||||
required: false
|
||||
type: int
|
||||
description: maximum sink or source current in μA
|
||||
|
||||
input-enable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
enable input on pin (no effect on output, such as enabling an input
|
||||
buffer)
|
||||
|
||||
input-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
disable input on pin (no effect on output, such as disabling an input
|
||||
buffer)
|
||||
|
||||
input-schmitt-enable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: enable schmitt-trigger mode
|
||||
|
||||
input-schmitt-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: disable schmitt-trigger mode
|
||||
|
||||
input-debounce:
|
||||
required: false
|
||||
type: int
|
||||
description: |
|
||||
Takes the debounce time in μsec, as argument or 0 to disable debouncing
|
||||
|
||||
power-source:
|
||||
required: false
|
||||
type: int
|
||||
description: select between different power supplies
|
||||
|
||||
low-power-enable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: enable low power mode
|
||||
|
||||
low-power-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: disable low power mode
|
||||
|
||||
output-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: disable output on a pin (such as disable an output buffer)
|
||||
|
||||
output-enable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
enable output on a pin without actively driving it (such as enabling
|
||||
an output buffer)
|
||||
|
||||
output-low:
|
||||
required: false
|
||||
type: boolean
|
||||
description: set the pin to output mode with low level
|
||||
|
||||
output-high:
|
||||
required: false
|
||||
type: boolean
|
||||
description: set the pin to output mode with high level
|
||||
|
||||
sleep-hardware-state:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
indicate this is sleep related state which will be programmed into
|
||||
the registers for the sleep state
|
||||
|
||||
slew-rate:
|
||||
required: false
|
||||
type: int
|
||||
description: set the slew rate
|
||||
|
||||
skew-delay:
|
||||
required: false
|
||||
type: int
|
||||
description: |
|
||||
This affects the expected clock skew on input pins and the delay
|
||||
before latching a value to an output pin. Typically indicates how
|
||||
many double-inverters are used to delay the signal.
|
||||
@@ -0,0 +1,43 @@
|
||||
# Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
This file needs to be included by devices that need to specify a set of pin
|
||||
controller states. The maximum number of supported states is 5 (pinctrl-0 ...
|
||||
pinctrl-4) but it can be incremented if required.
|
||||
|
||||
The bindings file for each pin controller driver implementation should provide
|
||||
more information on what is the expected pin configuration format.
|
||||
|
||||
properties:
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
description: |
|
||||
Pin configuration/s for the first state. Content is specific to the
|
||||
selected pin controller driver implementation.
|
||||
|
||||
pinctrl-1:
|
||||
type: phandles
|
||||
description: |
|
||||
Pin configuration/s for the second state. See pinctrl-0.
|
||||
|
||||
pinctrl-2:
|
||||
type: phandles
|
||||
description: |
|
||||
Pin configuration/s for the third state. See pinctrl-0.
|
||||
|
||||
pinctrl-3:
|
||||
type: phandles
|
||||
description: |
|
||||
Pin configuration/s for the fourth state. See pinctrl-0.
|
||||
|
||||
pinctrl-4:
|
||||
type: phandles
|
||||
description: |
|
||||
Pin configuration/s for the fifth state. See pinctrl-0.
|
||||
|
||||
pinctrl-names:
|
||||
type: string-array
|
||||
description: |
|
||||
Names for the provided states. The number of names needs to match the
|
||||
number of states.
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2021, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
SiFive FE310 IO Function (iof)
|
||||
Binding covers the IOF_EN/IOF_SEL registers that are a subset of the GPIO
|
||||
controller.
|
||||
|
||||
compatible: "sifive,iof"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
pinmux-cells:
|
||||
- pin
|
||||
- function
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (c) 2021, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Synopsys CREG HSDK GPIO pin mux
|
||||
|
||||
compatible: "snps,creg-gpio-mux-hsdk"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
pinmux-cells:
|
||||
- pin
|
||||
- function
|
||||
@@ -0,0 +1,94 @@
|
||||
# Copyright (c) 2020 Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
STM32 Pin controller Node
|
||||
Based on pincfg-node.yaml binding.
|
||||
|
||||
Note: `bias-disable` and `drive-push-pull` are default pin configurations.
|
||||
They will be applied in case no `bias-foo` or `driver-bar` properties
|
||||
are set.
|
||||
|
||||
compatible: "st,stm32-pinctrl"
|
||||
|
||||
include:
|
||||
- name: base.yaml
|
||||
- name: pincfg-node.yaml
|
||||
child-binding:
|
||||
property-allowlist:
|
||||
- bias-disable
|
||||
- bias-pull-down
|
||||
- bias-pull-up
|
||||
- drive-push-pull
|
||||
- drive-open-drain
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
remap-pa11:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Remaps the PA11 pin to operate as PA9 pin.
|
||||
Use of this property is restricted to STM32G0 SoCs.
|
||||
|
||||
remap-pa12:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Remaps the PA12 pin to operate as PA10 pin.
|
||||
Use of this property is restricted to STM32G0 SoCs.
|
||||
|
||||
remap-pa11-pa12:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Remaps the PA11/PA12 pin to operate as PA9/PA10 pin.
|
||||
Use of this property is restricted to STM32F070x SoCs.
|
||||
|
||||
child-binding:
|
||||
description: |
|
||||
This binding gives a base representation of the STM32 pins configration
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
Reused from https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
These defines are calculated as: ((port * 16 + line) << 8) | function
|
||||
With:
|
||||
- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
|
||||
- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
|
||||
- function: The function number, can be:
|
||||
* 0 : Alternate Function 0
|
||||
* 1 : Alternate Function 1
|
||||
* 2 : Alternate Function 2
|
||||
* ...
|
||||
* 15 : Alternate Function 15
|
||||
* 16 : Analog
|
||||
To simplify the usage, macro is available to generate "pinmux" field.
|
||||
This macro is available here:
|
||||
-include/dt-bindings/pinctrl/stm32-pinctrl-common.h
|
||||
Some examples of macro usage:
|
||||
GPIO A9 set as alernate function 2
|
||||
... {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF2)>;
|
||||
};
|
||||
GPIO A9 set as analog
|
||||
... {
|
||||
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
|
||||
};
|
||||
|
||||
slew-rate:
|
||||
required: false
|
||||
type: string
|
||||
default: "low-speed"
|
||||
enum:
|
||||
- "low-speed" # Default value.
|
||||
- "medium-speed"
|
||||
- "high-speed"
|
||||
- "very-high-speed"
|
||||
description: |
|
||||
Pin speed. Default to low-speed. For few pins (PA11 and
|
||||
PB3 depending on SoCs)hardware reset value could differ
|
||||
(very-high-speed). Carefully check reference manual for these pins.
|
||||
@@ -0,0 +1,105 @@
|
||||
# Copyright (c) 2020 Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STM32 Pin controller Node
|
||||
|
||||
compatible: "st,stm32f1-pinctrl"
|
||||
|
||||
include: [base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
child-binding:
|
||||
description: |
|
||||
This binding gives a base representation of the STM32F1 pins
|
||||
configration
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
Adapted from https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
These defines are calculated as: ((port * 16 + line) << 8) | (function << 6) | remap)
|
||||
With:
|
||||
- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
|
||||
- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
|
||||
- function: The configuration mode, can be:
|
||||
* 0 : Alternate function output
|
||||
* 1 : Input
|
||||
* 2 : Analog
|
||||
- remap: The pin remapping configuration. It allows to assign the pin
|
||||
function to a different peripheral. Remain configuration can be:
|
||||
* 0 : No remap
|
||||
* 1 : Partial remap 1
|
||||
* 2 : Partial remap 2
|
||||
* 3 : Partial remap 3
|
||||
* 4 : Full remap
|
||||
To simplify the usage, macro is available to generate "pinmux" field.
|
||||
This macro is available here:
|
||||
-include/dt-bindings/pinctrl/stm32f1-pinctrl.h
|
||||
Some examples of macro usage:
|
||||
GPIO A9 set as alernate with no remap
|
||||
... {
|
||||
pinmux = <STM32F1_PINMUX('A', 9, ALTERNATE, REMAP_NO)>;
|
||||
};
|
||||
GPIO A9 set as alernate with full remap
|
||||
... {
|
||||
pinmux = <STM32F1_PINMUX('A', 9, ALTERNATE, REMAP_FULL)>;
|
||||
};
|
||||
GPIO A9 set as input
|
||||
... {
|
||||
pinmux = <STM32F1_PINMUX('A', 9, GPIO_IN, REMAP_NO)>;
|
||||
};
|
||||
|
||||
bias-disable:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
Pin bias (push-pull) disabled. This is the default pin
|
||||
configuration and will be applied if no bias- property is
|
||||
specified. Only available in input mode ("floating" configuration).
|
||||
|
||||
bias-pull-down:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
Weak pull down resistor enabled. Not compatible with
|
||||
output configuration modes (atlernate or general purpose output).
|
||||
|
||||
bias-pull-up:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
Weak pull up resistor enabled. Not compatible with
|
||||
output configuration modes (atlernate or general purpose output).
|
||||
|
||||
drive-push-pull:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
Pin driven actively high and low. This is the default pin
|
||||
configueration and will be applied if no drive- property is
|
||||
specified. Only valid for output configuration modes.
|
||||
|
||||
drive-open-drain:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
Pin driven in open drain. Only valid for output
|
||||
configuration modes.
|
||||
|
||||
slew-rate:
|
||||
required: false
|
||||
type: string
|
||||
default: "max-speed-10mhz"
|
||||
enum:
|
||||
- "max-speed-10mhz" # Default
|
||||
- "max-speed-2mhz"
|
||||
- "max-speed-50mhz"
|
||||
description: |
|
||||
Pin output mode, maximum achievable speed. Only applies to
|
||||
output mode (alternate).
|
||||
@@ -0,0 +1,29 @@
|
||||
# Copyright (c) 2021, Telink Semiconductor
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Telink B91 PinMux
|
||||
|
||||
compatible: "telink,b91-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
pad-mul-sel:
|
||||
type: int
|
||||
required: true
|
||||
description: PinMux pad_mul_sel register values.
|
||||
|
||||
child-binding:
|
||||
description:
|
||||
This binding gives a base representation of the Telink B91 pins configration.
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
required: true
|
||||
type: int
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2019 Brett Witherspoon
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: TI SimpleLink CC13xx / CC26xx pinmux node
|
||||
|
||||
compatible: "ti,cc13xx-cc26xx-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
Reference in New Issue
Block a user