WIP: device tree MVP

2026-11-13 15:41:35 +08:00 · 2022-01-06 17:20:17 -05:00
parent 07d75d85cf
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+# Copyright (c) 2019 Vestas Wind Systems A/S
+# Copyright (c) 2018, Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel AT24 (or compatible) I2C EEPROM
+
+compatible: "atmel,at24"
+
+include: ["atmel,at2x-base.yaml", i2c-device.yaml]
@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel AT25 (or compatible) SPI EEPROM
+
+compatible: "atmel,at25"
+
+include: ["atmel,at2x-base.yaml", spi-device.yaml]
@@ -0,0 +1,29 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for AT24 (I2C) and AT25 (SPI) EEPROM devices
+
+include: eeprom-base.yaml
+
+properties:
+    size:
+      required: true
+    pagesize:
+      type: int
+      required: true
+      description: EEPROM page size in bytes
+    address-width:
+      type: int
+      required: true
+      description: EEPROM address width in bits
+    timeout:
+      type: int
+      required: true
+      description: EEPROM write cycle timeout in milliseconds
+    wp-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        GPIO to which the write-protect pin of the chip is connected.
+
+        The device will interpret this signal as active-low.
@@ -0,0 +1,80 @@
+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel AT45 (or compatible) SPI flash
+
+compatible: "atmel,at45"
+
+include: [spi-device.yaml]
+
+properties:
+  jedec-id:
+    type: uint8-array
+    required: true
+    description: JEDEC ID as manufacturer ID (1 byte) and device ID (2 bytes).
+
+  size:
+    type: int
+    required: true
+    description: Flash capacity in bits.
+
+  sector-size:
+    type: int
+    required: true
+    description: Flash sector size in bytes.
+
+  block-size:
+    type: int
+    required: true
+    description: Flash block size in bytes.
+
+  page-size:
+    type: int
+    required: true
+    description: Flash page size in bytes.
+
+  use-udpd:
+    type: boolean
+    required: false
+    description: |
+      When set, the driver will use the Ultra-Deep Power-Down command instead
+      of the default Deep Power-Down one to put the chip into low power mode.
+
+      From the driver perspective, as it does not rely on the contents of the
+      SRAM buffers in the chip, the difference between the Deep and Ultra-Deep
+      Power-Down modes is that the chip consumes far less power in the latter
+      but needs some more time to enter this mode and to exit from it.
+
+  enter-dpd-delay:
+    type: int
+    required: false
+    default: 0
+    description: |
+      Time, in nanoseconds, needed by the chip to enter the Deep Power-Down
+      mode (or Ultra-Deep Power-Down mode when the "use-udpd" property is set)
+      after the corresponding command is issued.
+
+  exit-dpd-delay:
+    type: int
+    required: false
+    default: 0
+    description: |
+      Time, in nanoseconds, needed by the chip to exit from the Deep Power-Down
+      mode (or Ultra-Deep Power-Down mode when the "use-udpd" property is set)
+      after the corresponding command is issued.
+
+  reset-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      The RESET pin of AT45 is active low.
+      If connected directly the MCU pin should be configured
+      as active low.
+
+  wp-gpios:
+    type: phandle-array
+    required: false
+    description: |
+      The WP pin of AT45 is active low.
+      If connected directly the MCU pin should be configured
+      as active low.
@@ -0,0 +1,18 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for EEPROM devices
+
+include: base.yaml
+
+properties:
+    size:
+      type: int
+      required: false
+      description: Total EEPROM size in bytes
+    read-only:
+      type: boolean
+      required: false
+      description: Disable writes to the EEPROM
+    label:
+      required: true
@@ -0,0 +1,39 @@
+description: Flash partitions parent node
+
+compatible: "fixed-partitions"
+
+properties:
+    "#address-cells":
+        type: int
+        required: false
+        description: number of address cells in reg property
+
+    "#size-cells":
+        type: int
+        required: false
+        description: number of size cells in reg property
+
+child-binding:
+    description: Flash partition child node
+    properties:
+       label:
+          type: string
+          required: false
+          description: Human readable string describing the device (used as device_get_binding() argument)
+       read-only:
+          type: boolean
+          required: false
+          description: if the partition is read-only or not
+       reg:
+          type: array
+          description: register space
+          required: true
+       zephyr,memory-region:
+          type: string
+          required: false
+          description: |
+            Signify that this node should result in a dedicated linker script
+            memory region in the final executable. The region address and size
+            is taken from the <reg> property, while the name is the value of
+            this property. This must only be added to memory-mapped partitions,
+            not partitions on external flash.
@@ -0,0 +1,75 @@
+# Copyright (c) 2018 Peter Bigot Consulting, LLC
+# Copyright (c) 2019-2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties used by nodes describing serial flash devices that
+# are compatible with the JESD216 Serial Flash Discoverable Parameters
+# specification.
+#
+# This allows encoding the entire BFP block in devicetree to avoid
+# reading at runtime, while still allowing the driver to pull out extra
+# data of interest, such as erase sizes.
+#
+# Alternatively the BFP block can be absent, but critical fields like
+# size can be provided directly along with the JEDEC ID of the expected
+# device to verify its presence at runtime.
+#
+# Only properties supported by parameter tables documented in the
+# JESD216 standards should be listed in this binding include file.
+
+properties:
+  jedec-id:
+    type: uint8-array
+    required: false
+    description: JEDEC ID as manufacturer ID, memory type, memory density
+
+  size:
+    type: int
+    required: false
+    description: flash capacity in bits
+
+  sfdp-bfp:
+    type: uint8-array
+    required: false
+    description: |
+      Contains the 32-bit words in little-endian byte order from the
+      JESD216 Serial Flash Discoverable Parameters Basic Flash
+      Parameters table.  This provides flash-specific configuration
+      information in cases were runtime retrieval of SFDP data
+      is not desired.
+
+  quad-enable-requirements:
+    type: string
+    enum:
+      - "NONE"
+      - "S2B1v1"
+      - "S1B6"
+      - "S2B7"
+      - "S2B1v4"
+      - "S2B1v5"
+      - "S2B1v6"
+    required: false
+    description: |
+      Quad Enable Requirements value from JESD216 BFP DW15.
+
+      Use NONE if the device detects 1-1-4 and 1-4-4 modes by the
+      instruction.  Use S1B6 if QE is bit 6 of the first status register
+      byte, and can be configured by reading then writing one byte with
+      RDSR and WRSR.  For other fields see the specification.
+
+  enter-4byte-addr:
+    type: int
+    required: false
+    description: |
+      Enter 4-Byte Addressing value from JESD216 BFP DW16
+
+      This property is ignored if the device is configured to use SFDP data
+      from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read
+      SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).
+
+      For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24
+      of DW16 identifying ways a device can be placed into 4-byte addressing
+      mode.  If provided as a non-zero value the driver assumes that 4-byte
+      addressing is require to access the full address range, and
+      automatically puts the device into 4-byte address mode when the device
+      is initialized.
@@ -0,0 +1,97 @@
+# Copyright (c) 2018 Peter Bigot Consulting, LLC
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common properties used by nodes describing M25P80-compatible SPI NOR
+# serial flash devices, regardless of which Zephyr driver is being used.
+#
+# This extends JESD216-defined features with additional functionality
+# that may be specific to the vendor of a M25P80-compatible device and
+# only supported in certain drivers.  Any information that can be
+# obtained from standardized SFDP parameter blocks should be in
+# jedec,jesd216.yaml instead.
+
+include: "jedec,jesd216.yaml"
+
+properties:
+  requires-ulbpr:
+    type: boolean
+    required: false
+    description: |
+      Indicates the device requires the ULBPR (0x98) command.
+
+      Some flash chips such as the Microchip SST26VF series have a block
+      protection register that initializes to write-protected.  Use this
+      property to indicate that the BPR must be unlocked before write
+      operations can proceed.
+
+  has-dpd:
+    type: boolean
+    required: false
+    description: |
+      Indicates the device supports the DPD (0xB9) command.
+
+      Use this property to indicate the flash chip supports the Deep
+      Power-Down mode that is entered by command 0xB9 to reduce power
+      consumption below normal standby levels.  Use of this property
+      implies that the RDPD (0xAB) Release from Deep Power Down command
+      is also supported.  (On some chips this command functions as Read
+      Electronic Signature; see t-enter-dpd).
+
+  dpd-wakeup-sequence:
+    type: array
+    required: false
+    description: |
+      Specifies wakeup durations for devices without RDPD.
+
+      Some devices (Macronix MX25R in particular) wake from deep power
+      down by a timed sequence of CSn toggles rather than the RDPD
+      command.  This property specifies three durations measured in
+      nanoseconds, in this order:
+      (1) tDPDD (Delay Time for Release from Deep Power-Down Mode)
+      (2) tCDRP (CSn Toggling Time before Release from Deep Power-Down Mode)
+      (3) tRDP (Recovery Time for Release from Deep Power-Down Mode)
+
+      Absence of this property indicates that the RDPD command should be
+      used to wake the chip from Deep Power-Down mode.
+
+  t-enter-dpd:
+    type: int
+    required: false
+    description: |
+      Duration required to complete the DPD command.
+
+      This provides the duration, in nanoseconds, that CSn must be
+      remain deasserted after issuing DPD before the chip will enter
+      deep power down.
+
+      If not provided the driver does not enforce a delay.
+
+  t-exit-dpd:
+    type: int
+    required: false
+    description: |
+      Duration required to complete the RDPD command.
+
+      This provides the duration, in nanoseconds, that CSn must be
+      remain deasserted after issuing RDPD before the chip will exit
+      deep power down and be ready to receive additional commands.
+
+      If not provided the driver does not enforce a delay.
+
+  has-lock:
+    type: int
+    required: false
+    description: |
+      Bit mask of bits of the status register that should be cleared on
+      startup.
+
+      Some devices from certain vendors power-up with block protect bits
+      set in the status register, which prevent any erase or program
+      operation from working.  Devices that have this behavior need to
+      clear those bits on startup.  However, other devices have
+      non-volatile bits in the status register that should not be
+      cleared.
+
+      This value, when present, identifies bits in the status register
+      that should be cleared when the device is initialized.
@@ -0,0 +1,26 @@
+# Copyright (c) 2018 Peter Bigot Consulting, LLC
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Properties supporting Zephyr spi-nor flash driver (over the Zephyr SPI
+  API) control of serial flash memories using the standard M25P80-based
+  command set.
+
+compatible: "jedec,spi-nor"
+
+include: [spi-device.yaml, "jedec,spi-nor-common.yaml"]
+
+properties:
+  wp-gpios:
+    type: phandle-array
+    required: false
+    description: WPn pin
+  hold-gpios:
+    type: phandle-array
+    required: false
+    description: HOLDn pin
+  reset-gpios:
+    type: phandle-array
+    required: false
+    description: RESETn pin
@@ -0,0 +1,102 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  QSPI NOR flash supporting the JEDEC CFI interface.
+
+compatible: "nordic,qspi-nor"
+
+include: [base.yaml, "jedec,spi-nor-common.yaml"]
+
+on-bus: qspi
+
+properties:
+  reg:
+    required: true
+
+  label:
+    required: true
+
+  jedec-id:
+    required: true
+
+  size:
+    required: true
+
+  # Match original driver NORDIC_QSPI_NOR_QE_BIT Kconfig default.
+  quad-enable-requirements:
+    default: "S1B6"
+
+  readoc:
+    type: string
+    required: false
+    enum:
+      - "fastread"        # Single data line SPI, FAST_READ (0x0B)
+      - "read2o"          # Dual data line SPI, READ2O (0x3B)
+      - "read2io"         # Dual data line SPI, READ2IO (0xBB)
+      - "read4o"          # Quad data line SPI, READ4O (0x6B)
+      - "read4io"         # Quad data line SPI, READ4IO (0xEB)
+    description: |
+      Specify the number of data lines and opcode used for reading.
+      If not provided fastread will be selected.
+
+  writeoc:
+    type: string
+    required: false
+    enum:
+      - "pp"            # Single data line SPI, PP (0x02)
+      - "pp2o"          # Dual data line SPI, PP2O (0xA2)
+      - "pp4o"          # Quad data line SPI, PP4O (0x32)
+      - "pp4io"         # Quad data line SPI, PP4IO (0x38)
+    description: |
+      Specify the number of data lines and opcode used for writing.
+      If not provided pp will be selected.
+
+  address-size-32:
+    type: boolean
+    required: false
+    description: |
+      Set to indicate that 32-bit addressing is to be used.
+      If not specified 24-bit addressing will be used.
+
+  ppsize-512:
+    type: boolean
+    required: false
+    description: |
+      Set to indicate that the write opcode operates on 512-byte pages.
+      If not specified the write opcode operates on 256-byte pages.
+
+  sck-delay:
+    type: int
+    required: false
+    default: 0
+    description: |
+      Number of clock cycles CSn must be asserted before it can go low
+      again, specified in nanoseconds.
+
+  rx-delay:
+    type: int
+    required: false
+    description: |
+      Number of clock cycles from the rising edge of the SPI clock
+      until the input serial data is sampled.
+
+  cpha:
+    type: boolean
+    required: false
+    description: |
+      Set to indicate phase starts with asserted half-phase (CPHA=1).
+      For this driver using this property requires also using cpol.
+
+  cpol:
+    type: boolean
+    required: false
+    description: |
+      Set to indicate clock leading edge is falling (CPOL=1).
+      For this driver using this property requires also using cpha.
+
+  sck-frequency:
+    type: int
+    required: true
+    description: |
+      Maximum clock speed supported by the device, in Hz.
@@ -0,0 +1,101 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI device
+
+compatible: "nxp,imx-flexspi-device"
+
+include: [spi-device.yaml, "jedec,jesd216.yaml"]
+
+properties:
+    cs-interval-unit:
+      type: int
+      required: false
+      default: 1
+      enum:
+        - 1
+        - 256
+      description: |
+        Chip select interval units, in serial clock cycles. See the
+        CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
+        default corresponds to the reset value of the register field.
+
+    cs-interval:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Minimum interval between chip select deassertion and assertion. See the
+        CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
+        default corresponds to the reset value of the register field.
+
+    cs-setup-time:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Chip select setup time, in serial clock cycles. See the TCSS field in
+        registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
+        reset value of the register field.
+
+    cs-hold-time:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Chip select hold time, in serial clock cycles. See the TCSH field in
+        registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
+        reset value of the register field.
+
+    data-valid-time:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Data valid time, in nanoseconds. See the registers DLLACR through
+        DLLBCR.
+
+    column-space:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Column address bit width. Set to zero if the flash does not support
+        column address. See the CAS field in registers FLASHA1CR0 through
+        FLASHB2CR0. The default corresponds to the reset value of the register
+        field.
+
+    word-addressable:
+      type: boolean
+      required: false
+      description: |
+        Don't transmit the least significant address bit when the flash is word
+        addressable. See the WA field in registers FLASHA1CR0 through
+        FLASHB2CR0.
+
+    ahb-write-wait-unit:
+      type: int
+      required: false
+      default: 2
+      enum:
+        - 2
+        - 8
+        - 32
+        - 128
+        - 512
+        - 2048
+        - 8192
+        - 32768
+      description: |
+        AHB write wait interval units, in AHB clock cycles. See the AWRWAITUNIT
+        field in registers FLASHA1CR2 through FLASHB2CR2. The default
+        corresponds to the reset value of the register field.
+
+    ahb-write-wait-interval:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Time to wait between AHB triggered command sequences. See the AWRWAIT
+        field in registers FLASHA1CR2 through FLASHB2CR2. The default
+        corresponds to the reset value of the register field.
@@ -0,0 +1,8 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI HyperFlash
+
+compatible: "nxp,imx-flexspi-hyperflash"
+
+include: nxp,imx-flexspi-device.yaml
@@ -0,0 +1,8 @@
+# Copyright 2021 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI HyperRAM
+
+compatible: "nxp,imx-flexspi-hyperram"
+
+include: nxp,imx-flexspi-device.yaml
@@ -0,0 +1,8 @@
+# Copyright 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI MX25UM51345G
+
+compatible: "nxp,imx-flexspi-mx25um51345g"
+
+include: ["nxp,imx-flexspi-device.yaml", soc-nv-flash.yaml]
@@ -0,0 +1,8 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI NOR
+
+compatible: "nxp,imx-flexspi-nor"
+
+include: ["nxp,imx-flexspi-device.yaml", soc-nv-flash.yaml]
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Seagate Technology LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC11U6X on-chip EEPROM node
+
+compatible: "nxp,lpc11u6x-eeprom"
+
+include: eeprom-base.yaml
@@ -0,0 +1,19 @@
+description: Flash node
+
+compatible: "soc-nv-flash"
+
+include: base.yaml
+
+properties:
+    label:
+      required: false
+
+    erase-block-size:
+     type: int
+     description: address alignment required by flash erase operations
+     required: false
+
+    write-block-size:
+     type: int
+     description: address alignment required by flash write operations
+     required: false
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Kwon Tae-young <tykwon@m2i.co.kr>
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 on-chip EEPROM
+
+compatible: "st,stm32-eeprom"
+
+include: eeprom-base.yaml
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,14 @@
+description: |
+  STM32 flash memory. This binding is for the flash memory itself, not
+  the flash controller peripheral. For that, see the
+  "st,stm32-flash-controller" binding.
+
+include: soc-nv-flash.yaml
+
+compatible: st,stm32-nv-flash
+
+properties:
+    max-erase-time:
+     type: int
+     description: max erase time(millisecond) of a flash sector or page or half-page
+     required: true
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 Innoseis B.V
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI TMP116 EEPROM controller binding
+
+compatible: "ti,tmp116-eeprom"
+
+include: eeprom-base.yaml
+
+on-bus: tmp116
@@ -0,0 +1,31 @@
+# Copyright (c) 2019 Laczen
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr Emulated EEPROM device
+
+compatible: "zephyr,emu-eeprom"
+
+include: eeprom-base.yaml
+
+properties:
+    size:
+      required: true
+    pagesize:
+      type: int
+      required: true
+      description: Size of a page used to emulate EEPROM in flash
+    partition:
+      type: phandle
+      required: true
+      description: Flash partition used to store the emulated EEPROM data
+    rambuf:
+      type: boolean
+      required: false
+      description: Enable a ram buffer of EEPROM size for improved read speed
+    partition-erase:
+      type: boolean
+      required: false
+      description: |
+        Delay erase until complete partition is used. This enables a
+        ram buffer to allow data to be copied during the partition erase. If
+        power is lost during the partition erase the data will be lost.
@@ -0,0 +1,12 @@
+# Copyright (c) 2019 Laczen
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr Simulated EEPROM device
+
+compatible: "zephyr,sim-eeprom"
+
+include: eeprom-base.yaml
+
+properties:
+    size:
+      required: true