WIP: device tree MVP

2026-11-10 00:41:35 +08:00 · 2022-01-06 17:20:17 -05:00
parent 07d75d85cf
commit 1f39b42525
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+# Copyright (c) 2021 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: GIC v3 Interrupt Translation Service
+
+compatible: "arm,gic-v3-its"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
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+# Copyright (c) 2018 Marvell
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARMv7-R Generic Interrupt Controller
+
+compatible: "arm,gic"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+interrupt-cells:
+  - type
+  - irq
+  - flags
+  - priority
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+description: ARMv6-M NVIC (Nested Vectored Interrupt Controller) controller
+
+compatible: "arm,v6m-nvic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    arm,num-irq-priority-bits:
+      required: true
+      type: int
+      description: number of bits of IRQ priorities
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
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+description: ARMv7-M NVIC (Nested Vectored Interrupt Controller)
+
+compatible: "arm,v7m-nvic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    arm,num-irq-priority-bits:
+      required: true
+      type: int
+      description: number of bits of IRQ priorities
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
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+description: ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)
+
+compatible: "arm,v8.1m-nvic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    arm,num-irq-priority-bits:
+      required: true
+      type: int
+      description: number of bits of IRQ priorities
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
@@ -0,0 +1,21 @@
+description: ARMv8-M NVIC (Nested Vectored Interrupt Controller)
+
+compatible: "arm,v8m-nvic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    arm,num-irq-priority-bits:
+      required: true
+      type: int
+      description: number of bits of IRQ priorities
+
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
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+description: Atmel SAM0 series External Interrupt Controller
+
+compatible: "atmel,sam0-eic"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  label:
+    required: true
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+description: Xtensa Core interrupt controller
+
+compatible: "cdns,xtensa-core-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 3
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
@@ -0,0 +1,26 @@
+# Copyright (c) 2019, Linaro Limited
+# Copyright (c) 2020, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Cypress Interrupt Multiplex Channel
+
+  see cypress,psoc6-intmux
+
+compatible: "cypress,psoc6-intmux-ch"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  label:
+      required: true
+
+  interrupts:
+      required: true
+
+interrupt-cells:
+  - irq
+  - priority
@@ -0,0 +1,79 @@
+# Copyright (c) 2018 Foundries.io
+# Copyright (c) 2020 ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Cypress Interrupt Multiplex
+
+  The PSoC-6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
+  user can select up to 32 interrupts sources from the 240 possible vectors
+  to be processed in the Cortex-M0+ CPU.
+
+  At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to
+  configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
+  4 interrupt sources by grouping intmux channels. These means that each byte
+  from intmux[0~7] store a 'vector number' which selects the peripheral
+  interrupt source in the multiplexer. The multiplexer is placed before
+  Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
+  directly connected to NVIC and doesn't require any special configuration.
+
+  On a general view, the below represents the Interrupt Multiplexer
+  configuration and how the Cortex-M0+ NVIC sources are organized. Each
+  channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
+  The vector number selects the PSoC-6 peripheral interrupt source for the
+  Cortex-M0+ NVIC controller line.
+
+  intmux[0] = {ch03, ch02, ch01, ch00}
+  intmux[1] = {ch07, ch06, ch05, ch04}
+  ...
+  intmux[7] = {ch31, ch30, ch29, ch28}
+
+  In pratical terms, the Cortex-M0+ requires user to define all NVIC interrupt
+  sources and the proper NVIC interrupt order. With that, the system configures
+  the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
+  More information about it at PSoC-6 Architecture Technical Reference Manual,
+  section CPU Sub System (CPUSS) Registers.
+
+
+  The below fragment configure the GPIO Port 0 to generate an interrupt at
+  Cortex-M0+ NVIC:
+
+  At psoc6.dtsi file the gpio_prt0 peripheral had the interrupt source 2:
+
+  gpio_prt0: gpio@40320100 {
+    interrupts = <2 1>;
+  };
+
+  In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
+  must be defined at gpio_prt0 node selecting the Interrupt Multiplex Channel.
+  This can be defined at <board>_m0.dts file:
+
+  &gpio_prt0 {
+    interrupt-parent = <&intmux_ch20>;
+  };
+
+  The translation of these two definitions is:
+         CH   REGS  INT NUM    CH   CH/REG
+  intmux[20 mod 8] |= 0x02 << (20 mod 4);
+
+  These results in Cortex-M0+ NVIC line 20 handling PSoC-6 interrupt source 2.
+  The interrupt can be enabled/disable at NVIC at line 20 as usual.
+
+  Notes:
+  1) Multiple definitions will generate multiple interrutps
+  2) The interrupt sources are shared between Cortex-M0+/M4. These means, can
+     trigger action in parallel in both processors.
+  3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
+     at interrupt-parent properties.
+  4) Only the peripherals used by Cortex-M0+ should be configured.
+
+compatible: "cypress,psoc6-intmux"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  label:
+      required: true
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ESP32 Interrupt controller
+compatible: "espressif,esp32-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+interrupt-cells:
+  - irq
@@ -0,0 +1,22 @@
+# Copyright (c) 2020 Cobham Gaisler AB
+# SPDX-License-Identifier: Apache-2.0
+
+description: GRLIB Multiprocessor Interrupt Controller
+
+compatible: "gaisler,irqmp"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    eirq:
+      type: int
+      description: Extended interrupt number (or 0 for none)
+
+    "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
@@ -0,0 +1,23 @@
+description: CAVS interrupt controller
+
+compatible: "intel,cavs-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  label:
+      required: true
+
+  "#interrupt-cells":
+      const: 3
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
@@ -0,0 +1,17 @@
+description: Intel I/O Advanced Programmable Interrupt Controller (APIC)
+
+compatible: "intel,ioapic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 3
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel VT-D Interrupt Remapping Controller
+
+compatible: "intel,vt-d"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
@@ -0,0 +1,14 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for interrupt controllers
+
+properties:
+    "interrupt-controller":
+      type: boolean
+      required: true
+      description: Convey's this node is an interrupt controller
+    "#interrupt-cells":
+      type: int
+      required: true
+      description: Number of items to expect in an interrupt specifier
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE Interrupt controller
+compatible: "ite,it8xxx2-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+interrupt-cells:
+  - irq
+  - flags
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+description: Microchip XEC series External Interrupt Aggregator GIRQ
+
+compatible: "microchip,xec-ecia-girq"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
+
+    girq-id:
+       type: int
+       required: true
+       description: GIRQ ID number [0, 18]
+
+    sources:
+      type: array
+      required: true
+      description: |
+        Bit positions of each source implemented by this GIRQ.
@@ -0,0 +1,22 @@
+description: Microchip XEC series External Interrupt Aggregator Controller
+
+compatible: "microchip,xec-ecia"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    clocks:
+      required: true
+
+    direct-capable-girqs:
+      type: array
+      required: true
+      description: |
+        Array of GIRQ numbers in [8, 26] whose result bits can be connected
+        directly to the ARM NVIC.
@@ -0,0 +1,19 @@
+# Copyright (c) 2021, Tokita, Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuclei ECLIC interrupt controller
+
+compatible: "nuclei,eclic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
@@ -0,0 +1,32 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: NPCX-MIWU group-interrupt mapping child node
+
+compatible: "nuvoton,npcx-miwu-int-map"
+
+properties:
+    parent:
+        type: phandle
+        required: true
+        description: parent device node of miwu groups
+
+child-binding:
+    description: Child node to present the mapping between MIWU group and interrupt
+    properties:
+       irq:
+          type: int
+          required: true
+          description: irq for miwu group
+       irq-prio:
+          type: int
+          required: true
+          description: irq's priority for miwu group. The valid number is from 0 to 7.
+       group-mask:
+          type: int
+          required: true
+          description: group bit-mask for miwu interrupts
+       groups:
+          type: array
+          required: false
+          description: groups shared the same interrupt
@@ -0,0 +1,13 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: NPCX-MIWU Wake-Up Unit Input (WUI) mapping child node
+
+compatible: "nuvoton,npcx-miwu-wui-map"
+
+child-binding:
+    description: Child node to present the mapping between input of MIWU and its source device
+    properties:
+       miwus:
+            type: phandle-array
+            required: true
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX Multi-Input Wake-Up Unit (MIWU) node
+
+compatible: "nuvoton,npcx-miwu"
+
+include: [base.yaml]
+
+properties:
+    label:
+        required: true
+
+    index:
+        type: int
+        required: true
+        description: index of miwu device
+
+    "#miwu-cells":
+        type: int
+        required: true
+        description: Number of items to present a MIWU input souce specifier
+
+miwu-cells:
+  - group
+  - bit
@@ -0,0 +1,19 @@
+# Copyright (c) 2018, Linaro Inc.
+# Copyright (c) 2018, Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 Event Unit
+
+compatible: "openisa,rv32m1-event-unit"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
@@ -0,0 +1,21 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 INTMUX channel
+
+compatible: "openisa,rv32m1-intmux-ch"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  label:
+      required: true
+
+  interrupts:
+      required: true
+
+interrupt-cells:
+  - irq
@@ -0,0 +1,15 @@
+# Copyright (c) 2018 Foundries.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: RV32M1 INTMUX IP
+
+compatible: "openisa,rv32m1-intmux"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  label:
+      required: true
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+# Copyright (c) 2020, Katsuhiro Suzuki.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Common fields for the RISC-V Core-Local interruptor.
+
+include: [interrupt-controller.yaml, base.yaml]
+
+compatible: "riscv,clint0"
+
+properties:
+  reg:
+      required: true
+
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: RISC-V CPU interrupt controller
+
+compatible: "riscv,cpu-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq
@@ -0,0 +1,22 @@
+# Copyright (c) 2018, SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for the RISC-V platform-local interrupt controller
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  riscv,max-priority:
+      type: int
+      description: maximum interrupt priority
+      required: true
+
+  "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
@@ -0,0 +1,12 @@
+description: Shared IRQ interrupt dispatcher
+
+compatible: "shared-irq"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  interrupts:
+      required: true
+
+  label:
+      required: true
@@ -0,0 +1,14 @@
+# Copyright (c) 2018, SiFive Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive RISCV-V platform-local interrupt controller
+
+compatible: "sifive,plic-1.0.0"
+
+include: riscv,plic0.yaml
+
+properties:
+    riscv,ndev:
+        type: int
+        description: Number of external interrupts supported
+        required: true
@@ -0,0 +1,15 @@
+# Copyright (c) 2019, synopsys
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ARC-HS Interrupt Distribution Unit 2nd-level interrupt controller. Can be
+    used in SMP configurations for dynamic IRQ routing and load balancing of
+    common/external IRQs towards the core interrupt controller.
+
+compatible: "snps,archs-idu-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+interrupt-cells:
+  - irq
+  - priority
@@ -0,0 +1,16 @@
+# Copyright (c) 2018, synopsys
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARCV2 interrupt controller
+
+compatible: "snps,arcv2-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+    "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority
@@ -0,0 +1,25 @@
+description: DesignWare programmable interrupt controller
+
+compatible: "snps,designware-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  "#interrupt-cells":
+      const: 3
+
+  num-irqs:
+      type: int
+      required: true
+      description: Number of irq the controller manages
+
+interrupt-cells:
+  - irq
+  - sense
+  - priority
@@ -0,0 +1,9 @@
+description: STMicroelectronics STM32 family External Interrupt Controller
+
+compatible: "st,stm32-exti"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: SweRV EH1 PIC (Programmable Interrupt Controller)
+
+compatible: "swerv,pic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  riscv,max-priority:
+      type: int
+      description: maximum interrupt priority
+      required: true
+
+interrupt-cells:
+  - irq
+  - priority
@@ -0,0 +1,24 @@
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteX VexRiscV interrupt controller
+
+compatible: "vexriscv-intc0"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+      required: true
+
+  riscv,max-priority:
+      type: int
+      description: maximum interrupt priority
+      required: true
+
+  "#interrupt-cells":
+      const: 2
+
+interrupt-cells:
+  - irq
+  - priority