mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,15 @@
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# Copyright (c) 2018 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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||||
|
||||
description: Altera NIOS2 I2C
|
||||
|
||||
compatible: "altr,nios2-i2c"
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||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
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||||
# Copyright (c) 2018, Linaro Limited
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||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ARM SBCon two-wire serial bus interface
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||||
|
||||
compatible: "arm,versatile-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,16 @@
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||||
# Copyright (c) 2020 Seagate Technology LLC
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||||
# SPDX-License-Identifier: Apache-2.0
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||||
|
||||
description: ASMedia ASM2364 USB-to-PCIe bridge controller
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||||
|
||||
compatible: "asmedia,asm2364"
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||||
|
||||
include: base.yaml
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||||
|
||||
on-bus: i2c
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||||
|
||||
properties:
|
||||
int-gpios:
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||||
type: phandle-array
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||||
required: true
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||||
description: Interrupt GPIO for read requests
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||||
@@ -0,0 +1,32 @@
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# Copyright (c) 2017 Piotr Mienkowski
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||||
# SPDX-License-Identifier: Apache-2.0
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||||
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||||
description: Atmel SAM Family I2C (TWI) node
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||||
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compatible: "atmel,sam-i2c-twi"
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||||
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||||
include: i2c-controller.yaml
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||||
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||||
properties:
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reg:
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||||
required: true
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||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
peripheral-id:
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||||
type: int
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||||
description: peripheral ID
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||||
required: true
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||||
|
||||
pinctrl-0:
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||||
type: phandles
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required: true
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||||
description: |
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PIO pin configuration for TWCK & TWD signals. We expect that
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the phandles will reference pinctrl nodes. These nodes will
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||||
have a nodelabel that matches the Atmel SoC HAL defines and
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be of the form p<port><pin><periph>_<inst>_<signal>.
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For example the I2C on SAM3x would be
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pinctrl-0 = <&pa18a_twi0_twck0 &pa17a_twi0_twd0>;
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@@ -0,0 +1,32 @@
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# Copyright (c) 2017 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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description: Atmel SAM Family I2C (TWIHS) node
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compatible: "atmel,sam-i2c-twihs"
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include: i2c-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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peripheral-id:
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type: int
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description: peripheral ID
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required: true
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pinctrl-0:
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type: phandles
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required: true
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||||
description: |
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PIO pin configuration for TWCK & TWD signals. We expect that
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the phandles will reference pinctrl nodes. These nodes will
|
||||
have a nodelabel that matches the Atmel SoC HAL defines and
|
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be of the form p<port><pin><periph>_<inst>_<signal>.
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For example the I2C on SAME7x would be
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pinctrl-0 = <&pa4a_twihs0_twck0 &pa3a_twihs0_twd0>;
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@@ -0,0 +1,215 @@
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# Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Atmel SAM4L Family I2C (TWIM) node
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The Atmel Two-wire Master Interface (TWIM) interconnects components on a
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unique two-wire bus, made up of one clock line and one data line with speeds
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of up to 3.4 Mbit/s, based on a byte-oriented transfer format. The TWIM is
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always a bus master and can transfer sequential or single bytes. Multiple
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master capability is supported. Arbitration of the bus is performed
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internally and relinquishes the bus automatically if the bus arbitration is
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lost.
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When using speeds above standard mode, user may need adjust clock and data
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||||
lines slew and strength parameters. In general, slew 0 and minimal strength
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||||
is enougth for short buses and light loads. As reference, the below
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||||
is the lowest power configuration:
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std-clk-slew-lim = <0>;
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||||
std-clk-strength-low = "0.5";
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std-data-slew-lim = <0>;
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std-data-strength-low = "0.5";
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||||
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hs-clk-slew-lim = <0>;
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||||
hs-clk-strength-high = "0.5";
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||||
hs-clk-strength-low = "0.5";
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hs-data-slew-lim = <0>;
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||||
hs-data-strength-low = "0.5";
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||||
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For best performances, user can tune the slope curves using an osciloscope.
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The tuning should be performed by groups defined <mode>-<line>. The prefix
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std-<line> configures fast/fast-plus mode speeds and hs-<line> selects the
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high speed mode. The tune should be performed for both clock and data lines
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on both speed modes.
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compatible: "atmel,sam-i2c-twim"
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||||
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include: i2c-controller.yaml
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||||
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||||
properties:
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||||
reg:
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||||
required: true
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||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
peripheral-id:
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||||
type: int
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||||
required: true
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||||
description: peripheral ID
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||||
|
||||
std-clk-slew-lim:
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type: int
|
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required: true
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||||
description: |
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Slew limit of the TWCK output buffer. This should be adjusted with
|
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std-clk-strength-low to fine tune the TWCK slope.
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||||
enum:
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- 0
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- 1
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- 2
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||||
- 3
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||||
|
||||
std-clk-strength-low:
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type: string
|
||||
required: true
|
||||
description: |
|
||||
Pull-down drive strength of the TWCK output buffer in fast/fast plus
|
||||
mode. This should be adjusted to provide proper TWCK line fall time.
|
||||
The value represents the port output current in mA when signal on
|
||||
low level.
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||||
enum:
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||||
- "0.5"
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||||
- "1.0"
|
||||
- "1.6"
|
||||
- "3.1"
|
||||
- "6.2"
|
||||
- "9.3"
|
||||
- "15.5"
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||||
- "21.8"
|
||||
|
||||
std-data-slew-lim:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Slew limit of the TWD output buffer. This should be adjusted with
|
||||
std-data-strength-low to fine tune the TWD slope.
|
||||
enum:
|
||||
- 0
|
||||
- 1
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||||
- 2
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||||
- 3
|
||||
|
||||
std-data-strength-low:
|
||||
type: string
|
||||
required: true
|
||||
description: |
|
||||
Pull-down drive strength of the TWD output buffer in fast/fast plus
|
||||
mode. This should be adjusted to provide proper TWD line fall time.
|
||||
The value represents the port output current in mA when signal on
|
||||
low level.
|
||||
enum:
|
||||
- "0.5"
|
||||
- "1.0"
|
||||
- "1.6"
|
||||
- "3.1"
|
||||
- "6.2"
|
||||
- "9.3"
|
||||
- "15.5"
|
||||
- "21.8"
|
||||
|
||||
hs-clk-slew-lim:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Slew limit of the TWCK output buffer in high speed mode. This
|
||||
should be adjusted with both hs-clk-strength-high and
|
||||
hs-clk-strength-low to fine tune the TWCK slope.
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
|
||||
hs-clk-strength-high:
|
||||
type: string
|
||||
required: true
|
||||
description: |
|
||||
Pull-up drive strength of the TWCK output buffer in high speed
|
||||
mode. This should be adjusted to provide proper TWCK line rise time.
|
||||
The value represents the port output current in mA when signal on
|
||||
high level.
|
||||
enum:
|
||||
- "0.5"
|
||||
- "1.0"
|
||||
- "1.5"
|
||||
- "3.0"
|
||||
|
||||
hs-clk-strength-low:
|
||||
type: string
|
||||
required: true
|
||||
description: |
|
||||
Pull-down drive strength of the TWCK output buffer in high speed
|
||||
mode. This should be adjusted to provide proper TWCK line fall time.
|
||||
The value represents the port output current in mA when signal on
|
||||
low level.
|
||||
enum:
|
||||
- "0.5"
|
||||
- "1.0"
|
||||
- "1.6"
|
||||
- "3.1"
|
||||
- "6.2"
|
||||
- "9.3"
|
||||
- "15.5"
|
||||
- "21.8"
|
||||
|
||||
hs-data-slew-lim:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Slew limit of the TWD output buffer in high speed mode. This
|
||||
should be adjusted with hs-data-strength-low to fine tune the TWD
|
||||
slope.
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
|
||||
hs-data-strength-low:
|
||||
type: string
|
||||
description: |
|
||||
Pull-down drive strength of the TWD output buffer in high speed
|
||||
mode. This should be adjusted to provide proper TWD line fall time.
|
||||
The value represents the port output current in mA when signal on
|
||||
low level.
|
||||
enum:
|
||||
- "0.5"
|
||||
- "1.0"
|
||||
- "1.6"
|
||||
- "3.1"
|
||||
- "6.2"
|
||||
- "9.3"
|
||||
- "15.5"
|
||||
- "21.8"
|
||||
|
||||
hs-master-code:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
3-bit code to be prefixed with 0b00001 to form a unique
|
||||
8-bit HS-mode master code (0000 1XXX)
|
||||
enum:
|
||||
- 0 # 000
|
||||
- 1 # 001
|
||||
- 2 # 010
|
||||
- 3 # 011
|
||||
- 4 # 100
|
||||
- 5 # 101
|
||||
- 6 # 110
|
||||
- 7 # 111
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
description: |
|
||||
GPIO pin configuration for TWCK & TWD signals. We expect that
|
||||
the phandles will reference pinctrl nodes. These nodes will
|
||||
have a nodelabel that matches the Atmel SoC HAL defines and
|
||||
be of the form p<port><pin><periph>_<inst>_<signal>.
|
||||
|
||||
For example the I2C on SAM4L would be
|
||||
pinctrl-0 = <&pb0a_twi1_twd1 &pb1a_twi1_twck1>;
|
||||
@@ -0,0 +1,38 @@
|
||||
# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Atmel SAM0 series SERCOM I2C node
|
||||
|
||||
compatible: "atmel,sam0-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
clock-names:
|
||||
required: true
|
||||
|
||||
dmas:
|
||||
description: |
|
||||
Optional TX & RX dma specifiers. Each specifier will have a phandle
|
||||
reference to the dmac controller, the channel number, and peripheral
|
||||
trigger source.
|
||||
|
||||
For example dmas for TX, RX on SERCOM3
|
||||
dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
|
||||
|
||||
dma-names:
|
||||
description: |
|
||||
Required if the dmas property exists. This should be "tx" and "rx"
|
||||
to match the dmas property.
|
||||
|
||||
For example
|
||||
dma-names = "tx", "rx";
|
||||
@@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2019 Mohamed ElShahawi (ExtremeGTX@hotmail.com)
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ESP32 I2C
|
||||
|
||||
compatible: "espressif,esp32-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: false
|
||||
|
||||
sda-pin:
|
||||
type: int
|
||||
description: SDA pin
|
||||
required: true
|
||||
|
||||
scl-pin:
|
||||
type: int
|
||||
description: SCL pin
|
||||
required: true
|
||||
|
||||
tx-lsb:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Set I2C TX data as LSB
|
||||
|
||||
rx-lsb:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Set I2C RX data as LSB
|
||||
@@ -0,0 +1,20 @@
|
||||
# Copyright (c) 2018 Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX I2C node
|
||||
|
||||
compatible: "fsl,imx21-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
rdc:
|
||||
type: int
|
||||
required: true
|
||||
description: Set the RDC permission for this peripheral
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (c) 2020 Vestas Wind Systems A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: GPIO bitbanging I2C support
|
||||
|
||||
compatible: "gpio-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
scl-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: GPIO to which the SCL pin of the I2C bus is connected.
|
||||
sda-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: GPIO to which the SDA pin of the I2C bus is connected.
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright (c) 2017 I-SENSE group of ICCS
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for I2C controllers
|
||||
|
||||
include: base.yaml
|
||||
|
||||
bus: i2c
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
required: true
|
||||
const: 1
|
||||
"#size-cells":
|
||||
required: true
|
||||
const: 0
|
||||
clock-frequency:
|
||||
type: int
|
||||
required: false
|
||||
description: Initial clock frequency in Hz
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2017, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for I2C devices
|
||||
|
||||
include: [base.yaml, power.yaml]
|
||||
|
||||
on-bus: i2c
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
description: device address on i2c bus
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ITE it8xxx2 I2C
|
||||
|
||||
compatible: "ite,it8xxx2-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
port-num:
|
||||
type: int
|
||||
required: true
|
||||
description: Ordinal identifying the port
|
||||
|
||||
gpio-dev:
|
||||
type: phandle
|
||||
required: true
|
||||
description: Get the handle of the GPIO device
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
description: Configuration of I2C SCL and SDA pinmux controller.
|
||||
The SCL pin must be specified first and the SDA pin
|
||||
second in the pinctrl-0 array.
|
||||
@@ -0,0 +1,15 @@
|
||||
#
|
||||
# Copyright (c) 2019 Antmicro <www.antmicro.com>
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: LiteX I2C controller
|
||||
|
||||
compatible: "litex,i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,43 @@
|
||||
# Copyright (c) 2019 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip I2C/SMB V2 controller
|
||||
|
||||
compatible: "microchip,xec-i2c-v2"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
port_sel:
|
||||
type: int
|
||||
description: soc block mapping to pin
|
||||
required: true
|
||||
|
||||
girqs:
|
||||
type: array
|
||||
required: true
|
||||
description: array of GIRQ numbers [8:26] and bit positions [0:31]
|
||||
|
||||
pcrs:
|
||||
type: array
|
||||
required: true
|
||||
description: PCR sleep register index and bit position
|
||||
|
||||
"#girq-cells":
|
||||
type: int
|
||||
const: 2
|
||||
|
||||
"pcr-cells":
|
||||
type: int
|
||||
const: 2
|
||||
|
||||
girq-cells:
|
||||
- girq_num
|
||||
- bitpos
|
||||
|
||||
pcr-cells:
|
||||
- regidx
|
||||
- bitpos
|
||||
@@ -0,0 +1,27 @@
|
||||
# Copyright (c) 2019 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip I2C/SMB controller
|
||||
|
||||
compatible: "microchip,xec-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
port_sel:
|
||||
type: int
|
||||
description: soc block mapping to pin
|
||||
required: true
|
||||
|
||||
girq:
|
||||
type: int
|
||||
required: true
|
||||
description: GIRQ for this device
|
||||
|
||||
girq-bit:
|
||||
type: int
|
||||
required: true
|
||||
description: Bit position in GIRQ for this device
|
||||
@@ -0,0 +1,37 @@
|
||||
# Copyright (c) 2018 Aapo Vienamo
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for Nordic nRF family TWI peripherals
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
sda-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The SDA pin to use.
|
||||
|
||||
For pins P0.0 through P0.31, use the pin number. For example,
|
||||
to use P0.16 for SDA, set:
|
||||
|
||||
sda-pin = <16>;
|
||||
|
||||
For pins P1.0 through P1.31, add 32 to the pin number. For
|
||||
example, to use P1.2 for SDA, set:
|
||||
|
||||
sda-pin = <34>; /* 32 + 2 */
|
||||
|
||||
scl-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The SCL pin to use. The pin numbering scheme is the same as
|
||||
the sda-pin property's.
|
||||
@@ -0,0 +1,45 @@
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nordic nRF family TWI (TWI master).
|
||||
|
||||
This binding can be used for nodes which can represent TWI
|
||||
peripherals. When a single SoC peripheral ID corresponds to multiple
|
||||
I2C peripherals (like TWI or TWIM), the corresponding devicetree
|
||||
nodes must be set up to select TWI before use.
|
||||
|
||||
To select TWI, set the node's "compatible" to "nordic,nrf-twi" and
|
||||
its "status" to "okay", e.g. using an overlay file like this:
|
||||
|
||||
/* This is for TWI0 -- change to "i2c1" for TWI1. */
|
||||
&i2c0 {
|
||||
compatible = "nordic,nrf-twi";
|
||||
status = "okay";
|
||||
/* other property settings can go here */
|
||||
};
|
||||
|
||||
You can use either of these options to check TWI availability on
|
||||
your SoC:
|
||||
|
||||
1. Check the peripheral Instantiation table in the Memory
|
||||
section of your SoC's Product Specification document.
|
||||
A "TWI0" instance in the table means "i2c0" in the devicetree
|
||||
can be used with this binding, and similarly for "TWI1".
|
||||
|
||||
2. Open your SoC's .dtsi file and look for a node definition that
|
||||
documents TWI support, like this:
|
||||
|
||||
i2c0: i2c@40003000 {
|
||||
/*
|
||||
* This i2c node can be TWI, [...].
|
||||
*/
|
||||
...
|
||||
};
|
||||
|
||||
If your SoC only has TWIM and TWIS I2C peripherals, you cannot use
|
||||
this binding. See the "nordic,nrf-twim" binding instead.
|
||||
|
||||
compatible: "nordic,nrf-twi"
|
||||
|
||||
include: nordic,nrf-twi-common.yaml
|
||||
@@ -0,0 +1,63 @@
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nordic nRF family TWIM (TWI master with EasyDMA).
|
||||
|
||||
This binding can be used for nodes which can represent TWIM
|
||||
peripherals. A single SoC peripheral ID is often associated with
|
||||
multiple I2C peripherals, like a TWIM and a TWIS. You can choose
|
||||
TWIM by setting the node's "compatible" to "nordic,nrf-twim"
|
||||
and "status" to "okay", e.g. using an overlay file like this one:
|
||||
|
||||
/* This is for TWIM0 -- change to "i2c1" for TWIM1, etc. */
|
||||
&i2c0 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
status = "okay";
|
||||
/* other property settings can go here */
|
||||
};
|
||||
|
||||
This works on any supported SoC, for all TWIM instances.
|
||||
|
||||
Note: on nRF51 SoCs, use the "nordic,nrf-twi" binding instead.
|
||||
|
||||
compatible: "nordic,nrf-twim"
|
||||
|
||||
include: nordic,nrf-twi-common.yaml
|
||||
|
||||
properties:
|
||||
zephyr,concat-buf-size:
|
||||
type: int
|
||||
required: false
|
||||
default: 16
|
||||
description: |
|
||||
Size of a concatenation buffer that the driver is to use for merging
|
||||
multiple same direction I2C messages that have no RESTART or STOP
|
||||
flag between them (see e.g. the i2c_burst_write() function) into one
|
||||
transfer on the bus.
|
||||
|
||||
This property must be provided when interacting with devices like
|
||||
the SSD1306 display that cannot tolerate a repeated start and
|
||||
address appearing on the bus between message fragments. For many
|
||||
devices a concatenation buffer is not necessary.
|
||||
|
||||
zephyr,flash-buf-max-size:
|
||||
type: int
|
||||
required: false
|
||||
default: 16
|
||||
description: |
|
||||
TWIM peripherals cannot perform write transactions from buffers
|
||||
located in flash. If such buffers are expected to be used with
|
||||
a given instance of the TWIM peripheral, this property must be
|
||||
set to the maximum possible size of those buffers, so that the
|
||||
driver can reserve enough space in RAM to copy there the contents
|
||||
of particular buffers before requesting the actual transfers.
|
||||
|
||||
If this property is not set to a value adequate for a given
|
||||
application, write transactions may fail for buffers that are
|
||||
located in flash, what in turn may cause certain components,
|
||||
like the DPS310 sensor driver, to not work.
|
||||
|
||||
It is recommended to use the same value for this property and for
|
||||
the zephyr,concat-buf-size one, as both these buffering mechanisms
|
||||
can utilize the same space in RAM.
|
||||
@@ -0,0 +1,41 @@
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nordic nRF family TWIS (TWI slave with EasyDMA).
|
||||
|
||||
Note: for Zephyr users, the I2C slave API is not available for
|
||||
these devices. See this issue for more details and a HAL-based
|
||||
workaround:
|
||||
|
||||
https://github.com/zephyrproject-rtos/zephyr/issues/21445
|
||||
|
||||
This binding can be used for nodes which can represent TWIS
|
||||
peripherals. A single SoC peripheral ID is often associated with
|
||||
multiple I2C peripherals, like a TWIM and a TWIS. You can choose
|
||||
TWIS by setting the node's "compatible" to "nordic,nrf-twis"
|
||||
and its "status" to "okay", e.g. using an overlay file like this:
|
||||
|
||||
/* This is for TWIS0 -- change to "i2c1" for TWIS1, etc. */
|
||||
&i2c0 {
|
||||
compatible = "nordic,nrf-twis";
|
||||
status = "okay";
|
||||
/* other property settings can go here */
|
||||
};
|
||||
|
||||
This works on any supported SoC, for all TWIS instances.
|
||||
|
||||
compatible: "nordic,nrf-twis"
|
||||
|
||||
include: nordic,nrf-twi-common.yaml
|
||||
|
||||
properties:
|
||||
address-0:
|
||||
type: int
|
||||
required: false
|
||||
description: TWI slave address 0
|
||||
|
||||
address-1:
|
||||
type: int
|
||||
required: false
|
||||
description: TWI slave address 1
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX-I2C controller node
|
||||
|
||||
compatible: "nuvoton,npcx-i2c-ctrl"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
clocks:
|
||||
required: true
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,27 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX-I2C port pads node
|
||||
|
||||
compatible: "nuvoton,npcx-i2c-port"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
port:
|
||||
type: int
|
||||
required: true
|
||||
description: index of i2c port
|
||||
|
||||
controller:
|
||||
type: phandle
|
||||
required: true
|
||||
description: i2c controller to handle signals from port pads
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
description: configurations of pinmux controllers
|
||||
|
||||
clock-frequency:
|
||||
required: true
|
||||
@@ -0,0 +1,20 @@
|
||||
# Copyright (c) 2019, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP i.MX LPI2C controller
|
||||
|
||||
compatible: "nxp,imx-lpi2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
bus-idle-timeout:
|
||||
required: false
|
||||
type: int
|
||||
description: Bus idle timeout in nanoseconds
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2017 Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Kinetis I2C node
|
||||
|
||||
compatible: "nxp,kinetis-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
@@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2019 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC I2C node
|
||||
|
||||
compatible: "nxp,lpc-i2c"
|
||||
|
||||
include: [i2c-controller.yaml, "nxp,lpc-flexcomm.yaml"]
|
||||
@@ -0,0 +1,28 @@
|
||||
# Copyright (c) 2020 Seagate Technology LLC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC11U6X I2C Controller
|
||||
|
||||
compatible: "nxp,lpc11u6x-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
pinmuxs:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: SDA and SCL pins
|
||||
|
||||
pinmux-names:
|
||||
type: string-array
|
||||
required: true
|
||||
description: Pin names for SDA and SCL
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2019, Henrik Brix Andersen <henrik@brixandersen.dk>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: OpenISA LPI2C controller
|
||||
|
||||
compatible: "openisa,rv32m1-lpi2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2021, IoT.bzh
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Renesas R-Car I2C controller
|
||||
|
||||
compatible: "renesas,rcar-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
interrupts:
|
||||
required: true
|
||||
clocks:
|
||||
required: true
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (c) 2018 SiFive Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: SiFive Freedom I2C interface
|
||||
|
||||
compatible: "sifive,i2c0"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
input-frequency:
|
||||
type: int
|
||||
required: false
|
||||
description: Frequency of the peripheral input clock.
|
||||
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,28 @@
|
||||
# Copyright (c) 2018 Diego Sueiro <diego.sueiro@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Silabs Gecko I2C node
|
||||
|
||||
compatible: "silabs,gecko-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
# Note: Not all SoC series support setting individual pin location. If this
|
||||
# is a case all location-* properties need to have identical value.
|
||||
|
||||
location-sda:
|
||||
type: array
|
||||
required: true
|
||||
description: SDA pin configuration defined as <location port pin>
|
||||
|
||||
location-scl:
|
||||
type: array
|
||||
required: true
|
||||
description: SCL pin configuration defined as <location port pin>
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2018 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Synopsys DesignWare I2C node
|
||||
|
||||
compatible: "snps,designware-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2017 I-SENSE group of ICCS
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STM32 I2C V1 controller
|
||||
|
||||
compatible: "st,stm32-i2c-v1"
|
||||
|
||||
include: [i2c-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
@@ -0,0 +1,46 @@
|
||||
# Copyright (c) 2017 I-SENSE group of ICCS
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STM32 I2C V2 controller
|
||||
|
||||
compatible: "st,stm32-i2c-v2"
|
||||
|
||||
include: [i2c-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
|
||||
timings:
|
||||
type: array
|
||||
required: false
|
||||
description: |
|
||||
An optional table of pre-computed i2c timing values with the
|
||||
matching clock configuration.
|
||||
|
||||
Precise timings values for a given Hardware can be pre-computed
|
||||
with a tool like STM32CubeMX or directly from I2C_TIMINGR register
|
||||
description.
|
||||
|
||||
Because timing value is valid for a given I2C peripheral clock
|
||||
frequency and target I2C bus clock, each timing value must be
|
||||
provided with the matching configuration.
|
||||
|
||||
The resulting table entries should look like <periph_clock
|
||||
clock-frequency timing>
|
||||
|
||||
For example timings could be defined as
|
||||
|
||||
timings = <64000000 I2C_BITRATE_STANDARD 0x10707DBC>,
|
||||
<64000000 I2C_BITRATE_FAST 0x00603D56>,
|
||||
<56000000 I2C_BITRATE_STANDARD 0x10606DA4>,
|
||||
<56000000 I2C_BITRATE_FAST 0x00501D63>;
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2021, Telink Semiconductor
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Telink B91 I2C
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
compatible: "telink,b91-i2c"
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
required: true
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2019 Brett Witherspoon
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: TI CC13xx / CC26xx I2C node
|
||||
|
||||
compatible: "ti,cc13xx-cc26xx-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
sda-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: SDA pin
|
||||
|
||||
scl-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: SCL pin
|
||||
@@ -0,0 +1,12 @@
|
||||
description: TI CC32XX I2C controller
|
||||
|
||||
compatible: "ti,cc32xx-i2c"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,10 @@
|
||||
#Binding for TI TCA9546A, compatible with NXP PCA9546A
|
||||
|
||||
description: Texas Instruments TCA9546A binding
|
||||
|
||||
compatible: "ti,tca9546a"
|
||||
|
||||
include: ti,tca954x-base.yaml
|
||||
|
||||
child-binding:
|
||||
compatible: "ti,tca9546a-channel"
|
||||
@@ -0,0 +1,10 @@
|
||||
#Binding for TI TCA9548A, compatible with NXP PCA9548A
|
||||
|
||||
description: Texas Instruments TCA9548A binding
|
||||
|
||||
compatible: "ti,tca9548a"
|
||||
|
||||
include: ti,tca954x-base.yaml
|
||||
|
||||
child-binding:
|
||||
compatible: "ti,tca9548a-channel"
|
||||
@@ -0,0 +1,60 @@
|
||||
# Copyright (c) 2020, Innoseis BV
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for TI TCA954X I2C mux family
|
||||
|
||||
description: |
|
||||
TCA954x I2C switch
|
||||
|
||||
Each channel is represented by a separate devicetree child node.
|
||||
The channel node can then be used as a standard i2c bus controller
|
||||
like in the following simplified example:
|
||||
|
||||
/* The tca954x node must be a child of an i2c controller */
|
||||
mux: tca9546a@77 {
|
||||
compatible = "ti,tca9546a";
|
||||
reg = <0x77>;
|
||||
status = "okay";
|
||||
label = "i2c_mux";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
mux_i2c@0 {
|
||||
compatible: "ti,tca9546a-channel"
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
temp_sens_0: tmp116@49 {
|
||||
compatible = "ti,tmp116";
|
||||
reg = <0x49>;
|
||||
};
|
||||
};
|
||||
|
||||
mux_i2c@1 {
|
||||
compatible: "ti,tca9546a-channel"
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
temp_sens_1: tmp116@49 {
|
||||
compatible = "ti,tmp116";
|
||||
reg = <0x49>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
include: [i2c-device.yaml]
|
||||
|
||||
properties:
|
||||
reset-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
GPIO connected to the controller RESET pin. This pin is active-low.
|
||||
|
||||
child-binding:
|
||||
description: TCA954x I2C switch channel node
|
||||
include: [i2c-controller.yaml]
|
||||
on-bus: i2c
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright 2020 Google LLC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Zephyr I2C Emulation controller
|
||||
|
||||
compatible: "zephyr,i2c-emul-controller"
|
||||
|
||||
include: i2c-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
Reference in New Issue
Block a user