mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-11-16 00:51:35 +08:00
WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,39 @@
|
||||
# Copyright (c) 2020 Richard Osterloh
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
GPIO pins exposed on Adafruit Feather headers.
|
||||
|
||||
The Feather layout provides two headers, one each along
|
||||
opposite edges of the board.
|
||||
Proceeding counter-clockwise:
|
||||
* A 16-pin header. 12 pins on this header are exposed
|
||||
by this binding.
|
||||
* A 12-pin header. 9 pins on this header are exposed
|
||||
by this binding.
|
||||
|
||||
This binding provides a nexus mapping for 21 pins where parent pins 0
|
||||
through 5 correspond to A0 through A5, and parent pins 6 through 20
|
||||
correspond as depicted below:
|
||||
|
||||
- RESET
|
||||
- 3V3
|
||||
- 3V3
|
||||
- GND
|
||||
0 A0 - VBAT
|
||||
1 A1 - EN
|
||||
2 A2 - VBUS
|
||||
3 A3 D13 20
|
||||
4 A4 D12 19
|
||||
5 A5 D11 18
|
||||
6 SCK D10 17
|
||||
7 MOSI D9 16
|
||||
8 MISO D6 15
|
||||
9 RX D5 14
|
||||
10 TX SCL 13
|
||||
11 D4 SDA 12
|
||||
|
||||
|
||||
compatible: "adafruit-feather-header"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,27 @@
|
||||
# Copyright (c) 2021, Andes Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description:
|
||||
This is a representation of Andes Technology atcgpio100 GPIO node
|
||||
|
||||
compatible: "andestech,atcgpio100"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,50 @@
|
||||
# Copyright (c) 2019 Foundries.io
|
||||
# Copyright (C) 2019 Peter Bigot Consulting, LLC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
GPIO pins exposed on Arduino Uno (R3) headers.
|
||||
|
||||
The Arduino Uno layout provides four headers, two each along
|
||||
opposite edges of the board.
|
||||
|
||||
Proceeding counter-clockwise:
|
||||
* An 8-pin Power Supply header. No pins on this header are exposed
|
||||
by this binding.
|
||||
* A 6-pin Analog Input header. This has analog input signals
|
||||
labeled from A0 at the top through A5 at the bottom.
|
||||
* An 8-pin header (opposite Analog Input). This has digital input
|
||||
signals labeled from D0 at the bottom D7 at the top;
|
||||
* A 10-pin header (opposite Power Supply). This has six additional
|
||||
digital input signals labelled from D8 at the bottom through D13
|
||||
towards the top, skipping two pins, then finishing with D14 and
|
||||
D15 at the top.
|
||||
|
||||
This binding provides a nexus mapping for 20 pins where parent pins 0
|
||||
through 5 correspond to A0 through A5, and parent pins 6 through 21
|
||||
correspond to D0 through D15, as depicted below:
|
||||
|
||||
D15 21
|
||||
D14 20
|
||||
AREF -
|
||||
GND -
|
||||
- N/C D13 19
|
||||
- IOREF D12 18
|
||||
- RESET D11 17
|
||||
- 3V3 D10 16
|
||||
- 5V D9 15
|
||||
- GND D8 14
|
||||
- GND
|
||||
- VIN D7 13
|
||||
D6 12
|
||||
0 A0 D5 11
|
||||
1 A1 D4 10
|
||||
2 A2 D3 9
|
||||
3 A3 D2 8
|
||||
4 A4 D1 7
|
||||
5 A5 D0 6
|
||||
|
||||
|
||||
compatible: "arduino-header-r3"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,22 @@
|
||||
description: ARM CMSDK GPIO
|
||||
|
||||
compatible: "arm,cmsdk-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,18 @@
|
||||
description: GPIO controller on ARM MPS2 FPGA
|
||||
|
||||
compatible: "arm,mps2-fpgaio-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
ngpios:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 1
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
@@ -0,0 +1,18 @@
|
||||
description: GPIO controller on ARM MPS3 FPGA
|
||||
|
||||
compatible: "arm,mps3-fpgaio-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
ngpios:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 1
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
@@ -0,0 +1,38 @@
|
||||
description: SAM GPIO PORT node
|
||||
|
||||
compatible: "atmel,sam-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
peripheral-id:
|
||||
type: int
|
||||
description: peripheral ID
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
"#atmel,pin-cells":
|
||||
type: int
|
||||
required: true
|
||||
const: 2
|
||||
description: Number of items to expect in a atmel,pins specifier
|
||||
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
|
||||
atmel,pin-cells:
|
||||
- pin
|
||||
- peripheral
|
||||
@@ -0,0 +1,29 @@
|
||||
description: SAM0 GPIO PORT node
|
||||
|
||||
compatible: "atmel,sam0-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
"#atmel,pin-cells":
|
||||
type: int
|
||||
required: true
|
||||
const: 2
|
||||
description: Number of items to expect in a atmel,pins specifier
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
|
||||
atmel,pin-cells:
|
||||
- pin
|
||||
- peripheral
|
||||
@@ -0,0 +1,5 @@
|
||||
description: SAM4L GPIO PORT node
|
||||
|
||||
compatible: "atmel,sam4l-gpio"
|
||||
|
||||
include: ["atmel,sam-gpio.yaml"]
|
||||
@@ -0,0 +1,45 @@
|
||||
# Copyright (C) 2020 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
GPIO pins exposed on Atmel Xplained headers.
|
||||
|
||||
The Xplained layout provide a standard 10 pin header. A board can have
|
||||
one or more headers and can share pins. This connector was developed to
|
||||
match with Atmel AVR XMEGA devices GPIO port plus power signals. The Atmel
|
||||
Xplained Pro standard connector keep compatibility with this header and it
|
||||
can be defined on every board with an Xplained Pro Connector extension and
|
||||
every pin can be defined as general purpose GPIO.
|
||||
|
||||
The AVR XMEGA port was designed as:
|
||||
|
||||
Signal Main Function
|
||||
Px0 SDA
|
||||
Px1 SCL
|
||||
Px2 RX
|
||||
Px3 TX
|
||||
Px4 SS
|
||||
Px5 MOSI
|
||||
Px6 MISO
|
||||
Px7 SCK
|
||||
GND
|
||||
VDD
|
||||
|
||||
Documentation:
|
||||
* https://www.microchip.com/development-tools/xplained-boards
|
||||
* http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Development-Kit_User%20Guide.pdf
|
||||
|
||||
This binding provides a nexus mapping for 10 pins where pins are disposed
|
||||
to have a even and odd column:
|
||||
|
||||
Connector
|
||||
Bind Pin Name Pin Pin Pin Name Bind
|
||||
0 I2C(SDA) 1 2 I2C(SCL) 1
|
||||
2 UART(RX) 3 4 UART(TX) 3
|
||||
4 SPI(CS0) 5 6 SPI(MOSI) 5
|
||||
6 SPI(MISO) 7 8 SPI(SCK) 7
|
||||
GND 9 10 VDD(+3.3V)
|
||||
|
||||
compatible: "atmel-xplained-header"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,49 @@
|
||||
# Copyright (C) 2020 Gerson Fernando Budke <nandojve@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
GPIO pins exposed on Atmel Xplained Pro headers.
|
||||
|
||||
The Xplained Pro layout provide a standard 20 pin header. A board can have
|
||||
one or more headers and can share pins. The extension headers are given
|
||||
names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
|
||||
to the embedded debugger. A header with ID7 signal from the embedded
|
||||
debugger connected should be called EXT7. PWR, EXT1, EXT2 and EXT3 are
|
||||
standard extension headers that have a predefined position according to the
|
||||
list below:
|
||||
* PWR is right angled at the top right hand side of the board. This
|
||||
header must always be implemented.
|
||||
* EXT1 is right angled at the top right hand side of the board, located
|
||||
below the PWR header. This header must always be present.
|
||||
* EXT2 is right angled and at the bottom right hand side of the board.
|
||||
This header is mandatory for medium and large boards and should not be
|
||||
implemented on small boards.
|
||||
* EXT3 is right angled pointing downwards
|
||||
All MCU boards have to implement at least PWR, EXT1, EXT2 (on medium and
|
||||
large boards), and EXT3. EXT4 to EXT7 can be placed differently depending
|
||||
on the board design. EXT4 to EXT7 can either be standard extension headers
|
||||
or application specific headers.
|
||||
|
||||
Documentation:
|
||||
* https://www.microchip.com/development-tools/xplained-boards
|
||||
* http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Development-Kit_User%20Guide.pdf
|
||||
|
||||
This binding provides a nexus mapping for 20 pins where pins are disposed
|
||||
to have a even and odd column:
|
||||
|
||||
Connector
|
||||
Bind Pin Name Pin Pin Pin Name Bind
|
||||
ID 1 2 GND
|
||||
0 ADC(+) 3 4 ADC(-) 1
|
||||
2 UART(RTS)/GPIO1 5 6 UART(CTS)/GPIO2 3
|
||||
4 PWM(+) 7 8 PWM(-) 5
|
||||
6 IRQ/GPIO3 9 10 SPI(CS1)/GPIO4 7
|
||||
8 I2C(SDA) 11 12 I2C(SCL) 9
|
||||
10 UART(RX) 13 14 UART(TX) 11
|
||||
12 SPI(CS0) 15 16 SPI(MOSI) 13
|
||||
14 SPI(MISO) 17 18 SPI(SCK) 15
|
||||
GND 19 20 VDD(+3.3V)
|
||||
|
||||
compatible: "atmel-xplained-pro-header"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,26 @@
|
||||
# Copyright (c) 2021 Synopsys
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Cypress cy8c95xx GPIO port node
|
||||
|
||||
compatible: "cypress,cy8c95xx-gpio-port"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
ngpios:
|
||||
required: true
|
||||
const: 8
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2021 Synopsys
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Cypress cy8c95xx GPIO node
|
||||
|
||||
compatible: "cypress,cy8c95xx-gpio"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2020-2021 ATL Electronics
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Cypress GPIO PORT node
|
||||
|
||||
compatible: "cypress,psoc6-gpio"
|
||||
|
||||
include: ["gpio-controller.yaml", "base.yaml"]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
"#cypress,pin-cells":
|
||||
type: int
|
||||
required: true
|
||||
const: 2
|
||||
description: Number of items to expect in a cypress,pins specifier
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
|
||||
cypress,pin-cells:
|
||||
- pin
|
||||
- hsiom
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (c) 2020 ATL Electronics
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Cypress High Speed I/O Matrix
|
||||
|
||||
compatible: "cypress,psoc6-hsiom"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright (c) 2019, Yannis Damigos
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ESP32 GPIO controller
|
||||
|
||||
compatible: "espressif,esp32-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2021 Abel Sensors
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: FXL6408 I2C-based GPIO expander
|
||||
|
||||
compatible: "fcs,fxl6408"
|
||||
|
||||
include: [gpio-controller.yaml, i2c-device.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,27 @@
|
||||
# Copyright (c) 2021 Teslabs Engineering S.L.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: GD32 GPIO node
|
||||
|
||||
compatible: "gd,gd32-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
rcu-periph-clock:
|
||||
type: int
|
||||
description: Reset Control Unit Peripheral Clock ID
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,45 @@
|
||||
# Copyright (c) 2019, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for GPIO controllers
|
||||
|
||||
properties:
|
||||
"gpio-controller":
|
||||
type: boolean
|
||||
required: true
|
||||
description: Convey's this node is a GPIO controller
|
||||
"#gpio-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a GPIO specifier
|
||||
ngpios:
|
||||
type: int
|
||||
required: false
|
||||
default: 32
|
||||
description: |
|
||||
This property indicates the number of in-use slots of available slots
|
||||
for GPIOs. The typical example is something like this: the hardware
|
||||
register is 32 bits wide, but only 18 of the bits have a physical
|
||||
counterpart. The driver is generally written so that all 32 bits can
|
||||
be used, but the IP block is reused in a lot of designs, some using
|
||||
all 32 bits, some using 18 and some using 12. In this case, setting
|
||||
"ngpios = <18>;" informs the driver that only the first 18 GPIOs, at
|
||||
local offset 0 .. 17, are in use. For cases in which there might be
|
||||
holes in the slot range, this value should be the max slot number-1.
|
||||
gpio-reserved-ranges:
|
||||
type: array
|
||||
required: false
|
||||
description: |
|
||||
If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
|
||||
this property contains an additional set of tuples which specify which GPIOs
|
||||
are unusable. This property indicates the start and size of the GPIOs
|
||||
that can't be used.
|
||||
|
||||
For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
|
||||
GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>.
|
||||
gpio-line-names:
|
||||
type: string-array
|
||||
required: false
|
||||
description: |
|
||||
This is an array of strings defining the names of the GPIO lines
|
||||
going out of the GPIO controller
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (c) 2018, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: GPIO KEYS parent node
|
||||
|
||||
compatible: "gpio-keys"
|
||||
|
||||
child-binding:
|
||||
description: GPIO KEYS child node
|
||||
properties:
|
||||
gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
label:
|
||||
required: true
|
||||
type: string
|
||||
description: Human readable string describing the device (used as device_get_binding() argument)
|
||||
@@ -0,0 +1,32 @@
|
||||
# Copyright (c) 2018, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: GPIO LEDs parent node
|
||||
|
||||
compatible: "gpio-leds"
|
||||
|
||||
include:
|
||||
- name: base.yaml
|
||||
property-allowlist: [label]
|
||||
|
||||
properties:
|
||||
label:
|
||||
description: |
|
||||
Human readable string describing the device and used to set the device
|
||||
name. It can be passed as argument to device_get_binding() to retrieve
|
||||
the device. If this property is omitted, then the device name is set
|
||||
from the node full name.
|
||||
|
||||
child-binding:
|
||||
description: GPIO LED child node
|
||||
properties:
|
||||
gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
label:
|
||||
required: false
|
||||
type: string
|
||||
description: |
|
||||
Human readable string describing the LED. It can be used by an
|
||||
application to identify this LED or to retrieve its number/index
|
||||
(i.e. child node number) on the parent device.
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright (c) 2019, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for GPIO nexus nodes
|
||||
|
||||
properties:
|
||||
gpio-map:
|
||||
type: compound
|
||||
required: true
|
||||
|
||||
gpio-map-mask:
|
||||
type: compound
|
||||
required: false
|
||||
|
||||
gpio-map-pass-thru:
|
||||
type: compound
|
||||
required: false
|
||||
|
||||
"#gpio-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a GPIO specifier
|
||||
@@ -0,0 +1,38 @@
|
||||
# Copyright (c) 2018-2019 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Intel GPIO node
|
||||
|
||||
compatible: "intel,gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
group-index:
|
||||
type: int
|
||||
description: Group number for this GPIO entry
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
ngpios:
|
||||
required: true
|
||||
description: Number of pins for this GPIO entry
|
||||
|
||||
pin-offset:
|
||||
type: int
|
||||
required: true
|
||||
description: Pin offset of this GPIO entry
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: This binding gives a base representation of the ITE gpio
|
||||
|
||||
compatible: "ite,it8xxx2-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2019 Linaro Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Represents GPIO pin nodes exposed on the 96Boards 1.8v low-speed header
|
||||
|
||||
compatible: "linaro,96b-lscon-1v8"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,9 @@
|
||||
# Copyright (c) 2019 Linaro Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Represents GPIO pin nodes exposed on the 96Boards 3.3v low-speed header
|
||||
|
||||
compatible: "linaro,96b-lscon-3v3"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,32 @@
|
||||
#
|
||||
# Copyright (c) 2019 Antmicro <www.antmicro.com>
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: Litex GPIO
|
||||
|
||||
compatible: "litex,gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
port-is-output:
|
||||
type: boolean
|
||||
description: Indicates if the port is an output port
|
||||
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
ngpios:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2020 Micro:bit Educational Foundation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
GPIO pins exposed on BBC MicroBit headers.
|
||||
|
||||
The edge connector on the micro:bit is used to connect to external
|
||||
circuits and components.
|
||||
|
||||
There are 25 strips/pins including 5 rings for using with 4mm banana
|
||||
plugs or crocodile clips. 3 of these rings are for general purpose
|
||||
input and output (GPIO) and are also capable of analog, PWM and touch
|
||||
sensing, and two are connected to the micro:bit power supply.
|
||||
|
||||
The smaller strips spaced at 1.27mm on the edge connector have additional
|
||||
signals, some of which are used by the micro:bit, and others that are free
|
||||
for you to use. There are a number of external PCB connectors for purchase
|
||||
with an 80w 1.27mm pitch that can be used to easily access these extra pins.
|
||||
|
||||
Only the pins on the front are connected to signals. The back rings are
|
||||
connected to the front rings, but the back small strips are unconnected.
|
||||
|
||||
compatible: "microbit,edge-connector"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,29 @@
|
||||
#
|
||||
# Copyright (c) 2021 metraTec GmbH
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: |
|
||||
This is a representation of the Microchip MCP230xx I2C Gpio Expander.
|
||||
|
||||
compatible: "microchip,mcp230xx"
|
||||
|
||||
include: [gpio-controller.yaml, i2c-device.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
ngpios:
|
||||
type: int
|
||||
enum:
|
||||
- 8
|
||||
- 16
|
||||
required: true
|
||||
description: |
|
||||
Number of gpios supported by the chip.
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,29 @@
|
||||
#
|
||||
# Copyright (c) 2020 Geanix ApS
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: |
|
||||
This is a representation of the Microchip MCP23S17 SPI Gpio Expander.
|
||||
|
||||
compatible: "microchip,mcp23s17"
|
||||
|
||||
include: [gpio-controller.yaml, spi-device.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
ngpios:
|
||||
type: int
|
||||
required: true
|
||||
const: 16
|
||||
description: Number of gpios supported
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,32 @@
|
||||
#
|
||||
# Copyright (c) 2020 Geanix ApS
|
||||
# Copyright (c) 2021 Peter Johanson
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: |
|
||||
This is a representation of the Microchip MCP23SXX SPI Gpio Expander.
|
||||
|
||||
compatible: "microchip,mcp23sxx"
|
||||
|
||||
include: [gpio-controller.yaml, spi-device.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
ngpios:
|
||||
type: int
|
||||
required: true
|
||||
enum:
|
||||
- 8
|
||||
- 16
|
||||
description: Number of gpios supported
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2019, Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip CEC/MEC GPIO V2 node
|
||||
|
||||
compatible: "microchip,xec-gpio-v2"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: false
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
port-id:
|
||||
type: int
|
||||
required: true
|
||||
description: Zero based GPIO port number
|
||||
|
||||
girq-id:
|
||||
type: int
|
||||
required: true
|
||||
description: Aggregated GIRQ number for this bank of 32 GPIO pins.
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2019, Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip CEC/MEC GPIO node
|
||||
|
||||
compatible: "microchip,xec-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: false
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,33 @@
|
||||
# Copyright (C) 2020 Linaro
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
GPIO pins exposed on Mikro BUS headers.
|
||||
|
||||
The Mikro BUS layout provides two headers, aligned on the opposite
|
||||
edges of the board.
|
||||
|
||||
Documentation:
|
||||
* https://www.mikroe.com/mikrobus
|
||||
* https://download.mikroe.com/documents/standards/mikrobus/mikrobus-standard-specification-v200.pdf
|
||||
|
||||
This binding provides a nexus mapping for 10 pins, left side pins are
|
||||
numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
|
||||
(PWM - SDA). The bottom 2 pins on each side are used for input voltage
|
||||
and ground, they are not mapped in the nexus.
|
||||
|
||||
Analog - AN PWM - PWM output
|
||||
Reset - RST INT - Hardware Interrupt
|
||||
SPI Chip Select - CS RX - UART Receive
|
||||
SPI Clock - SCK TX - UART Transmit
|
||||
SPI Master Input Slave Output - MISO SCL - I2C Clock
|
||||
SPI Master Output Slave Input - MOSI SDA - I2C Data
|
||||
VCC-3.3V power - +3.3V +5V - VCC-5V power
|
||||
Reference Ground - GND GND - Reference Ground
|
||||
|
||||
Board's silkscreen may vary depending you board, but coherent with
|
||||
the description above as it's according to the standard's specification.
|
||||
|
||||
compatible: "mikro-bus"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,25 @@
|
||||
description: NEORV32 GPIO
|
||||
|
||||
compatible: "neorv32-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
reg-names:
|
||||
required: true
|
||||
|
||||
syscon:
|
||||
type: phandle
|
||||
required: true
|
||||
description: |
|
||||
phandle to syscon (NEORV32 SYSINFO) node.
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,41 @@
|
||||
# Copyright (c) 2018, marc-cpdesign
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NRF5 GPIO node
|
||||
|
||||
compatible: "nordic,nrf-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
sense-edge-mask:
|
||||
required: false
|
||||
type: int
|
||||
description: |
|
||||
Mask of pins that use the GPIO sense mechanism for edge detection.
|
||||
Pins not included in the mask use GPIOTE channels in the event mode.
|
||||
|
||||
port:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The GPIO port number. GPIO port P0 has:
|
||||
|
||||
port = <0>;
|
||||
|
||||
And P1 has:
|
||||
|
||||
port = <1>;
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (c) 2018, marc-cpdesign
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NRF5 GPIOTE node
|
||||
|
||||
compatible: "nordic,nrf-gpiote"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,32 @@
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nuvoton NCT38XX series I2C-based GPIO expander alert handler
|
||||
|
||||
Example:
|
||||
nct3807_alert_1 {
|
||||
compatible = "nuvoton,nct38xx-gpio-alert";
|
||||
irq-gpios = <&gpiod 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
||||
nct38xx-dev = <&nct3808_0_P1 &nct3808_0_P2>;
|
||||
label = "NCT3808_ALERT_0";
|
||||
};
|
||||
|
||||
compatible: "nuvoton,nct38xx-gpio-alert"
|
||||
|
||||
include: [base.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
irq-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: Interrupt GPIO pin
|
||||
|
||||
nct38xx-dev:
|
||||
type: phandles
|
||||
required: true
|
||||
description: |
|
||||
NCT38XX devices which alert are handled by this alert handler.
|
||||
@@ -0,0 +1,44 @@
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton NCT38XX series I2C-based GPIO expander port
|
||||
|
||||
compatible: "nuvoton,nct38xx-gpio-port"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
reg:
|
||||
required: true
|
||||
|
||||
pin_mask:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Not every GPIOs are usable for different NCT38XX series. This property
|
||||
indicates the usable GPIO mask.
|
||||
|
||||
NCT3808: <0xdc>
|
||||
others: <0xff>
|
||||
|
||||
pinmux_mask:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
NCT38XX series port 0 has Pin Multiplexing functionality. However, not
|
||||
every GPIOs have pinmux controller functionality. This property
|
||||
indicates the usable GPIO pinmux mask. For port 1, this property is
|
||||
ignored.
|
||||
|
||||
NCT3807 port 0: <0xf7>
|
||||
others: <0xff>
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,83 @@
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nuvoton NCT38XX series I2C-based GPIO expander
|
||||
|
||||
Example:
|
||||
&i2c0_0 {
|
||||
nct3807@70 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nuvoton,nct38xx-gpio";
|
||||
reg = <0x70>;
|
||||
label = "NCT3807_0";
|
||||
|
||||
gpio@0 {
|
||||
compatible = "nuvoton,nct38xx-gpio-port";
|
||||
reg = <0x0>;
|
||||
label = "NCT3807_0_GPIO0";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <8>;
|
||||
pin_mask = <0xff>;
|
||||
pinmux_mask = <0xf7>;
|
||||
};
|
||||
|
||||
gpio@1 {
|
||||
compatible = "nuvoton,nct38xx-gpio-port";
|
||||
reg = <0x1>;
|
||||
label = "NCT3807_0_GPIO1";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <8>;
|
||||
pin_mask = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
nct3808_0_P1@71 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nuvoton,nct38xx-gpio";
|
||||
reg = <0x71>;
|
||||
label = "NCT3808_0_P1";
|
||||
|
||||
gpio@0 {
|
||||
compatible = "nuvoton,nct38xx-gpio-port";
|
||||
reg = <0x0>;
|
||||
label = "NCT3808_0_P1_GPIO0";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <8>;
|
||||
pin_mask = <0xdc>;
|
||||
pinmux_mask = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
nct3808_0_P2@75 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "nuvoton,nct38xx-gpio";
|
||||
reg = <0x75>;
|
||||
label = "NCT3808_0_P2";
|
||||
|
||||
gpio@0 {
|
||||
compatible = "nuvoton,nct38xx-gpio-port";
|
||||
reg = <0x0>;
|
||||
label = "NCT3808_0_P2_GPIO0";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <8>;
|
||||
pin_mask = <0xdc>;
|
||||
pinmux_mask = <0xff>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
compatible: "nuvoton,nct38xx-gpio"
|
||||
|
||||
include: [i2c-device.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,39 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX-GPIO node
|
||||
|
||||
compatible: "nuvoton,npcx-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
index:
|
||||
type: int
|
||||
required: true
|
||||
description: index of gpio device
|
||||
|
||||
wui-maps:
|
||||
type: phandles
|
||||
required: true
|
||||
description: |
|
||||
Mapping table between Wake-Up Input (WUI) and 8 IOs belong to this device.
|
||||
Please notice not all IOs connect to WUIs.
|
||||
In this case, it will be presented by wui_none.
|
||||
|
||||
For example the WUI mapping on NPCX7 GPIO8 would be
|
||||
wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
|
||||
&wui_none &wui_none &wui_io86 &wui_io87>;
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nuvoton, NPCX-PSL (Power Switch Logic) Output node
|
||||
|
||||
compatible: "nuvoton,npcx-psl-out"
|
||||
|
||||
include: [base.yaml]
|
||||
|
||||
properties:
|
||||
controller:
|
||||
type: phandle
|
||||
required: true
|
||||
description: gpio controller to handle PSL output pad.
|
||||
|
||||
pin:
|
||||
type: int
|
||||
required: true
|
||||
description: pin in gpio controller for PSL output.
|
||||
@@ -0,0 +1,30 @@
|
||||
# Copyright (c) 2017, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX GPIO node
|
||||
|
||||
compatible: "nxp,imx-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: false
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
rdc:
|
||||
type: int
|
||||
required: false
|
||||
description: Set the RDC permission for this peripheral
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,26 @@
|
||||
description: Kinetis GPIO node
|
||||
|
||||
compatible: "nxp,kinetis-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
nxp,kinetis-port:
|
||||
required: true
|
||||
type: phandle
|
||||
description: |
|
||||
A phandle reference to the device tree node that contains the pinmux
|
||||
port associated with this GPIO controller.
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,31 @@
|
||||
# Copyright (c) 2019, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC GPIO node
|
||||
|
||||
compatible: "nxp,lpc-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
port:
|
||||
type: int
|
||||
required: true
|
||||
description: The GPIO port this node describes
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
- 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,41 @@
|
||||
# Copyright (c) 2020 Seagate Technology LLC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP LPC11U6X GPIO node
|
||||
|
||||
compatible: "nxp,lpc11u6x-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
base:
|
||||
type: int
|
||||
required: false
|
||||
default: 0
|
||||
description: index of the first GPIO for this port.
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
pinmux-port:
|
||||
required: true
|
||||
type: phandle
|
||||
description: |
|
||||
a phandle reference to the device tree node that contains the pinmux
|
||||
port associated with this GPIO controller.
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,29 @@
|
||||
# Copyright (c) 2019 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: PCA95xx series I2C-based GPIO expander
|
||||
|
||||
compatible: "nxp,pca95xx"
|
||||
|
||||
include: [gpio-controller.yaml, i2c-device.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
has-pud:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Supports pull-up/pull-down
|
||||
|
||||
interrupt-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: Interrupt GPIO pin (active-low open-drain)
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: PCAL6408A 8-bit I2C-based I/O expander
|
||||
|
||||
compatible: "nxp,pcal6408a"
|
||||
|
||||
include: [i2c-device.yaml, gpio-controller.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
ngpios:
|
||||
required: true
|
||||
const: 8
|
||||
|
||||
int-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
GPIO connected to the controller INT pin. This pin is active-low.
|
||||
|
||||
reset-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
GPIO connected to the controller RESET pin. This pin is active-low.
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,29 @@
|
||||
description: OpenISA GPIO node
|
||||
|
||||
compatible: "openisa,rv32m1-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
openisa,rv32m1-port:
|
||||
required: true
|
||||
type: phandle
|
||||
description: |
|
||||
A phandle reference to the device tree node that contains the pinmux
|
||||
port associated with this GPIO controller.
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,43 @@
|
||||
# Copyright (C) 2020 Peter Bigot Consulting, LLC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
GPIO pins exposed on Particle Gen3 (Feather) headers.
|
||||
|
||||
The Particle Gen3 boards are compatible with the Adafruit Feather
|
||||
"shields" but use a different orientation and pin numbering scheme.
|
||||
|
||||
With the board oriented with the micro USB at the top:
|
||||
* A 12-pin header on the right. 9 pins on this header are exposed
|
||||
by this binding
|
||||
* A 16-pin header. 13 pins on this header are exposed by this
|
||||
binding.
|
||||
|
||||
This binding provides a nexus mapping for 22 pins where parent pins
|
||||
0 through 8 correspond to the pins on the 12-pin header, starting
|
||||
from the bottom; and pins 9 through 21 correspond to pins on the
|
||||
16-pin header, skipping the bottom pin then assigning 9 through 19,
|
||||
skipping over GND, and replacing the lower 3V3 with pin 20. The
|
||||
physical layout is depicted below.
|
||||
|
||||
21 RESETn
|
||||
- 3V3
|
||||
20 MODEn
|
||||
- GND
|
||||
19 ADC0 LiPo+ -
|
||||
18 ADC1 ENABLE -
|
||||
17 ADC2 VBUS -
|
||||
16 ADC3 PWM1 8
|
||||
15 ADC4 PWM0 7
|
||||
14 SS PWM1 6
|
||||
13 SCK PWM1 5
|
||||
12 MOSI PWM1 4
|
||||
11 MISO PWM3 3
|
||||
10 RX PWM3 2
|
||||
9 TX SCL 1
|
||||
- n/c SDA 0
|
||||
|
||||
|
||||
compatible: "particle-gen3-header"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,39 @@
|
||||
description: EOS S3 GPIO node
|
||||
|
||||
compatible: "quicklogic,eos-s3-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
pin-secondary-config:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
This property is used to preconfigure the GPIOs and connect them to
|
||||
a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs
|
||||
which can be configured as follows
|
||||
"GPIO_NUM : primary_pin_num / secondary_pin_num"
|
||||
"0 : 6 / 24"
|
||||
"1 : 9 / 26"
|
||||
"2 : 11 / 28"
|
||||
"3 : 14 / 30"
|
||||
"4 : 18 / 31"
|
||||
"5 : 21 / 36"
|
||||
"6 : 22 / 38"
|
||||
"7 : 23 / 45"
|
||||
E.g. configuring GPIO 2 as secondary results in controlling pin 28,
|
||||
to do so set the bit on the 2nd index of this property
|
||||
"pin-secondary-config = <0x04>;"
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,28 @@
|
||||
#
|
||||
# Copyright (c) 2020 IoT.bzh
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: Renesas RCAR GPIO
|
||||
|
||||
compatible: "renesas,rcar-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,33 @@
|
||||
# Copyright (c) 2019 Foundries.io
|
||||
# Copyright (C) 2019 Peter Bigot Consulting, LLC
|
||||
# Copyright (C) 2021 Peter Johanson
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
GPIO pins exposed on Seeeduino Xiao (and compatible devices) headers.
|
||||
|
||||
The Seeeeduino Xiao layout provides two headers, along opposite
|
||||
edges of the board.
|
||||
|
||||
Proceeding counter-clockwise:
|
||||
* A 7-pin Digital/Analog Input header. This has input signals
|
||||
labeled from 0 at the top through 6 at the bottom.
|
||||
* An 7-pin header Power and Digital/Analog Input header. This
|
||||
has three power pins, followed by four inputs labeled 10 at the
|
||||
top through 7 at the bottom.
|
||||
|
||||
This binding provides a nexus mapping for 10 pins where parent pins 0
|
||||
through 10 correspond to D0 through D10, as depicted below:
|
||||
|
||||
0 D0 5V -
|
||||
1 D1 GND -
|
||||
2 D2 3V3 -
|
||||
3 D3 D10 10
|
||||
4 A4 D9 9
|
||||
5 D5 D8 8
|
||||
6 D6 D7 7
|
||||
|
||||
|
||||
compatible: "seeed,xiao-gpio"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,46 @@
|
||||
# Copyright (c) 2018, Aapo Vienamo
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: SX1509B GPIO node
|
||||
|
||||
compatible: "semtech,sx1509b"
|
||||
|
||||
include: [i2c-device.yaml, gpio-controller.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
ngpios:
|
||||
required: true
|
||||
const: 16
|
||||
|
||||
nint-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
Connection for the NINT signal. This signal is active-low when
|
||||
produced by sx1509b GPIO node.
|
||||
|
||||
init-out-low:
|
||||
type: int
|
||||
required: false
|
||||
default: 0
|
||||
description: |
|
||||
Bit mask identifying pins that should be initialized as outputs
|
||||
driven low.
|
||||
|
||||
init-out-high:
|
||||
type: int
|
||||
required: false
|
||||
default: 0
|
||||
description: |
|
||||
Bit mask identifying pins that should be initialized as outputs
|
||||
driven high.
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2018, SiFive Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: SiFive GPIO node
|
||||
|
||||
compatible: "sifive,gpio0"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,24 @@
|
||||
description: SiLabs Gecko GPIO port node
|
||||
|
||||
compatible: "silabs,gecko-gpio-port"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
peripheral-id:
|
||||
type: int
|
||||
required: true
|
||||
description: peripheral ID
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,20 @@
|
||||
description: SiLabs Gecko GPIO node
|
||||
|
||||
compatible: "silabs,gecko-gpio"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
location-swo:
|
||||
type: int
|
||||
required: false
|
||||
description: Serial Wire Output (SWO) PIN location
|
||||
@@ -0,0 +1,34 @@
|
||||
# Copyright (c) 2021 Synopsys, Inc. All rights reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Synopsys CREG GPIO node
|
||||
|
||||
compatible: "snps,creg-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
bit_per_gpio:
|
||||
type: int
|
||||
required: true
|
||||
|
||||
off_val:
|
||||
type: int
|
||||
required: true
|
||||
|
||||
on_val:
|
||||
type: int
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Synopsys DesignWare GPIO node
|
||||
|
||||
compatible: "snps,designware-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2018, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STM32 GPIO node
|
||||
|
||||
compatible: "st,stm32-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2021 Titouan Christophe
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STMPE1600 I2C-based GPIO expander
|
||||
|
||||
compatible: "st,stmpe1600"
|
||||
|
||||
include: [gpio-controller.yaml, i2c-device.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright (c) 2021, Telink Semiconductor
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Telink B91 GPIO node
|
||||
|
||||
compatible: "telink,b91-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,34 @@
|
||||
# Copyright (c) 2019 Brett Witherspoon
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
TI BoosterPack GPIO header
|
||||
|
||||
GPIO pins exposed as BoosterPack headers on TI LaunchPads.
|
||||
|
||||
BoosterPack plug-in modules are available in 20 and 40 pin variants. The
|
||||
20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
|
||||
10 x 2 pin headers. Both variants are compatible and stackable.
|
||||
|
||||
The pins of the 20 pin variant and the outer row of the 40 pin variant are
|
||||
numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
|
||||
through 40. The BoosterPack pinout is depicted below:
|
||||
|
||||
1 3.3V 21 5V 40 GPIO 20 GND
|
||||
2 Analog 22 GND 39 GPIO 19 GPIO / SPI CS
|
||||
3 UART RXD 23 Analog 38 GPIO 18 GPIO
|
||||
4 UART TXD 24 Analog 37 GPIO 17 GPIO
|
||||
5 GPIO 25 Analog 36 GPIO 16 RESET
|
||||
6 Analog 26 Analog 35 GPIO 15 SPI MOSI
|
||||
7 SPI CLK 27 Analog 34 GPIO 14 SPI MISO
|
||||
8 GPIO 28 Analog 33 GPIO 13 GPIO / SPI CS
|
||||
9 I2C SCL 29 32 GPIO 12 GPIO / SPI CS
|
||||
10 I2C SDA 30 31 GPIO 11 GPIO
|
||||
|
||||
Additional information about the BoosterPack pinout can be found at
|
||||
http://processors.wiki.ti.com/index.php/BYOB or in the documentation for
|
||||
a TI LaunchPad development kit,
|
||||
|
||||
compatible: "ti,boosterpack-header"
|
||||
|
||||
include: [gpio-nexus.yaml, base.yaml]
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2019 Brett Witherspoon
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: TI SimpleLink CC13xx / CC26xx GPIO node
|
||||
|
||||
compatible: "ti,cc13xx-cc26xx-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,23 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
description: TI CC32XX GPIO node
|
||||
|
||||
compatible: "ti,cc32xx-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,18 @@
|
||||
description: TI LMP90xxx GPIO controller binding
|
||||
|
||||
compatible: "ti,lmp90xxx-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
on-bus: lmp90xxx
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,24 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: TI Stellaris GPIO node
|
||||
|
||||
compatible: "ti,stellaris-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,33 @@
|
||||
# Copyright (c) 2018, Aapo Vienamo
|
||||
# Copyright (c) 2021, Laird Connectivity
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: TCA9538 GPIO node
|
||||
|
||||
compatible: "ti,tca9538"
|
||||
|
||||
include: [i2c-device.yaml, gpio-controller.yaml]
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
ngpios:
|
||||
required: true
|
||||
const: 8
|
||||
description: |
|
||||
Number of GPIOs available on port expander.
|
||||
|
||||
nint-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
Connection for the NINT signal. This signal is active-low when
|
||||
produced by tca9538 GPIO node.
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,18 @@
|
||||
description: Xilinx AXI GPIO IP GPIO2 node
|
||||
|
||||
compatible: "xlnx,xps-gpio-1.00.a-gpio2"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
on-bus: xlnx,xps-gpio-1.00.a
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,79 @@
|
||||
description: Xilinx AXI GPIO IP node
|
||||
|
||||
compatible: "xlnx,xps-gpio-1.00.a"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
bus: xlnx,xps-gpio-1.00.a
|
||||
|
||||
# Property names correspond to a subset of those generated by
|
||||
# https://github.com/Xilinx/device-tree-xlnx
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
xlnx,all-inputs:
|
||||
type: int
|
||||
description: |
|
||||
1 if all GPIOs are inputs, 0 otherwise
|
||||
|
||||
xlnx,all-outputs:
|
||||
type: int
|
||||
description: |
|
||||
1 if all GPIOs are outputs, 0 otherwise
|
||||
|
||||
xlnx,dout-default:
|
||||
type: int
|
||||
description: |
|
||||
Default output value. If n-th bit is 1, GPIO-n default value is 1.
|
||||
|
||||
xlnx,gpio-width:
|
||||
type: int
|
||||
description: |
|
||||
Number of GPIOs supported
|
||||
|
||||
xlnx,tri-default:
|
||||
type: int
|
||||
description: |
|
||||
Default tristate register value. If n-th bit is 1, GPIO-n is an input.
|
||||
|
||||
xlnx,is-dual:
|
||||
type: int
|
||||
description: |
|
||||
1 if controller has GPIO2 enabled, 0 otherwise
|
||||
|
||||
xlnx,all-inputs-2:
|
||||
type: int
|
||||
description: |
|
||||
1 if all GPIO2s are inputs, 0 otherwise
|
||||
|
||||
xlnx,all-outputs-2:
|
||||
type: int
|
||||
description: |
|
||||
1 if all GPIO2s are outputs, 0 otherwise
|
||||
|
||||
xlnx,dout-default-2:
|
||||
type: int
|
||||
description: |
|
||||
Default output value. If n-th bit is 1, GPIO2-n default value is 1.
|
||||
|
||||
xlnx,gpio2-width:
|
||||
type: int
|
||||
description: |
|
||||
Number of GPIO2s supported
|
||||
|
||||
xlnx,tri-default-2:
|
||||
type: int
|
||||
description: |
|
||||
Default tristate register value. If n-th bit is 1, GPIO2-n is an input.
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
@@ -0,0 +1,38 @@
|
||||
# Copyright 2020, Friedt Professional Engineering Services, Inc
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: GPIO Emulator
|
||||
|
||||
compatible: "zephyr,gpio-emul"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
rising-edge:
|
||||
description: Enables support for rising edge interrupt detection
|
||||
type: boolean
|
||||
|
||||
falling-edge:
|
||||
description: Enables support for falling edge interrupt detection
|
||||
type: boolean
|
||||
|
||||
high-level:
|
||||
description: Enables support for high level interrupt detection
|
||||
type: boolean
|
||||
|
||||
low-level:
|
||||
description: Enables support for low level interrupt detection
|
||||
type: boolean
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
Reference in New Issue
Block a user