WIP: device tree MVP

2026-11-09 21:01:36 +08:00 · 2022-01-06 17:20:17 -05:00
parent 07d75d85cf
commit 1f39b42525
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+# Copyright (c) 2018, Aurelien Jarno
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM Enhanced Embedded Flash Controller (EEFC)
+
+compatible: "atmel,sam-flash-controller"
+
+include: flash-controller.yaml
+
+properties:
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
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+description: Atmel SAM0 NVMC (Non-Volatile Memory Controller)
+
+compatible: "atmel,sam0-nvmctrl"
+
+include: flash-controller.yaml
+
+properties:
+    lock-regions:
+      type: int
+      required: true
+      description: Number of lock regions
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+# Copyright (c) 2018, Cypress
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cypress flash controller
+
+compatible: "cypress,psoc6-flash-controller"
+
+include: flash-controller.yaml
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+description: ESP32 Family flash controller
+
+compatible: "espressif,esp32-flash-controller"
+
+include: flash-controller.yaml
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+# Common fields for flash controllers
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    reg:
+      required: true
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+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE IT8XXX2 flash memory
+
+compatible: "ite,it8xxx2-flash-controller"
+
+include: flash-controller.yaml
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+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Properties defining the interface for the Nordic QSPI peripheral.
+
+    The reg property describes two register blocks: one for the memory
+    corresponding to the QSPI peripheral registers, and another for
+    the memory mapped XIP area:
+
+        qspi: qspi@2b000 {
+                compatible = "nordic,nrf-qspi";
+                reg = <0x2b000 0x1000>, <0x10000000 0x10000000>;
+                reg-names = "qspi", "qspi_mm";
+                ...
+        };
+
+    Above, the register block with base address 0x2b000 and name
+    "qspi" are the QSPI peripheral registers. The register block with
+    base address 0x10000000 and name "qspi_mm" is the XIP area.
+
+compatible: "nordic,nrf-qspi"
+
+include: flash-controller.yaml
+
+bus: qspi
+
+properties:
+  "#address-cells":
+    required: true
+    const: 1
+
+  "#size-cells":
+    required: true
+    const: 0
+
+  interrupts:
+    required: true
+
+  sck-pin:
+    type: int
+    required: true
+    description: |
+      The SCK pin to use.
+
+      For pins P0.0 through P0.31, use the pin number. For example,
+      to use P0.16 for SCK, set:
+
+          sck-pin = <16>;
+
+      For pins P1.0 through P1.31, add 32 to the pin number. For
+      example, to use P1.2 for SCK, set:
+
+          sck-pin = <34>;  /* 32 + 2 */
+  io-pins:
+    type: array
+    required: true
+    description: |
+      Pin numbers associated with IO0 through IO3 signals.
+
+      Examples:
+
+          io-pins = <io0-pin io1-pin>; // two pins
+
+          io-pins = <io0-pin io1-pin io2-pin io3-pin>; // four pins
+
+      Either two or four pins must be configured using this property
+      as shown above. The pin numbering scheme is the same as the
+      sck-pin property's.
+  csn-pins:
+    type: array
+    required: true
+    description: |
+      Chip select signal pin number. Exactly one pin should be
+      given. The pin numbering scheme is the same as the
+      sck-pin property's.
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+description: Nordic NVMC (Non-Volatile Memory Controller)
+
+compatible: "nordic,nrf51-flash-controller"
+
+include: flash-controller.yaml
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+description: Nordic NVMC (Non-Volatile Memory Controller)
+
+compatible: "nordic,nrf52-flash-controller"
+
+include: flash-controller.yaml
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+description: Nordic NVMC (Non-Volatile Memory Controller)
+
+compatible: "nordic,nrf53-flash-controller"
+
+include: flash-controller.yaml
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+description: Nordic NVMC (Non-Volatile Memory Controller)
+
+compatible: "nordic,nrf91-flash-controller"
+
+include: flash-controller.yaml
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+description: NXP Kinetis Flash Memory Module A (FTFA)
+
+compatible: "nxp,kinetis-ftfa"
+
+include: flash-controller.yaml
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+description: NXP Kinetis Flash Memory Module E (FTFE)
+
+compatible: "nxp,kinetis-ftfe"
+
+include: flash-controller.yaml
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+description: NXP Kinetis Flash Memory Module L (FTFL)
+
+compatible: "nxp,kinetis-ftfl"
+
+include: flash-controller.yaml
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+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP LPC IAP (In-Application Programming) flash memory controller
+
+compatible: "nxp,lpc-iap"
+
+include: flash-controller.yaml
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+description: OpenISA Flash Memory Module E (FTFE)
+
+compatible: "openisa,rv32m1-ftfe"
+
+include: flash-controller.yaml
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+# Copyright (c) 2018, Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silicon Labs Gecko flash controller
+
+compatible: "silabs,gecko-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 Family flash controller
+
+compatible: "st,stm32-flash-controller"
+
+include: flash-controller.yaml
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+# Copyright (c) 2020, Linaro limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STM32 QSPI Flash controller supporting the JEDEC CFI interface
+
+    Representation of a serial flash on a quadspi bus:
+
+        mx25r6435f: qspi-nor-flash@0 {
+                compatible = "st,stm32-qspi-nor";
+                label = "MX25R6435F";
+                reg = <0>;
+                qspi-max-frequency = <80000000>;
+                size = <0x4000000>;
+                status = "okay";
+        };
+
+compatible: "st,stm32-qspi-nor"
+
+include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
+
+on-bus: qspi
+
+properties:
+    reg:
+      required: true
+    qspi-max-frequency:
+      type: int
+      required: true
+      description: Maximum clock frequency of device's QSPI interface in Hz
+    label:
+      required: true
+    size:
+      required: true
+      description: Flash Memory size in bits
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+description: STM32 F0 flash controller
+
+compatible: "st,stm32f0-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 F1 flash controller
+
+compatible: "st,stm32f1-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 F2 flash controller
+
+compatible: "st,stm32f2-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 F3 flash controller
+
+compatible: "st,stm32f3-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 F4 flash controller
+
+compatible: "st,stm32f4-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 F7 flash controller
+
+compatible: "st,stm32f7-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 G0 flash controller
+
+compatible: "st,stm32g0-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 G4 flash controller
+
+compatible: "st,stm32g4-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 H7 flash controller
+
+compatible: "st,stm32h7-flash-controller"
+
+include: flash-controller.yaml
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+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 L0 flash controller
+
+compatible: "st,stm32l0-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 L1 flash controller
+
+compatible: "st,stm32l1-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 L4 flash controller
+
+compatible: "st,stm32l4-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 L5 flash controller
+
+compatible: "st,stm32l5-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 U5 flash controller
+
+compatible: "st,stm32u5-flash-controller"
+
+include: flash-controller.yaml
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+description: STM32 WB flash controller
+
+compatible: "st,stm32wb-flash-controller"
+
+include: flash-controller.yaml
+
+properties:
+    single-bank:
+      type: boolean
+      description: dual-bank mode not enabled (page erase 4096k)
+      required: false
+
+    dual-bank:
+      type: boolean
+      description: dual-bank mode enabled (page erase 2048k)
+      required: false
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+description: Telink B91 Flash Controller
+
+compatible: "telink,b91-flash-controller"
+
+include: flash-controller.yaml
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+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI Stellaris flash controller
+
+compatible: "ti,stellaris-flash-controller"
+
+include: flash-controller.yaml
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+# SPDX-License-Identifier: Apache-2.0
+
+description: Simulated flash memory
+
+compatible: "zephyr,sim-flash"
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    erase-value:
+      type: int
+      description: Value of erased flash cell
+      required: false