mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,73 @@
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# Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
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# Copyright (c) 2020-2021 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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include: ethernet.yaml
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properties:
|
||||
reg:
|
||||
required: true
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||||
|
||||
num-queues:
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type: int
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required: true
|
||||
description: |
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||||
Number of hardware TX and RX queues.
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||||
|
||||
max-frame-size:
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type: int
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default: 1518
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description: |
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Maximum ethernet frame size. The current ethernet frame sizes
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supported by hardware are 1518, 1536 and 10240 (jumbo frames). This
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means that normally gmac will reject any frame above max-frame-size
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value. The default value is 1518, which represents an usual
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IEEE 802.3 ethernet frame:
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Ethernet Frame [ 14 MAC HEADER | 1500 MTU | 4 FCS ] = 1518 bytes
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When using value 1536 it is possible extend ethernet MAC HEADER up
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to 32 bytes. The hardware have support to jumbo frames and it can be
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enabled by selecting the value 10240.
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max-speed:
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type: int
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default: 100
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description: |
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This specifies maximum speed in Mbit/s supported by the device. The
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gmac driver supports 10Mbit/s and 100Mbit/s. Using 100, as default
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value, enables driver to configure 10 and 100Mbit/s speeds.
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phy-connection-type:
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type: string
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enum:
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- "rmii"
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- "mii"
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default: "rmii"
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description: |
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||||
Phy connection type define the physical interface connection between
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PHY and MAC. The default value uses gmac register reset value, which
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represents Reduced Media-Independent Interface (RMII) mode.
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This property must be used with pinctrl-0.
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pinctrl-0:
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type: phandles
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required: false
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description: |
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PIO pin configuration for the various GMAC signals that include GTXCK,
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GTXEN, GTX[3..0], GTXER, GRXCK, GRXDV, GRX[3..0], GRXER, GCRS, GCOL,
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GMDC, and GMDIO. Which signals are used vary based on if the PHY
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connection is MII or RMII (see datasheet for more details). We expect
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that the phandles will reference pinctrl nodes. These nodes will have
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a nodelabel that matches the Atmel SoC HAL defines and be of the form
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p<port><pin><periph>_<inst>_<signal>.
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For example the GMAC on SAME7x would be for RMII
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pinctrl-0 = <&pd0a_gmac_gtxck &pd1a_gmac_gtxen
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&pd2a_gmac_gtx0 &pd3a_gmac_gtx1
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&pd4a_gmac_grxdv &pd5a_gmac_grx0
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&pd6a_gmac_grx1 &pd7a_gmac_grxer
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&pd8a_gmac_gmdc &pd9a_gmac_gmdio>;
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This property must be used with phy-connection-type.
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@@ -0,0 +1,18 @@
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# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Atmel SAM-family GMAC Ethernet
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compatible: "atmel,sam-gmac"
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include: atmel,gmac-common.yaml
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properties:
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peripheral-id:
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type: int
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required: true
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description: |
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The peripheral identifier is required for Atmel SAMs MCUs to indicate
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which is the clock line associated with a specific peripheral. This
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clock line is defined at Power Management Controller (PMC) and it
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enables the peripheral.
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@@ -0,0 +1,8 @@
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# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Atmel SAM0-family GMAC Ethernet
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compatible: "atmel,sam0-gmac"
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include: atmel,gmac-common.yaml
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@@ -0,0 +1,18 @@
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# Copyright (c) 2020, DENX Software Engineering GmbH
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# Lukasz Majewski <lukma@denx.de>
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# SPDX-License-Identifier: Apache-2.0
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child-binding:
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description: Fixed link ethernet node
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properties:
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speed:
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type: int
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required: true
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description: The speed of fixed link
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enum:
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- 100
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- 10
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full-duplex:
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type: boolean
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required: false
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description: The fixed link operates in full duplex mode
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@@ -0,0 +1,33 @@
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# Copyright (c) 2021 IP-Logix Inc.
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# SPDX-License-Identifier: Apache-2.0
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# Common fields for MIIPHY devices
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description: Generic MII PHY
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compatible: "ethernet-phy"
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include: phy.yaml
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properties:
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address:
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type: int
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required: true
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description: PHY address
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mdio:
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type: phandle
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required: true
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description: MDIO driver node
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no-reset:
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type: boolean
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required: false
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description: Do not reset the PHY during initialization
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fixed-link:
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type: string
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required: false
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description: This link is fixed and does not require PHY configuration
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enum:
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- "10BASE-T Half-Duplex"
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- "10BASE-T Full-Duplex"
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- "100BASE-T Half-Duplex"
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- "100BASE-T Full-Duplex"
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@@ -0,0 +1,27 @@
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# Copyright (c) 2018, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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# Common fields for Ethernet devices
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include: base.yaml
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properties:
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local-mac-address:
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type: uint8-array
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required: false
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description: Specifies the MAC address that was assigned to the network device
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label:
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required: true
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zephyr,random-mac-address:
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type: boolean
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required: false
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description: |
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Use a random MAC address generated when the driver is initialized.
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Note that using this choice and rebooting a board may leave stale
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MAC address in peers' ARP caches and lead to issues and delays in
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communication. (Use "ip neigh flush all" on Linux peers to clear
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ARP cache.)
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It is driver specific how the OUI octets are handled.
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If set we ignore any setting of the local-mac-address property.
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@@ -0,0 +1,15 @@
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# Copyright (c) 2018 Intel Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: Intel E1000 Ethernet controller
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compatible: "intel,e1000"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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@@ -0,0 +1,15 @@
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# Copyright (c) 2019 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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description: LiteX Ethernet
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compatible: "litex,eth0"
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include: ethernet.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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@@ -0,0 +1,18 @@
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# Copyright (c) 2018, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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description: ENC28J60 standalone 10BASE-T Ethernet controller with SPI interface
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compatible: "microchip,enc28j60"
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include: [spi-device.yaml, ethernet.yaml]
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properties:
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int-gpios:
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type: phandle-array
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required: true
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description: Interrupt pin.
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The interrupt pin of ENC28J60 is active low.
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If connected directly the MCU pin should be configured
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as active low.
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@@ -0,0 +1,19 @@
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# Copyright (c) 2019, Phytec Messtechnik GmbH
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# SPDX-License-Identifier: Apache-2.0
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description: |
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ENC424J600 standalone 100BASE-T Ethernet controller with SPI interface
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compatible: "microchip,enc424j600"
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include: [spi-device.yaml, ethernet.yaml]
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properties:
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int-gpios:
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type: phandle-array
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required: true
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description: Interrupt pin.
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|
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The interrupt pin of ENC424J600 is active low.
|
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If connected directly the MCU pin should be configured
|
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as active low.
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@@ -0,0 +1,14 @@
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# Copyright (c) 2018, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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description: NXP Kinetis Ethernet
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compatible: "nxp,kinetis-ethernet"
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include: ["ethernet.yaml", "ethernet,fixed-link.yaml"]
|
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|
||||
properties:
|
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reg:
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required: true
|
||||
interrupts:
|
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required: true
|
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@@ -0,0 +1,12 @@
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# Copyright (c) 2018, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
|
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description: NXP Kinetis Ethernet PTP (Precision Time Protocol)
|
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|
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compatible: "nxp,kinetis-ptp"
|
||||
|
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include: base.yaml
|
||||
|
||||
properties:
|
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interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,6 @@
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# Copyright (c) 2021 IP-Logix Inc.
|
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# SPDX-License-Identifier: Apache-2.0
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|
||||
# Common fields for PHY devices
|
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|
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include: base.yaml
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||||
@@ -0,0 +1,101 @@
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# Copyright (c) 2019 Interay Solutions B.V.
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# Copyright (c) 2019 Oane Kingma
|
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# SPDX-License-Identifier: Apache-2.0
|
||||
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description: SiLabs Gecko Ethernet
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||||
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compatible: "silabs,gecko-ethernet"
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||||
|
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include: ethernet.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
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description: mmio register space
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|
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interrupts:
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required: true
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description: required interrupts
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||||
|
||||
# PHY address
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phy-address:
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type: int
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required: true
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description: address of the PHY on the MDIO bus
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|
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# RMII interface location
|
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location-rmii:
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type: int
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required: true
|
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description: location of RMII pins, configuration defined as <location>
|
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|
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# PHY management interface location
|
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location-mdio:
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type: int
|
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required: true
|
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description: location of MDC and MDIO pins, configuration defined as <location>
|
||||
|
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# PHY management pins
|
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location-phy_mdc:
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type: array
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required: true
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description: PHY MDC individual pin configuration defined as <location port pin>
|
||||
|
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location-phy_mdio:
|
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type: array
|
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required: true
|
||||
description: PHY MDIO individual pin configuration defined as <location port pin>
|
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|
||||
# RMII interface pins
|
||||
location-rmii_refclk:
|
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type: array
|
||||
required: true
|
||||
description: Reference clock individual pin configuration defined as <location port pin>
|
||||
|
||||
location-rmii_crs_dv:
|
||||
type: array
|
||||
required: true
|
||||
description: Receive data valid individual pin configuration defined as <location port pin>
|
||||
|
||||
location-rmii_txd0:
|
||||
type: array
|
||||
required: true
|
||||
description: Transmit data 0 individual pin configuration defined as <location port pin>
|
||||
|
||||
location-rmii_txd1:
|
||||
type: array
|
||||
required: true
|
||||
description: Transmit data 1 individual pin configuration defined as <location port pin>
|
||||
|
||||
location-rmii_tx_en:
|
||||
type: array
|
||||
required: true
|
||||
description: Transmit enable individual pin configuration defined as <location port pin>
|
||||
|
||||
location-rmii_rxd0:
|
||||
type: array
|
||||
required: true
|
||||
description: Receive data 0 individual pin configuration defined as <location port pin>
|
||||
|
||||
location-rmii_rxd1:
|
||||
type: array
|
||||
required: true
|
||||
description: Receive data 1 individual pin configuration defined as <location port pin>
|
||||
|
||||
location-rmii_rx_er:
|
||||
type: array
|
||||
required: true
|
||||
description: Receive error individual pin configuration defined as <location port pin>
|
||||
|
||||
# PHY control pins
|
||||
location-phy_pwr_enable:
|
||||
type: array
|
||||
description: PHY power enable individual pin configuration defined as <port pin>
|
||||
|
||||
location-phy_reset:
|
||||
type: array
|
||||
description: PHY reset individual pin configuration defined as <port pin>
|
||||
|
||||
location-phy_interrupt:
|
||||
type: array
|
||||
description: PHY interrupt individual pin configuration defined as <port pin>
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2018 Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: SMSC (now Microchip) LAN9220 Ethernet controller
|
||||
|
||||
compatible: "smsc,lan9220"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2021, BayLibre SAS
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Synopsys DesignWare Ethernet
|
||||
|
||||
compatible: "snps,designware-ethernet"
|
||||
|
||||
include: ethernet.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright (c) 2020, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ST STM32 Ethernet
|
||||
|
||||
compatible: "st,stm32-ethernet"
|
||||
|
||||
include: [ethernet.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
interrupts:
|
||||
required: true
|
||||
clocks:
|
||||
required: true
|
||||
clock-names:
|
||||
required: true
|
||||
pinctrl-0:
|
||||
required: true
|
||||
pinctrl-names:
|
||||
required: true
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2018 Zilogic Systems
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: TI Stellaris Ethernet
|
||||
|
||||
compatible: "ti,stellaris-ethernet"
|
||||
|
||||
include: ethernet.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,26 @@
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: W5500 standalone 10/100BASE-T Ethernet controller with SPI interface
|
||||
|
||||
compatible: "wiznet,w5500"
|
||||
|
||||
include: [spi-device.yaml, ethernet.yaml]
|
||||
|
||||
properties:
|
||||
int-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: Interrupt pin.
|
||||
|
||||
The interrupt pin of W5500 is active low.
|
||||
If connected directly the MCU pin should be configured
|
||||
as active low.
|
||||
reset-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: Reset pin.
|
||||
|
||||
The reset pin of W5500 is active low.
|
||||
If connected directly the MCU pin should be configured
|
||||
as active low.
|
||||
@@ -0,0 +1,378 @@
|
||||
#
|
||||
# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
description: Xilinx GEM Ethernet controller
|
||||
|
||||
compatible: "xlnx,gem"
|
||||
|
||||
include: ethernet.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clock-frequency:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Specifies the base clock frequency from which the GEM's TX clock
|
||||
frequency will be derived using two dividers in the respective GEM's
|
||||
clock control register in the CRL_APB. The GEM's TX clock frequency
|
||||
is determined by the current link speed reported by the PHY, to
|
||||
which it will be adjusted at run-time. Therefore, the value of this
|
||||
item must be set to the clock frequency of the PLL supplying the
|
||||
respective GEM's TX clock - by default, this is the IO PLL.
|
||||
|
||||
mdc-divider:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The MDC clock divider for the respective GEM. This is the divider
|
||||
applied to the LPD_LSBUS clock in order to derive MDIO interface
|
||||
clock driving communications with the attached PHY. Refer to the
|
||||
ZynqMP register documentation (ug1087), network_config (GEM) Register
|
||||
Description, bits [20:18] to determine the appropriate divider for
|
||||
the current target's LPD LSBUS clock frequency.
|
||||
|
||||
init-mdio-phy:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Activates the management of a PHY associated with the controller in-
|
||||
stance. If this parameter is activated at the board level, the de-
|
||||
fault values of the associated parameters mdio-phy-address, phy-poll-
|
||||
interval, link-speed and advertise-lower-link-speeds should be checked
|
||||
and overwritten at the board level if required.
|
||||
|
||||
mdio-phy-address:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The address on the MDIO bus of the PHY associated with the controller
|
||||
instance. Set the address to 0 for auto-detection (first responding
|
||||
PHY will be claimed by the driver, watch out in case of shared MDIO
|
||||
use), or to a fixed address between 1 and 32.
|
||||
|
||||
phy-poll-interval:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
PHY status polling interval in milliseconds for a driver instance
|
||||
managing an associated PHY.
|
||||
|
||||
link-speed:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Nominal link speed. If no PHY is managed by an instance of this driver,
|
||||
the respective controller will be configured to match the link speed
|
||||
specified here. If a PHY is managed by the driver, advertisement of
|
||||
the link speed specified here will be requested. If the optional pro-
|
||||
perty advertise-lower-link-speeds is set, advertisement of the link
|
||||
speed specified here plus any valid link speed below this value will
|
||||
be requested.
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
|
||||
advertise-lower-link-speeds:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Indicates to a driver instance which manages an associated PHY on
|
||||
the MDIO bus to include link speeds lower than the nominal value
|
||||
set in the link-speed property in the advertisement when requesting
|
||||
link speed auto-negotiation with a peer system.
|
||||
|
||||
handle-rx-in-isr:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Moves the handling of the frame received interrupt including the
|
||||
transfer of packet data from the DMA to network packet buffers and
|
||||
the subsequent propagation of the received packets to the network
|
||||
stack into the context of the ISR. Due to the unpredictability of
|
||||
the runtime of the ISR whenever large amounts of data are received,
|
||||
handling of the RX interrupt is normally deferred to the context
|
||||
of the system work queue.
|
||||
|
||||
handle-tx-in-workq:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Moves the handling of the frame transmission done interrupt into the
|
||||
context of the system work queue. By default, TX done handling is per-
|
||||
formed in the context of the ISR, as it only involves a limited number
|
||||
of memory accesses. This option CAN NOT be used if any component ex-
|
||||
ists within the current system setup that triggers the transmission
|
||||
of packets from within the context of the system work queue!
|
||||
|
||||
amba-ahb-dbus-width:
|
||||
type: int
|
||||
required: true
|
||||
description: AMBA AHB data bus width.
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
- 2
|
||||
|
||||
amba-ahb-burst-length:
|
||||
type: int
|
||||
required: true
|
||||
description: AMBA AHB burst length for DMA operations.
|
||||
enum:
|
||||
- 1
|
||||
- 4
|
||||
- 8
|
||||
- 16
|
||||
|
||||
hw-rx-buffer-size:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Hardware RX buffer size, scalable between 1 kB and 8 kB, where the full
|
||||
8 kB should be the default.
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
|
||||
hw-rx-buffer-offset:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Data offset in the hardware RX packet buffer (in bytes). Valid range is
|
||||
0-3 bytes.
|
||||
|
||||
hw-tx-buffer-size-full:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
When set, the hardware TX data buffer will make use of the full 4 kB
|
||||
that are available. If unset, the hardware TX data buffer will be
|
||||
limited to 2 kB.
|
||||
|
||||
rx-buffer-descriptors:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The number of descriptors to be allocated in the RX buffer descriptor
|
||||
ring. Must be <= 255.
|
||||
|
||||
rx-buffer-size:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The size of each receive data buffer, must be a multiple of 8, highest
|
||||
valid value is 16320, values less than 64 are not really useful.
|
||||
|
||||
tx-buffer-descriptors:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The number of descriptors to be allocated in the TX buffer descriptor
|
||||
ring. Must be <= 255.
|
||||
|
||||
tx-buffer-size:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
The size of each transmit data buffer, highest valid value is 16380,
|
||||
values less than 64 are not really useful.
|
||||
|
||||
ignore-ipg-rxer:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Ignore IPG rx_er. When set, rx_er has no
|
||||
effect on the GEM's operation when rx_dv is low. Set this when using
|
||||
the RGMII wrapper in half-duplex mode.
|
||||
|
||||
disable-reject-nsp:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Receive bad preamble. When set, frames with
|
||||
non-standard preamble will not be rejected.
|
||||
|
||||
ipg-stretch:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable IPG stretch. When set, the transmit
|
||||
IPG can be increased above 96 bit times depending on the previous
|
||||
frame length using the IPG stretch register.
|
||||
|
||||
sgmii-mode:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable SGMII mode. Changes the behaviour of
|
||||
the auto-negotiation advertisement and link partner ability registers
|
||||
to meet the requirements of SGMII and reduces the duration of the link
|
||||
timer from 10 ms to 1.6 ms.
|
||||
|
||||
disable-reject-fcs-crc-errors:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Disable rejection of FCS/CRC errors.
|
||||
When set, frames with FCS/CRC errors will not be rejected. FCS error
|
||||
statistics will still be collected for frames with bad FCS and FCS
|
||||
status will be recorded in the frame's DMA descriptor. This option
|
||||
should not be activated for normal operation.
|
||||
|
||||
rx-halfdup-while-tx:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable frames to be received in half-duplex
|
||||
mode while transmitting.
|
||||
|
||||
rx-checksum-offload:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable RX IP/TCP/UDP checksum offload to
|
||||
hardware. Frames with bad IP, TCP or UDP checksums will be discarded.
|
||||
This option is NOT supported by the QEMU implementation of the GEM!
|
||||
|
||||
tx-checksum-offload:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable TX IP/TCP/UDP checksum offload to
|
||||
hardware. This option is NOT supported by the QEMU implementation
|
||||
of the GEM!
|
||||
|
||||
disable-pause-copy:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Do not copy received pause frames to memory.
|
||||
Set this option in order to prevent valid pause frames from being
|
||||
copied to memory. When set, pause frames are not copied to memory
|
||||
regardless of the state of the copy all frames bit, whether a hash
|
||||
match is found or whether a type ID match is identified. If a desti-
|
||||
nation address match is found the pause frame will be copied to
|
||||
memory. Note that valid pause frames received will still increment
|
||||
pause statistics and pause the transmission of frames as required.
|
||||
|
||||
discard-rx-fcs:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Remove FCS of received frames.
|
||||
When set, received frames will be written to memory without their
|
||||
frame check sequence (last 4 bytes). The frame length indicated will
|
||||
be reduced by four bytes in this mode.
|
||||
|
||||
discard-rx-length-errors:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Discard frames with length field errors.
|
||||
When set, frames with a measured length shorter than the extracted
|
||||
length field (as indicated by bytes 13 and 14 in a non-VLAN tagged
|
||||
frame) will be discarded. This only applies to frames with a length
|
||||
field less than 0x0600.
|
||||
|
||||
pause-frame:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable pause. When set, transmission will
|
||||
pause if a non zero 802.3 classic pause frame is received and PFC
|
||||
has not been negotiated.
|
||||
|
||||
tbi:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable TBI. When set, the TBI interface is en-
|
||||
bled instead of the GMII/MII interface.
|
||||
|
||||
ext-address-match:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable external address match. When set, the
|
||||
external address match interface can be used to copy frames to memory.
|
||||
|
||||
long-frame-rx-support:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable reception of 1536 byte frames.
|
||||
Normally, the GEM rejects any frame above 1518 bytes.
|
||||
|
||||
unicast-hash:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable unicast hash. When set, unicast frames
|
||||
will be accepted when the 6 bit hash function of the destination
|
||||
address points to a bit that is set in the hash register.
|
||||
|
||||
multicast-hash:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable multicast hash. When set, mutlicast
|
||||
frames will be accepted when the 6 bit hash function of the desti-
|
||||
nation address points to a bit that is set in the hash register.
|
||||
|
||||
reject-broadcast:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Reject broadcast frames. When set, frames
|
||||
addressed to the all-ones broadcast address will be rejected.
|
||||
|
||||
promiscuous-mode:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable promiscuous mode. When set, all valid
|
||||
frames will be accepted.
|
||||
|
||||
discard-non-vlan:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Optional feature flag - Discard non-VLAN frames. When set,
|
||||
only VLAN tagged frames will be passed to the address matching logic.
|
||||
|
||||
full-duplex:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enables full duplex reception and transmission.
|
||||
|
||||
discard-rx-frame-ahb-unavail:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Discard received packets when no AHB resource
|
||||
is available.
|
||||
|
||||
ahb-packet-endian-swap:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable AHB packet data endianness swap to big
|
||||
endian. If this flag is not set, data will be little endian.
|
||||
|
||||
ahb-md-endian-swap:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Optional feature flag - Enable AHB management descriptor data endian-
|
||||
ness swap to big endian. If this flag is not set, data will be little
|
||||
endian.
|
||||
Reference in New Issue
Block a user