WIP: device tree MVP

dts/bindings/espi/espi-controller.yaml

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+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for ESPI devices
+
+include: base.yaml
+
+bus: espi
+
+properties:
+    label:
+      required: true

dts/bindings/espi/microchip,xec-espi-host-dev.yaml

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+# Copyright (c) 2021, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC eSPI Host devices
+
+compatible: "microchip,xec-espi-host-dev"
+
+include: [base.yaml]
+
+on-bus: espi
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    interrupt-names:
+      required: false
+
+    ldn:
+      type: int
+      required: true
+      description: logical device number
+
+    girqs:
+      type: array
+      required: false
+      description: array of GIRQ and bit positions
+
+    pcrs:
+      type: array
+      required: false
+      description: PCR sleep register index and bit position
+
+# optional properties application to different host facing devices
+    host-io:
+      type: int
+      required: false
+      description: |
+        Logical device Host I/O (x86) base. Refer to SoC documentation for the
+        number of I/O decoders implemented by a device (1 or 2) and the fixed
+        I/O masks.
+
+    host-io-addr-mask:
+      type: int
+      required: false
+      description: |
+        Host I/O address mask. This value is fixed for all HW and is only
+        used by Port80 BIOS debug alias device to specify the byte lane the
+        alias address is mapped to in the 80h to 83h I/O range.
+
+    host-mem:
+      type: int
+      required: false
+      description: |
+        Logical device Host memory (x86) base address. Refer to SoC
+        documentation for which logical devices implement a memory decoder
+        and the fixed memory address masking.
+
+    emi-mems:
+      type: array
+      required: false
+      description: |
+        Each EMI host device supports Host access to two SoC data memory
+        regions. Each region requires three configuration parameters:
+        Base address in the SoC data memory, read limit, and write limit.
+        If bits[14:2] of the address written by the Host to the EC address
+        register is less than the limit value the access is allowed. Bit[15]
+        of the EC address selects which of the two memory regions is accessed.
+
+    "emi-mem-cells":
+      type: int
+      const: 3
+
+    "#girq-cells":
+      type: int
+      const: 1
+
+    "#pcr-cells":
+      type: int
+      const: 2
+
+emi-mem-cells:
+    - base
+    - rdlimit
+    - wrlimit
+
+girq-cells:
+    - girqinfo
+
+pcr-cells:
+    - reg_idx
+    - bitpos

dts/bindings/espi/microchip,xec-espi-saf.yaml

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+# Copyright (c) 2019 Intel Corporation
+# Copyright (c) 2020 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip ESPI SAF controller
+
+compatible: "microchip,xec-espi-saf"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    io_girq:
+      type: int
+      description: soc group irq index for eSPI I/O
+      required: false
+
+    poll_timeout:
+      type: int
+      description: poll flash busy timeout in 32KHz periods
+      required: false
+
+    poll_interval:
+      type: int
+      description: interval between flash busy poll in 20 ns units
+      required: false
+
+    consec_rd_timeout:
+      type: int
+      description: timeout after last read to resume supended operations in 20 ns units
+      required: false
+
+    sus_chk_delay:
+      type: int
+      description: hold off poll after suspend in 20 ns units
+      required: false
+
+    sus_rsm_interval:
+      type: int
+      description: force suspended erase or program to resume in 32KHz periods
+      required: false

dts/bindings/espi/microchip,xec-espi-v2.yaml

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+# Copyright (c) 2019 Intel Corporation
+# Copyright (c) 2021 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip ESPI V2 controller
+
+compatible: "microchip,xec-espi-v2"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    reg-names:
+      required: true
+      description: Name of each register space
+
+    girqs:
+      type: array
+      required: true
+      description: |
+        Array of encoded interrupt information
+
+    pcrs:
+      type: array
+      required: true
+      description: eSPI PCR register index and bit position
+
+    "#girq-cells":
+      type: int
+      const: 1
+
+    "#pcr-cells":
+      type: int
+      const: 2
+
+girq-cells:
+    - girqinfo
+
+pcr-cells:
+    - regidx
+    - bitpos

dts/bindings/espi/microchip,xec-espi-vw-routing.yaml

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+# Copyright (c) 2021 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC eSPI Virtual Wire routing
+
+compatible: "microchip,xec-espi-vw-routing"
+
+child-binding:
+    description: |
+      Child node containing the routing of an eSPI virtual wire to the SoC
+      VW registers and ECIA GIRQ registers.
+    properties:
+       vw-reg:
+          type: array
+          required: true
+          description: vw signal's register index and vw bitmask.
+
+       vw-girq:
+        type: array
+        required: false
+        description: |
+            Routing of MSVW source to aggregated GIRQs
+
+            Example: OOB_RST_WARN is source 2 of MSVW01 routed to GIRQ24 b[5]
+               vw-girq = <24 5>;

dts/bindings/espi/microchip,xec-espi.yaml

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+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip ESPI controller
+
+compatible: "microchip,xec-espi"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    io_girq:
+      type: int
+      description: soc group irq index for eSPI I/O
+      required: true
+
+    vw_girqs:
+      type: array
+      description: soc group irq indexes for eSPI virtual wires channel
+      required: true
+
+    pc_girq:
+      type: int
+      description: soc group irq index for eSPI peripheral channel
+      required: true

dts/bindings/espi/nuvoton,npcx-espi-vw-conf.yaml

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+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton NPCX eSPI Virtual Wire (VW) mapping child node
+
+compatible: "nuvoton,npcx-espi-vw-conf"
+
+child-binding:
+    description: Child node to to present the mapping between VW signal, its core register and input source of MIWU
+    properties:
+       vw-reg:
+          type: array
+          required: true
+          description: vw signal's register index and vw bitmask.
+
+       vw-wui:
+        type: phandle
+        description: |
+            Mapping table between Wake-Up Input (WUI) and vw input signal.
+
+            For example the WUI mapping on NPCX7 for VW_SLP5 would be
+               vw-wui = <&wui_vw_slp_s5>;

dts/bindings/espi/nuvoton,npcx-espi.yaml

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+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-eSPI node
+
+compatible: "nuvoton,npcx-espi"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    clocks:
+        required: true
+        description: configurations of device source clock controller
+
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of pinmux controllers
+
+    espi-rst-wui:
+        type: phandle
+        required: true
+        description: |
+            Mapping table between Wake-Up Input (WUI) and ESPI_RST signal.
+
+            For example the WUI mapping on NPCX7 would be
+               espi-rst-wui = <&wui_cr_sin1>;

dts/bindings/espi/nuvoton,npcx-host-sub.yaml

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+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-Host Sub-Modules node
+
+compatible: "nuvoton,npcx-host-sub"
+
+include: [base.yaml]
+
+properties:
+    reg:
+      description: mmio register space
+      required: true
+
+    clocks:
+        required: true
+        description: configurations of device source clock controller
+
+    host-acc-wui:
+        type: phandle
+        required: true
+        description: |
+            Mapping table between Wake-Up Input (WUI) and any legacy host
+            access transactions.
+
+            For example the WUI mapping on NPCX7 would be
+               host-acc-wui = <&wui_host_acc>;

dts/bindings/espi/nuvoton,npcx-host-uart.yaml

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+# Copyright (c) 2020 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuvoton, NPCX-Host UART IO node
+
+compatible: "nuvoton,npcx-host-uart"
+
+include: [base.yaml]
+
+properties:
+    pinctrl-0:
+        type: phandles
+        required: true
+        description: configurations of host uart pinmux controllers

dts/bindings/espi/zephyr,espi-emul-controller.yaml

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+# Copyright 2020 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr eSPI Emulation controller
+
+compatible: "zephyr,espi-emul-controller"
+
+include: espi-controller.yaml
+
+properties:
+    reg:
+      required: true