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WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,18 @@
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# Copyright (c) 2021 Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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|
||||
description: Altera mSGDMA (Modular Scatter-Gather DMA)
|
||||
|
||||
compatible: "altr,msgdma"
|
||||
|
||||
include: dma-controller.yaml
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||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#dma-cells":
|
||||
const: 0
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||||
@@ -0,0 +1,45 @@
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# Copyright 2020 Broadcom
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# SPDX-License-Identifier: Apache-2.0
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||||
|
||||
description: |
|
||||
PL330 DMA Controller
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||||
|
||||
A phandle to the DMA controller plus "channel" integer cell specifying
|
||||
channel to be used for data transfer
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||||
|
||||
Example for pl330 DMA Controller
|
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pl330: pl330@48300000 {
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||||
compatible = "arm,dma-pl330";
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||||
...
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dma-channels = <8>;
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#dma-cells = <1>;
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||||
label = "PL330";
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||||
};
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||||
|
||||
If PCIe EP client uses channel 0 for Tx DMA and channel 1 for Rx DMA
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pcie0_ep: pcie@4e100000 {
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compatible = "brcm,iproc-pcie-ep";
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||||
...
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dmas = <&pl330 0>, <&pl330 1>;
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dma-names = "txdma", "rxdma";
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||||
label = "PCIE_0";
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||||
};
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||||
compatible: "arm,dma-pl330"
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||||
|
||||
include: dma-controller.yaml
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|
||||
properties:
|
||||
reg:
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||||
required: true
|
||||
microcode:
|
||||
type: array
|
||||
required: true
|
||||
description: microcode's physical memory address
|
||||
label:
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||||
required: true
|
||||
"#dma-cells":
|
||||
const: 1
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||||
|
||||
# Parameter syntax
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dma-cells:
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||||
- channel
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||||
@@ -0,0 +1,27 @@
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# Copyright (c) 2020, Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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||||
|
||||
description: Atmel SAM XDMAC controller
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compatible: "atmel,sam-xdmac"
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|
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include: dma-controller.yaml
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|
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properties:
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reg:
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required: true
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|
||||
interrupts:
|
||||
required: true
|
||||
|
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peripheral-id:
|
||||
type: int
|
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description: peripheral ID
|
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required: true
|
||||
|
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"#dma-cells":
|
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const: 2
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|
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dma-cells:
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- channel
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- perid
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@@ -0,0 +1,39 @@
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description: Atmel SAM0 DMA controller
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|
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compatible: "atmel,sam0-dmac"
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|
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include: dma-controller.yaml
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|
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properties:
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reg:
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required: true
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|
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interrupts:
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required: true
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|
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"#dma-cells":
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const: 2
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# #dma-cells : Must be <2>.
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# The 1st cell specifies the DMAC channel to be used for the data transfer.
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# This channel should be unique between all peripherals that are using the
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# DMAC instance.
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# The 2nd cell defines the peripheral trigger which is the source of the transfer.
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# For details on trigger selection and trigger modes, refer to
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# "Transfer Triggers and Actions".
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# See the SoC's reference manual for all the supported request sources.
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#
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# Example of devicetree dma channel configuration:
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#
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# &sercom3 {
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# /* Configure DMA channels for async operation */
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# dmas = <&dmac 10 7>, <&dmac 11 8>;
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# dma-names = "rx", "tx";
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# };
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#
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# In above fragment 10 and 11 represents the different channels used to
|
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# transfer data between peripheral and ram. The numbers 7/8 are, for instance,
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# uart_rx/tx peripheral trigger for sercom3.
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dma-cells:
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- channel
|
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- trigsrc
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@@ -0,0 +1,38 @@
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# Copyright 2020 Broadcom
|
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# SPDX-License-Identifier: Apache-2.0
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description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 1
|
||||
|
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include: dma-controller.yaml
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|
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compatible: brcm,iproc-pax-dma-v1
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|
||||
properties:
|
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reg:
|
||||
description: |
|
||||
Register space for the memory mapped PAX DMA controller registers,
|
||||
It includes data mover engine(dme), ring manager, ring manager common
|
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registers.
|
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required: true
|
||||
label:
|
||||
required: true
|
||||
bd-memory:
|
||||
type: array
|
||||
description: Uncached memory address to populate dma buffer descriptors
|
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required: true
|
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scr-addr-loc:
|
||||
type: int
|
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description: Location where address of the scratch buffer host has populated
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required: true
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scr-size-loc:
|
||||
type: int
|
||||
description: Location where size of the scratch buffer host has populated
|
||||
required: true
|
||||
interrupts:
|
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type: array
|
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description: Ring manager line interrupt number
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required: false
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pcie-ep:
|
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type: phandle
|
||||
description: Pcie endpoint handle
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required: true
|
||||
@@ -0,0 +1,38 @@
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# Copyright 2020 Broadcom
|
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# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 2
|
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|
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include: dma-controller.yaml
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|
||||
compatible: brcm,iproc-pax-dma-v2
|
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|
||||
properties:
|
||||
reg:
|
||||
description: |
|
||||
Register space for the memory mapped PAX DMA controller registers,
|
||||
It includes data mover engine(dme), ring manager, ring manager common
|
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registers.
|
||||
required: true
|
||||
label:
|
||||
required: true
|
||||
bd-memory:
|
||||
type: array
|
||||
description: Uncached memory address to populate dma buffer descriptors
|
||||
required: true
|
||||
scr-addr-loc:
|
||||
type: int
|
||||
description: Location where address of the scratch buffer host has populated
|
||||
required: true
|
||||
scr-size-loc:
|
||||
type: int
|
||||
description: Location where size of the scratch buffer host has populated
|
||||
required: true
|
||||
interrupts:
|
||||
type: array
|
||||
description: Ring manager line interrupt number
|
||||
required: false
|
||||
pcie-ep:
|
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type: phandle
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||||
description: Pcie endpoint handle
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||||
required: true
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||||
@@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
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||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for DMA controllers
|
||||
|
||||
include: base.yaml
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||||
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||||
bus: dma
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||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#dma-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a DMA specifier
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||||
|
||||
dma-channel-mask:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
Bitmask of available DMA channels in ascending order that are
|
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not reserved by firmware and are available to the
|
||||
kernel. i.e. first channel corresponds to LSB.
|
||||
|
||||
dma-channels:
|
||||
type: int
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||||
required: false
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description: Number of DMA channels supported by the controller
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||||
|
||||
dma-requests:
|
||||
type: int
|
||||
required: false
|
||||
description: Number of DMA request signals supported by the controller.
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||||
@@ -0,0 +1,34 @@
|
||||
# Copyright (c) 2019, STMicroelectronics
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||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for DMAMUX controllers
|
||||
|
||||
include: base.yaml
|
||||
|
||||
bus: dmamux
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#dma-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a DMA specifier (see dma V2)
|
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|
||||
dma-channels:
|
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type: int
|
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required: true
|
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description: Number of DMAMUX output request channels supported by the controller
|
||||
|
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dma-generators:
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type: int
|
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required: false
|
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description: Number of DMAMUX Request generator supported by the controller
|
||||
|
||||
dma-requests:
|
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type: int
|
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required: true
|
||||
description: |
|
||||
Number of DMAMUX Peripheral Request Line inputs supported by the controller
|
||||
This is not directly the value to program in the DMAREQ_ID of the DMAMUX_CxCR
|
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@@ -0,0 +1,29 @@
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# Copyright (c) 2020, NXP
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# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP LPC DMA controller
|
||||
|
||||
compatible: "nxp,lpc-dma"
|
||||
|
||||
include: dma-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
dma-channels:
|
||||
required: true
|
||||
|
||||
"#dma-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a DMA specifier
|
||||
|
||||
#- #dma-cells : Must be <1>.
|
||||
# channel: the dma channel, each channel supports one DMA request line
|
||||
|
||||
dma-cells:
|
||||
- channel
|
||||
@@ -0,0 +1,54 @@
|
||||
# Copyright (c) 2020, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP MCUX EDMA controller
|
||||
|
||||
compatible: "nxp,mcux-edma"
|
||||
|
||||
include: dma-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
dma-channels:
|
||||
required: true
|
||||
|
||||
dma-requests:
|
||||
required: true
|
||||
|
||||
nxp,mem2mem:
|
||||
type: boolean
|
||||
description: If the DMA controller supports memory to memory transfer
|
||||
|
||||
nxp,a_on:
|
||||
type: boolean
|
||||
description: If the DMA controller supports always on
|
||||
|
||||
"#dma-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a DMAMUX specifier
|
||||
|
||||
# Parameter syntax of NXP follows the dmamux client dts syntax
|
||||
# in the Linux kernel declared in
|
||||
# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/tree/Bindings/dma/fsl-edma.txt
|
||||
#
|
||||
#- #dma-cells : Must be <2>.
|
||||
# The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
|
||||
# Specific request source can only be multiplexed by specific channels
|
||||
# group called DMAMUX.
|
||||
# The 2nd cell specifies the request source(slot) ID.
|
||||
# See the SoC's reference manual for all the supported request sources.
|
||||
# * DMA clients
|
||||
# DMA client drivers that uses the DMA function must use the format described
|
||||
# in the dma.txt file, using a two-cell specifier for each channel: the 1st
|
||||
# specifies the channel group(DMAMUX) in which this request can be multiplexed,
|
||||
# and the 2nd specifies the request source.
|
||||
|
||||
dma-cells:
|
||||
- mux
|
||||
- source
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2019 Intel Corporation. All rights reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Synopsys Designware DMA Controller node
|
||||
|
||||
compatible: "snps,designware-dma"
|
||||
|
||||
include: dma-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#dma-cells":
|
||||
const: 1
|
||||
|
||||
dma-cells:
|
||||
- channel
|
||||
@@ -0,0 +1,90 @@
|
||||
# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
STM32 DMA controller (V1)
|
||||
|
||||
It is present on stm32 devices like stm32F4 or stm32F2.
|
||||
This DMA controller includes FIFO control registers.
|
||||
DMA clients connected to the STM32 DMA controller must use the format
|
||||
described in the dma.txt file, using a four-cell specifier for each
|
||||
channel: a phandle to the DMA controller plus the following four integer cells:
|
||||
1. channel: the dma stream from 0 to <dma-requests>
|
||||
2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
|
||||
this value is 0 for Memory-to-memory transfers
|
||||
or a value between <1> .. <dma-generators> (not supported yet)
|
||||
or a value beweeen <dma-generators>+1 .. <dma-generators>+<dma-requests>
|
||||
3. channel-config: A 32bit mask specifying the DMA channel configuration
|
||||
which is device dependent:
|
||||
-bit 6-7 : Direction (see dma.h)
|
||||
0x0: MEM to MEM
|
||||
0x1: MEM to PERIPH
|
||||
0x2: PERIPH to MEM
|
||||
0x3: reserved for PERIPH to PERIPH
|
||||
-bit 9 : Peripheral Increment Address
|
||||
0x0: no address increment between transfers
|
||||
0x1: increment address between transfers
|
||||
-bit 10 : Memory Increment Address
|
||||
0x0: no address increment between transfers
|
||||
0x1: increment address between transfers
|
||||
-bit 11-12 : Peripheral data size
|
||||
0x0: Byte (8 bits)
|
||||
0x1: Half-word (16 bits)
|
||||
0x2: Word (32 bits)
|
||||
0x3: reserved
|
||||
-bit 13-14 : Memory data size
|
||||
0x0: Byte (8 bits)
|
||||
0x1: Half-word (16 bits)
|
||||
0x2: Word (32 bits)
|
||||
0x3: reserved
|
||||
-bit 15: Peripheral Increment Offset Size
|
||||
0x0: offset size is linked to the peripheral bus width
|
||||
0x1: offset size is fixed to 4 (32-bit alignment)
|
||||
-bit 16-17 : Priority level
|
||||
0x0: low
|
||||
0x1: medium
|
||||
0x2: high
|
||||
0x3: very high
|
||||
4. features: A 32bit bitfield value specifying DMA features
|
||||
-bit 0-1: DMA FIFO threshold selection
|
||||
0x0: 1/4 full FIFO
|
||||
0x1: 1/2 full FIFO
|
||||
0x2: 3/4 full FIFO
|
||||
0x3: full FIFO
|
||||
|
||||
examples for stm32f411
|
||||
dma2: dma-controller@40020400 {
|
||||
compatible = "st,stm32-dma-v1";
|
||||
...
|
||||
st,mem2mem;
|
||||
dma-requests = <7>;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
|
||||
For the client part, example for stm32f411 on DMA2 instance
|
||||
Tx using stream 5 on channel 3 (stream 2 on channel 2 is also possible)
|
||||
Rx using stream 2 on channel 3 (stream 0 on channel 3 is also possible)
|
||||
spi1 {
|
||||
dmas = <&dma2 5 3 0x28440 0x03>,
|
||||
<&dma2 2 3 0x28480 0x03>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
compatible: "st,stm32-dma-v1"
|
||||
|
||||
include: st,stm32-dma.yaml
|
||||
|
||||
properties:
|
||||
"#dma-cells":
|
||||
const: 4
|
||||
|
||||
# Parameter syntax of stm32 follows the dma client dts syntax
|
||||
# in the Linux kernel declared in
|
||||
# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
|
||||
|
||||
dma-cells:
|
||||
- channel
|
||||
- slot
|
||||
- channel-config
|
||||
- features
|
||||
@@ -0,0 +1,83 @@
|
||||
# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
STM32 DMA controller (V2)
|
||||
|
||||
It is present on stm32 devices like stm32L4 or stm32WB.
|
||||
This DMA controller includes several channels with different requests.
|
||||
DMA clients connected to the STM32 DMA controller must use the format
|
||||
described in the dma.txt file, using a four-cell specifier for each
|
||||
capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
|
||||
DMA clients connected to the STM32 DMA controller must use the format
|
||||
described in the dma.txt file, using a 3-cell specifier for each
|
||||
channel: a phandle to the DMA controller plus the following four integer cells:
|
||||
1. channel: the dma stream from 1 to <dma-requests>
|
||||
2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
|
||||
this value is 0 for Memory-to-memory transfers
|
||||
or a value between <1> .. <dma-generators> (not supported yet)
|
||||
or a value beweeen <dma-generators>+1 .. <dma-generators>+<dma-requests>
|
||||
3. channel-config: A 32bit mask specifying the DMA channel configuration
|
||||
which is device dependent:
|
||||
-bit 6-7 : Direction (see dma.h)
|
||||
0x0: MEM to MEM
|
||||
0x1: MEM to PERIPH
|
||||
0x2: PERIPH to MEM
|
||||
0x3: reserved for PERIPH to PERIPH
|
||||
-bit 9 : Peripheral Increment Address
|
||||
0x0: no address increment between transfers
|
||||
0x1: increment address between transfers
|
||||
-bit 10 : Memory Increment Address
|
||||
0x0: no address increment between transfers
|
||||
0x1: increment address between transfers
|
||||
-bit 11-12 : Peripheral data size
|
||||
0x0: Byte (8 bits)
|
||||
0x1: Half-word (16 bits)
|
||||
0x2: Word (32 bits)
|
||||
0x3: reserved
|
||||
-bit 13-14 : Memory data size
|
||||
0x0: Byte (8 bits)
|
||||
0x1: Half-word (16 bits)
|
||||
0x2: Word (32 bits)
|
||||
0x3: reserved
|
||||
-bit 15: Reserved
|
||||
-bit 16-17 : Priority level
|
||||
0x0: low
|
||||
0x1: medium
|
||||
0x2: high
|
||||
0x3: very high
|
||||
Example of dma node for stm32wb55x
|
||||
dma2: dma-controller@40020400 {
|
||||
compatible = "st,stm32-dma-v2";
|
||||
...
|
||||
dma-requests = <7>;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
|
||||
For the client part, example for stm32l476 on DMA1 instance
|
||||
Tx using channel 3 with request 1
|
||||
Rx using channel 2 with request 1
|
||||
spi1 {
|
||||
compatible = "st,stm32-spi";
|
||||
dmas = <&dma1 3 1 0x20440>,
|
||||
<&dma1 2 1 0x20480>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
compatible: "st,stm32-dma-v2"
|
||||
|
||||
include: st,stm32-dma.yaml
|
||||
|
||||
properties:
|
||||
"#dma-cells":
|
||||
const: 3
|
||||
|
||||
# Parameter syntax of stm32 follows the dma client dts syntax
|
||||
# in the Linux kernel declared in
|
||||
# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
|
||||
|
||||
dma-cells:
|
||||
- channel
|
||||
- slot
|
||||
- channel-config
|
||||
@@ -0,0 +1,77 @@
|
||||
# Copyright (c) 2021, STMicroelectronics
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
|
||||
|
||||
This DMA controller includes several channels with different requests.
|
||||
All the requests ar ORed before entering the DMA, so that only one request
|
||||
must be enabled at a time.
|
||||
DMA clients connected to the STM32 DMA controller must use the format
|
||||
described in the dma.txt file, using a 2-cell specifier for each
|
||||
channel: a phandle to the DMA controller plus the following four integer cells:
|
||||
1. channel: the dma stream from 1 to <dma-requests>
|
||||
2. channel-config: A 32bit mask specifying the DMA channel configuration
|
||||
which is device dependent:
|
||||
-bit 6-7 : Direction (see dma.h)
|
||||
0x0: MEM to MEM
|
||||
0x1: MEM to PERIPH
|
||||
0x2: PERIPH to MEM
|
||||
0x3: reserved for PERIPH to PERIPH
|
||||
-bit 9 : Peripheral Increment Address
|
||||
0x0: no address increment between transfers
|
||||
0x1: increment address between transfers
|
||||
-bit 10 : Memory Increment Address
|
||||
0x0: no address increment between transfers
|
||||
0x1: increment address between transfers
|
||||
-bit 11-12 : Peripheral data size
|
||||
0x0: Byte (8 bits)
|
||||
0x1: Half-word (16 bits)
|
||||
0x2: Word (32 bits)
|
||||
0x3: reserved
|
||||
-bit 13-14 : Memory data size
|
||||
0x0: Byte (8 bits)
|
||||
0x1: Half-word (16 bits)
|
||||
0x2: Word (32 bits)
|
||||
0x3: reserved
|
||||
-bit 15: Reserved
|
||||
-bit 16-17 : Priority level
|
||||
0x0: low
|
||||
0x1: medium
|
||||
0x2: high
|
||||
0x3: very high
|
||||
Example of dma node for stm32f103
|
||||
dma1: dma-controller@40020400 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
...
|
||||
dma-requests = <7>;
|
||||
status = "disabled";
|
||||
label = "DMA_1";
|
||||
};
|
||||
|
||||
For the client part, example for stm32f103 on DMA1 instance
|
||||
Tx using channel 3
|
||||
Rx using channel 2
|
||||
spi1 {
|
||||
compatible = "st,stm32-spi";
|
||||
dmas = <&dma1 3 0x20440>,
|
||||
<&dma1 2 0x20480>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
compatible: "st,stm32-dma-v2bis"
|
||||
|
||||
include:
|
||||
- name: st,stm32-dma.yaml
|
||||
|
||||
properties:
|
||||
"#dma-cells":
|
||||
const: 2
|
||||
|
||||
# Parameter syntax of stm32 follows the dma client dts syntax
|
||||
# in the Linux kernel declared in
|
||||
# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
|
||||
|
||||
dma-cells:
|
||||
- channel
|
||||
- channel-config
|
||||
@@ -0,0 +1,38 @@
|
||||
# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
STM32 DMA controller
|
||||
|
||||
The STM32 DMA is a general-purpose direct memory access controller
|
||||
capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
|
||||
Each stm32 soc with a DMA is of a special version type, which could be
|
||||
V1 like stm32F4 or stm32F2 socs, they include FIFO control registers
|
||||
or V2 like stm32L4 soc or stm322WB, some also have DMAMUX controller
|
||||
or V2bis like stm32F1 or stm32L1, where requests are multiplexed
|
||||
|
||||
compatible: "st,stm32-dma"
|
||||
|
||||
include: dma-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
st,mem2mem:
|
||||
type: boolean
|
||||
required: false
|
||||
description: If the DMA controller V1 supports memory to memory transfer
|
||||
|
||||
dma-offset:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
offset in the table of channels when mapping to a DMAMUX
|
||||
for 1st dma instance, offset is 0,
|
||||
for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
|
||||
for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
|
||||
plus the nb of dma channels of the 1st dma instance, etc.
|
||||
@@ -0,0 +1,83 @@
|
||||
# Copyright (c) 2019, STMicroelectronics
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
STM32 DMAMUX controller
|
||||
|
||||
The STM32 DMAMUX is a direct memory access multiplexer
|
||||
capable of supporting independent DMA channels.
|
||||
DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
|
||||
for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
|
||||
1. channel: the mux channel from 0 to <dma-channels> - 1
|
||||
2. slot: the request line Multiplexer ID
|
||||
3. channel-config: A 32bit mask specifying the DMA channel configuration
|
||||
which is device dependent:
|
||||
-bit 6-7 : Direction (see dma.h)
|
||||
0x0: MEM to MEM
|
||||
0x1: MEM to PERIPH
|
||||
0x2: PERIPH to MEM
|
||||
0x3: reserved for PERIPH to PERIPH
|
||||
-bit 9 : Peripheral Increment Address
|
||||
0x0: no address increment between transfers
|
||||
0x1: increment address between transfers
|
||||
-bit 10 : Memory Increment Address
|
||||
0x0: no address increment between transfers
|
||||
0x1: increment address between transfers
|
||||
-bit 11-12 : Peripheral data size
|
||||
0x0: Byte (8 bits)
|
||||
0x1: Half-word (16 bits)
|
||||
0x2: Word (32 bits)
|
||||
0x3: reserved
|
||||
-bit 13-14 : Memory data size
|
||||
0x0: Byte (8 bits)
|
||||
0x1: Half-word (16 bits)
|
||||
0x2: Word (32 bits)
|
||||
0x3: reserved
|
||||
-bit 15: Peripheral Increment Offset Size not USED for DMA V2
|
||||
0x0: offset size is linked to the peripheral bus width
|
||||
0x1: offset size is fixed to 4 (32-bit alignment)
|
||||
-bit 16-17 : Priority level
|
||||
0x0: low
|
||||
0x1: medium
|
||||
0x2: high
|
||||
0x3: very high
|
||||
exemple for stm32wb55x
|
||||
dmamux1: dmamux@40020800 {
|
||||
compatible = "st,stm32-dmamux";
|
||||
...
|
||||
dma-channels = <14>;
|
||||
dma-generators = <4>;
|
||||
dma-requests= <36>;
|
||||
status = "disabled";
|
||||
label = "DMAMUX_1";
|
||||
};
|
||||
for client SPI of stm32wb55x
|
||||
spi1: spi@40013000 {
|
||||
compatible = "st,stm32-spi";
|
||||
dmas = <&dmamux1 11 7 0x20440
|
||||
&dmamux1 1 6 0x20480>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
compatible: "st,stm32-dmamux"
|
||||
|
||||
include: dmamux-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#dma-cells":
|
||||
const: 3
|
||||
|
||||
# Parameter syntax of stm32 follows the dma client dts syntax
|
||||
# in the Linux kernel declared in
|
||||
# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dmamux.yaml
|
||||
|
||||
dma-cells:
|
||||
- channel
|
||||
- slot
|
||||
- channel-config
|
||||
Reference in New Issue
Block a user