WIP: device tree MVP

2026-11-12 20:21:36 +08:00 · 2022-01-06 17:20:17 -05:00
parent 07d75d85cf
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+# Copyright (c) 2021 Nordic Semiconductor ASA
+# Common fields for display controllers
+
+include: base.yaml
+
+properties:
+    height:
+      type: int
+      required: true
+      description: |
+        Height of the panel driven by the controller, with the units in pixels.
+
+    width:
+      type: int
+      required: true
+      description: |
+        Width of the panel driven by the controller, with the units in pixels.
+
+    label:
+      required: true
@@ -0,0 +1,18 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP i.MX eLCDIF (Enhanced LCD Interface) controller
+
+compatible: "fsl,imx6sx-lcdif"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    label:
+      required: true
@@ -0,0 +1,107 @@
+# Copyright (c) 2020 Hubert Miś <hubert.mis@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: FTDI FT800 graphic controller
+
+compatible: "ftdi,ft800"
+
+include: spi-device.yaml
+
+properties:
+    irq-gpios:
+      type: phandle-array
+      required: false
+      description: Optional IRQ line of FT800 controller
+
+    pclk:
+      type: int
+      required: true
+      description: |
+        The value to divide the main clock by for PCLK. If the
+        typical main clock was 48MHz and this value is 5, the PCLK
+        will be 9.6 MHz. Must be positive value to enable the screen
+
+    pclk_pol:
+      type: int
+      required: true
+      description: |
+        Polarity of PCLK. If it is set to zero, PCLK polarity is on
+        the rising edge. If it is set to one, PCLK polarity is on
+        the falling edge.
+
+    cspread:
+      type: int
+      required: true
+      description: |
+        Controls the transition of RGB signals with PCLK active clock
+        edge. When set to 0, R[7:2],G[7:2] and B[7:2] signals change
+        following the active edge of PCLK. When set to 1, R[7:2]
+        changes a PCLK clock early and B[7:2] a PCLK clock later,
+        which helps reduce the system noise.
+
+    swizzle:
+      type: int
+      required: true
+      description: |
+        Controls the arrangement of output RGB pins, which may help
+        support different LCD panel. Please check FT800 Programmers
+        Guide for details.
+
+    vsize:
+      type: int
+      required: true
+      description: Number of visible lines of pixels in one frame
+
+    voffset:
+      type: int
+      required: true
+      description: Number of invisible lines at the beginning of a new frame
+
+    vcycle:
+      type: int
+      required: true
+      description: |
+        Number of all lines in a frame. It includes all visible and
+        invisible lines at the beginning and at the end of a frame.
+
+    vsync0:
+      type: int
+      required: true
+      description: |
+        Number of lines for the high state of signal VSYNC at
+        the start of new frame.
+
+    vsync1:
+      type: int
+      required: true
+      description: |
+        Number of lines for signal VSYNC toggle takes at the start
+        of new frame.
+
+    hsize:
+      type: int
+      required: true
+      description: Number of PCLK cycles per visible part of horizontal line
+
+    hoffset:
+      type: int
+      required: true
+      description: |
+        Number of PCLK cycles before pixels are scanned out for
+        given line
+
+    hcycle:
+      type: int
+      required: true
+      description: Number of total PCLK cycles per horizontal line scan.
+
+    hsync0:
+      type: int
+      required: true
+      description: Number of PCLK cycles of HSYNC high state during start of
+        line
+
+    hsync1:
+      type: int
+      required: true
+      description: Number of PCLK cycles for HSYNC toggle during start of line.
@@ -0,0 +1,56 @@
+# Copyright (c) 2020, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: GD7965 EPD display controller
+
+compatible: "gooddisplay,gd7965"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: RESET pin.
+
+        The RESET pin of GD7965 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    dc-gpios:
+      type: phandle-array
+      required: true
+      description: DC pin.
+
+        The DC pin of GD7965 is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    busy-gpios:
+      type: phandle-array
+      required: true
+      description: BUSY pin.
+
+        The BUSY pin of GD7965 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    pwr:
+      type: uint8-array
+      required: true
+      description: Power Setting (PWR) values
+
+    softstart:
+      type: uint8-array
+      required: true
+      description: Booster Soft Start (BTST) values
+
+    cdi:
+      type: int
+      required: true
+      description: VCOM and data interval value
+
+    tcon:
+      type: int
+      required: true
+      description: TCON setting value
@@ -0,0 +1,97 @@
+# Copyright (c) 2018, Jan Van Winkel <jan.van_winkel@dxplore.eu>
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ILI9340 320x240 display controller
+
+compatible: "ilitek,ili9340"
+
+include: ilitek,ili9xxx-common.yaml
+
+properties:
+    gamset:
+      type: uint8-array
+      default: [0x01]
+      description:
+        Gamma set (GAMSET) register value.
+
+    frmctr1:
+      type: uint8-array
+      default: [0x00, 0x1b]
+      description:
+        Frame rate control (in normal mode / full colors) (FRMCTR1) register value.
+
+    disctrl:
+      type: uint8-array
+      default: [0x0a, 0x82, 0x27]
+      description:
+        Display function control (DISCTRL) register value. Note that changing
+        default SS bit value (0) may interfere with display rotation.
+
+    pwctrl1:
+      type: uint8-array
+      default: [0x26, 0x00]
+      description:
+        Power control 1 (PWCTRL1) register values.
+
+    pwctrl2:
+      type: uint8-array
+      default: [0x00]
+      description:
+        Power control 2 (PWCTRL2) register values.
+
+    vmctrl1:
+      type: uint8-array
+      default: [0x31, 0x3c]
+      description:
+        VCOM control 1 (VMCTRL1) register values.
+
+    vmctrl2:
+      type: uint8-array
+      default: [0xc0]
+      description:
+        VCOM control 2 (VMCTRL2) register values.
+
+    pgamctrl:
+      type: uint8-array
+      default: [
+        0x0f,
+        0x22,
+        0x1f,
+        0x0a,
+        0x0e,
+        0x06,
+        0x4d,
+        0x76,
+        0x3b,
+        0x03,
+        0x0e,
+        0x04,
+        0x13,
+        0x0e,
+        0x0c
+      ]
+      description:
+        Positive gamma correction (PGAMCTRL) register values.
+
+    ngamctrl:
+      type: uint8-array
+      default: [
+        0x0c,
+        0x23,
+        0x26,
+        0x04,
+        0x10,
+        0x04,
+        0x39,
+        0x24,
+        0x4b,
+        0x03,
+        0x0b,
+        0x0b,
+        0x33,
+        0x37,
+        0x0f
+      ]
+      description:
+        Negative gamma correction (NGAMCTRL) register values.
@@ -0,0 +1,146 @@
+# Copyright (c) 2018, Jan Van Winkel <jan.van_winkel@dxplore.eu>
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# Copyright (c) 2021, Krivorot Oleg <krivorot.oleg@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ILI9341 320x240 display controller
+
+compatible: "ilitek,ili9341"
+
+include: ilitek,ili9xxx-common.yaml
+
+properties:
+    pwctrla:
+      type: uint8-array
+      default: [0x39, 0x2c, 0x00, 0x34, 0x02]
+      description:
+        Power control A (PWCTRLA) register value.
+
+    pwctrlb:
+      type: uint8-array
+      default: [0x00, 0x8b, 0x30]
+      description:
+        Power control B (PWCTRLB) register value.
+
+    pwseqctrl:
+      type: uint8-array
+      default: [0x55, 0x01, 0x23, 0x01]
+      description:
+        Power on sequence control (PWSEQCTRL) register value.
+
+    timctrla:
+      type: uint8-array
+      default: [0x84, 0x11, 0x7a]
+      description:
+        Driver timing control A (TIMCTRLA) register value.
+
+    timctrlb:
+      type: uint8-array
+      default: [0x00, 0x00]
+      description:
+        Driver timing control B (TIMCTRLB) register value.
+
+    pumpratioctrl:
+      type: uint8-array
+      default: [0x10]
+      description:
+        Pump ratio control (PUMPRATIOCTRL) register value.
+
+    enable3g:
+      type: uint8-array
+      default: [0x02]
+      description:
+        Enable 3G (ENABLE3G) register value.
+
+    etmod:
+      type: uint8-array
+      default: [ 0x06 ]
+      description:
+        Entry Mode Set (ETMOD) register value.
+
+    gamset:
+      type: uint8-array
+      default: [0x01]
+      description:
+        Gamma set (GAMSET) register value.
+
+    frmctr1:
+      type: uint8-array
+      default: [0x00, 0x1b]
+      description:
+        Frame rate control (in normal mode / full colors) (FRMCTR1) register value.
+
+    disctrl:
+      type: uint8-array
+      default: [0x0a, 0x82, 0x27]
+      description:
+        Display function control (DISCTRL) register value. Note that changing
+        default SS bit value (0) may interfere with display rotation.
+
+    pwctrl1:
+      type: uint8-array
+      default: [0x21]
+      description:
+        Power control 1 (PWCTRL1) register values.
+
+    pwctrl2:
+      type: uint8-array
+      default: [0x10]
+      description:
+        Power control 2 (PWCTRL2) register values.
+
+    vmctrl1:
+      type: uint8-array
+      default: [0x31, 0x3c]
+      description:
+        VCOM control 1 (VMCTRL1) register values.
+
+    vmctrl2:
+      type: uint8-array
+      default: [0xc0]
+      description:
+        VCOM control 2 (VMCTRL2) register values.
+
+    pgamctrl:
+      type: uint8-array
+      default: [
+        0x0f,
+        0x22,
+        0x1f,
+        0x0a,
+        0x0e,
+        0x06,
+        0x4d,
+        0x76,
+        0x3b,
+        0x03,
+        0x0e,
+        0x04,
+        0x13,
+        0x0e,
+        0x0c
+      ]
+      description:
+        Positive gamma correction (PGAMCTRL) register values.
+
+    ngamctrl:
+      type: uint8-array
+      default: [
+        0x0c,
+        0x23,
+        0x26,
+        0x04,
+        0x10,
+        0x04,
+        0x39,
+        0x24,
+        0x4b,
+        0x03,
+        0x0b,
+        0x0b,
+        0x33,
+        0x37,
+        0x0f
+      ]
+      description:
+        Negative gamma correction (NGAMCTRL) register values.
@@ -0,0 +1,84 @@
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ILI9488 320x480 display controller
+
+compatible: "ilitek,ili9488"
+
+include: ilitek,ili9xxx-common.yaml
+
+properties:
+    frmctr1:
+      type: uint8-array
+      default: [0xb0, 0x11]
+      description:
+        Frame rate control (in normal mode / full colors) (FRMCTR1) register value.
+
+    disctrl:
+      type: uint8-array
+      default: [0x02, 0x02, 0x3b]
+      description:
+        Display function control (DISCTRL) register value. Note that changing
+        default SS bit value (0) may interfere with display rotation.
+
+    pwctrl1:
+      type: uint8-array
+      default: [0x0e, 0x0e]
+      description:
+        Power control 1 (PWCTRL1) register values.
+
+    pwctrl2:
+      type: uint8-array
+      default: [0x43]
+      description:
+        Power control 2 (PWCTRL2) register values.
+
+    vmctrl:
+      type: uint8-array
+      default: [0x00, 0x40, 0x00, 0x40]
+      description:
+        VCOM control (VMCTRL) register values.
+
+    pgamctrl:
+      type: uint8-array
+      default: [
+        0x0f,
+        0x1f,
+        0x1c,
+        0x0b,
+        0x0e,
+        0x09,
+        0x48,
+        0x99,
+        0x38,
+        0x0a,
+        0x14,
+        0x06,
+        0x11,
+        0x09,
+        0x00
+      ]
+      description:
+        Positive gamma correction (PGAMCTRL) register values.
+
+    ngamctrl:
+      type: uint8-array
+      default: [
+        0x0f,
+        0x36,
+        0x2e,
+        0x09,
+        0x0a,
+        0x04,
+        0x46,
+        0x66,
+        0x37,
+        0x06,
+        0x10,
+        0x04,
+        0x24,
+        0x20,
+        0x00
+      ]
+      description:
+        Negative gamma correction (NGAMCTRL) register values.
@@ -0,0 +1,54 @@
+# Copyright (c) 2018, Jan Van Winkel <jan.van_winkel@dxplore.eu>
+# Copyright (c) 2020, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ILI9XXX display controllers common properties.
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: RESET pin.
+
+        The RESET pin of ILI9340 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    cmd-data-gpios:
+      type: phandle-array
+      required: true
+      description: D/CX pin.
+
+        The D/CX pin of ILI9340 is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    pixel-format:
+      type: int
+      default: 0
+      enum:
+        - 0 # RGB565
+        - 1 # RGB888
+      description:
+        Display pixel format. Note that when RGB888 pixel format is selected
+        only 6 color bits are actually used being in practice equivalent to
+        RGB666.
+
+    rotation:
+      type: int
+      default: 0
+      enum:
+        - 0
+        - 90
+        - 180
+        - 270
+      description:
+        Display rotation (CW) in degrees.
+
+    display-inversion:
+      type: boolean
+      description:
+        Display inversion mode. Every bit is inverted from the frame memory to
+        the display.
@@ -0,0 +1,82 @@
+# Copyright (c) 2021, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic LED matrix driven by nRF SoC GPIOs
+
+compatible: "nordic,nrf-led-matrix"
+
+include: display-controller.yaml
+
+properties:
+    row-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        Array of GPIOs to be used as rows of the matrix.
+
+    col-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        Array of GPIOs to be used as columns of the matrix.
+
+    pixel-mapping:
+      type: uint8-array
+      required: true
+      description: |
+        Array of bytes that specify which rows and columns of the matrix
+        control its particular pixels, line by line. Each byte in this
+        array corresponds to one pixel of the matrix and specifies the row
+        index in the high nibble and the column index in the low nibble.
+
+        For example, the following snippet (from the bbc_microbit board DTS):
+
+          width = <5>;
+          height = <5>;
+          pixel-mapping = [00 13 01 14 02
+                           23 24 25 26 27
+                           ...
+
+        specifies that:
+        - pixel (0,0) is controlled by row 0 and column 0
+        - pixel (1,0) is controlled by row 1 and column 3
+        - pixel (0,1) is controlled by row 2 and column 3
+        - pixel (1,1) is controlled by row 2 and column 4
+        and so on.
+
+    refresh-frequency:
+      type: int
+      required: true
+      description: |
+        Frequency of refreshing the matrix, in Hz.
+
+    timer:
+      type: phandle
+      required: true
+      description: |
+        Reference to a TIMER instance for controlling refreshing of the matrix.
+
+    pwm:
+      type: phandle
+      required: false
+      description: |
+        Reference to a PWM instance for generating pulse signals on column
+        GPIOs. If not provided, GPIOTE and PPI channels are allocated and
+        used instead for generating those pulses.
+
+    pixel-group-size:
+      type: int
+      required: true
+      description: |
+        This value specifies the maximum number of LEDs in one row that can
+        be lit simultaneously.
+        If set to 1, only a single LED is turned on in a particular time slot.
+        Bigger values increase the maximum achievable brightness of the LEDs
+        and lower the CPU load by decreasing the frequency of execution of
+        the timer interrupt handler.
+        In case GPIOTE and PPI channels are used for generating the pixel pulse
+        signals, the number of channels that need to be allocated is equal to
+        this value.
+        If GPIOTE and PPI channels are used, the upper limit for the value is
+        defined by the number of CC channels in the used timer minus one.
+        If PWM is used, the upper limit is the number of PWM channels.
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Rocktech LCD module with LED backlight and capacitive touch panel
+
+compatible: "rocktech,rk043fn02h-ct"
+
+include: base.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2020, Rohit Gujarathi
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sharp memory display controller
+
+compatible: "sharp,ls0xx"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    extcomin-gpios:
+      type: phandle-array
+      required: false
+      description: EXTCOMIN pin
+
+        The EXTCOMIN pin is where a square pulse for toggling VCOM will
+        be given
+
+    extcomin-frequency:
+      type: int
+      required: false
+      description: EXTCOMIN pin toggle frequency
+
+        The frequency with which the EXTCOMIN pin should be toggled. See
+        datasheet of particular display. Higher frequency gives better
+        contrast while low frequency saves power.
+
+    disp-en-gpios:
+      type: phandle-array
+      required: false
+      description: DISPLAY pin
+
+        The DISPLAY pin controls if the LCD displays memory contents or
+        white screen. If defined, the pin will be set high during driver
+        initialization. display blanking apis can be used to control it.
@@ -0,0 +1,117 @@
+# Copyright (c) 2020, Kim Bøndergaard <kim@fam-boendergaard.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST7735R 160x128 display controller
+
+compatible: "sitronix,st7735r"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: RESET pin.
+
+        The RESET pin of ST7735R is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    cmd-data-gpios:
+      type: phandle-array
+      required: true
+      description: D/CX pin.
+
+        The D/CX pin of ST7735R is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    x-offset:
+      type: int
+      required: true
+      description: The column offset in pixels of the LCD to the controller memory
+
+    y-offset:
+      type: int
+      required: true
+      description: The row offset in pixels of the LCD to the controller memory
+
+    madctl:
+      type: int
+      default: 0x00
+      description: Memory Data Access Control
+
+    colmod:
+      type: int
+      default: 0x06
+      description: Interface Pixel Format
+
+    pwctr1:
+      type: uint8-array
+      default: [0xb4, 0x14, 0x04]
+      description: Power Control 1 Parameter
+
+    pwctr2:
+      type: uint8-array
+      default: [0xc0]
+      description: Power Control 2 Parameter
+
+    pwctr3:
+      type: uint8-array
+      default: [0x0a, 0x00]
+      description: Power Control 3 Parameter
+
+    pwctr4:
+      type: uint8-array
+      default: [0x8a, 0x26]
+      description: Power Control 4 Parameter
+
+    pwctr5:
+      type: uint8-array
+      default: [0x8a, 0xee]
+      description: Power Control 5 Parameter
+
+    gamctrp1:
+      type: uint8-array
+      required: true
+      description: Positive Voltage Gamma Control Parameter
+
+    gamctrn1:
+      type: uint8-array
+      required: true
+      description: Negative Voltage Gamma Control Parameter
+
+    frmctr1:
+      type: uint8-array
+      default: [0x05, 0x3a, 0x3a]
+      description: Frame rate control (normal mode / full colors)
+
+    frmctr2:
+      type: uint8-array
+      default: [0x05, 0x3a, 0x3a]
+      description: Frame rate control (idle mode / 8 colors)
+
+    frmctr3:
+      type: uint8-array
+      default: [0x05, 0x3a, 0x3a, 0x05, 0x3a, 0x3a]
+      description: Frame rate control (partial mode / full colors)
+
+    caset:
+      type: uint8-array
+      default: [0x00, 0x00, 0x00, 0x7f]
+      description: Column Address Set
+
+    raset:
+      type: uint8-array
+      default: [0x00, 0x00, 0x00, 0x9f]
+      description: Row Address Set
+
+    vmctr1:
+      type: int
+      default: 0x0a
+      description: VCOM Control 1
+
+    invctr:
+      type: int
+      default: 0x07
+      description: Display Inversion Control
@@ -0,0 +1,115 @@
+# Copyright (c) 2019, Marc Reilly <marc@cpdesign.com.au>
+# Copyright (c) 2019, PHYTEC Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST7789V 320x240 display controller
+
+compatible: "sitronix,st7789v"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        RESET pin.
+
+        The RESET pin of ST7789V is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    cmd-data-gpios:
+      type: phandle-array
+      required: true
+      description: |
+        D/CX pin.
+
+        The D/CX pin of ST7789V is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    x-offset:
+      type: int
+      required: true
+      description: The column offset in pixels of the LCD to the controller memory
+
+    y-offset:
+      type: int
+      required: true
+      description: The row offset in pixels of the LCD to the controller memory
+
+    vcom:
+      type: int
+      required: true
+      description: VCOM Setting
+
+    gctrl:
+      type: int
+      required: true
+      description: Gate Control
+
+    vrhs:
+      type: int
+      required: false
+      description: VRH Setting
+
+    vdvs:
+      type: int
+      required: false
+      description: VDV Setting
+
+    mdac:
+      type: int
+      required: true
+      description: Memory Data Access Control
+
+    lcm:
+      type: int
+      required: true
+      description: LCM Setting
+
+    colmod:
+      type: int
+      required: true
+      description: Interface Pixel Format
+
+    gamma:
+      type: int
+      required: true
+      description: Gamma Setting
+
+    porch-param:
+      type: uint8-array
+      required: true
+      description: Porch Setting
+
+    cmd2en-param:
+      type: uint8-array
+      required: true
+      description: Command 2 Enable Parameter
+
+    pwctrl1-param:
+      type: uint8-array
+      required: true
+      description: Power Control 1 Parameter
+
+    pvgam-param:
+      type: uint8-array
+      required: true
+      description: Positive Voltage Gamma Control Parameter
+
+    nvgam-param:
+      type: uint8-array
+      required: true
+      description: Negative Voltage Gamma Control Parameter
+
+    ram-param:
+      type: uint8-array
+      required: true
+      description: RAM Control Parameter
+
+    rgb-param:
+      type: uint8-array
+      required: true
+      description: RGB Interface Control Parameter
@@ -0,0 +1,54 @@
+# Copyright (c) 2018, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+include: display-controller.yaml
+
+properties:
+    segment-offset:
+      type: int
+      required: true
+      description: 8-bit column start address for Page Addressing Mode
+
+    page-offset:
+      type: int
+      required: true
+      description: Start address for Page Addressing Mode
+
+    display-offset:
+      type: int
+      required: true
+      description: mapping of the display start line to one of COM0 .. COM63
+
+    multiplex-ratio:
+      type: int
+      required: true
+      description: Multiplex Ratio
+
+    segment-remap:
+      type: boolean
+      required: false
+      description: Last column address is mapped to first segment
+
+    com-invdir:
+      type: boolean
+      required: false
+      description: Scan direction is from last COM output to first COM output
+
+    com-sequential:
+      type: boolean
+      required: false
+      description: Sequential COM pin configuration
+
+    prechargep:
+      type: int
+      required: true
+      description: Duration of the pre-charge period
+
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: RESET pin.
+
+        The RESET pin of SSD1306 is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
@@ -0,0 +1,8 @@
+# Copyright (c) 2020, Marco Peter
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD1306 128x64 dot-matrix display controller on I2C bus
+
+compatible: "solomon,ssd1306fb"
+
+include: ["solomon,ssd1306fb-common.yaml", "i2c-device.yaml"]
@@ -0,0 +1,14 @@
+# Copyright (c) 2020, Marco Peter
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD1306 128x64 dot-matrix display controller on SPI bus
+
+compatible: "solomon,ssd1306fb"
+
+include: ["solomon,ssd1306fb-common.yaml", "spi-device.yaml"]
+
+properties:
+    data_cmd-gpios:
+      type: phandle-array
+      required: true
+      description: D/C# pin.
@@ -0,0 +1,93 @@
+# Copyright (c) 2018, Phytec Messtechnik GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD16XX 250x150 EPD display controller
+
+compatible: "solomon,ssd16xxfb"
+
+include: [spi-device.yaml, display-controller.yaml]
+
+properties:
+    pp-height-bits:
+      type: int
+      required: true
+      description: Number of bits used for the height parameters
+
+    pp-width-bits:
+      type: int
+      required: true
+      description: Number of bits used for the width parameters
+
+    gdv:
+      type: uint8-array
+      required: true
+      description: Gate driving voltage values
+
+    sdv:
+      type: uint8-array
+      required: true
+      description: Source driving voltage values
+
+    vcom:
+      type: int
+      required: true
+      description: VCOM voltage
+
+    border-waveform:
+      type: int
+      required: true
+      description: Border waveform
+
+    softstart:
+      type: uint8-array
+      required: false
+      description: Booster soft start values
+
+    orientation-flipped:
+      type: boolean
+      required: false
+      description: Last column address is mapped to first segment
+
+    reset-gpios:
+      type: phandle-array
+      required: true
+      description: RESET pin.
+
+        The RESET pin of SSD16XX is active low.
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    dc-gpios:
+      type: phandle-array
+      required: true
+      description: DC pin.
+
+        The DC pin of SSD16XX is active low (transmission command byte).
+        If connected directly the MCU pin should be configured
+        as active low.
+
+    busy-gpios:
+      type: phandle-array
+      required: true
+      description: BUSY pin.
+
+        The BUSY pin of SSD16XX is active high.
+        If connected directly the MCU pin should be configured
+        as active high.
+
+    lut-initial:
+      type: uint8-array
+      required: false
+
+    lut-default:
+      type: uint8-array
+      required: false
+
+    tssv:
+      type: int
+      required: false
+      description: Temperature Sensor Selection Value
+
+        Display controller can have integrated temperature sensor or
+        an external temperature sensor is connected to the controller.
+        The value selects which sensor should be used.
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Dummy display controller
+
+compatible: "zephyr,dummy-dc"
+
+include: display-controller.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: SDL based emulated display controller
+
+compatible: "zephyr,sdl-dc"
+
+include: display-controller.yaml