WIP: device tree MVP

dts/bindings/cpu/altr,nios2f.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Altera NIOS-2F CPU
+
+compatible: "altr,nios2f"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq

dts/bindings/cpu/arm,cortex-a53.yaml

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+# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: This is a representation of ARM Cortex-A53 CPU.
+
+compatible: "arm,cortex-a53"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-a72.yaml

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+# SPDX-License-Identifier: Apache-2.0
+
+description: This is a representation of ARM Cortex-A72 CPU.
+
+compatible: "arm,cortex-a72"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-m.yaml

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+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for ARM Cortex-M CPU
+
+include: cpu.yaml
+
+properties:
+    swo-ref-frequency:
+      type: int
+      required: false
+      description: Reference clock frequency for SWO if different than CPU clock.

dts/bindings/cpu/arm,cortex-m0+.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M0+ CPU
+
+compatible: "arm,cortex-m0+"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-m0.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M0 CPU
+
+compatible: "arm,cortex-m0"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-m1.yaml

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+# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M1 CPU
+
+compatible: "arm,cortex-m1"
+
+include: arm,cortex-m.yaml

dts/bindings/cpu/arm,cortex-m23.yaml

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+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M23 CPU
+
+compatible: "arm,cortex-m23"
+
+include: arm,cortex-m.yaml

dts/bindings/cpu/arm,cortex-m3.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M3 CPU
+
+compatible: "arm,cortex-m3"
+
+include: arm,cortex-m.yaml

dts/bindings/cpu/arm,cortex-m33.yaml

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+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M33 CPU
+
+compatible: "arm,cortex-m33"
+
+include: arm,cortex-m.yaml

dts/bindings/cpu/arm,cortex-m33f.yaml

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+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M33F CPU
+
+compatible: "arm,cortex-m33f"
+
+include: arm,cortex-m.yaml

dts/bindings/cpu/arm,cortex-m4.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M4 CPU
+
+compatible: "arm,cortex-m4"
+
+include: arm,cortex-m.yaml

dts/bindings/cpu/arm,cortex-m4f.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M4F CPU
+
+compatible: "arm,cortex-m4f"
+
+include: arm,cortex-m.yaml

dts/bindings/cpu/arm,cortex-m7.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-M7 CPU
+
+compatible: "arm,cortex-m7"
+
+include: arm,cortex-m.yaml

dts/bindings/cpu/arm,cortex-r4.yaml

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+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R4 CPU
+
+compatible: "arm,cortex-r4"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-r4f.yaml

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+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R4F CPU
+
+compatible: "arm,cortex-r4f"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-r5.yaml

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+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R5 CPU
+
+compatible: "arm,cortex-r5"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-r5f.yaml

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+# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R5F CPU
+
+compatible: "arm,cortex-r5f"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-r7.yaml

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+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-R7 CPU
+
+compatible: "arm,cortex-r7"
+
+include: cpu.yaml

dts/bindings/cpu/arm,cortex-r82.yaml

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+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: This is a representation of ARM Cortex-R82 CPU.
+
+compatible: "arm,cortex-r82"
+
+include: cpu.yaml

dts/bindings/cpu/cdns,tensilica-xtensa-lx4.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence Tensilica Xtensa LX4 CPU
+
+compatible: "cdns,tensilica-xtensa-lx4"
+
+include: cpu.yaml

dts/bindings/cpu/cdns,tensilica-xtensa-lx6.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence Tensilica Xtensa LX6 CPU
+
+compatible: "cdns,tensilica-xtensa-lx6"
+
+include: cpu.yaml
+
+properties:
+    clock-source:
+      type: int
+      description: cpu clock source
+      required: false

dts/bindings/cpu/cdns,tensilica-xtensa-lx7.yaml

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+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence Tensilica Xtensa LX7 CPU
+
+compatible: "cdns,tensilica-xtensa-lx7"
+
+include: cpu.yaml
+
+properties:
+    clock-source:
+      type: int
+      description: cpu clock source
+      required: false

dts/bindings/cpu/cpu.yaml

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+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for CPUs
+
+include: base.yaml
+
+properties:
+    clock-frequency:
+      type: int
+      required: false
+      description: Clock frequency in Hz
+    cpu-power-states:
+       type: phandles
+       required: false
+       description: List of power management states supported by this cpu
+    i-cache-line-size:
+      type: int
+      required: false
+      description: i-cache line size
+    d-cache-line-size:
+      type: int
+      required: false
+      description: d-cache line size

dts/bindings/cpu/espressif,riscv.yml

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+# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Espressif RISC-V CPU
+
+compatible: "esp,riscv"
+
+include: cpu.yaml
+
+properties:
+    clock-source:
+      type: int
+      description: cpu clock source
+      required: false

dts/bindings/cpu/intel,apollo_lake.yaml

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+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Apollo lake CPU
+
+compatible: "intel,apollo_lake"
+
+include: cpu.yaml

dts/bindings/cpu/intel,atom.yaml

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+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Atom CPU
+
+compatible: "intel,atom"
+
+include: cpu.yaml

dts/bindings/cpu/intel,elkhart_lake.yaml

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+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Elkhart Lake CPU
+
+compatible: "intel,elkhart_lake"
+
+include: cpu.yaml

dts/bindings/cpu/intel,lakemont.yml

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+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Lakemont CPU
+
+compatible: "intel,lakemont"
+
+include: cpu.yaml

dts/bindings/cpu/intel,x86.yaml

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+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Generic x86 qemu CPU
+
+compatible: "intel,x86"
+
+include: cpu.yaml

dts/bindings/cpu/ite,riscv-ite.yaml

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+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE IT8XXX2 RISC-V CPU
+
+compatible: "ite,riscv-ite"
+
+include: cpu.yaml

dts/bindings/cpu/neorv32-cpu.yaml

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+# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: NEORV32 RISC-V CPU
+
+compatible: "neorv32-cpu"
+
+include: cpu.yaml

dts/bindings/cpu/nuclei,bumblebee.yaml

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+# Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nuclei Bumblebee RISC-V Core
+
+compatible: "nuclei,bumblebee"
+
+include: cpu.yaml
+
+properties:
+  mcause-exception-mask:
+    type: int
+    required: true
+    description:  Specify the bits to use for exception code in mcause register.

dts/bindings/cpu/qemu,nios2-zephyr.yaml

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+# Copyright (c) 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: QEMU NIOS2 Zephyr CPU
+
+compatible: "qemu,nios2-zephyr"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  "#interrupt-cells":
+      const: 1
+
+interrupt-cells:
+  - irq

dts/bindings/cpu/sample_controller.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sample controller CPU
+
+compatible: "sample_controller"
+
+include: cpu.yaml

dts/bindings/cpu/snps,arcem.yaml

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+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Synopsys ARC EM CPU
+
+compatible: "snps,arcem"
+
+include: cpu.yaml

dts/bindings/cpu/telink,b91.yaml

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+# Copyright (c) 2021 Telink Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+description: Telink RISC-V CPU
+
+compatible: "telink,b91"
+
+include: cpu.yaml