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Daniel Agar
2022-01-06 17:20:17 -05:00
parent 07d75d85cf
commit 1f39b42525
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dts/bindings/clock/atmel,samd2x-gclk.yaml
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# Copyright (c) 2020, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: Atmel SAMD2x Generic Clock Controller (GCLK)
compatible: "atmel,samd2x-gclk"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 1
clock-cells:
- clkctrl_id
dts/bindings/clock/atmel,samd5x-gclk.yaml
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# Copyright (c) 2020, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: Atmel SAMD5x Generic Clock Controller (GCLK)
compatible: "atmel,samd5x-gclk"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 1
clock-cells:
- periph_ch
dts/bindings/clock/atmel,samd5x-mclk.yaml
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# Copyright (c) 2020, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: Atmel SAMD5x Generic Clock Controller (MCLK)
compatible: "atmel,samd5x-mclk"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 2
clock-cells:
- offset
- bit
dts/bindings/clock/clock-controller.yaml
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# Copyright (c) 2019, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
# Common fields for clock controllers
properties:
"#clock-cells":
type: int
required: true
description: Number of items to expect in a Clock specifier
dts/bindings/clock/espressif,esp32-rtc.yaml
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# Copyright (c) 2020, Mohamed ElShahawi
# SPDX-License-Identifier: Apache-2.0
description: ESP32 RTC (Power & Clock Controller Module) Module
compatible: "espressif,esp32-rtc"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
xtal-freq:
type: int
required: true
description: Value of the external XTAL connected to ESP32.
xtal-div:
type: int
required: false
description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div
"#clock-cells":
const: 1
clock-cells:
- offset # Index of the peripheral in esp32 modules list (Check esp32_clock.h)
dts/bindings/clock/fixed-clock.yaml
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# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
# SPDX-License-Identifier: Apache-2.0
description: Generic fixed-rate clock provider
compatible: "fixed-clock"
include: clock-controller.yaml
properties:
label:
type: string
required: false
description: Human readable string describing the device (used as device_get_binding() argument)
clock-frequency:
type: int
description: output clock frequency (Hz)
required: true
clocks:
type: array
required: false
description: input clock source
"#clock-cells":
const: 0
dts/bindings/clock/fixed-factor-clock.yaml
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# Copyright (c) 2021 Prevas A/S
# SPDX-License-Identifier: Apache-2.0
description: Generic fixed factor clock provider
compatible: "fixed-factor-clock"
include: clock-controller.yaml
properties:
clock-div:
type: int
description: fixed clock divider
clock-mult:
type: int
description: fixed clock multiplier
clocks:
type: phandle-array
description: input clock source
"#clock-cells":
const: 0
dts/bindings/clock/litex,clk.yaml
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
include: [clock-controller.yaml, base.yaml]
description: |
LiteX Mixed Mode Clock Manager
Common clock driver with MMCM unit for dynamic reconfiguration
of up to 7 clock outputs with ability to change frequency, duty
cycle and phase offset
compatible: "litex,clk"
clock-cells:
- id
properties:
reg:
description: Base address and lengths of the register space
"#clock-cells":
required: true
const: 1
clock-output-names:
required: true
type: string-array
description: |
List of strings of clock output signal names indexed
by the first cell in the clock specifier.
litex,lock-timeout:
required: true
type: int
description: |
Number of ms to wait for MMCM to assert LOCK signal
litex,drdy-timeout:
required: true
type: int
description: |
Number of ms to wait for MMCM to assert DRDY signal
litex,sys-clock-frequency:
required: true
type: int
description: |
System clock frequency
litex,divclk-divide-min:
required: true
type: int
description: |
minimal global divider
litex,divclk-divide-max:
required: true
type: int
description: |
maximal global divider
litex,clkfbout-mult-min:
required: true
type: int
description: |
minimal global multiplier
litex,clkfbout-mult-max:
required: true
type: int
description: |
maximal global multiplier
litex,vco-freq-min:
required: true
type: int
description: |
minimal frequency after global divider and multiplier
litex,vco-freq-max:
required: true
type: int
description: |
maximal frequency after global divider and multiplier
litex,clkout-divide-min:
required: true
type: int
description: |
minimal clock output divider
litex,clkout-divide-max:
required: true
type: int
description: |
maximal clock output divider
litex,vco-margin:
required: true
type: int
description: |
tolerancy for vco frequency
const: 0
dts/bindings/clock/litex,clkout.yaml
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
include: base.yaml
description: |
LiteX Mixed Mode Clock Manager clock output binding
compatible: "litex,clkout"
properties:
"#clock-cells":
required: true
type: int
description: |
Number of cells in a clock specifier;
Typically 0 for nodes with a single clock output
and 1 for nodes with multiple clock outputs.
const: 1
clock-output-names:
required: true
type: string
description: |
string of clock output signal name.
litex,clock-frequency:
required: true
type: int
description: |
default frequency in Hz for clock output
litex,clock-phase:
required: true
type: int
description: |
default phase offset given in degrees
litex,clock-duty-num:
required: true
type: int
description: |
default duty cycle numerator value
litex,clock-duty-den:
required: true
type: int
description: |
default duty cycle denominator value
litex,clock-margin:
required: true
type: int
description: |
clock output margin coefficient
litex,clock-margin-exp:
required: true
type: int
description: |
exponent for clkout margin
effective clkout margin shall be
margin * 10^(-exponent) * 100%
clock-cells:
- id
dts/bindings/clock/microchip,xec-pcr.yaml
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# Copyright (c) 2021, Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
description: Microchip XEC Power Clock Reset and VBAT register (PCR)
compatible: "microchip,xec-pcr"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
interrupts:
required: true
label:
required: true
core-clock-div:
type: int
required: true
description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
slow-clock-div:
type: int
required: false
description: |
PWM and TACH clock domain divided down from 48 MHz AHB clock. The
default value is 480 for 100 kHz.
pll-32k-src:
type: int
required: true
description: 32 KHz clock source for PLL
periph-32k-src:
type: int
required: true
description: 32 KHz clock source for peripherals
xtal-single-ended:
type: boolean
required: false
description: Use single ended crystal connection to XTAL2 pin.
"#clock-cells":
const: 2
clock-cells:
- regidx
- bitpos
dts/bindings/clock/nordic,nrf-clock.yaml
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# Copyright (c) 2018 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: Nordic nRF clock control node
compatible: "nordic,nrf-clock"
include: base.yaml
properties:
label:
required: true
reg:
required: true
interrupts:
required: true
hfclkaudio-frequency:
type: int
required: false
description: |
Frequency of the HFCLKAUDIO clock in Hz. Adjustable with 3.3 ppm
resolution in two frequency bands - 11.176 MHz to 11.402 MHz, and
12.165 MHz to 12.411 MHz (refer to the relevant Product Specification).
The HFCLKAUDIO clock is only available in the nRF53 Series SoCs.
dts/bindings/clock/nuvoton,npcx-pcc.yaml
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# Copyright (c) 2020 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
description: |
Nuvoton, NPCX PCC (Power and Clock Controller) node.
Besides power management, this node is also in charge of configuring the
Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
and most of NPCX hardware modules.
Here is an example of configuring OFMCLK and the other clock sources derived
from it in board dts file.
&pcc {
clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
};
compatible: "nuvoton,npcx-pcc"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
clock-frequency:
required: true
type: int
description: |
Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
only the following values are allowed:
100000000, 100 MHz
96000000, 96 MHz
90000000, 90 MHz
80000000, 80 MHz
66000000, 66 MHz
50000000, 50 MHz
48000000, 48 MHz
40000000, 40 MHz (default value after reset)
33000000, 33 MHz
enum:
- 100000000
- 96000000
- 90000000
- 80000000
- 66000000
- 50000000
- 48000000
- 40000000
- 33000000
core-prescaler:
type: int
required: true
description: |
Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
dividing OFMCLK(MCLK) and needs to meet the following requirements.
- CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
= Only the following values are allowed:
1, CORE_CLK = OFMCLK
2, CORE_CLK = OFMCLK / 2
3, CORE_CLK = OFMCLK / 3
4, CORE_CLK = OFMCLK / 4
5, CORE_CLK = OFMCLK / 5
6, CORE_CLK = OFMCLK / 6
7, CORE_CLK = OFMCLK / 7
8, CORE_CLK = OFMCLK / 8
9, CORE_CLK = OFMCLK / 9
10, CORE_CLK = OFMCLK / 10
enum:
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
apb1-prescaler:
type: int
required: true
description: |
APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
OFMCLK(MCLK) and needs to meet the following requirements.
- APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
- APB1_CLK must be an integer division (including 1) of CORE_CLK.
= Only the following values are allowed:
1, APB1_CLK = OFMCLK
2, APB1_CLK = OFMCLK / 2
3, APB1_CLK = OFMCLK / 3
4, APB1_CLK = OFMCLK / 4
5, APB1_CLK = OFMCLK / 5
6, APB1_CLK = OFMCLK / 6
7, APB1_CLK = OFMCLK / 7
8, APB1_CLK = OFMCLK / 8
9, APB1_CLK = OFMCLK / 9
10, APB1_CLK = OFMCLK / 10
enum:
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
apb2-prescaler:
type: int
required: true
description: |
APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
OFMCLK(MCLK) and needs to meet the following requirements.
- APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
- APB2_CLK must be an integer division (including 1) of CORE_CLK.
= Only the following values are allowed:
1, APB2_CLK = OFMCLK
2, APB2_CLK = OFMCLK / 2
3, APB2_CLK = OFMCLK / 3
4, APB2_CLK = OFMCLK / 4
5, APB2_CLK = OFMCLK / 5
6, APB2_CLK = OFMCLK / 6
7, APB2_CLK = OFMCLK / 7
8, APB2_CLK = OFMCLK / 8
9, APB2_CLK = OFMCLK / 9
10, APB2_CLK = OFMCLK / 10
enum:
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
apb3-prescaler:
type: int
required: true
description: |
APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
OFMCLK(MCLK) and needs to meet the following requirements.
- APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
- APB3_CLK must be an integer division (including 1) of CORE_CLK.
= Only the following values are allowed:
1, APB3_CLK = OFMCLK
2, APB3_CLK = OFMCLK / 2
3, APB3_CLK = OFMCLK / 3
4, APB3_CLK = OFMCLK / 4
5, APB3_CLK = OFMCLK / 5
6, APB3_CLK = OFMCLK / 6
7, APB3_CLK = OFMCLK / 7
8, APB3_CLK = OFMCLK / 8
9, APB3_CLK = OFMCLK / 9
10, APB3_CLK = OFMCLK / 10
enum:
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
apb4-prescaler:
type: int
required: false
description: |
APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
OFMCLK(MCLK) and needs to meet the following requirements.
- APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
- APB4_CLK must be an integer division (including 1) of CORE_CLK.
= Only the following values are allowed:
1, APB4_CLK = OFMCLK
2, APB4_CLK = OFMCLK / 2
3, APB4_CLK = OFMCLK / 3
4, APB4_CLK = OFMCLK / 4
5, APB4_CLK = OFMCLK / 5
6, APB4_CLK = OFMCLK / 6
7, APB4_CLK = OFMCLK / 7
8, APB4_CLK = OFMCLK / 8
9, APB4_CLK = OFMCLK / 9
10, APB4_CLK = OFMCLK / 10
enum:
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
ram-pd-depth:
required: false
type: int
enum:
- 12
- 15
description: |
Valid bit-depth of RAM block Power-Down control (RAM_PD) registers.
Each bit in RAM_PDn can power down the relevant RAM block by setting
itself to 1 for better power consumption and this valid bit-depth
varies in different NPCX series.
clock-cells:
- bus
- ctl
- bit
dts/bindings/clock/nxp,imx-anatop.yaml
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# Copyright (c) 2021, NXP
# SPDX-License-Identifier: Apache-2.0
description: i.MX ANATOP (Analog Clock Controller Module) IP node
compatible: "nxp,imx-anatop"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
"#clock-cells":
type: int
const: 4
required: true
description: Number of items to expect in a clock specifier
"#pll-clock-cells":
type: int
const: 3
required: true
description: Number of items to expect in a PLL specifier
clock-cells:
- name
- offset
- bits
- value
pll-clock-cells:
- offset
- bits
- value
dts/bindings/clock/nxp,imx-ccm-rev2.yaml
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# Copyright (c) 2021, NXP
# SPDX-License-Identifier: Apache-2.0
description: i.MX CCM Rev2 (Clock Controller Module) IP node
compatible: "nxp,imx-ccm-rev2"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
"#clock-cells":
const: 3
clock-cells:
- name
- offset
- bits
dts/bindings/clock/nxp,imx-ccm.yaml
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# Copyright (c) 2017, NXP
# SPDX-License-Identifier: Apache-2.0
description: i.MX CCM (Clock Controller Module) IP node
compatible: "nxp,imx-ccm"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
"#clock-cells":
const: 3
clock-cells:
- name
- offset
- bits
dts/bindings/clock/nxp,lpc-syscon.yaml
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# Copyright (c) 2020, NXP
# SPDX-License-Identifier: Apache-2.0
description: LPC SYSCON & CLKCTL IP node
compatible: "nxp,lpc-syscon"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
"#clock-cells":
const: 1
clock-cells:
- name
dts/bindings/clock/nxp,lpc11u6x-syscon.yaml
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# Copyright (c) 2020, Seagate
# SPDX-License-Identifier: Apache-2.0
description: LPC11U6X clock controller node
compatible: "nxp,lpc11u6x-syscon"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
pinmuxs:
type: phandle-array
required: true
description: system oscillator pinmux configuration
pinmux-names:
type: string-array
required: false
description: system oscillator pins names
"#clock-cells":
const: 1
clock-cells:
- clkid
dts/bindings/clock/renesas,rcar-cpg-mssr.yaml
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# Copyright (c) 2020, IoT.bzh
# SPDX-License-Identifier: Apache-2.0
description: Renesas Clock Pulse Generator / Module Standby and Software Reset
compatible: "renesas,rcar-cpg-mssr"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 2
clock-cells:
- domain
- module
dts/bindings/clock/st,stm32-hse-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: STM32 HSE Clock
compatible: "st,stm32-hse-clock"
include: [fixed-clock.yaml]
properties:
hse-bypass:
type: boolean
required: false
description: |
HSE crystal oscillator bypass
Set to the property to by-pass the oscillator with an external clock.
dts/bindings/clock/st,stm32-msi-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: STM32 MSI Clock
compatible: "st,stm32-msi-clock"
include: [clock-controller.yaml, base.yaml]
properties:
msi-range:
required: true
type: int
default: 6
description: |
MSI clock ranges
enum:
- 0 # range 0 around 100 kHz
- 1 # range 1 around 200 kHz
- 2 # range 2 around 400 kHz
- 3 # range 3 around 800 kHz
- 4 # range 4 around 1M Hz
- 5 # range 5 around 2 MHz
- 6 # range 6 around 4 MHz (reset value)
- 7 # range 7 around 8 MHz
- 8 # range 8 around 16 MHz
- 9 # range 9 around 24 MHz
- 10 # range 10 around 32 MHz
- 11 # range 11 around 48 MHz
msi-pll-mode:
type: boolean
required: false
description: |
MSI clock PLL enable
Enables the PLL part of the MSI clock source.
dts/bindings/clock/st,stm32-rcc.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32 Reset and Clock controller node.
This node is in charge of system clock ('SYSCLK') source selection and controlling
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
Configuring STM32 Reset and Clock controller node:
System clock source should be selected amongst the clock nodes available in "clocks"
node (typically 'clk_hse, clk_hsi', 'pll', ...).
As part of this node configuration, SYSCLK frequency should also be defined, using
"clock-frequency" property.
Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
prescaler properties.
Here is an example of correctly configured rcc node:
&rcc {
clocks = <&pll>; /* Set pll as SYSCLK source */
clock-frequency = <DT_FREQ_M(80)>; /* SYSCLK runs at 80MHz */
ahb-prescaler = <1>;
apb1-presacler = <1>;
apb2-presacler = <1>;
}
Specifying a gated clock:
To specify a gated clock, a peripheral should define a "clocks" property encoded
in the following way:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
...
}
After the phandle referring to rcc node, the first index specifies the registers of
the bus controlling the peripheral and the second index specifies the bit used to
control the peripheral clock in that bus register.
compatible: "st,stm32-rcc"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 2
clock-frequency:
required: true
type: int
description: |
default frequency in Hz for clock output
ahb-prescaler:
type: int
required: true
enum:
- 1
- 2
- 4
- 8
- 16
- 64
- 128
- 256
- 512
description: |
AHB prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
lower than SYSCLK frequency (actual core frequency).
The HCLK clocks CPU, AHB, memories and DMA.
apb1-prescaler:
type: int
required: true
enum:
- 1
- 2
- 4
- 8
- 16
apb2-prescaler:
type: int
required: true
enum:
- 1
- 2
- 4
- 8
- 16
clock-cells:
- bus
- bits
dts/bindings/clock/st,stm32f0-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
Main PLL node binding for STM32F0 and STM32F3 devices.
Takes one of clk_hse or clk_hsi as input clock.
Note: Some STM32F0 SoC variants (STM32072 for instance) may also support HSI48
as input clock. This case is not supported yet.
Frequency calculation for output clock is as follows:
f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
with, depending on the case:
If input_clk = clk_hse
f(PLLIN) = f(input_clk) / PREDIV
If input_clk = clk_hsi
On STM32F3, STM32F03x, STM32F05x, STM32F030x4, STM32F030x6 and STM32F030x8
f(PLLIN) = f(input_clk) / 2
On STM32F04x, STM32F07x, STM32F09x, STM32F070x6, STM32F070xB and STM32F030xC
f(PLLIN) = f(input_clk) / PREDIV
The PLL output frequency must be set in range 16-48MHz
compatible: "st,stm32f0-pll-clock"
include:
- name: st,stm32f105-pll-clock.yaml
property-blocklist:
- mul
properties:
mul:
type: int
required: true
description: |
PLL multiplication factor for output clock
Valid range: 2 - 16
dts/bindings/clock/st,stm32f0-rcc.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32F0 and G0 Reset and Clock controller node.
For more description confere st,stm32-rcc.yaml
compatible: "st,stm32f0-rcc"
include:
- name: st,stm32-rcc.yaml
property-blocklist:
- apb2-prescaler
dts/bindings/clock/st,stm32f1-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
as input clock.
Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:
f(PLLCLK) = f(input clk) x PLLMUL --> SYSCLK (System Clock)
f(USBCLK) = f(PLLCLK) / USBPRE --> USB
The PLL output frequency must not exceed 72 MHz.
compatible: "st,stm32f1-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
mul:
type: int
required: true
description: |
Main PLL multiplication factor for VCO
Valid range: 2 - 16
xtpre:
type: boolean
required: false
description: |
Otpional HSE divider for PLL entry
usbpre:
type: int
required: false
description: |
Otpional HSE divider for PLL entry
dts/bindings/clock/st,stm32f100-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
Main PLL node binding for STM32F100 devices
Takes one of clk_hse or clk_hsi as input clock.
When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
pll2, configurable prescaler is used.
Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:
f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
with, depending on the case:
f(PLLIN) = f(input_clk) / 2 if input_clk = clk_hsi
f(PLLIN) = f(input_clk) / PREDIV if input_clk = clk_hse
The PLL output frequency must not exceed 24 MHz.
compatible: "st,stm32f100-pll-clock"
include:
- name: st,stm32f105-pll-clock.yaml
property-blocklist:
- mul
properties:
mul:
type: int
required: true
description: |
PLL multiplication factor for output clock
Valid range: 2 - 16
dts/bindings/clock/st,stm32f105-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
Takes one of clk_hse, pll2 or clk_hsi as input clock.
When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
pll2, configurable prescaler is used.
Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:
f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
f(USBCLK) = f(PLLCLK) * 2 / USBPRE --> USB
with, depending on the case:
f(PLLIN) = f(input_clk) / 2 if input_clk = clk_hsi
f(PLLIN) = f(input_clk) / PREDIV if input_clk = clk_hse or pll2
The PLL output frequency must not exceed 72 MHz.
compatible: "st,stm32f105-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
mul:
type: int
required: true
description: |
Main PLL multiplication factor for VCO.
Note: For x6.5 multiplier value, please use "mul = <15>;"
enum:
- 4 # x4
- 5 # x5
- 6 # x6
- 7 # x7
- 8 # x8
- 9 # x9
- 15 # x6.5
prediv:
type: int
required: false
description: |
Configurable prescaler
Valid range: 1 - 16
dts/bindings/clock/st,stm32f105-pll2-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)
Takes clk_hse as input clock, using prediv as prescaler.
Each PLL as its own output clock.
f(PLL2CLK) = f(PLL2IN) / PREDIV * PLLMUL --> PLL (System Clock)
compatible: "st,stm32f105-pll2-clock"
include:
- name: st,stm32f105-pll-clock.yaml
property-blocklist:
- mul
properties:
mul:
type: int
required: true
description: |
PLL multiplication factor for output clock
enum:
- 8
- 9
- 10
- 11
- 12
- 13
- 14
- 16
- 20
dts/bindings/clock/st,stm32f2-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32F2 Main PLL node binding:
Takes one of clk_hse or clk_hsi as input clock.
Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:
f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
The PLL output frequency must not exceed 168 MHz.
compatible: "st,stm32f2-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div-m:
type: int
required: true
description: |
Division factor for the PLL input clock
Valid range: 2 - 63
mul-n:
type: int
required: true
description: |
PLL multiplication factor for VCO
Valid range: 192 - 432
div-p:
type: int
required: true
description: |
PLL division factor for PLLCLK
enum:
- 2
- 4
- 6
- 8
div-q:
type: int
required: false
description: |
PLL division factor for PLL48CK
Valid range: 2 - 15
dts/bindings/clock/st,stm32f4-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32L4 Main PLL node binding:
Takes one of clk_hse or clk_hsi as input clock, with an
input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
in this acceptable range.
Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:
f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
The PLL output frequency must not exceed 80 MHz.
compatible: "st,stm32f4-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div-m:
type: int
required: true
description: |
Division factor for the PLL input clock
Valid range: 2 - 63
mul-n:
type: int
required: true
description: |
Main PLL multiplication factor for VCO
Valid range: 50 - 432
div-p:
type: int
required: true
description: |
Main PLL division factor for PLLSAI2CLK
enum:
- 2
- 4
- 6
- 8
div-q:
type: int
required: false
description: |
Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
generator clocks.
Valid range: 2 - 15
dts/bindings/clock/st,stm32f7-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32F7 Main PLL node binding:
Takes one of clk_hse or clk_hsi as input clock.
Up to 2 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:
f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
compatible: "st,stm32f7-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div-m:
type: int
required: true
description: |
Division factor for the PLL input clock
Valid range: 2 - 63
mul-n:
type: int
required: true
description: |
PLL multiplication factor for VCO
Valid range: 50 - 432
div-p:
type: int
required: true
description: |
PLL division factor for PLLCLK
enum:
- 2
- 4
- 6
- 8
div-q:
type: int
required: false
description: |
PLL division factor for PLL48CK
Valid range: 2 - 15
dts/bindings/clock/st,stm32g0-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
PLL node binding for STM32G0 devices
It can take one of clk_hse or clk_hsi as input clock, with
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.
PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:
f(PLL_P) = f(VCO clock) / PLLP --> to I2S
f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
The PLL output frequency must not exceed 64 MHz.
compatible: "st,stm32g0-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div-m:
type: int
required: true
description: |
Division factor for PLL input clock
Valid range: 1 - 8
mul-n:
type: int
required: true
description: |
Main PLL multiplication factor for VCO
Valid range: 8 - 86
div-p:
type: int
required: false
description: |
PLL division factor for PLL P output
Valid range: 2 - 32
div-q:
type: int
required: false
description: |
PLL division factor for PLL Q output
Valid range: 2 - 8
div-r:
type: int
required: true
description: |
PLL division factor for PLLCLK (system clock)
Valid range: 2 - 8
dts/bindings/clock/st,stm32g4-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
PLL node binding for STM32G4 devices
It can take one of clk_hse or clk_hsi as input clock, with
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.
PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:
f(PLL_P) = f(VCO clock) / PLLP --> to ADC
f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48MCLK (for USB, RNG)
f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
The PLL output frequency must not exceed 170 MHz.
compatible: "st,stm32g4-pll-clock"
include:
- name: st,stm32l4-pll-clock.yaml
property-blocklist:
- div-m
- mul-n
properties:
div-m:
type: int
required: true
description: |
Division factor for PLL input clock
Valid range: 1 - 16
mul-n:
type: int
required: true
description: |
Main PLL multiplication factor for VCO
Valid range: 8 - 127
dts/bindings/clock/st,stm32h7-hsi-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: STM32 HSI Clock
compatible: "st,stm32h7-hsi-clock"
include: [fixed-clock.yaml]
properties:
hsi-div:
type: int
required: true
description: |
HSI clock divider. Configures the output HSI clock frequency
enum:
- 1 # hsi_clk = 64MHz
- 2 # hsi_clk = 32MHz
- 4 # hsi_clk = 16MHz
- 8 # hsi_clk = 8MHz
dts/bindings/clock/st,stm32h7-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
PLL node binding for STM32H7 devices
It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
Only PLL1 and PLL3 are supported for now.
These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.
Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:
f(PLL_Px) = f(VCOx clock) / PLLPx -> pllx_p_ck ((pll1_p_ck : sys_ck))
f(PLL_Qx) = f(VCOx clock) / PLLQx -> pllx_q_ck
f(PLL_Rx) = f(VCOx clock) / PLLRx -> pllx_r_ck
with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
The PLL output frequency must not exceed 80 MHz.
compatible: "st,stm32h7-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div-m:
type: int
required: true
description: |
Division factor for PLLx
input clock
Valid range: 0 - 63
mul-n:
type: int
required: true
description: |
Main PLL multiplication factor for VCOx
Valid range: 4 - 512
div-p:
type: int
required: false
description: |
PLL division factor for pllx_p_ck
Valid range: 1 - 128
div-q:
type: int
required: false
description: |
PLL division factor for pllx_q_ck
Valid range: 1 - 128
div-r:
type: int
required: false
description: |
PLL division factor for pllx_r_ck
Valid range: 1 - 128
dts/bindings/clock/st,stm32h7-rcc.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32 Reset and Clock controller node for STM32H7 devices
This node is in charge of system clock ('SYSCLK') source selection and
System Clock Generation.
Configuring STM32 Reset and Clock controller node:
System clock source should be selected amongst the clock nodes available in "clocks"
node (typically 'clk_hse, clk_csi', 'pll', ...).
As part of this node configuration, SYSCLK frequency should also be defined, using
"clock-frequency" property.
Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
prescaler properties.
Here is an example of correctly configured rcc node:
&rcc {
clocks = <&pll>; /* Set pll as SYSCLK source */
clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
}
Specifying a gated clock:
To specify a gated clock, a peripheral should define a "clocks" property encoded
in the following way:
... {
...
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
...
}
After the phandle referring to rcc node, the first index specifies the registers of
the bus controlling the peripheral and the second index specifies the bit used to
control the peripheral clock in that bus register.
compatible: "st,stm32h7-rcc"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 2
clock-frequency:
required: true
type: int
description: |
default frequency in Hz for clock output
d1cpre:
type: int
required: true
enum:
- 1
description: |
D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
lower than SYSCLK frequency (actual core frequency).
Zephyr doesn't make a difference today between these two clocks.
Changing this prescaler is not allowed until it is made possible to
use them independently in Zephyr clock subsystem.
hpre:
type: int
required: true
description: |
D2 domain, CPU2 core clock and AHB(1/2/3/4) peripheral prescaler
enum:
- 1
- 2
- 4
- 8
- 16
- 64
- 128
- 256
- 512
d1ppre:
type: int
required: true
description: |
D1 domain, APB3 peripheral prescaler
enum:
- 1
- 2
- 4
- 8
- 16
d2ppre1:
type: int
required: true
description: |
D2 domain, APB1 peripheral prescaler
enum:
- 1
- 2
- 4
- 8
- 16
d2ppre2:
type: int
required: true
description: |
D2 domain, APB2 peripheral prescaler
enum:
- 1
- 2
- 4
- 8
- 16
d3ppre:
type: int
required: true
description: |
D3 domain, APB4 peripheral prescaler
enum:
- 1
- 2
- 4
- 8
- 16
clock-cells:
- bus
- bits
dts/bindings/clock/st,stm32l0-msi-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: STM32L0 and STM32L1 Multi Speed Internal Clock
compatible: "st,stm32l0-msi-clock"
include:
- name: st,stm32-msi-clock.yaml
property-blocklist:
- msi-range
properties:
msi-range:
required: true
type: int
default: 5
description: |
MSI clock ranges
0: range 0 around 65.536 kHz
1: range 1 around 131.072 kHz
2: range 2 around 262.144 kHz
3: range 3 around 524.288 kHz
4: range 4 around 1.048 MHz
5: range 5 around 2.097 MHz (reset value)
6: range 6 around 4.194 MHz
dts/bindings/clock/st,stm32l0-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32L0 and STM32L1 Main PLL node binding:
Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
input frequency from 2 to 24 MHz.
The desired PLL frequency can be computed with the following formula:
f(PLL) = f(VCO clock) / PLLDIV --> PLLCLK (System Clock)
with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
The PLL output frequency must not exceed 32 MHz.
compatible: "st,stm32l0-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div:
type: int
required: true
description: |
PLL output division
enum:
- 2
- 3
- 4
mul:
type: int
required: true
description: |
PLL multiplication factor for VCO
The PLL VCO clock frequency must not exceed:
- 96 MHz when the product is in Range 1
- 48 MHz when the product is in Range 2
- 24 MHz when the product is in Range 3
If the USB uses the PLL as clock source, the PLL VCO clock must be
programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
enum:
- 3
- 4
- 6
- 8
- 12
- 16
- 24
- 32
- 48
dts/bindings/clock/st,stm32l4-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
PLL node binding for STM32L4 and STM32L5 devices
It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
Only main PLL is supported for now.
These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.
Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:
f(PLL_P) = f(VCO clock) / PLLP --> PLLSAI3CLK
f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48M1CLK
f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
The PLL output frequency must not exceed 80 MHz.
compatible: "st,stm32l4-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div-m:
type: int
required: true
description: |
Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
input clock
Valid range: 1 - 8
mul-n:
type: int
required: true
description: |
Main PLL multiplication factor for VCO
Valid range: 8 - 86
div-p:
type: int
required: false
description: |
Main PLL division factor for PLLSAI3CLK
enum:
- 7
- 17
div-q:
type: int
required: false
description: |
Main PLL division factor for PLL48M1CLK (48 MHz clock).
enum:
- 2
- 4
- 6
- 8
div-r:
type: int
required: true
description: |
Main PLL division factor for PLLCLK (system clock)
enum:
- 2
- 4
- 6
- 8
dts/bindings/clock/st,stm32mp1-rcc.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32MP1 Reset and Clock controller node.
On STM32MP1 platforms, clock control configuration is performed on A9 side.
As a consequence, the only property to be set in devicetree node is the
clock-frequency (mlhclk_ck).
compatible: "st,stm32mp1-rcc"
include:
- name: st,stm32-rcc.yaml
property-blocklist:
- ahb-prescaler
- apb1-prescaler
- apb2-prescaler
dts/bindings/clock/st,stm32u5-msi-clock.yaml
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# Copyright (c) 2021, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: STM32U5 Multi Speed Internal Clock
compatible: "st,stm32u5-msi-clock"
include:
- name: st,stm32-msi-clock.yaml
property-blocklist:
- msi-range
properties:
msi-range:
default: 4
required: true
type: int
description: |
MSI clock ranges
enum:
- 0 # range 0 around 48 MHz
- 1 # range 1 around 24 MHz
- 2 # range 2 around 16 MHz
- 3 # range 3 around 12 MHz
- 4 # range 4 around 4 MHz (reset value)
- 5 # range 5 around 2 MHz
- 6 # range 6 around 1.33 MHz
- 7 # range 7 around 1 MHz
- 8 # range 8 around 3.072 MHz
- 9 # range 9 around 1.536 MHz
- 10 # range 10 around 1.024 MHz
- 11 # range 11 around 768 KHz
- 12 # range 12 around 400 KHz
- 13 # range 13 around 200 KHz
- 14 # range 14 around 133 KHz
- 15 # range 14 around 100 KHz
dts/bindings/clock/st,stm32u5-pll-clock.yaml
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# Copyright (c) 2021, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: |
PLL node binding for STM32U5 devices
It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
Only main PLL (PLL1) is supported for now.
These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.
Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:
f(PLL_P) = f(VCO clock) / PLLP
f(PLL_Q) = f(VCO clock) / PLLQ
f(PLL_R) = f(VCO clock) / PLLR
with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
Note: To reduce the power consumption, it is recommended to configure the VCOx
clock output to the lowest frequency.
The PLL output frequency must not exceed 160 MHz.
compatible: "st,stm32u5-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div-m:
type: int
required: true
description: |
Prescaler for PLLx
input clock
Valid range: 1 - 16
mul-n:
type: int
required: true
description: |
PLLx multiplication factor for VCO
Valid range: 4 - 512
div-q:
type: int
required: false
description: |
PLLx DIVQ division factor
Valid range: 2 - 128
div-r:
type: int
required: true
description: |
PLLx DIVR division factor
Valid range: 2 - 128
dts/bindings/clock/st,stm32u5-rcc.yaml
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# Copyright (c) 2021, Linaro Limited
# SPDX-License-Identifier: Apache-2.0
description: |
STM32U5 Reset and Clock controller node.
For more description confere st,stm32-rcc.yaml
compatible: "st,stm32u5-rcc"
include: st,stm32-rcc.yaml
properties:
apb3-prescaler:
type: int
required: true
enum:
- 1
- 2
- 4
- 8
- 16
dts/bindings/clock/st,stm32wb-pll-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32WB and STM32WL PLL node.
It can be used to describe 2 different PLLs: PLL, PLLSAI1.
Only main PLL is supported for now.
These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.
Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:
f(PLL_P) = f(VCO clock) / PLLP --> PLLPCLK
f(PLL_Q) = f(VCO clock) / PLLQ --> PLLQCLK
f(PLL_R) = f(VCO clock) / PLLR --> PLLRCLK (System Clock)
with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
The PLL output frequency must not exceed:
- 64 MHz on STM32WB
- 62 MHz on STM32WL
compatible: "st,stm32wb-pll-clock"
include: [clock-controller.yaml, base.yaml]
properties:
"#clock-cells":
const: 0
clocks:
required: true
div-m:
type: int
required: true
description: |
Main PLL division factor for PLL input clock
Valid range: 1 - 8
mul-n:
type: int
required: true
description: |
Main PLL multiplication factor for VCO
Valid range: 6 - 127
div-p:
type: int
required: false
description: |
Main PLL division factor for PLLPCLK
Valid range: 2 - 32
div-q:
type: int
required: false
description: |
Main PLL division factor for PLLQCLK
Valid range: 2 - 8
div-r:
type: int
required: true
description: |
Main PLL division factor for PLLRCLK (system clock)
Valid range: 2 - 8
dts/bindings/clock/st,stm32wb-rcc.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32WB Reset and Clock controller node.
For more description confere st,stm32-rcc.yaml
compatible: "st,stm32wb-rcc"
include:
- name: st,stm32-rcc.yaml
property-blocklist:
- ahb-prescaler
properties:
cpu1-prescaler:
type: int
required: true
enum:
- 1
- 2
- 3
- 4
- 5
- 6
- 8
- 10
- 16
- 32
- 64
- 128
- 256
- 512
description: |
CPU1 prescaler. Sets a HCLK1 frequency (feeding Cortex-M Systick)
lower than SYSCLK frequency (actual core frequency).
The HCLK1 clocks CPU1, AHB1, AHB2, AHB3 and SRAM1.
cpu2-prescaler:
type: int
required: true
enum:
- 1
- 2
- 4
- 8
- 16
- 32
- 64
- 128
- 256
- 512
description: |
CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
(A.K.A C2HPRE)
ahb4-prescaler:
type: int
required: true
enum:
- 1
- 2
- 4
- 8
- 16
- 32
- 64
- 128
- 256
- 512
description: |
HCLK4 shared prescaler (AHB4, Flash memory and SRAM2).
(A.K.A SHDHPRE)
clock-cells:
- bus
- bits
dts/bindings/clock/st,stm32wl-hse-clock.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: STM32WL HSE Clock
compatible: "st,stm32wl-hse-clock"
include: [fixed-clock.yaml]
properties:
hse-tcxo:
type: boolean
required: false
description: |
When set, TCXO is selected as external source clock for HSE.
Otherwise, external cyrstal is selected as HSE source clock.
hse-div2:
type: boolean
required: false
description: |
When set HSE output clock is divided by 2.
Otherwise, no prescaler is used.
dts/bindings/clock/st,stm32wl-rcc.yaml
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# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0
description: |
STM32WL Reset and Clock controller node.
For more description confere st,stm32-rcc.yaml
compatible: "st,stm32wl-rcc"
include:
- name: st,stm32wb-rcc.yaml
property-blocklist:
- ahb4-prescaler
- cpu2-prescaler
properties:
cpu2-prescaler:
type: int
required: false
enum:
- 1
- 2
- 4
- 8
- 16
- 32
- 64
- 128
- 256
- 512
description: |
CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
(A.K.A C2HPRE)
ahb3-prescaler:
type: int
required: true
enum:
- 1
- 2
- 4
- 8
- 16
- 32
- 64
- 128
- 256
- 512
description: |
HCLK3 shared prescaler (AHB3, Flash memory, SRAM1 and SRAM2).
(A.K.A SHDHPRE)
clock-cells:
- bus
- bits